diff options
| author | Thierry Reding <treding@nvidia.com> | 2014-04-16 09:09:34 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2014-12-04 16:16:14 +0100 |
| commit | b26ea06babf5026f68d5da98edfc164f8aee7346 (patch) | |
| tree | 1031cbe8d9d9f64145b6bbd592cbb45e514e0619 /arch/arm/boot/dts/tegra124.dtsi | |
| parent | c6f70a4d175bcecd56e0ba541ecf6905b4fb80fe (diff) | |
ARM: tegra: Add memory controller support for Tegra124
Add the memory controller and wire up the interrupt that is used to
report errors. Provide a reference to the memory controller clock and
mark the device as being an IOMMU by adding an #iommu-cells property.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra124.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/tegra124.dtsi | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index af2eace5eb63..5fcc6e704faa 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -552,6 +552,17 @@ reset-names = "fuse"; }; + mc: memory-controller@0,70019000 { + compatible = "nvidia,tegra124-mc"; + reg = <0x0 0x70019000 0x0 0x1000>; + clocks = <&tegra_car TEGRA124_CLK_MC>; + clock-names = "mc"; + + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; + + #iommu-cells = <1>; + }; + sata@0,70020000 { compatible = "nvidia,tegra124-ahci"; |