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authorGabriel FERNANDEZ <gabriel.fernandez@st.com>2015-01-14 10:54:00 +0100
committerMaxime Coquelin <maxime.coquelin@st.com>2015-01-16 12:57:12 +0100
commitb26373c0da982f8a29406f10db39e287c1f0696b (patch)
tree118f23ad466420dd9194944ef557ef524c5cdf36 /arch/arm/boot/dts/stih407-family.dtsi
parent3fba7036c53e2c24c7505b7869dc77464fdd7d9e (diff)
ARM: DT: STi: STiH407: Add DT node for MiPHY28lp
The MiPHY28lp is a Generic PHY which can serve various SATA, PCIe or USB3 devices. The two first ports can be use for either; both SATA, both PCIe or one of each in any configuration. The Third port is only for USB3. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
Diffstat (limited to 'arch/arm/boot/dts/stih407-family.dtsi')
-rw-r--r--arch/arm/boot/dts/stih407-family.dtsi53
1 files changed, 53 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi
index d4a8f843cdc8..c06a54681912 100644
--- a/arch/arm/boot/dts/stih407-family.dtsi
+++ b/arch/arm/boot/dts/stih407-family.dtsi
@@ -283,5 +283,58 @@
<&picophyreset STIH407_PICOPHY0_RESET>;
reset-names = "global", "port";
};
+
+ miphy28lp_phy: miphy28lp@9b22000 {
+ compatible = "st,miphy28lp-phy";
+ st,syscfg = <&syscfg_core>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ phy_port0: port@9b22000 {
+ reg = <0x9b22000 0xff>,
+ <0x9b09000 0xff>,
+ <0x9b04000 0xff>;
+ reg-names = "sata-up",
+ "pcie-up",
+ "pipew";
+
+ st,syscfg = <0x114 0x818 0xe0 0xec>;
+ #phy-cells = <1>;
+
+ reset-names = "miphy-sw-rst";
+ resets = <&softreset STIH407_MIPHY0_SOFTRESET>;
+ };
+
+ phy_port1: port@9b2a000 {
+ reg = <0x9b2a000 0xff>,
+ <0x9b19000 0xff>,
+ <0x9b14000 0xff>;
+ reg-names = "sata-up",
+ "pcie-up",
+ "pipew";
+
+ st,syscfg = <0x118 0x81c 0xe4 0xf0>;
+
+ #phy-cells = <1>;
+
+ reset-names = "miphy-sw-rst";
+ resets = <&softreset STIH407_MIPHY1_SOFTRESET>;
+ };
+
+ phy_port2: port@8f95000 {
+ reg = <0x8f95000 0xff>,
+ <0x8f90000 0xff>;
+ reg-names = "pipew",
+ "usb3-up";
+
+ st,syscfg = <0x11c 0x820>;
+
+ #phy-cells = <1>;
+
+ reset-names = "miphy-sw-rst";
+ resets = <&softreset STIH407_MIPHY2_SOFTRESET>;
+ };
+ };
};
};