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authorDinh Nguyen <dinguyen@altera.com>2014-04-16 15:05:15 -0500
committerDinh Nguyen <dinguyen@altera.com>2014-05-05 22:33:18 -0500
commit8cb289ed60668d3350dda5aa19b4fa1dce1c07f1 (patch)
tree2c254d8089be3b05be5db6db16f07d23ab11986d /arch/arm/boot/dts/socfpga.dtsi
parent16fb4f8bd59e0e954991f624bcc53dad2052ef0d (diff)
ARM: socfpga: dts: Add div-reg to the main_pll clocks
The mpu_clk, main_clk, and dbg_base_clk outputs from the main PLL go through a pre-divider. Update socfpga.dtsi to represent those dividers for these clocks. Re-use the "div-reg" property that was used for the socfpga-gate-clock as this is the same thing. Also update the documentation. Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Diffstat (limited to 'arch/arm/boot/dts/socfpga.dtsi')
-rw-r--r--arch/arm/boot/dts/socfpga.dtsi6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 917464ac01ef..280966b92e5e 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -148,7 +148,7 @@
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&main_pll>;
- fixed-divider = <2>;
+ div-reg = <0xe0 0 9>;
reg = <0x48>;
};
@@ -156,7 +156,7 @@
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&main_pll>;
- fixed-divider = <4>;
+ div-reg = <0xe4 0 9>;
reg = <0x4C>;
};
@@ -164,7 +164,7 @@
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&main_pll>;
- fixed-divider = <4>;
+ div-reg = <0xe8 0 9>;
reg = <0x50>;
};