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authorTroy Kisky <troy.kisky@boundarydevices.com>2013-12-16 18:12:52 -0700
committerShawn Guo <shawn.guo@linaro.org>2014-02-09 21:29:21 +0800
commit0e06842fb7e73af038ccbf409080349e902e3f4b (patch)
tree18e0e6d32a04bef2c4b8c213db5cc14d85ed9309 /arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
parent1169cf1f4d609f1e2046c8fb1a3c47c8a478d214 (diff)
ARM: dts: imx6qdl-sabrelite: move USDHC4 CD to pinctrl_usdhc4
This patch moves pin NANDF_D6 (CD) from pinctrl_hog to pinctrl_usdhc4. It also explicitly sets the pad to 0x1b0b0, which is also the value that it has before this patch if using mainline u-boot. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/imx6qdl-sabrelite.dtsi')
-rw-r--r--arch/arm/boot/dts/imx6qdl-sabrelite.dtsi2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
index 82b728375070..d5629a50fc06 100644
--- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
@@ -114,7 +114,6 @@
imx6q-sabrelite {
pinctrl_hog: hoggrp {
fsl,pins = <
- MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000
MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000
MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
@@ -208,6 +207,7 @@
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
+ MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 /* CD */
>;
};
};