diff options
| author | Mark Langsdorf <mark.langsdorf@calxeda.com> | 2013-01-28 16:13:15 +0000 |
|---|---|---|
| committer | Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 2013-02-02 00:01:15 +0100 |
| commit | 6754f556103be5bd172263b1075ddbb7157afbad (patch) | |
| tree | cd913973afd0247175e3adeecaf19d484753580a /arch/arm/boot/dts/highbank.dts | |
| parent | 300586778d405f0a4d1f6dc51fcfb4fed567d020 (diff) | |
cpufreq / highbank: add support for highbank cpufreq
Highbank processors depend on the external ECME to perform voltage
management based on a requested frequency. Communication between the
A9 cores and the ECME happens over the pl320 IPC channel.
Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com>
Reviewed-by: Shawn Guo <shawn.guo@linaro.org>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'arch/arm/boot/dts/highbank.dts')
| -rw-r--r-- | arch/arm/boot/dts/highbank.dts | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts index 5927a8df5625..6aad34ad9517 100644 --- a/arch/arm/boot/dts/highbank.dts +++ b/arch/arm/boot/dts/highbank.dts @@ -37,6 +37,16 @@ next-level-cache = <&L2>; clocks = <&a9pll>; clock-names = "cpu"; + operating-points = < + /* kHz ignored */ + 1300000 1000000 + 1200000 1000000 + 1100000 1000000 + 800000 1000000 + 400000 1000000 + 200000 1000000 + >; + clock-latency = <100000>; }; cpu@901 { |