diff options
| author | Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> | 2014-05-20 16:48:10 +0200 |
|---|---|---|
| committer | Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> | 2014-10-29 19:44:45 +0100 |
| commit | 652538c4d27df714efc4dd092e6defe87c0bbeb9 (patch) | |
| tree | 5bd705cec6173dcf85cc22435747a4dea1c55252 /arch/arm/boot/dts/berlin2cd.dtsi | |
| parent | 60daa9f71de148cbfc33187c2ce6d3dd80cf8fa0 (diff) | |
ARM: dts: berlin: Add SDHCI controller nodes to BG2/BG2CD
Marvell Berlin BG2 has three, BG2CD just one pxav3 compatible
sdhci controllers, add them to the corresponding DT SoC
includes.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Diffstat (limited to 'arch/arm/boot/dts/berlin2cd.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/berlin2cd.dtsi | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/berlin2cd.dtsi b/arch/arm/boot/dts/berlin2cd.dtsi index fff23aad8205..9e338ff80fd3 100644 --- a/arch/arm/boot/dts/berlin2cd.dtsi +++ b/arch/arm/boot/dts/berlin2cd.dtsi @@ -45,6 +45,15 @@ ranges = <0 0xf7000000 0x1000000>; + sdhci0: sdhci@ab0000 { + compatible = "mrvl,pxav3-mmc"; + reg = <0xab0000 0x200>; + clocks = <&chip CLKID_SDIO0XIN>, <&chip CLKID_SDIO0>; + clock-names = "io", "core"; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + l2: l2-cache-controller@ac0000 { compatible = "arm,pl310-cache"; reg = <0xac0000 0x1000>; |