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authorAndreas Färber <afaerber@suse.de>2014-11-06 18:22:10 +0100
committerOlof Johansson <olof@lixom.net>2014-11-08 16:57:44 -0800
commit92c9e0c780e61f821ab8a08f0d4d4fd33ba1197c (patch)
tree8b4261a61703ce295f6e8f64b65251f0fe183824 /Makefile
parent5305e4d674ed5ec9bebd11d948affd411594d4cf (diff)
downloadlinux-linaro-stable-92c9e0c780e61f821ab8a08f0d4d4fd33ba1197c.tar.gz
ARM: dts: zynq: Enable PL clocks for Parallella
The Parallella board comes with a U-Boot bootloader that loads one of two predefined FPGA bitstreams before booting the kernel. Both define an AXI interface to the on-board Epiphany processor. Enable clocks FCLK0..FCLK3 for the Programmable Logic by default. Otherwise accessing, e.g., the ESYSRESET register freezes the board, as seen with the Epiphany SDK tools e-reset and e-hw-rev, using /dev/mem. Cc: <stable@vger.kernel.org> # 3.17.x Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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