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authorLinus Torvalds <torvalds@linux-foundation.org>2013-05-09 14:38:16 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2013-05-09 14:38:16 -0700
commitc61c48dfe00907007df3b87e4ed271a5c143bdda (patch)
tree6d26bd3a8b4aa3cf35cad35fa27d1e0afe715db3 /Documentation
parente30f4192456971623b40c97a027346b69457ef69 (diff)
parentb341d84c8ac5ecbf7aa0b3ccd0745d87e881953c (diff)
downloadlinux-linaro-stable-c61c48dfe00907007df3b87e4ed271a5c143bdda.tar.gz
Merge tag 'xtensa-next-20130508' of git://github.com/czankel/xtensa-linux
Pull xtensa updates from Chris Zankel: "Support for the latest MMU architecture that allows for a larger accessible memory region, and various bug-fixes" * tag 'xtensa-next-20130508' of git://github.com/czankel/xtensa-linux: xtensa: Switch to asm-generic/linkage.h xtensa: fix redboot load address xtensa: ISS: fix timer_lock usage in rs_open xtensa: disable IRQs while IRQ handler is running xtensa: enable lockdep support xtensa: fix arch_irqs_disabled_flags implementation xtensa: add irq flags trace support xtensa: provide custom CALLER_ADDR* implementations xtensa: add stacktrace support xtensa: clean up stpill_registers xtensa: don't use a7 in simcalls xtensa: don't attempt to use unconfigured timers xtensa: provide default platform_pcibios_init implementation xtensa: remove KCORE_ELF again xtensa: document MMUv3 setup sequence xtensa: add MMU v3 support xtensa: fix ibreakenable register update xtensa: fix oprofile building as module
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/xtensa/mmu.txt46
1 files changed, 46 insertions, 0 deletions
diff --git a/Documentation/xtensa/mmu.txt b/Documentation/xtensa/mmu.txt
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+MMUv3 initialization sequence.
+
+The code in the initialize_mmu macro sets up MMUv3 memory mapping
+identically to MMUv2 fixed memory mapping. Depending on
+CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX symbol this code is
+located in one of the following address ranges:
+
+ 0xF0000000..0xFFFFFFFF (will keep same address in MMU v2 layout;
+ typically ROM)
+ 0x00000000..0x07FFFFFF (system RAM; this code is actually linked
+ at 0xD0000000..0xD7FFFFFF [cached]
+ or 0xD8000000..0xDFFFFFFF [uncached];
+ in any case, initially runs elsewhere
+ than linked, so have to be careful)
+
+The code has the following assumptions:
+ This code fragment is run only on an MMU v3.
+ TLBs are in their reset state.
+ ITLBCFG and DTLBCFG are zero (reset state).
+ RASID is 0x04030201 (reset state).
+ PS.RING is zero (reset state).
+ LITBASE is zero (reset state, PC-relative literals); required to be PIC.
+
+TLB setup proceeds along the following steps.
+
+ Legend:
+ VA = virtual address (two upper nibbles of it);
+ PA = physical address (two upper nibbles of it);
+ pc = physical range that contains this code;
+
+After step 2, we jump to virtual address in 0x40000000..0x5fffffff
+that corresponds to next instruction to execute in this code.
+After step 4, we jump to intended (linked) address of this code.
+
+ Step 0 Step1 Step 2 Step3 Step 4 Step5
+ ============ ===== ============ ===== ============ =====
+ VA PA PA VA PA PA VA PA PA
+ ------ -- -- ------ -- -- ------ -- --
+ E0..FF -> E0 -> E0 E0..FF -> E0 F0..FF -> F0 -> F0
+ C0..DF -> C0 -> C0 C0..DF -> C0 E0..EF -> F0 -> F0
+ A0..BF -> A0 -> A0 A0..BF -> A0 D8..DF -> 00 -> 00
+ 80..9F -> 80 -> 80 80..9F -> 80 D0..D7 -> 00 -> 00
+ 60..7F -> 60 -> 60 60..7F -> 60
+ 40..5F -> 40 40..5F -> pc -> pc 40..5F -> pc
+ 20..3F -> 20 -> 20 20..3F -> 20
+ 00..1F -> 00 -> 00 00..1F -> 00