|author||Liviu Dudau <Liviu.Dudau@arm.com>||2015-01-20 16:52:59 +0000|
|committer||Alex Shi <email@example.com>||2015-11-07 12:44:26 +0800|
irqchip: gic: Allow interrupt level to be set for PPIs
During a recent cleanup of the arm64 DTs it has become clear that the handling of PPIs in xxxx_set_type() is incorrect. The ARM TRMs for GICv2 and later allow for "implementation defined" support for setting the edge or level type of the PPI interrupts and don't restrict the activation level of the signal. Current ARM implementations do restrict the PPI level type to IRQ_TYPE_LEVEL_LOW, but licensees of the IP can decide to shoot themselves in the foot at any time. Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com> Acked-by: Marc Zyngier <Marc.Zyngier@arm.com> Cc: LAKML <firstname.lastname@example.org> Cc: Russell King <email@example.com> Cc: Rob Herring <firstname.lastname@example.org> Cc: Mark Rutland <email@example.com> Cc: Ian Campbell <firstname.lastname@example.org> Cc: Jason Cooper <email@example.com> Cc: Haojian Zhuang <firstname.lastname@example.org> Link: http://lkml.kernel.org/r/1421772779-25764-1-git-send-email-Liviu.Dudau@arm.com Signed-off-by: Thomas Gleixner <email@example.com> (cherry picked from commit fb7e7deb7fc348ae131268d30e391c8184285de6) Signed-off-by: Alex Shi <firstname.lastname@example.org>
Diffstat (limited to 'Documentation')
1 files changed, 6 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/arm/gic.txt b/Documentation/devicetree/bindings/arm/gic.txt
index 375147e5a5fb..45ccc2db3436 100644
@@ -31,12 +31,16 @@ Main node required properties:
The 3rd cell is the flags, encoded as follows:
bits[3:0] trigger type and level flags.
1 = low-to-high edge triggered
- 2 = high-to-low edge triggered
+ 2 = high-to-low edge triggered (invalid for SPIs)
4 = active high level-sensitive
- 8 = active low level-sensitive
+ 8 = active low level-sensitive (invalid for SPIs).
bits[15:8] PPI interrupt cpu mask. Each bit corresponds to each of
the 8 possible cpus attached to the GIC. A bit set to '1' indicated
the interrupt is wired to that CPU. Only valid for PPI interrupts.
+ Also note that the configurability of PPI interrupts is IMPLEMENTATION
+ DEFINED and as such not guaranteed to be present (most SoC available
+ in 2014 seem to ignore the setting of this flag and use the hardware
+ default value).
- reg : Specifies base physical address(s) and size of the GIC registers. The
first region is the GIC distributor register base and size. The 2nd region is