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authorAneesh Kumar <aneesh.kumar@gmail.com>2006-05-15 09:44:36 -0700
committerLinus Torvalds <torvalds@g5.osdl.org>2006-05-15 11:20:58 -0700
commit79afecfaabbe42e2a8a7e28880517f1721f2f3a7 (patch)
tree26b577c7c882e1fec21e4dedb2c938bc742e8964 /Documentation/memory-barriers.txt
parentbfe2e9349f318883c036607c64b6205d573a28ff (diff)
downloadlinux-linaro-stable-79afecfaabbe42e2a8a7e28880517f1721f2f3a7.tar.gz
[PATCH] Fix typos in Documentation/memory-barriers.txt
Fix some typos in Documentation/memory-barriers.txt Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@gmail.com> Cc: David Howells <dhowells@redhat.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'Documentation/memory-barriers.txt')
-rw-r--r--Documentation/memory-barriers.txt4
1 files changed, 2 insertions, 2 deletions
diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt
index 92f0056d928c..c61d8b876fdb 100644
--- a/Documentation/memory-barriers.txt
+++ b/Documentation/memory-barriers.txt
@@ -1031,7 +1031,7 @@ conflict on any particular lock.
LOCKS VS MEMORY ACCESSES
------------------------
-Consider the following: the system has a pair of spinlocks (N) and (Q), and
+Consider the following: the system has a pair of spinlocks (M) and (Q), and
three CPUs; then should the following sequence of events occur:
CPU 1 CPU 2
@@ -1678,7 +1678,7 @@ CPU's caches by some other cache event:
smp_wmb();
<A:modify v=2> <C:busy>
<C:queue v=2>
- p = &b; q = p;
+ p = &v; q = p;
<D:request p>
<B:modify p=&v> <D:commit p=&v>
<D:read p>