diff options
| author | Dong Aisheng <b29396@freescale.com> | 2013-10-18 19:48:47 +0800 |
|---|---|---|
| committer | Chris Ball <chris@printf.net> | 2013-10-21 15:58:13 -0400 |
| commit | 602519b2bd63adfdf9e24b2f94aaddcfeb464e9e (patch) | |
| tree | 818c25ef9f7c6db0d89f09753896666f013bf4e6 /Documentation/devicetree/bindings/mmc | |
| parent | de5bdbffd89dea0e3de76f99b0b036422bb93686 (diff) | |
mmc: sdhci-esdhc-imx: add delay line setting support
The DLL(Delay Line) is newly added to assist in sampling read data.
The DLL provides the ability to programmatically select a quantized
delay (in fractions of the clock period) regardless of on-chip variations
such as process, voltage and temperature (PVT).
This patch adds a user interface to set slave delay line via device tree.
It's usually used in high speed mode like mmc DDR mode when the signal
quality is not good caused by board design, e.g. the signal path is too
long. User can manually set delay line to find a suitable data sampling
window for card to work properly.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Chris Ball <cjb@laptop.org>
Diffstat (limited to 'Documentation/devicetree/bindings/mmc')
| -rw-r--r-- | Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt index 1dd622546d06..9046ba06c47a 100644 --- a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt +++ b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt @@ -12,6 +12,11 @@ Required properties: Optional properties: - fsl,cd-controller : Indicate to use controller internal card detection - fsl,wp-controller : Indicate to use controller internal write protection +- fsl,delay-line : Specify the number of delay cells for override mode. + This is used to set the clock delay for DLL(Delay Line) on override mode + to select a proper data sampling window in case the clock quality is not good + due to signal path is too long on the board. Please refer to eSDHC/uSDHC + chapter, DLL (Delay Line) section in RM for details. Examples: |