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| author | Mark Brown <broonie@linaro.org> | 2014-07-23 13:16:53 +0100 |
|---|---|---|
| committer | Mark Brown <broonie@linaro.org> | 2014-07-23 13:16:53 +0100 |
| commit | 6a87ef22a8b54095478561f9f2664c40c5c76d98 (patch) | |
| tree | 66292f45032cad8d8978a8d53b51b398fc91a000 /Documentation/arm64/booting.txt | |
| parent | 6c45113800d819f87b0af7f80d627d0208e10a6c (diff) | |
| parent | a4121f52920d3588e475336bf076915899e51509 (diff) | |
Merge branch 'linux-linaro-lsk-v3.14' into linux-linaro-lsk-v3.14-androidlsk-v3.14-android-preview-14.07
Diffstat (limited to 'Documentation/arm64/booting.txt')
| -rw-r--r-- | Documentation/arm64/booting.txt | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/Documentation/arm64/booting.txt b/Documentation/arm64/booting.txt index a9691cc48fe3..beb754e87c65 100644 --- a/Documentation/arm64/booting.txt +++ b/Documentation/arm64/booting.txt @@ -111,8 +111,14 @@ Before jumping into the kernel, the following conditions must be met: - Caches, MMUs The MMU must be off. Instruction cache may be on or off. - Data cache must be off and invalidated. - External caches (if present) must be configured and disabled. + The address range corresponding to the loaded kernel image must be + cleaned to the PoC. In the presence of a system cache or other + coherent masters with caches enabled, this will typically require + cache maintenance by VA rather than set/way operations. + System caches which respect the architected cache maintenance by VA + operations must be configured and may be enabled. + System caches which do not respect architected cache maintenance by VA + operations (not recommended) must be configured and disabled. - Architected timers CNTFRQ must be programmed with the timer frequency and CNTVOFF must |