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authorSteve Capper <steve.capper@linaro.org>2014-07-02 11:46:23 +0100
committerMark Brown <broonie@linaro.org>2014-07-25 12:59:06 +0100
commita95eca36ffbf8891d1e1a20d5c4a237f6d8f6a1f (patch)
treedc8eaa34513ceafa6977c4a1148867d90801f324
parent6dca4f12e885d399d7a6fb9ab396981153886f9e (diff)
downloadlinux-linaro-stable-a95eca36ffbf8891d1e1a20d5c4a237f6d8f6a1f.tar.gz
arm64: mm: Make icache synchronisation logic huge page aware
The __sync_icache_dcache routine will only flush the dcache for the first page of a compound page, potentially leading to stale icache data residing further on in a hugetlb page. This patch addresses this issue by taking into consideration the order of the page when flushing the dcache. Reported-by: Mark Brown <broonie@linaro.org> Tested-by: Mark Brown <broonie@linaro.org> Signed-off-by: Steve Capper <steve.capper@linaro.org> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Cc: <stable@vger.kernel.org> # v3.11+ (cherry picked from commit 923b8f5044da753e4985ab15c1374ced2cdf616c) Signed-off-by: Mark Brown <broonie@linaro.org>
-rw-r--r--arch/arm64/mm/flush.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm64/mm/flush.c b/arch/arm64/mm/flush.c
index e4193e3adc7f..0d64089d28b5 100644
--- a/arch/arm64/mm/flush.c
+++ b/arch/arm64/mm/flush.c
@@ -79,7 +79,8 @@ void __sync_icache_dcache(pte_t pte, unsigned long addr)
return;
if (!test_and_set_bit(PG_dcache_clean, &page->flags)) {
- __flush_dcache_area(page_address(page), PAGE_SIZE);
+ __flush_dcache_area(page_address(page),
+ PAGE_SIZE << compound_order(page));
__flush_icache_all();
} else if (icache_is_aivivt()) {
__flush_icache_all();