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authorWill Deacon <will.deacon@arm.com>2015-03-23 19:07:02 +0000
committerKevin Hilman <khilman@linaro.org>2015-05-18 16:16:15 -0700
commita0121477d2c5e7b62436edca6dac4cd8058c15a5 (patch)
tree2b46b301ba1b982339c222e2f9566b095d33f4e4
parent96dade5633c3ebb68fc191fd2cc03f89fc4f57f9 (diff)
downloadlinux-linaro-stable-a0121477d2c5e7b62436edca6dac4cd8058c15a5.tar.gz
arm64: errata: add workaround for cortex-a53 erratum #845719v3.10/topic/arm64-errata
When running a compat (AArch32) userspace on Cortex-A53, a load at EL0 from a virtual address that matches the bottom 32 bits of the virtual address used by a recent load at (AArch64) EL1 might return incorrect data. This patch works around the issue by writing to the contextidr_el1 register on the exception return path when returning to a 32-bit task. Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Tested-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> (cherry picked from commit 905e8c5dcaa147163672b06fe9dcb5abaacbc711) [khilman: modified to remove dependency on alternatives framwork. Feature is now only compile-time selectable, and defaults to off. ] Signed-off-by: Kevin Hilman <khilman@linaro.org>
-rw-r--r--arch/arm64/Kconfig26
-rw-r--r--arch/arm64/kernel/entry.S11
2 files changed, 37 insertions, 0 deletions
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 56b3f6d447ae..50d090002bc8 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -122,6 +122,32 @@ endmenu
menu "Kernel Features"
+menu "ARM errata workarounds"
+
+config ARM64_ERRATUM_845719
+ bool "Cortex-A53: 845719: a load might read incorrect data"
+ depends on COMPAT
+ default n
+ help
+ This option adds an alternative code sequence to work around ARM
+ erratum 845719 on Cortex-A53 parts up to r0p4.
+
+ When running a compat (AArch32) userspace on an affected Cortex-A53
+ part, a load at EL0 from a virtual address that matches the bottom 32
+ bits of the virtual address used by a recent load at (AArch64) EL1
+ might return incorrect data.
+
+ The workaround is to write the contextidr_el1 register on exception
+ return to a 32-bit task.
+ Please note that this does not necessarily enable the workaround,
+ as it depends on the alternative framework, which will only patch
+ the kernel if an affected CPU is detected.
+
+ If unsure, say Y.
+
+endmenu
+
+
config ARM64_64K_PAGES
bool "Enable 64KB pages support"
help
diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S
index 1d1314280a03..bb64eedfbefd 100644
--- a/arch/arm64/kernel/entry.S
+++ b/arch/arm64/kernel/entry.S
@@ -89,6 +89,17 @@
ldp x21, x22, [sp, #S_PC] // load ELR, SPSR
.if \el == 0
ldr x23, [sp, #S_SP] // load return stack pointer
+#ifdef CONFIG_ARM64_ERRATUM_845719
+ tbz x22, #4, 1f
+#ifdef CONFIG_PID_IN_CONTEXTIDR
+ mrs x29, contextidr_el1
+ msr contextidr_el1, x29
+1:
+#else
+ msr contextidr_el1, xzr
+1:
+#endif
+#endif
.endif
.if \ret
ldr x1, [sp, #S_X1] // preserve x0 (syscall return)