diff options
| author | Marc Zyngier <marc.zyngier@arm.com> | 2018-02-01 11:07:37 +0000 |
|---|---|---|
| committer | Alex Shi <alex.shi@linaro.org> | 2018-03-07 13:15:37 +0800 |
| commit | d3d5150314e05cc7698ee54786c590f6b14ff4c8 (patch) | |
| tree | a1bbd700a9582898c0cbca927576640c44009984 | |
| parent | 8b1b5add9b4a152613ee439f179ca72e0721cec0 (diff) | |
arm: Invalidate icache on prefetch abort outside of user mapping on Cortex-A15
** Not yet queued for inclusion in mainline **
In order to prevent aliasing attacks on the branch predictor,
invalidate the icache on Cortex-A15, which has the side effect
of invalidating the BTB. This requires ACTLR[0] to be set to 1
(secure operation).
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Alex Shi <alex.shi@linaro.org>
| -rw-r--r-- | arch/arm/include/asm/cp15.h | 1 | ||||
| -rw-r--r-- | arch/arm/mm/fault.c | 4 |
2 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/include/asm/cp15.h b/arch/arm/include/asm/cp15.h index 0672ddc7654f..b74b174ac9fc 100644 --- a/arch/arm/include/asm/cp15.h +++ b/arch/arm/include/asm/cp15.h @@ -65,6 +65,7 @@ #define write_sysreg(v, ...) __write_sysreg(v, __VA_ARGS__) #define BPIALL __ACCESS_CP15(c7, 0, c5, 6) +#define ICIALLU __ACCESS_CP15(c7, 0, c5, 0) extern unsigned long cr_alignment; /* defined in entry-armv.S */ diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c index 17fd0c7ae95b..a9c924bafbb3 100644 --- a/arch/arm/mm/fault.c +++ b/arch/arm/mm/fault.c @@ -409,6 +409,10 @@ do_pabt_page_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs) case ARM_CPU_PART_CORTEX_A17: write_sysreg(0, BPIALL); break; + + case ARM_CPU_PART_CORTEX_A15: + write_sysreg(0, ICIALLU); + break; } } #endif |