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authorRussell King <rmk+kernel@arm.linux.org.uk>2013-11-06 17:18:42 +0000
committerRussell King <rmk+kernel@arm.linux.org.uk>2014-04-04 00:30:21 +0100
commit45da7b0451b1fe15e882b08c79be58458cbe7a2f (patch)
tree2ab0905104403822ec05c5f402e9e39cb720dd91
parent59871902703c47acc730555be41bd9cb36d3700c (diff)
downloadlinux-linaro-stable-45da7b0451b1fe15e882b08c79be58458cbe7a2f.tar.gz
dmaengine: omap-dma: use cached CCR value when enabling DMA
We don't need to read-modify-write the CCR register; we already know what value it should contain at this point. Use the cached CCR value when setting the enable bit. Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
-rw-r--r--drivers/dma/omap-dma.c6
1 files changed, 2 insertions, 4 deletions
diff --git a/drivers/dma/omap-dma.c b/drivers/dma/omap-dma.c
index 49b303296d75..b270aedf1d15 100644
--- a/drivers/dma/omap-dma.c
+++ b/drivers/dma/omap-dma.c
@@ -181,7 +181,6 @@ static void omap_dma_clear_csr(struct omap_chan *c)
static void omap_dma_start(struct omap_chan *c, struct omap_desc *d)
{
struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
- uint32_t val;
if (__dma_omap15xx(od->plat->dma_attr))
c->plat->dma_write(0, CPC, c->dma_ch);
@@ -193,9 +192,8 @@ static void omap_dma_start(struct omap_chan *c, struct omap_desc *d)
/* Enable interrupts */
c->plat->dma_write(d->cicr, CICR, c->dma_ch);
- val = c->plat->dma_read(CCR, c->dma_ch);
- val |= CCR_ENABLE;
- c->plat->dma_write(val, CCR, c->dma_ch);
+ /* Enable channel */
+ c->plat->dma_write(d->ccr | CCR_ENABLE, CCR, c->dma_ch);
}
static void omap_dma_stop(struct omap_chan *c)