diff options
| author | Alex Deucher <alexander.deucher@amd.com> | 2013-04-18 09:36:42 -0400 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2014-06-07 16:02:13 -0700 |
| commit | d9d3e8ed90d9513ee90af49302cbcfcc636d71a5 (patch) | |
| tree | 217ad67a4b9847abd192525cb916d8e7709501a9 | |
| parent | 63034aee5f85e6c4decdaa600ed1febfa90a348f (diff) | |
drm/radeon: fix hdmi mode enable on RS600/RS690/RS740
commit dcb852905772416e322536ced5cb3c796d176af5 upstream.
These chips were previously skipped since they are
pre-R600.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[bwh: Backported to 3.2: adjust context]
Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
[wml: Backported to 3.4:
- adjust context
- no !ASIC_IS_DCE3(rdev)]
Signed-off-by: Weng Meiling <wengmeiling.weng@huawei.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| -rw-r--r-- | drivers/gpu/drm/radeon/r600_hdmi.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c index 0b5920671450..61ffe3c76474 100644 --- a/drivers/gpu/drm/radeon/r600_hdmi.c +++ b/drivers/gpu/drm/radeon/r600_hdmi.c @@ -530,7 +530,7 @@ void r600_hdmi_enable(struct drm_encoder *encoder) WREG32_P(radeon_encoder->hdmi_config_offset + 0x4, 0x1, ~0x1); } else if (ASIC_IS_DCE3(rdev)) { /* TODO */ - } else if (rdev->family >= CHIP_R600) { + } else if (ASIC_IS_DCE2(rdev)) { switch (radeon_encoder->encoder_id) { case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: WREG32_P(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN, @@ -602,7 +602,7 @@ void r600_hdmi_disable(struct drm_encoder *encoder) WREG32_P(radeon_encoder->hdmi_config_offset + 0xc, 0, ~0x1); } else if (ASIC_IS_DCE32(rdev)) { WREG32_P(radeon_encoder->hdmi_config_offset + 0x4, 0, ~0x1); - } else if (rdev->family >= CHIP_R600 && !ASIC_IS_DCE3(rdev)) { + } else if (ASIC_IS_DCE2(rdev) && !ASIC_IS_DCE3(rdev)) { switch (radeon_encoder->encoder_id) { case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: WREG32_P(AVIVO_TMDSA_CNTL, 0, |