diff options
| author | Will Deacon <will.deacon@arm.com> | 2015-10-06 18:46:21 +0100 |
|---|---|---|
| committer | Alex Shi <alex.shi@linaro.org> | 2016-05-18 20:59:50 +0800 |
| commit | b18cd6e3459c4554027e9de1cd6137c99f336821 (patch) | |
| tree | 44dafbaff3dadec63a952f2c1a211d31fed33e8a | |
| parent | f135c521812a74dc09cd2abccb59dc9e61832f27 (diff) | |
arm64: mm: remove unused cpu_set_idmap_tcr_t0sz function
With commit b08d4640a3dc ("arm64: remove dead code"),
cpu_set_idmap_tcr_t0sz is no longer called and can therefore be removed
from the kernel.
This patch removes the function and effectively inlines the helper
function __cpu_set_tcr_t0sz into cpu_set_default_tcr_t0sz.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
(cherry picked from commit c51e97d89e526368eb697f87cd4d391b9e19f369)
Signed-off-by: Alex Shi <alex.shi@linaro.org>
| -rw-r--r-- | arch/arm64/include/asm/mmu_context.h | 35 |
1 files changed, 12 insertions, 23 deletions
diff --git a/arch/arm64/include/asm/mmu_context.h b/arch/arm64/include/asm/mmu_context.h index 0ffd1d651cfd..4aa03c819834 100644 --- a/arch/arm64/include/asm/mmu_context.h +++ b/arch/arm64/include/asm/mmu_context.h @@ -77,34 +77,23 @@ static inline bool __cpu_uses_extended_idmap(void) unlikely(idmap_t0sz != TCR_T0SZ(VA_BITS))); } -static inline void __cpu_set_tcr_t0sz(u64 t0sz) -{ - unsigned long tcr; - - if (__cpu_uses_extended_idmap()) - asm volatile ( - " mrs %0, tcr_el1 ;" - " bfi %0, %1, %2, %3 ;" - " msr tcr_el1, %0 ;" - " isb" - : "=&r" (tcr) - : "r"(t0sz), "I"(TCR_T0SZ_OFFSET), "I"(TCR_TxSZ_WIDTH)); -} - -/* - * Set TCR.T0SZ to the value appropriate for activating the identity map. - */ -static inline void cpu_set_idmap_tcr_t0sz(void) -{ - __cpu_set_tcr_t0sz(idmap_t0sz); -} - /* * Set TCR.T0SZ to its default value (based on VA_BITS) */ static inline void cpu_set_default_tcr_t0sz(void) { - __cpu_set_tcr_t0sz(TCR_T0SZ(VA_BITS)); + unsigned long tcr; + + if (!__cpu_uses_extended_idmap()) + return; + + asm volatile ( + " mrs %0, tcr_el1 ;" + " bfi %0, %1, %2, %3 ;" + " msr tcr_el1, %0 ;" + " isb" + : "=&r" (tcr) + : "r"(TCR_T0SZ(VA_BITS)), "I"(TCR_T0SZ_OFFSET), "I"(TCR_TxSZ_WIDTH)); } static inline void switch_new_context(struct mm_struct *mm) |