diff options
| author | Mark Rutland <mark.rutland@arm.com> | 2015-03-24 15:10:21 +0000 |
|---|---|---|
| committer | Alex Shi <alex.shi@linaro.org> | 2016-05-18 15:24:45 +0800 |
| commit | 86cc4e3ea3758428a771c1136f83ff831bbacec2 (patch) | |
| tree | cce76272bd93a9580d4e72e9a0c7b04c3baef14a | |
| parent | 7b52ac2232db865bb78edc240cdedb479fca8b65 (diff) | |
arm64: head.S: ensure idmap_t0sz is visible
We write idmap_t0sz with SCTLR_EL1.{C,M} clear, but we only have the
guarnatee that the kernel Image is clean, not invalid in the caches, and
therefore we might read a stale value once the MMU is enabled.
This patch ensures we invalidate the corresponding cacheline after the
write as we do for all other data written before we set SCTLR_EL1.{C.M},
guaranteeing that the value will be visible later. We rely on the DSBs
in __create_page_tables to complete the maintenance.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
CC: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
(cherry picked from commit 0c20856c260236b96f54c452d38dbe1348ed34d2)
Signed-off-by: Alex Shi <alex.shi@linaro.org>
| -rw-r--r-- | arch/arm64/kernel/head.S | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index 41bea0e6306b..e51ea3b03362 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -414,7 +414,10 @@ __create_page_tables: cmp x5, TCR_T0SZ(VA_BITS) // default T0SZ small enough? b.ge 1f // .. then skip additional level - str_l x5, idmap_t0sz, x6 + adr_l x6, idmap_t0sz + str x5, [x6] + dmb sy + dc ivac, x6 // Invalidate potentially stale cache line create_table_entry x0, x3, EXTRA_SHIFT, EXTRA_PTRS, x5, x6 1: |