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authorAlex Shi <alex.shi@linaro.org>2014-07-16 13:00:26 +0800
committerAlex Shi <alex.shi@linaro.org>2014-07-17 15:01:42 +0800
commit8cf077805ea8e587e5e2511a17b51c6cf34f49a0 (patch)
tree7a6671a7e7bfb3c26fa9e5f20127f6ca8110feb4
parent951b6c8102437d60f9429dd074c8e48a80484aea (diff)
parent6b71859d5a360c94415543fe9cf4bda500f0a4d0 (diff)
Merge branch 'vexp-mcpm' into vexpress
-rw-r--r--arch/arm/kernel/setup.c13
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 1e8b030dbefd..4a5e9430f16b 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -273,6 +273,19 @@ static int cpu_has_aliasing_icache(unsigned int arch)
int aliasing_icache;
unsigned int id_reg, num_sets, line_size;
+#ifdef CONFIG_BIG_LITTLE
+ /*
+ * We expect a combination of Cortex-A15 and Cortex-A7 cores.
+ * A7 = VIPT aliasing I-cache
+ * A15 = PIPT (non-aliasing) I-cache
+ * To cater for this discrepancy, let's assume aliasing I-cache
+ * all the time. This means unneeded extra work on the A15 but
+ * only ptrace is affected which is not performance critical.
+ */
+ if ((read_cpuid_id() & 0xff0ffff0) == 0x410fc0f0)
+ return 1;
+#endif
+
/* PIPT caches never alias. */
if (icache_is_pipt())
return 0;