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authorBen Dooks <ben.dooks@codethink.co.uk>2013-02-01 16:23:08 +0100
committerVictor Kamensky <victor.kamensky@linaro.org>2014-03-13 14:42:28 -0700
commitc145b15891c0964d86d0ed3b6c79f5457f28db2d (patch)
treeefe7c6e8e8bed24a8f2d2246655dc1747cb90ae9
parent87d7e2fbb75c47fb83363953b8f865a6d4d359aa (diff)
downloadlinux-linaro-stable-c145b15891c0964d86d0ed3b6c79f5457f28db2d.tar.gz
ARM: fixup_pv_table bug when CPU_ENDIAN_BE8
The fixup_pv_table assumes that the instructions are in the same endian configuration as the data, but when the CPU is running in BE8 the instructions stay in little-endian format. Make sure if CONFIG_CPU_ENDIAN_BE8 is set that we do all the alterations to the instructions taking in to account the LDR/STR will be swapping the data endian-ness. Since the code is only modifying a byte, we avoid dual-swapping the data, and just change the bits we clear and ORR in (in the case where the code is not thumb2). For thumb2, we add the necessary rev16 instructions to ensure that the instructions are processed in the correct format, as it was easier than re-writing the code to contain a mask and shift. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Reviewed-by: Dave Martin <Dave.Martin@arm.com> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> (cherry picked from commit 2f9bf9beddb1649485b47302a5aba9761cbc9084) Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
-rw-r--r--arch/arm/kernel/head.S8
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 2725c87fade6..807a9f5a458c 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -583,8 +583,10 @@ __fixup_a_pv_table:
b 2f
1: add r7, r3
ldrh ip, [r7, #2]
+ARM_BE8(rev16 ip, ip)
and ip, 0x8f00
orr ip, r6 @ mask in offset bits 31-24
+ARM_BE8(rev16 ip, ip)
strh ip, [r7, #2]
2: cmp r4, r5
ldrcc r7, [r4], #4 @ use branch for delay slot
@@ -593,8 +595,14 @@ __fixup_a_pv_table:
#else
b 2f
1: ldr ip, [r7, r3]
+#ifdef CONFIG_CPU_ENDIAN_BE8
+ @ in BE8, we load data in BE, but instructions still in LE
+ bic ip, ip, #0xff000000
+ orr ip, ip, r6, lsl#24
+#else
bic ip, ip, #0x000000ff
orr ip, ip, r6 @ mask in offset bits 31-24
+#endif
str ip, [r7, r3]
2: cmp r4, r5
ldrcc r7, [r4], #4 @ use branch for delay slot