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authorCatalin Marinas <catalin.marinas@arm.com>2013-11-29 10:56:14 +0000
committerMark Brown <broonie@linaro.org>2014-05-14 12:17:58 +0100
commite850da006c7ca131c8aa1ef614bd1bcee4a3e929 (patch)
treed4f3ee188b029a5a953936fce7043af684405f15
parentb67a42ee58fa4e5a2d5a20a9009b160e77e132a7 (diff)
downloadlinux-linaro-stable-e850da006c7ca131c8aa1ef614bd1bcee4a3e929.tar.gz
arm64: Use Normal NonCacheable memory for writecombine
commit 4f00130b70e5eee813cc7bc298e0f3fdf79673cc upstream. This provides better performance compared to Device GRE and also allows unaligned accesses. Such memory is intended to be used with standard RAM (e.g. framebuffers) and not I/O. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Cc: Mark Brown <broonie@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> (cherry picked from commit 3655a197b1ea3ce989d34868768c5f4b6205061c) Signed-off-by: Mark Brown <broonie@linaro.org>
-rw-r--r--arch/arm64/include/asm/pgtable.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index e333a243bfcc..e9a1a1d81892 100644
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -184,7 +184,7 @@ static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
#define pgprot_noncached(prot) \
__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE))
#define pgprot_writecombine(prot) \
- __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_GRE))
+ __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC))
#define pgprot_dmacoherent(prot) \
__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC))
#define __HAVE_PHYS_MEM_ACCESS_PROT