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authorLucas Stach <dev@lynxeye.de>2016-10-24 23:32:04 +0200
committerSasha Levin <alexander.levin@verizon.com>2016-11-23 23:02:21 -0500
commit1d98a7de7025c96fcb196a43ff0021011c528d8a (patch)
tree2d176438a4c850e0fcf6d1003039d1ba810748d8
parent24542192519d21719377d89f14654b3afd993a61 (diff)
downloadlinux-linaro-stable-1d98a7de7025c96fcb196a43ff0021011c528d8a.tar.gz
drm/radeon: drop register readback in cayman_cp_int_cntl_setup
[ Upstream commit 537b4b462caa8bfb9726d9695b8e56e2d5e6b41e ] The read is taking a considerable amount of time (about 50us on this machine). The register does not ever hold anything other than the ring ID that is updated in this exact function, so there is no need for the read modify write cycle. This chops off a big chunk of the time spent in hardirq disabled context, as this function is called multiple times in the interrupt handler. With this change applied radeon won't show up in the list of the worst IRQ latency offenders anymore, where it was a regular before. Reviewed-by: Christian K├Ânig <christian.koenig@amd.com> Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
-rw-r--r--drivers/gpu/drm/radeon/ni.c4
1 files changed, 1 insertions, 3 deletions
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index a019ba246e39..3e8a0d634420 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -1339,9 +1339,7 @@ static void cayman_pcie_gart_fini(struct radeon_device *rdev)
void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
int ring, u32 cp_int_cntl)
{
- u32 srbm_gfx_cntl = RREG32(SRBM_GFX_CNTL) & ~3;
-
- WREG32(SRBM_GFX_CNTL, srbm_gfx_cntl | (ring & 3));
+ WREG32(SRBM_GFX_CNTL, RINGID(ring));
WREG32(CP_INT_CNTL, cp_int_cntl);
}