diff options
| author | Marc Zyngier <marc.zyngier@arm.com> | 2018-01-19 15:42:09 +0000 |
|---|---|---|
| committer | Alex Shi <alex.shi@linaro.org> | 2018-03-07 13:15:35 +0800 |
| commit | b9dd73697ea9aa35bab533a88e9131628ae5d180 (patch) | |
| tree | eb910cb19b5404e812da6f68549a6ec771872296 | |
| parent | ecd944eedd2788ee58fd75a024940d0e50a89fbf (diff) | |
arm64: Move BP hardening to check_and_switch_context
commit a8e4c0a919ae upstream.
We call arm64_apply_bp_hardening() from post_ttbr_update_workaround,
which has the unexpected consequence of being triggered on every
exception return to userspace when ARM64_SW_TTBR0_PAN is selected,
even if no context switch actually occured.
This is a bit suboptimal, and it would be more logical to only
invalidate the branch predictor when we actually switch to
a different mm.
In order to solve this, move the call to arm64_apply_bp_hardening()
into check_and_switch_context(), where we're guaranteed to pick
a different mm context.
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Alex Shi <alex.shi@linaro.org>
Conflicts:
no sw pan in arch/arm64/mm/context.c
| -rw-r--r-- | arch/arm64/mm/context.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c index accf7ead3945..362cc077c8e7 100644 --- a/arch/arm64/mm/context.c +++ b/arch/arm64/mm/context.c @@ -230,6 +230,7 @@ void check_and_switch_context(struct mm_struct *mm, unsigned int cpu) raw_spin_unlock_irqrestore(&cpu_asid_lock, flags); switch_mm_fastpath: + arm64_apply_bp_hardening(); cpu_switch_mm(mm->pgd, mm); } @@ -240,8 +241,6 @@ asmlinkage void post_ttbr_update_workaround(void) "ic iallu; dsb nsh; isb", ARM64_WORKAROUND_CAVIUM_27456, CONFIG_CAVIUM_ERRATUM_27456)); - - arm64_apply_bp_hardening(); } static int asids_init(void) |