aboutsummaryrefslogtreecommitdiff
path: root/arch/powerpc/boot/dts/pcm030.dts
blob: 9e354997eb7e3ccc29ac70ee5e7a31c3ce319b01 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
/*
 * phyCORE-MPC5200B-tiny (pcm030) board Device Tree Source
 *
 * Copyright 2006 Pengutronix
 * Sascha Hauer <s.hauer@pengutronix.de>
 * Copyright 2007 Pengutronix
 * Juergen Beisert <j.beisert@pengutronix.de>
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

/include/ "mpc5200b.dtsi"

/ {
	model = "phytec,pcm030";
	compatible = "phytec,pcm030";

	soc5200@f0000000 {
		timer@600 {		// General Purpose Timer
			fsl,has-wdt;
		};

		gpt2: timer@620 {	// General Purpose Timer in GPIO mode
			compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
			gpio-controller;
			#gpio-cells = <2>;
		};

		gpt3: timer@630 {	// General Purpose Timer in GPIO mode
			compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
			gpio-controller;
			#gpio-cells = <2>;
		};

		gpt4: timer@640 {	// General Purpose Timer in GPIO mode
			compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
			gpio-controller;
			#gpio-cells = <2>;
		};

		gpt5: timer@650 {	// General Purpose Timer in GPIO mode
			compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
			gpio-controller;
			#gpio-cells = <2>;
		};

		gpt6: timer@660 {	// General Purpose Timer in GPIO mode
			compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
			gpio-controller;
			#gpio-cells = <2>;
		};

		gpt7: timer@670 {	// General Purpose Timer in GPIO mode
			compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
			gpio-controller;
			#gpio-cells = <2>;
		};

		psc@2000 { /* PSC1 in ac97 mode */
			compatible = "mpc5200b-psc-ac97","fsl,mpc5200b-psc-ac97";
			cell-index = <0>;
		};

		/* PSC2 port is used by CAN1/2 */
		psc@2200 {
			status = "disabled";
		};

		psc@2400 { /* PSC3 in UART mode */
			compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
		};

		/* PSC4 is ??? */
		psc@2600 {
			status = "disabled";
		};

		/* PSC5 is ??? */
		psc@2800 {
			status = "disabled";
		};

		psc@2c00 { /* PSC6 in UART mode */
			compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
		};

		ethernet@3000 {
			phy-handle = <&phy0>;
		};

		mdio@3000 {
			phy0: ethernet-phy@0 {
				reg = <0>;
			};
		};

		i2c@3d40 {
			rtc@51 {
				compatible = "nxp,pcf8563";
				reg = <0x51>;
			};
			eeprom@52 {
				compatible = "catalyst,24c32";
				reg = <0x52>;
				pagesize = <32>;
			};
		};

		sram@8000 {
			compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
			reg = <0x8000 0x4000>;
		};
	};

	pci@f0000d00 {
		interrupt-map-mask = <0xf800 0 0 7>;
		interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
				 0xc000 0 0 2 &mpc5200_pic 1 1 3
				 0xc000 0 0 3 &mpc5200_pic 1 2 3
				 0xc000 0 0 4 &mpc5200_pic 1 3 3

				 0xc800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot
				 0xc800 0 0 2 &mpc5200_pic 1 2 3
				 0xc800 0 0 3 &mpc5200_pic 1 3 3
				 0xc800 0 0 4 &mpc5200_pic 0 0 3>;
		ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
			  0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
			  0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
	};

	localbus {
		status = "disabled";
	};
};