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path: root/arch/powerpc/math-emu/math_efp.c
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2011-10-06powerpc/math_emu/efp: Look for errata handler when type mismatchesLiu Yu
We already have cpu a005 errata handler when instruction cannot be recognized. Before we lookup the inst, there's type checking, and we also need to handle it in errata handler when the type checking failed. Signed-off-by: Liu Yu <yu.liu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-06powerpc/math_emu/efp: No need to round if the result is exactLiu Yu
Signed-off-by: Liu Yu <yu.liu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-06powerpc/math_emu/efp: Use pr_debug instead of printkLiu Yu
Signed-off-by: Liu Yu <yu.liu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-03-15powerpc/85xx: Fix SPE float to integer conversion failureShan Hai
Conversion from float to integer should based on both the instruction encoding and the sign of the operand. A simple testcase to show the issue: static float fm; static signed int si_min = (-2147483647 - 1); static unsigned int ui; int main() { fm = (float) si_min; ; ui = (unsigned int)fm; printf("ui=%d, should be %d\n", ui, si_min); return 0; } Result: ui=-1, should be -2147483648 Signed-off-by: Shan Hai <shan.hai@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-03-15powerpc/85xx: Workaroudn e500 CPU erratum A005Liu Yu
This erratum can occur if a single-precision floating-point, double-precision floating-point or vector floating-point instruction on a mispredicted branch path signals one of the floating-point data interrupts which are enabled by the SPEFSCR (FINVE, FDBZE, FUNFE or FOVFE bits). This interrupt must be recorded in a one-cycle window when the misprediction is resolved. If this extremely rare event should occur, the result could be: The SPE Data Exception from the mispredicted path may be reported erroneously if a single-precision floating-point, double-precision floating-point or vector floating-point instruction is the second instruction on the correct branch path. According to errata description, some efp instructions which are not supposed to trigger SPE exceptions can trigger the exceptions in this case. However, as we haven't emulated these instructions here, a signal will send to userspace, and userspace application would exit. This patch re-issue the efp instruction that we haven't emulated, so that hardware can properly execute it again if this case happen. Signed-off-by: Liu Yu <yu.liu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-12-03powerpc: Add SPE/EFP math emulation for E500v1/v2 processors.Liu Yu
This patch add the handlers of SPE/EFP exceptions. The code is used to emulate float point arithmetic, when MSR(SPE) is enabled and receive EFP data interrupt or EFP round interrupt. This patch has no conflict with or dependence on FP math-emu. The code has been tested by TestFloat. Now the code doesn't support SPE/EFP instructions emulation (it won't be called when receive program interrupt), but it could be easily added. Signed-off-by: Liu Yu <yu.liu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>