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authorDave Airlie <airlied@redhat.com>2013-03-07 11:12:14 +1000
committerDave Airlie <airlied@redhat.com>2013-03-07 11:12:14 +1000
commit2cc79544bd0aabb4b3cf467ead5df526d9134c64 (patch)
tree1cecfe645494883b5bb86ca500873626f1697e04 /drivers/gpu/drm/i915/intel_ddi.c
parent64e38a8c8d6882e321eb7a9959321a85d16a05aa (diff)
parentf40ebd6bcbbd0d30591f42dc16be52b5086a366b (diff)
Merge branch 'drm-intel-fixes' of git://people.freedesktop.org/~danvet/drm-intel into drm-next
A bunch of fixes, nothing truely horrible: - Fix PCH irq handling race which resulted in missed gmbus/dp aux irqs and subsequent fallout (Paulo) - Fixup off-by-one in our hsw id table (Kenneth) - Fixup ilk rc6 support (disabled by default), regression introduced in 3.8 - g4x plane w/a from Egbert Eich - gen2/3/4 dpms suspend/standy fixes for VGA outputs from Patrik Jakobsson - Workaround dying ivb machines with less aggressive rc6 values (Stéphane Marchesin) * 'drm-intel-fixes' of git://people.freedesktop.org/~danvet/drm-intel: drm/i915: Turn off hsync and vsync on ADPA when disabling crt drm/i915: Fix incorrect definition of ADPA HSYNC and VSYNC bits drm/i915: also disable south interrupts when handling them drm/i915: enable irqs earlier when resuming drm/i915: Increase the RC6p threshold. DRM/i915: On G45 enable cursor plane briefly after enabling the display plane. drm/i915: Fix Haswell/CRW PCI IDs. drm/i915: Don't clobber crtc->fb when queue_flip fails drm/i915: wait_event_timeout's timeout is in jiffies drm/i915: Fix missing variable initilization
Diffstat (limited to 'drivers/gpu/drm/i915/intel_ddi.c')
-rw-r--r--drivers/gpu/drm/i915/intel_ddi.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index d64af5aa4a1..8d0bac3c35d 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1391,8 +1391,8 @@ void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
struct intel_dp *intel_dp = &intel_dig_port->dp;
struct drm_i915_private *dev_priv = encoder->dev->dev_private;
enum port port = intel_dig_port->port;
- bool wait;
uint32_t val;
+ bool wait = false;
if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
val = I915_READ(DDI_BUF_CTL(port));