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authorMichael Ellerman <michael@ellerman.id.au>2006-11-23 00:46:43 +0100
committerPaul Mackerras <paulus@samba.org>2006-12-04 20:40:29 +1100
commitae06e374c15c5d62e08c19c15f2c247a86e240d4 (patch)
tree0126919fb2edccaa6f8a50545a403bd5e9deab6b /arch/powerpc/xmon/spu-opc.c
parent4c4c8723684b1b2cd0dfdf5e0685f35642bde253 (diff)
downloadlinaro-lsk-ae06e374c15c5d62e08c19c15f2c247a86e240d4.tar.gz
[POWERPC] Import spu disassembly code into xmon
This patch imports and munges the spu disassembly code from binutils. All files originated from version 1.1 in binutils cvs. * spu.h, spu-insns.h and spu-opc.c are unchanged except for pathnames. * spu-dis.c has been edited heavily: * use printf instead of info->fprintf_func and similar. * pass the instruction in rather than reading it. * we have no equivalent to symbol_at_address_func, so we just assume there is never a symbol at the address given. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
Diffstat (limited to 'arch/powerpc/xmon/spu-opc.c')
-rw-r--r--arch/powerpc/xmon/spu-opc.c44
1 files changed, 44 insertions, 0 deletions
diff --git a/arch/powerpc/xmon/spu-opc.c b/arch/powerpc/xmon/spu-opc.c
new file mode 100644
index 00000000000..efffde9edc6
--- /dev/null
+++ b/arch/powerpc/xmon/spu-opc.c
@@ -0,0 +1,44 @@
+/* SPU opcode list
+
+ Copyright 2006 Free Software Foundation, Inc.
+
+ This file is part of GDB, GAS, and the GNU binutils.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+
+#include "spu.h"
+
+/* This file holds the Spu opcode table */
+
+
+/*
+ Example contents of spu-insn.h
+ id_tag mode mode type opcode mnemonic asmtype dependency FPU L/S? branch? instruction
+ QUAD WORD (0,RC,RB,RA,RT) latency
+ APUOP(M_LQD, 1, 0, RI9, 0x1f8, "lqd", ASM_RI9IDX, 00012, FXU, 1, 0) Load Quadword d-form
+ */
+
+const struct spu_opcode spu_opcodes[] = {
+#define APUOP(TAG,MACFORMAT,OPCODE,MNEMONIC,ASMFORMAT,DEP,PIPE) \
+ { MACFORMAT, OPCODE, MNEMONIC, ASMFORMAT },
+#define APUOPFB(TAG,MACFORMAT,OPCODE,FB,MNEMONIC,ASMFORMAT,DEP,PIPE) \
+ { MACFORMAT, OPCODE, MNEMONIC, ASMFORMAT },
+#include "spu-insns.h"
+#undef APUOP
+#undef APUOPFB
+};
+
+const int spu_num_opcodes =
+ sizeof (spu_opcodes) / sizeof (spu_opcodes[0]);