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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2011-04-05 14:20:31 +1000
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2011-04-20 11:03:22 +1000
commita5d4f3ad3a28cf046836b9bfae61d532b8f77036 (patch)
tree6940ace9422e91459d819b385dacf9b2ab44bd50 /arch/powerpc/kernel/cpu_setup_power7.S
parent2dd60d79e0202628a47af9812a84d502cc63628c (diff)
downloadlinaro-lsk-a5d4f3ad3a28cf046836b9bfae61d532b8f77036.tar.gz
powerpc: Base support for exceptions using HSRR0/1
Pass the register type to the prolog, also provides alternate "HV" version of hardware interrupt (0x500) and adjust LPES accordingly We tag those interrupts by setting bit 0x2 in the trap number Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/kernel/cpu_setup_power7.S')
-rw-r--r--arch/powerpc/kernel/cpu_setup_power7.S3
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/powerpc/kernel/cpu_setup_power7.S b/arch/powerpc/kernel/cpu_setup_power7.S
index f2b317817c4..e801ef15d6d 100644
--- a/arch/powerpc/kernel/cpu_setup_power7.S
+++ b/arch/powerpc/kernel/cpu_setup_power7.S
@@ -52,13 +52,14 @@ __init_hvmode_206:
__init_LPCR:
/* Setup a sane LPCR:
*
- * LPES = 0b11 (SRR0/1 used for 0x500)
+ * LPES = 0b01 (HSRR0/1 used for 0x500)
* PECE = 0b111
*
* Other bits untouched for now
*/
mfspr r3,SPRN_LPCR
ori r3,r3,(LPCR_LPES0|LPCR_LPES1)
+ xori r3,r3, LPCR_LPES0
ori r3,r3,(LPCR_PECE0|LPCR_PECE1|LPCR_PECE2)
mtspr SPRN_LPCR,r3
isync