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authorRahul Sharma <rahul.sharma@samsung.com>2013-07-25 10:37:34 +0530
committerShow Liu <show.liu@linaro.org>2014-04-28 11:37:10 +0800
commit6f03be1975902f9e4ca41a6ec7074426dfa02554 (patch)
treeeb7621dd62765939cd83732c4a1593e324ad6d12
parentc65f02d55054f06b735ad765fcf9486350bdef1e (diff)
downloadlinaro-lsk-6f03be1975902f9e4ca41a6ec7074426dfa02554.tar.gz
clk/exynos5250: add mout_hdmi mux clock for hdmi
hdmi driver needs to change the parent of hdmi clock frequently between pixel clock and hdmiphy clock. hdmiphy is not stable after power on and for a short interval while changing the phy configuration. For this duration pixel clock is used to clock hdmi. This patch is exposing the mux for changing parent. Upstream commit ID: 4a453314883d Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
-rw-r--r--Documentation/devicetree/bindings/clock/exynos5250-clock.txt8
-rw-r--r--drivers/clk/samsung/clk-exynos5250.c5
2 files changed, 12 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
index 1a05761de4b..b3371479c12 100644
--- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
@@ -156,6 +156,14 @@ clock which they consume.
mixer 343
hdmi 344
+
+ [Clock Muxes]
+
+ Clock ID
+ ----------------------------
+ mout_hdmi 1024
+
+
Example 1: An example of a clock controller node is listed below.
clock: clock-controller@0x10010000 {
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index 92afc060673..87cccdf20b2 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -100,6 +100,9 @@ enum exynos5250_clks {
tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7, tzpc8, tzpc9, hdmi_cec, mct,
wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi,
+ /* mux clocks */
+ mout_hdmi = 1024,
+
nr_clks,
};
@@ -231,7 +234,7 @@ struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
MUX(none, "mout_fimd1", mout_group1_p, SRC_DISP1_0, 0, 4),
MUX(none, "mout_mipi1", mout_group1_p, SRC_DISP1_0, 12, 4),
MUX(none, "mout_dp", mout_group1_p, SRC_DISP1_0, 16, 4),
- MUX(none, "mout_hdmi", mout_hdmi_p, SRC_DISP1_0, 20, 1),
+ MUX(mout_hdmi, "mout_hdmi", mout_hdmi_p, SRC_DISP1_0, 20, 1),
MUX(none, "mout_audio0", mout_audio0_p, SRC_MAU, 0, 4),
MUX(none, "mout_mmc0", mout_group1_p, SRC_FSYS, 0, 4),
MUX(none, "mout_mmc1", mout_group1_p, SRC_FSYS, 4, 4),