diff options
| author | Sachin Kamat <sachin.kamat@linaro.org> | 2012-05-03 12:20:04 +0530 |
|---|---|---|
| committer | Tushar Behera <tushar.behera@linaro.org> | 2013-04-16 13:18:08 +0530 |
| commit | be757fb4d05bd6d05338a89516c9a681ac1c8b49 (patch) | |
| tree | 93fe1ce14bbd333e20c62bb28f86d5a0b35a30c3 | |
| parent | 8aaeeb69027335c60cd4bf7cfd3bae66e59a29c9 (diff) | |
video: s3c-fb: Add Overlay Support
Added pixel blending Support.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org>
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
| -rw-r--r-- | drivers/video/s3c-fb.c | 34 | ||||
| -rw-r--r-- | include/video/samsung_fimd.h | 16 |
2 files changed, 48 insertions, 2 deletions
diff --git a/drivers/video/s3c-fb.c b/drivers/video/s3c-fb.c index 62f3ab94ebc..7288c89a032 100644 --- a/drivers/video/s3c-fb.c +++ b/drivers/video/s3c-fb.c @@ -69,6 +69,8 @@ struct s3c_fb; #define VIDOSD_C(win, variant) (OSD_BASE(win, variant) + 0x08) #define VIDOSD_D(win, variant) (OSD_BASE(win, variant) + 0x0C) +#define S3CFB_WIN_SET_PIXEL_ALPHA _IOW('F', 204, __u32) + /** * struct s3c_fb_variant - fb variant information * @is_2443: Set if S3C2443/S3C2416 style hardware. @@ -1018,6 +1020,33 @@ static int s3c_fb_wait_for_vsync(struct s3c_fb *sfb, u32 crtc) return 0; } +int s3cfb_set_alpha_blending(struct s3c_fb *ctrl, int id) +{ + u32 avalue = 0, cfg; + + if (id == 0) { + dev_err(ctrl->dev, "[fb%d] does not support alpha blending\n", + id); + return -EINVAL; + } + + cfg = readl(ctrl->regs + S3C_WINCON(id)); + cfg |= (1 << 0); + writel(cfg, ctrl->regs + S3C_WINCON(id)); + cfg = readl(ctrl->regs + S3C_WINSHMAP); + cfg |= S3C_WINSHMAP_CH_ENABLE(id); + writel(cfg, ctrl->regs + S3C_WINSHMAP); + cfg = readl(ctrl->regs + S3C_WINCON(id)); + cfg &= ~(S3C_WINCON_BLD_MASK | S3C_WINCON_ALPHA_SEL_MASK); + + cfg |= (S3C_WINCON_BLD_PIXEL | S3C_WINCON_ALPHA1_SEL); + writel(cfg, ctrl->regs + S3C_WINCON(id)); + writel(avalue, ctrl->regs + S3C_VIDOSD_C(id)); + + cfg = readl(ctrl->regs + S3C_WINCON(id)); + return 0; +} + static int s3c_fb_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg) { @@ -1035,6 +1064,9 @@ static int s3c_fb_ioctl(struct fb_info *info, unsigned int cmd, ret = s3c_fb_wait_for_vsync(sfb, crtc); break; + case S3CFB_WIN_SET_PIXEL_ALPHA: + ret = s3cfb_set_alpha_blending(sfb, win->index); + break; default: ret = -ENOTTY; } @@ -1294,8 +1326,6 @@ static int s3c_fb_probe_win(struct s3c_fb *sfb, unsigned int win_no, else dev_err(sfb->dev, "failed to allocate fb cmap\n"); - s3c_fb_set_par(fbinfo); - dev_dbg(sfb->dev, "about to register framebuffer\n"); /* run the check_var and set_par on our configuration. */ diff --git a/include/video/samsung_fimd.h b/include/video/samsung_fimd.h index b0393209679..ed5230bfb77 100644 --- a/include/video/samsung_fimd.h +++ b/include/video/samsung_fimd.h @@ -435,6 +435,22 @@ #define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0) #define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0) +/* Blending control registers */ +#define S3C_WINCON_BLD_PIXEL (1 << 6) +#define S3C_WINCON_BLD_MASK (1 << 6) +#define S3C_WINCON_ALPHA1_SEL (1 << 1) +#define S3C_WINCON_ALPHA_SEL_MASK (1 << 1) +#define S3C_WINCON(x) (0x0020 + (x * 0x04)) +#define S3C_VIDOSD_C(x) (0x0048 + (x * 0x10)) +#define S3C_WINSHMAP (0x0034) +#define S3C_WINSHMAP_CH_ENABLE(x) (1 << (x)) +#define S3C_WINCON_BLD_PLANE (0 << 6) +#define S3C_WINCON_ALPHA0_SEL (0 << 1) +#define S3C_VIDOSD_ALPHA0_SHIFT (12) +#define S3C_VIDOSD_ALPHA1_SHIFT (0) + +#define S3C_FB_MAX_WIN (5) /* number of hardware windows available. */ + /* Notes on per-window bpp settings * * Value Win0 Win1 Win2 Win3 Win 4 |