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authorVivek Mahajan <vivek.mahajan@freescale.com>2009-12-08 13:01:15 +0530
committerKumar Gala <galak@kernel.crashing.org>2011-03-15 14:09:06 -0500
commita2b31dd93000136d82f675952e322ec18973a348 (patch)
tree6fcc4c42c9386d892a7f0a5559413fbf54691372
parent52052875549f6ecd6520279ee0f94e4721d80077 (diff)
downloadlinaro-lsk-a2b31dd93000136d82f675952e322ec18973a348.tar.gz
powerpc/fsl: 85xx: document cache sram bindings
Adds binding documentation for cache sram for the PQ3 and some QorIQ based platforms. Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
-rw-r--r--Documentation/devicetree/bindings/powerpc/fsl/cache_sram.txt20
1 files changed, 20 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cache_sram.txt b/Documentation/devicetree/bindings/powerpc/fsl/cache_sram.txt
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+* Freescale PQ3 and QorIQ based Cache SRAM
+
+Freescale's mpc85xx and some QorIQ platforms provide an
+option of configuring a part of (or full) cache memory
+as SRAM. This cache SRAM representation in the device
+tree should be done as under:-
+
+Required properties:
+
+- compatible : should be "fsl,p2020-cache-sram"
+- fsl,cache-sram-ctlr-handle : points to the L2 controller
+- reg : offset and length of the cache-sram.
+
+Example:
+
+cache-sram@fff00000 {
+ fsl,cache-sram-ctlr-handle = <&L2>;
+ reg = <0 0xfff00000 0 0x10000>;
+ compatible = "fsl,p2020-cache-sram";
+};