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/*
* Copyright (C) ST-Ericsson SA 2010
*
* Author: Hanumath Prasad <hanumath.prasad@stericsson.com>
* License terms: GNU General Public License (GPL) version 2
*/
#include <linux/kernel.h>
#include <linux/gpio.h>
#include <linux/amba/bus.h>
#include <linux/amba/mmci.h>
#include <linux/mmc/host.h>
#include <linux/platform_device.h>
#include <asm/mach-types.h>
#include <plat/pincfg.h>
#include <plat/ste_dma40.h>
#include <mach/devices.h>
#include <mach/hardware.h>
#include "devices-db8500.h"
#include "board-mop500.h"
#include <mach/ste-dma40-db8500.h>
#include "../drivers/mmc/host/mmci.h" /* to avoid MCI_ST* redefinition */
/*
* SDI 0 (MicroSD slot)
*/
static u32 mop500_sdi0_vdd_handler(struct device *dev, unsigned int vdd,
unsigned char power_mode)
{
int gpio;
if (!machine_is_snowball())
gpio = GPIO_SDMMC_EN;
else
gpio = SNOWBALL_SDMMC_EN_GPIO;
if (power_mode == MMC_POWER_UP)
gpio_set_value_cansleep(gpio, 1);
else if (power_mode == MMC_POWER_OFF)
gpio_set_value_cansleep(gpio, 0);
return MCI_ST_FBCLKEN | MCI_ST_CMDDIREN | MCI_ST_DATA0DIREN |
MCI_ST_DATA2DIREN;
}
#ifdef CONFIG_STE_DMA40
struct stedma40_chan_cfg mop500_sdi0_dma_cfg_rx = {
.mode = STEDMA40_MODE_LOGICAL,
.dir = STEDMA40_PERIPH_TO_MEM,
.src_dev_type = DB8500_DMA_DEV29_SD_MM0_RX,
.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
.src_info.data_width = STEDMA40_WORD_WIDTH,
.dst_info.data_width = STEDMA40_WORD_WIDTH,
};
static struct stedma40_chan_cfg mop500_sdi0_dma_cfg_tx = {
.mode = STEDMA40_MODE_LOGICAL,
.dir = STEDMA40_MEM_TO_PERIPH,
.src_dev_type = STEDMA40_DEV_SRC_MEMORY,
.dst_dev_type = DB8500_DMA_DEV29_SD_MM0_TX,
.src_info.data_width = STEDMA40_WORD_WIDTH,
.dst_info.data_width = STEDMA40_WORD_WIDTH,
};
#endif
static struct mmci_platform_data mop500_sdi0_data = {
.vdd_handler = mop500_sdi0_vdd_handler,
.ocr_mask = MMC_VDD_29_30,
.f_max = 50000000,
.capabilities = MMC_CAP_4_BIT_DATA |
MMC_CAP_SD_HIGHSPEED |
MMC_CAP_MMC_HIGHSPEED,
.gpio_wp = -1,
#ifdef CONFIG_STE_DMA40
.dma_filter = stedma40_filter,
.dma_rx_param = &mop500_sdi0_dma_cfg_rx,
.dma_tx_param = &mop500_sdi0_dma_cfg_tx,
#endif
};
#if defined(CONFIG_CW1200) || defined(CONFIG_CW1200_MODULE)
/*
* SDI1 (SDIO WLAN)
*/
#ifdef CONFIG_STE_DMA40
static struct stedma40_chan_cfg sdi1_dma_cfg_rx = {
.dir = STEDMA40_PERIPH_TO_MEM,
.src_dev_type = DB8500_DMA_DEV32_SD_MM1_RX,
.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
.src_info.data_width = STEDMA40_WORD_WIDTH,
.dst_info.data_width = STEDMA40_WORD_WIDTH,
};
static struct stedma40_chan_cfg sdi1_dma_cfg_tx = {
.dir = STEDMA40_MEM_TO_PERIPH,
.src_dev_type = STEDMA40_DEV_SRC_MEMORY,
.dst_dev_type = DB8500_DMA_DEV32_SD_MM1_TX,
.src_info.data_width = STEDMA40_WORD_WIDTH,
.dst_info.data_width = STEDMA40_WORD_WIDTH,
};
#endif
/*
* TODO 1: SDIO power management not fully supported.
*/
static struct mmci_platform_data mop500_sdi1_data = {
.ocr_mask = MMC_VDD_29_30,
.f_max = 15000000,
.capabilities = MMC_CAP_4_BIT_DATA |
MMC_CAP_SDIO_IRQ |
MMC_CAP_BROKEN_SDIO_CMD53,
.gpio_cd = -1,
.gpio_wp = -1,
#ifdef CONFIG_STE_DMA40
.dma_filter = stedma40_filter,
.dma_rx_param = &sdi1_dma_cfg_rx,
.dma_tx_param = &sdi1_dma_cfg_tx,
#endif
};
#endif /* CONFIG_CW1200 */
/* GPIO pins used by the sdi0 level shifter */
static int sdi0_en = -1;
static int sdi0_vsel = -1;
static void sdi0_sdi1_configure(void)
{
int ret;
u32 periphid = 0;
/* v2 has a new version of this block that need to be forced */
if (cpu_is_u8500v2())
periphid = 0x10480180;
ret = gpio_request(sdi0_en, "level shifter enable");
if (!ret)
ret = gpio_request(sdi0_vsel,
"level shifter 1v8-3v select");
if (ret) {
pr_warning("unable to config sdi0 gpios for level shifter.\n");
return;
}
/* Select the default 2.9V and enable level shifter */
gpio_direction_output(sdi0_vsel, 0);
gpio_direction_output(sdi0_en, 1);
db8500_add_sdi0(&mop500_sdi0_data, periphid);
#if defined(CONFIG_CW1200) || defined(CONFIG_CW1200_MODULE)
/* SDIO WLAN must be the last SDI device initialized
* to wait CW1200 detection without blocking others SDI init */
db8500_add_sdi1(&mop500_sdi1_data, periphid);
#endif
}
void mop500_sdi_tc35892_init(void)
{
mop500_sdi0_data.gpio_cd = GPIO_SDMMC_CD;
sdi0_en = GPIO_SDMMC_EN;
sdi0_vsel = GPIO_SDMMC_1V8_3V_SEL;
sdi0_sdi1_configure();
}
/*
* SDI 2 (POP eMMC, not on DB8500ed)
*/
#ifdef CONFIG_STE_DMA40
struct stedma40_chan_cfg mop500_sdi2_dma_cfg_rx = {
.mode = STEDMA40_MODE_LOGICAL,
.dir = STEDMA40_PERIPH_TO_MEM,
.src_dev_type = DB8500_DMA_DEV28_SD_MM2_RX,
.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
.src_info.data_width = STEDMA40_WORD_WIDTH,
.dst_info.data_width = STEDMA40_WORD_WIDTH,
};
static struct stedma40_chan_cfg mop500_sdi2_dma_cfg_tx = {
.mode = STEDMA40_MODE_LOGICAL,
.dir = STEDMA40_MEM_TO_PERIPH,
.src_dev_type = STEDMA40_DEV_SRC_MEMORY,
.dst_dev_type = DB8500_DMA_DEV28_SD_MM2_TX,
.src_info.data_width = STEDMA40_WORD_WIDTH,
.dst_info.data_width = STEDMA40_WORD_WIDTH,
};
#endif
static struct mmci_platform_data mop500_sdi2_data = {
.ocr_mask = MMC_VDD_165_195,
.f_max = 50000000,
.capabilities = MMC_CAP_4_BIT_DATA |
MMC_CAP_8_BIT_DATA |
MMC_CAP_MMC_HIGHSPEED,
.gpio_cd = -1,
.gpio_wp = -1,
#ifdef CONFIG_STE_DMA40
.dma_filter = stedma40_filter,
.dma_rx_param = &mop500_sdi2_dma_cfg_rx,
.dma_tx_param = &mop500_sdi2_dma_cfg_tx,
#endif
};
/*
* SDI 4 (on-board eMMC)
*/
#ifdef CONFIG_STE_DMA40
struct stedma40_chan_cfg mop500_sdi4_dma_cfg_rx = {
.mode = STEDMA40_MODE_LOGICAL,
.dir = STEDMA40_PERIPH_TO_MEM,
.src_dev_type = DB8500_DMA_DEV42_SD_MM4_RX,
.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
.src_info.data_width = STEDMA40_WORD_WIDTH,
.dst_info.data_width = STEDMA40_WORD_WIDTH,
};
static struct stedma40_chan_cfg mop500_sdi4_dma_cfg_tx = {
.mode = STEDMA40_MODE_LOGICAL,
.dir = STEDMA40_MEM_TO_PERIPH,
.src_dev_type = STEDMA40_DEV_SRC_MEMORY,
.dst_dev_type = DB8500_DMA_DEV42_SD_MM4_TX,
.src_info.data_width = STEDMA40_WORD_WIDTH,
.dst_info.data_width = STEDMA40_WORD_WIDTH,
};
#endif
static struct mmci_platform_data mop500_sdi4_data = {
.ocr_mask = MMC_VDD_29_30,
.f_max = 50000000,
.capabilities = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA |
MMC_CAP_MMC_HIGHSPEED,
.gpio_cd = -1,
.gpio_wp = -1,
#ifdef CONFIG_STE_DMA40
.dma_filter = stedma40_filter,
.dma_rx_param = &mop500_sdi4_dma_cfg_rx,
.dma_tx_param = &mop500_sdi4_dma_cfg_tx,
#endif
};
void __init mop500_sdi_init(void)
{
u32 periphid = 0;
/* v2 has a new version of this block that need to be forced */
if (cpu_is_u8500v2())
periphid = 0x10480180;
/* sdi2 on snowball is in ATL_B mode for FSMC (LAN) */
if (!machine_is_snowball())
db8500_add_sdi2(&mop500_sdi2_data, periphid);
/* On-board eMMC */
db8500_add_sdi4(&mop500_sdi4_data, periphid);
if (machine_is_hrefv60() || machine_is_snowball()) {
if (machine_is_hrefv60()) {
mop500_sdi0_data.gpio_cd = HREFV60_SDMMC_CD_GPIO;
sdi0_en = HREFV60_SDMMC_EN_GPIO;
sdi0_vsel = HREFV60_SDMMC_1V8_3V_GPIO;
} else if (machine_is_snowball()) {
mop500_sdi0_data.capabilities = (MMC_CAP_4_BIT_DATA |
MMC_CAP_MMC_HIGHSPEED);
mop500_sdi0_data.gpio_cd = SNOWBALL_SDMMC_CD_GPIO;
mop500_sdi0_data.cd_invert = true;
sdi0_en = SNOWBALL_SDMMC_EN_GPIO;
sdi0_vsel = SNOWBALL_SDMMC_1V8_3V_GPIO;
}
sdi0_sdi1_configure();
}
/*
* On boards with the TC35892 GPIO expander, sdi0 & sdi1 will finally
* be added when the TC35892 initializes and calls
* mop500_sdi_tc35892_init() above.
*/
}
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