From fe56cf45f951b3810313584605c1d8a4f20b33a4 Mon Sep 17 00:00:00 2001 From: Jesse Barnes Date: Mon, 23 Feb 2009 15:36:41 -0800 Subject: drm: Fix ordering of bit fields in EDID structure leading huge vsync values. Signed-off-by: Jesse Barnes Reviewed-by: Eric Anholt Signed-off-by: Dave Airlie --- include/drm/drm_edid.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h index c707c15f516..ff8d27af478 100644 --- a/include/drm/drm_edid.h +++ b/include/drm/drm_edid.h @@ -58,10 +58,10 @@ struct detailed_pixel_timing { u8 hsync_pulse_width_lo; u8 vsync_pulse_width_lo:4; u8 vsync_offset_lo:4; - u8 hsync_pulse_width_hi:2; - u8 hsync_offset_hi:2; u8 vsync_pulse_width_hi:2; u8 vsync_offset_hi:2; + u8 hsync_pulse_width_hi:2; + u8 hsync_offset_hi:2; u8 width_mm_lo; u8 height_mm_lo; u8 height_mm_hi:4; -- cgit v1.2.3