diff options
| author | Robert Richter <robert.richter@amd.com> | 2009-05-25 18:11:52 +0200 |
|---|---|---|
| committer | Robert Richter <robert.richter@amd.com> | 2009-06-11 19:42:15 +0200 |
| commit | dea3766ca052a4f572b16a23a322553c064d75af (patch) | |
| tree | 64d2a14629b8bfdfeccce1d722080ffa332cfc4e /arch/x86/oprofile/op_x86_model.h | |
| parent | 42399adb239d4f1413899cc618ecf640779e79df (diff) | |
x86/oprofile: replace CTRL_SET_*ACTIVE macros
The patch replaces all CTRL_SET_*ACTIVE macros. 64 bit MSR functions
and 64 bit counter values are used now. The code uses bit masks from
<asm/intel_arch_perfmon.h>.
Signed-off-by: Robert Richter <robert.richter@amd.com>
Diffstat (limited to 'arch/x86/oprofile/op_x86_model.h')
| -rw-r--r-- | arch/x86/oprofile/op_x86_model.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/arch/x86/oprofile/op_x86_model.h b/arch/x86/oprofile/op_x86_model.h index 3220d4ce632..1c4577795a9 100644 --- a/arch/x86/oprofile/op_x86_model.h +++ b/arch/x86/oprofile/op_x86_model.h @@ -17,8 +17,6 @@ #define CTR_IS_RESERVED(msrs, c) ((msrs)->counters[(c)].addr ? 1 : 0) #define CTRL_IS_RESERVED(msrs, c) ((msrs)->controls[(c)].addr ? 1 : 0) -#define CTRL_SET_ACTIVE(val) ((val) |= ARCH_PERFMON_EVENTSEL0_ENABLE) -#define CTRL_SET_INACTIVE(val) ((val) &= ~ARCH_PERFMON_EVENTSEL0_ENABLE) struct op_saved_msr { unsigned int high; |