ARM: u5500: PRCMU reset API

Added API for rebooting the board and for getting the last reboot code.

ST-Ericsson ID: 341245
ST-Ericsson Linux next: NA
ST-Ericsson FOSS-OUT ID: Trivial

Change-Id: I0dbc2f70727a6cc52a3e9522ad1c3dcf8525308c
Signed-off-by: Pawel Szyszuk <pawel.szyszuk@stericsson.com>
Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/25494
Reviewed-by: QATOOLS
Reviewed-by: Vijaya Kumar K-1 <vijay.kilari@stericsson.com>
Reviewed-by: QATEST
Reviewed-by: Srinidhi KASAGAR <srinidhi.kasagar@stericsson.com>

A mer

7 files changed, 63 insertions, 27 deletions

diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index a9b01188dc4..f28f7858040 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -64,13 +64,8 @@ void __init ux500_init_irq(void)
 	 * Init clocks here so that they are available for system timer
 	 * initialization.
 	 */
-	if (cpu_is_u5500())
-		db5500_prcmu_early_init();
-	if (cpu_is_u8500()) {
-		prcmu_early_init();
-		arm_pm_restart = ux500_restart;
-	}
-
+	prcmu_early_init();
+	arm_pm_restart = ux500_restart;
 	clk_init();
 }
 
diff --git a/arch/arm/mach-ux500/include/mach/prcmu-db5500.h b/arch/arm/mach-ux500/include/mach/prcmu-db5500.h
index 97f0f5e7e68..3f31bef433a 100644
--- a/arch/arm/mach-ux500/include/mach/prcmu-db5500.h
+++ b/arch/arm/mach-ux500/include/mach/prcmu-db5500.h
@@ -25,9 +25,7 @@ int prcmu_resetout(u8 resoutn, u8 state);
 int db5500_prcmu_set_power_state(u8 state, bool keep_ulp_clk,
 	bool keep_ap_pll);
 int db5500_prcmu_config_esram0_deep_sleep(u8 state);
-
-static inline void db5500_prcmu_system_reset(u16 reset_code) {}
-
+void db5500_prcmu_system_reset(u16 reset_code);
 u16 db5500_prcmu_get_reset_code(void);
 bool db5500_prcmu_is_ac_wake_requested(void);
 int db5500_prcmu_set_arm_opp(u8 opp);
@@ -35,9 +33,7 @@ int db5500_prcmu_get_arm_opp(void);
 
 #else /* !CONFIG_UX500_SOC_DB5500 */
 
-static inline void db5500_prcmu_early_init(void)
-{
-}
+static inline void db5500_prcmu_early_init(void) {}
 
 static inline int db5500_prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
 {
@@ -95,6 +91,8 @@ static inline int db5500_prcmu_set_power_state(u8 state, bool keep_ulp_clk,
 	return 0;
 }
 
+static inline void db5500_prcmu_system_reset(u16 reset_code) {}
+
 static inline u16 db5500_prcmu_get_reset_code(void)
 {
 	return 0;
diff --git a/arch/arm/mach-ux500/include/mach/prcmu-db8500.h b/arch/arm/mach-ux500/include/mach/prcmu-db8500.h
index 4545fb9b2cb..458ae2aaa44 100644
--- a/arch/arm/mach-ux500/include/mach/prcmu-db8500.h
+++ b/arch/arm/mach-ux500/include/mach/prcmu-db8500.h
@@ -157,6 +157,8 @@ enum ap_pwrst {
 
 #ifdef CONFIG_UX500_SOC_DB8500
 
+void db8500_prcmu_early_init(void);
+
 bool prcmu_is_u8400(void);
 
 int prcmu_request_ape_opp_100_voltage(bool enable);
@@ -211,6 +213,8 @@ int db8500_prcmu_get_arm_opp(void);
 
 #else /* !CONFIG_UX500_SOC_DB8500 */
 
+static inline void db8500_prcmu_early_init(void) {}
+
 static inline bool prcmu_is_u8400(void)
 {
 	return false;
@@ -339,6 +343,11 @@ static inline void db8500_prcmu_config_abb_event_readout(u32 abb_events) {}
 
 static inline void db8500_prcmu_get_abb_event_buffer(void __iomem **buf) {}
 
+static inline u16 db8500_prcmu_get_reset_code(void)
+{
+	return 0;
+}
+
 static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
 {
 	return 0;
diff --git a/arch/arm/mach-ux500/include/mach/prcmu.h b/arch/arm/mach-ux500/include/mach/prcmu.h
index 802daf8f060..e3ee37fa872 100644
--- a/arch/arm/mach-ux500/include/mach/prcmu.h
+++ b/arch/arm/mach-ux500/include/mach/prcmu.h
@@ -227,6 +227,14 @@ enum ddr_pwrst {
 
 #if defined(CONFIG_UX500_SOC_DB8500) || defined(CONFIG_UX500_SOC_DB5500)
 
+static inline void __init prcmu_early_init(void)
+{
+	if (machine_is_u5500())
+		return db5500_prcmu_early_init();
+	else
+		return db8500_prcmu_early_init();
+}
+
 static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
 		bool keep_ap_pll)
 {
@@ -317,7 +325,13 @@ static inline void prcmu_system_reset(u16 reset_code)
 		return db8500_prcmu_system_reset(reset_code);
 }
 
-u16 prcmu_get_reset_code(void);
+static inline u16 prcmu_get_reset_code(void)
+{
+	if (machine_is_u5500())
+		return db5500_prcmu_get_reset_code();
+	else
+		return db8500_prcmu_get_reset_code();
+}
 
 void prcmu_ac_wake_req(void);
 void prcmu_ac_sleep_req(void);
@@ -363,6 +377,8 @@ static inline int prcmu_config_esram0_deep_sleep(u8 state)
 }
 #else
 
+static inline void __init prcmu_early_init(void) {}
+
 static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
 	bool keep_ap_pll)
 {
@@ -475,14 +491,4 @@ static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
 
 #endif
 
-#if defined(CONFIG_UX500_SOC_DB8500)
-
-void __init prcmu_early_init(void);
-
-#else
-
-static inline void __init prcmu_early_init(void) {}
-
-#endif
-
 #endif /* __MACH_PRCMU_H */
diff --git a/arch/arm/mach-ux500/prcmu-db5500.c b/arch/arm/mach-ux500/prcmu-db5500.c
index a2c1386ed9a..ce214be2c3a 100644
--- a/arch/arm/mach-ux500/prcmu-db5500.c
+++ b/arch/arm/mach-ux500/prcmu-db5500.c
@@ -28,6 +28,8 @@
 
 #include "prcmu-regs-db5500.h"
 
+#define PRCM_SW_RST_REASON (tcdm_base + 0xFF8) /* 2 bytes */
+
 #define _PRCM_MB_HEADER (tcdm_base + 0xFE8)
 #define PRCM_REQ_MB0_HEADER (_PRCM_MB_HEADER + 0x0)
 #define PRCM_REQ_MB1_HEADER (_PRCM_MB_HEADER + 0x1)
@@ -959,6 +961,29 @@ int db5500_prcmu_set_display_clocks(void)
 	return 0;
 }
 
+/**
+ * db5500_prcmu_system_reset - System reset
+ *
+ * Saves the reset reason code and then sets the APE_SOFTRST register which
+ * fires an interrupt to fw
+ */
+void db5500_prcmu_system_reset(u16 reset_code)
+{
+	writew(reset_code, PRCM_SW_RST_REASON);
+	writel(1, (_PRCMU_BASE + PRCM_APE_SOFTRST));
+}
+
+/**
+ * db5500_prcmu_get_reset_code - Retrieve SW reset reason code
+ *
+ * Retrieves the reset reason code stored by prcmu_system_reset() before
+ * last restart.
+ */
+u16 db5500_prcmu_get_reset_code(void)
+{
+	return readw(PRCM_SW_RST_REASON);
+}
+
 static void ack_dbb_wakeup(void)
 {
 	unsigned long flags;
diff --git a/arch/arm/mach-ux500/prcmu-db8500.c b/arch/arm/mach-ux500/prcmu-db8500.c
index 11a35a15a81..be4942cf6e7 100644
--- a/arch/arm/mach-ux500/prcmu-db8500.c
+++ b/arch/arm/mach-ux500/prcmu-db8500.c
@@ -1852,12 +1852,12 @@ void db8500_prcmu_system_reset(u16 reset_code)
 }
 
 /**
- * prcmu_get_reset_code - Retrieve SW reset reason code
+ * db8500_prcmu_get_reset_code - Retrieve SW reset reason code
  *
  * Retrieves the reset reason code stored by prcmu_system_reset() before
  * last restart.
  */
-u16 prcmu_get_reset_code(void)
+u16 db8500_prcmu_get_reset_code(void)
 {
 	return readw(tcdm_base + PRCM_SW_RST_REASON);
 }
@@ -2112,7 +2112,7 @@ static struct irq_chip prcmu_irq_chip = {
 	.irq_unmask	= prcmu_irq_unmask,
 };
 
-void __init prcmu_early_init(void)
+void __init db8500_prcmu_early_init(void)
 {
 	unsigned int i;
 
diff --git a/arch/arm/mach-ux500/prcmu-regs-db5500.h b/arch/arm/mach-ux500/prcmu-regs-db5500.h
index 331609a918c..e9c9f8e2b77 100644
--- a/arch/arm/mach-ux500/prcmu-regs-db5500.h
+++ b/arch/arm/mach-ux500/prcmu-regs-db5500.h
@@ -60,6 +60,9 @@
 #define PRCM_MBOX_CPU_VAL 0x0FC
 #define PRCM_MBOX_CPU_SET 0x100
 
+/* System reset register */
+#define PRCM_APE_SOFTRST 0x228
+
 /* PRCMU clock/PLL/reset registers */
 #define PRCM_PLLDSI_FREQ	0x500
 #define PRCM_PLLDSI_ENABLE	0x504