ARM: u8500: context: Remove v1 support

ST-Ericsson Linux next: ER338824
ST-Ericsson ID: 342987
ST-Ericsson FOSS-OUT ID: Trivial

Change-Id: I031e785a559cfa1191992ba24ddacb21614a51ae
Signed-off-by: Jonas Aaberg <jonas.aberg@stericsson.com>
Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/24281
Reviewed-by: QATEST
Reviewed-by: Rickard ANDERSSON <rickard.andersson@stericsson.com>

2 files changed, 62 insertions, 96 deletions

diff --git a/arch/arm/mach-ux500/pm/context-db8500.c b/arch/arm/mach-ux500/pm/context-db8500.c
index 6ed059619b0..ad21163917d 100644
--- a/arch/arm/mach-ux500/pm/context-db8500.c
+++ b/arch/arm/mach-ux500/pm/context-db8500.c
@@ -48,15 +48,9 @@
 #define NODE_HIBW2_DDR_IN_0_PRIORITY		0xC00
 #define NODE_HIBW2_DDR_IN_1_PRIORITY		0xC04
 #define NODE_HIBW2_DDR_IN_2_PRIORITY		0xC08
-/* only in v1 */
-#define NODE_HIBW2_DDR_IN_3_PRIORITY		0xC0C
-/* address update between v1 and v2 */
-#define NODE_HIBW2_DDR_IN_0_LIMIT_V1		0xC30
-#define NODE_HIBW2_DDR_IN_1_LIMIT_V1		0xC34
 
 #define NODE_HIBW2_DDR_IN_0_LIMIT		0xC24
 #define NODE_HIBW2_DDR_IN_1_LIMIT		0xC28
-/* only in v2 */
 #define NODE_HIBW2_DDR_IN_2_LIMIT		0xC2C
 #define NODE_HIBW2_DDR_OUT_0_PRIORITY		0xC30
 
@@ -217,46 +211,35 @@ void u8500_context_save_icn(void)
 	context_icn.hibw2_ddr_in_prio[2] =
 		readl_relaxed(b + NODE_HIBW2_DDR_IN_2_PRIORITY);
 
-	if (cpu_is_u8500v1()) {
-		context_icn.hibw2_ddr_in_prio[3] =
-			readl_relaxed(b + NODE_HIBW2_DDR_IN_3_PRIORITY);
-
-		context_icn.hibw2_ddr_in_limit[0] =
-			readl_relaxed(b + NODE_HIBW2_DDR_IN_0_LIMIT_V1);
-		context_icn.hibw2_ddr_in_limit[1] =
-			readl_relaxed(b + NODE_HIBW2_DDR_IN_1_LIMIT_V1);
-	}
-
-	if (cpu_is_u8500v2()) {
-		context_icn.hibw2_ddr_in_limit[0] =
-			readl_relaxed(b + NODE_HIBW2_DDR_IN_0_LIMIT);
-		context_icn.hibw2_ddr_in_limit[1] =
-			readl_relaxed(b + NODE_HIBW2_DDR_IN_1_LIMIT);
-
-		context_icn.hibw2_ddr_in_limit[2] =
-			readl_relaxed(b + NODE_HIBW2_DDR_IN_2_LIMIT);
-
-		context_icn.hibw2_ddr_out_prio =
-			readl_relaxed(b + NODE_HIBW2_DDR_OUT_0_PRIORITY);
-
-		context_icn.esram0_in_prio[0] =
-			readl_relaxed(b + NODE_ESRAM0_IN_0_PRIORITY);
-		context_icn.esram0_in_prio[1] =
-			readl_relaxed(b + NODE_ESRAM0_IN_1_PRIORITY);
-		context_icn.esram0_in_prio[2] =
-			readl_relaxed(b + NODE_ESRAM0_IN_2_PRIORITY);
-		context_icn.esram0_in_prio[3] =
-			readl_relaxed(b + NODE_ESRAM0_IN_3_PRIORITY);
-
-		context_icn.esram0_in_lim[0] =
-			readl_relaxed(b + NODE_ESRAM0_IN_0_LIMIT);
-		context_icn.esram0_in_lim[1] =
-			readl_relaxed(b + NODE_ESRAM0_IN_1_LIMIT);
-		context_icn.esram0_in_lim[2] =
-			readl_relaxed(b + NODE_ESRAM0_IN_2_LIMIT);
-		context_icn.esram0_in_lim[3] =
-			readl_relaxed(b + NODE_ESRAM0_IN_3_LIMIT);
-	}
+	context_icn.hibw2_ddr_in_limit[0] =
+		readl_relaxed(b + NODE_HIBW2_DDR_IN_0_LIMIT);
+	context_icn.hibw2_ddr_in_limit[1] =
+		readl_relaxed(b + NODE_HIBW2_DDR_IN_1_LIMIT);
+
+	context_icn.hibw2_ddr_in_limit[2] =
+		readl_relaxed(b + NODE_HIBW2_DDR_IN_2_LIMIT);
+
+	context_icn.hibw2_ddr_out_prio =
+		readl_relaxed(b + NODE_HIBW2_DDR_OUT_0_PRIORITY);
+
+	context_icn.esram0_in_prio[0] =
+		readl_relaxed(b + NODE_ESRAM0_IN_0_PRIORITY);
+	context_icn.esram0_in_prio[1] =
+		readl_relaxed(b + NODE_ESRAM0_IN_1_PRIORITY);
+	context_icn.esram0_in_prio[2] =
+		readl_relaxed(b + NODE_ESRAM0_IN_2_PRIORITY);
+	context_icn.esram0_in_prio[3] =
+		readl_relaxed(b + NODE_ESRAM0_IN_3_PRIORITY);
+
+	context_icn.esram0_in_lim[0] =
+		readl_relaxed(b + NODE_ESRAM0_IN_0_LIMIT);
+	context_icn.esram0_in_lim[1] =
+		readl_relaxed(b + NODE_ESRAM0_IN_1_LIMIT);
+	context_icn.esram0_in_lim[2] =
+		readl_relaxed(b + NODE_ESRAM0_IN_2_LIMIT);
+	context_icn.esram0_in_lim[3] =
+		readl_relaxed(b + NODE_ESRAM0_IN_3_LIMIT);
+
 	context_icn.esram12_in_prio[0] =
 		readl_relaxed(b + NODE_ESRAM1_2_IN_0_PRIORITY);
 	context_icn.esram12_in_prio[1] =
@@ -388,42 +371,32 @@ void u8500_context_restore_icn(void)
 		       b + NODE_HIBW2_DDR_IN_1_PRIORITY);
 	writel_relaxed(context_icn.hibw2_ddr_in_prio[2],
 		       b + NODE_HIBW2_DDR_IN_2_PRIORITY);
-	if (cpu_is_u8500v1()) {
-		writel_relaxed(context_icn.hibw2_ddr_in_prio[3],
-			       b + NODE_HIBW2_DDR_IN_3_PRIORITY);
-		writel_relaxed(context_icn.hibw2_ddr_in_limit[0],
-			       b + NODE_HIBW2_DDR_IN_0_LIMIT_V1);
-		writel_relaxed(context_icn.hibw2_ddr_in_limit[1],
-			       b + NODE_HIBW2_DDR_IN_1_LIMIT_V1);
-	}
-	if (cpu_is_u8500v2()) {
-		writel_relaxed(context_icn.hibw2_ddr_in_limit[0],
-			       b + NODE_HIBW2_DDR_IN_0_LIMIT);
-		writel_relaxed(context_icn.hibw2_ddr_in_limit[1],
-			       b + NODE_HIBW2_DDR_IN_1_LIMIT);
-		writel_relaxed(context_icn.hibw2_ddr_in_limit[2],
-			       b + NODE_HIBW2_DDR_IN_2_LIMIT);
-		writel_relaxed(context_icn.hibw2_ddr_out_prio,
-			       b + NODE_HIBW2_DDR_OUT_0_PRIORITY);
-
-		writel_relaxed(context_icn.esram0_in_prio[0],
-			       b + NODE_ESRAM0_IN_0_PRIORITY);
-		writel_relaxed(context_icn.esram0_in_prio[1],
-			       b + NODE_ESRAM0_IN_1_PRIORITY);
-		writel_relaxed(context_icn.esram0_in_prio[2],
-			       b + NODE_ESRAM0_IN_2_PRIORITY);
-		writel_relaxed(context_icn.esram0_in_prio[3],
-			       b + NODE_ESRAM0_IN_3_PRIORITY);
-
-		writel_relaxed(context_icn.esram0_in_lim[0],
-			       b + NODE_ESRAM0_IN_0_LIMIT);
-		writel_relaxed(context_icn.esram0_in_lim[1],
-			       b + NODE_ESRAM0_IN_1_LIMIT);
-		writel_relaxed(context_icn.esram0_in_lim[2],
-			       b + NODE_ESRAM0_IN_2_LIMIT);
-		writel_relaxed(context_icn.esram0_in_lim[3],
-			       b + NODE_ESRAM0_IN_3_LIMIT);
-	}
+	writel_relaxed(context_icn.hibw2_ddr_in_limit[0],
+		       b + NODE_HIBW2_DDR_IN_0_LIMIT);
+	writel_relaxed(context_icn.hibw2_ddr_in_limit[1],
+		       b + NODE_HIBW2_DDR_IN_1_LIMIT);
+	writel_relaxed(context_icn.hibw2_ddr_in_limit[2],
+		       b + NODE_HIBW2_DDR_IN_2_LIMIT);
+	writel_relaxed(context_icn.hibw2_ddr_out_prio,
+		       b + NODE_HIBW2_DDR_OUT_0_PRIORITY);
+
+	writel_relaxed(context_icn.esram0_in_prio[0],
+		       b + NODE_ESRAM0_IN_0_PRIORITY);
+	writel_relaxed(context_icn.esram0_in_prio[1],
+		       b + NODE_ESRAM0_IN_1_PRIORITY);
+	writel_relaxed(context_icn.esram0_in_prio[2],
+		       b + NODE_ESRAM0_IN_2_PRIORITY);
+	writel_relaxed(context_icn.esram0_in_prio[3],
+		       b + NODE_ESRAM0_IN_3_PRIORITY);
+
+	writel_relaxed(context_icn.esram0_in_lim[0],
+		       b + NODE_ESRAM0_IN_0_LIMIT);
+	writel_relaxed(context_icn.esram0_in_lim[1],
+		       b + NODE_ESRAM0_IN_1_LIMIT);
+	writel_relaxed(context_icn.esram0_in_lim[2],
+		       b + NODE_ESRAM0_IN_2_LIMIT);
+	writel_relaxed(context_icn.esram0_in_lim[3],
+		       b + NODE_ESRAM0_IN_3_LIMIT);
 
 	writel_relaxed(context_icn.esram12_in_prio[0],
 		       b + NODE_ESRAM1_2_IN_0_PRIORITY);
diff --git a/arch/arm/mach-ux500/pm/context.c b/arch/arm/mach-ux500/pm/context.c
index ccabc5375ba..777be3bbebc 100644
--- a/arch/arm/mach-ux500/pm/context.c
+++ b/arch/arm/mach-ux500/pm/context.c
@@ -852,20 +852,6 @@ static int __init context_init(void)
 	writel(virt_to_phys(ux500_backup_ptr),
 	       IO_ADDRESS(U8500_EXT_RAM_LOC_BACKUPRAM_ADDR));
 
-	/* Give logical address to backup RAM. For both CPUs */
-	if (cpu_is_u8500v20_or_later()) {
-		writel(IO_ADDRESS(U8500_PUBLIC_BOOT_ROM_BASE),
-		       IO_ADDRESS(U8500_CPU0_BACKUPRAM_ADDR_PUBLIC_BOOT_ROM_LOG_ADDR));
-
-		writel(IO_ADDRESS(U8500_PUBLIC_BOOT_ROM_BASE),
-		       IO_ADDRESS(U8500_CPU1_BACKUPRAM_ADDR_PUBLIC_BOOT_ROM_LOG_ADDR));
-	} else {
-		writel(IO_ADDRESS(U8500_BACKUPRAM0_BASE),
-		       IO_ADDRESS(U8500_CPU0_BACKUPRAM_ADDR_BACKUPRAM_LOG_ADDR));
-
-		writel(IO_ADDRESS(U8500_BACKUPRAM0_BASE),
-		       IO_ADDRESS(U8500_CPU1_BACKUPRAM_ADDR_BACKUPRAM_LOG_ADDR));
-	}
 
 	if (cpu_is_u5500()) {
 		context_tpiu.base = ioremap(U5500_TPIU_BASE, SZ_4K);
@@ -881,6 +867,13 @@ static int __init context_init(void)
 		context_gic_dist_common.base = ioremap(U5500_GIC_DIST_BASE, SZ_4K);
 		per_cpu(context_gic_cpu, 0).base = ioremap(U5500_GIC_CPU_BASE, SZ_4K);
 	} else if (cpu_is_u8500()) {
+		/* Give logical address to backup RAM. For both CPUs */
+		writel(IO_ADDRESS(U8500_PUBLIC_BOOT_ROM_BASE),
+		       IO_ADDRESS(U8500_CPU0_BACKUPRAM_ADDR_PUBLIC_BOOT_ROM_LOG_ADDR));
+
+		writel(IO_ADDRESS(U8500_PUBLIC_BOOT_ROM_BASE),
+		       IO_ADDRESS(U8500_CPU1_BACKUPRAM_ADDR_PUBLIC_BOOT_ROM_LOG_ADDR));
+
 		context_tpiu.base = ioremap(U8500_TPIU_BASE, SZ_4K);
 		context_stm_ape.base = ioremap(U8500_STM_REG_BASE, SZ_4K);
 		context_scu.base = ioremap(U8500_SCU_BASE, SZ_4K);