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authorLinus Torvalds <torvalds@woody.linux-foundation.org>2007-12-10 19:45:17 -0800
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-12-10 19:45:17 -0800
commitc34c15b02e0af7e235f84ca1471747ee1cbb1b87 (patch)
treeea6a40c40601e8a1af8c21cd537340179427732d
parent3790ee4bd86396558eedd86faac1052cb782e4e1 (diff)
parentba0f00b9fcb02b10cc9929fec660f86d1af6a41a (diff)
downloadlinux-2.6.38-lt-ux500-c34c15b02e0af7e235f84ca1471747ee1cbb1b87.tar.gz
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: [MIPS] Malta: Enable tickless and highres timers. [MIPS] Bigsur: Enable tickless and and highres timers. qemu: do not enable IP7 blindly [MIPS] Alchemy: Fix Au1x SD controller IRQ [MIPS] Don't byteswap writes to display when running bigendian
-rw-r--r--arch/mips/configs/bigsur_defconfig9
-rw-r--r--arch/mips/configs/malta_defconfig8
-rw-r--r--arch/mips/mips-boards/generic/display.c4
-rw-r--r--arch/mips/qemu/q-irq.c2
-rw-r--r--include/asm-mips/mach-au1x00/au1100_mmc.h7
5 files changed, 25 insertions, 5 deletions
diff --git a/arch/mips/configs/bigsur_defconfig b/arch/mips/configs/bigsur_defconfig
index 80b0c99c2cf..3c70c9d16d0 100644
--- a/arch/mips/configs/bigsur_defconfig
+++ b/arch/mips/configs/bigsur_defconfig
@@ -76,9 +76,13 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
CONFIG_GENERIC_FIND_NEXT_BIT=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CMOS_UPDATE=y
CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
+CONFIG_CEVT_BCM1480=y
+CONFIG_CSRC_BCM1480=y
CONFIG_DMA_COHERENT=y
CONFIG_CPU_BIG_ENDIAN=y
# CONFIG_CPU_LITTLE_ENDIAN is not set
@@ -91,6 +95,11 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
#
# CPU selection
#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_CPU_LOONGSON2 is not set
# CONFIG_CPU_MIPS32_R1 is not set
# CONFIG_CPU_MIPS32_R2 is not set
# CONFIG_CPU_MIPS64_R1 is not set
diff --git a/arch/mips/configs/malta_defconfig b/arch/mips/configs/malta_defconfig
index fbd2d802fdf..4b7e43c9f69 100644
--- a/arch/mips/configs/malta_defconfig
+++ b/arch/mips/configs/malta_defconfig
@@ -49,10 +49,13 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
CONFIG_GENERIC_FIND_NEXT_BIT=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CMOS_UPDATE=y
CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
CONFIG_ARCH_MAY_HAVE_PC_FDC=y
+CONFIG_CEVT_R4K=y
CONFIG_DMA_NONCOHERENT=y
CONFIG_DMA_NEED_PCI_MAP_STATE=y
CONFIG_EARLY_PRINTK=y
@@ -76,6 +79,10 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
#
# CPU selection
#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
# CONFIG_CPU_LOONGSON2 is not set
# CONFIG_CPU_MIPS32_R1 is not set
CONFIG_CPU_MIPS32_R2=y
@@ -253,6 +260,7 @@ CONFIG_HW_HAS_PCI=y
CONFIG_PCI=y
# CONFIG_ARCH_SUPPORTS_MSI is not set
CONFIG_MMU=y
+CONFIG_I8253=y
#
# PCCARD (PCMCIA/CardBus) support
diff --git a/arch/mips/mips-boards/generic/display.c b/arch/mips/mips-boards/generic/display.c
index 5d600054090..2a0057cfc30 100644
--- a/arch/mips/mips-boards/generic/display.c
+++ b/arch/mips/mips-boards/generic/display.c
@@ -37,9 +37,9 @@ void mips_display_message(const char *str)
for (i = 0; i <= 14; i=i+2) {
if (*str)
- writel(*str++, display + i);
+ __raw_writel(*str++, display + i);
else
- writel(' ', display + i);
+ __raw_writel(' ', display + i);
}
}
diff --git a/arch/mips/qemu/q-irq.c b/arch/mips/qemu/q-irq.c
index 11f98476788..7df36dbe65c 100644
--- a/arch/mips/qemu/q-irq.c
+++ b/arch/mips/qemu/q-irq.c
@@ -33,5 +33,5 @@ void __init arch_init_irq(void)
mips_cpu_irq_init();
init_i8259_irqs();
- set_c0_status(0x8400);
+ set_c0_status(0x400);
}
diff --git a/include/asm-mips/mach-au1x00/au1100_mmc.h b/include/asm-mips/mach-au1x00/au1100_mmc.h
index 9e7d1ba21b5..9e0028f60a4 100644
--- a/include/asm-mips/mach-au1x00/au1100_mmc.h
+++ b/include/asm-mips/mach-au1x00/au1100_mmc.h
@@ -41,8 +41,11 @@
#define NUM_AU1100_MMC_CONTROLLERS 2
-
-#define AU1100_SD_IRQ 2
+#if defined(CONFIG_SOC_AU1100)
+#define AU1100_SD_IRQ AU1100_SD_INT
+#elif defined(CONFIG_SOC_AU1200)
+#define AU1100_SD_IRQ AU1200_SD_INT
+#endif
#define SD0_BASE 0xB0600000