From 8c47209c5bf71bfcb79544171a2ac744b93eb081 Mon Sep 17 00:00:00 2001 From: Jimmy Rubin Date: Fri, 11 Jun 2010 13:38:15 +0200 Subject: MCDE: Supports new HDMI features This patch does the following: * Dynamic resolution change (HDMI and TV-out) * Dynamic change of rotation (Main display) * Dynamic change to 24 and 32 bpp (RGB888, RGBA8888, RGBX8888) * HDMI stability improvements * Removes Framebuffer_console for V.20 and HREF+. * Support for disabling display initialization if u-boot supports startup graphics * Adds prcmu handling from the mcde driver ST Ericsson Change-Id: WP259361 Signed-off-by: Mian Yousaf Kaukab Change-Id: I37e91d49f1550a3ecd041d4ddf67ce57e086772c Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/2536 Reviewed-by: Jonas ABERG --- arch/arm/mach-ux500/include/mach/prcmu-regs.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'arch/arm/mach-ux500/include/mach/prcmu-regs.h') diff --git a/arch/arm/mach-ux500/include/mach/prcmu-regs.h b/arch/arm/mach-ux500/include/mach/prcmu-regs.h index b852663a270..0972342dfb5 100755 --- a/arch/arm/mach-ux500/include/mach/prcmu-regs.h +++ b/arch/arm/mach-ux500/include/mach/prcmu-regs.h @@ -67,4 +67,30 @@ /* System reset register */ #define PRCM_APE_SOFTRST (_PRCMU_BASE + 0x228) +/* Level shifter and clamp control registers */ +#define PRCM_MMIP_LS_CLAMP_SET (_PRCMU_BASE + 0x420) +#define PRCM_MMIP_LS_CLAMP_CLR (_PRCMU_BASE + 0x424) + +/* PRCMU clock/PLL/reset registers */ +#define PRCM_PLLDSI_FREQ (_PRCMU_BASE + 0x500) +#define PRCM_PLLDSI_ENABLE (_PRCMU_BASE + 0x504) +#define PRCM_LCDCLK_MGT (_PRCMU_BASE + 0x044) +#define PRCM_MCDECLK_MGT (_PRCMU_BASE + 0x064) +#define PRCM_HDMICLK_MGT (_PRCMU_BASE + 0x058) +#define PRCM_TVCLK_MGT (_PRCMU_BASE + 0x07c) +#define PRCM_DSI_PLLOUT_SEL (_PRCMU_BASE + 0x530) +#define PRCM_DSITVCLK_DIV (_PRCMU_BASE + 0x52C) +#define PRCM_APE_RESETN_SET (_PRCMU_BASE + 0x1E4) +#define PRCM_APE_RESETN_CLR (_PRCMU_BASE + 0x1E8) + +/* ePOD and memory power signal control registers */ +#define PRCM_EPOD_C_SET (_PRCMU_BASE + 0x410) +#define PRCM_SRAM_LS_SLEEP (_PRCMU_BASE + 0x304) + +/* Debug power control unit registers */ +#define PRCM_POWER_STATE_SET (_PRCMU_BASE + 0x254) + +/* Miscellaneous unit registers */ +#define PRCM_DSI_SW_RESET (_PRCMU_BASE + 0x324) + #endif /* __MACH_PRCMU__REGS_H */ -- cgit v1.2.1