diff options
Diffstat (limited to 'include/asm-blackfin/mach-bf548/defBF544.h')
| -rw-r--r-- | include/asm-blackfin/mach-bf548/defBF544.h | 60 |
1 files changed, 0 insertions, 60 deletions
diff --git a/include/asm-blackfin/mach-bf548/defBF544.h b/include/asm-blackfin/mach-bf548/defBF544.h index 8fc77ea12aa..dd955dcd39b 100644 --- a/include/asm-blackfin/mach-bf548/defBF544.h +++ b/include/asm-blackfin/mach-bf548/defBF544.h @@ -538,21 +538,13 @@ /* Bit masks for PIXC_CTL */ #define PIXC_EN 0x1 /* Pixel Compositor Enable */ -#define nPIXC_EN 0x0 #define OVR_A_EN 0x2 /* Overlay A Enable */ -#define nOVR_A_EN 0x0 #define OVR_B_EN 0x4 /* Overlay B Enable */ -#define nOVR_B_EN 0x0 #define IMG_FORM 0x8 /* Image Data Format */ -#define nIMG_FORM 0x0 #define OVR_FORM 0x10 /* Overlay Data Format */ -#define nOVR_FORM 0x0 #define OUT_FORM 0x20 /* Output Data Format */ -#define nOUT_FORM 0x0 #define UDS_MOD 0x40 /* Resampling Mode */ -#define nUDS_MOD 0x0 #define TC_EN 0x80 /* Transparent Color Enable */ -#define nTC_EN 0x0 #define IMG_STAT 0x300 /* Image FIFO Status */ #define OVR_STAT 0xc00 /* Overlay FIFO Status */ #define WM_LVL 0x3000 /* FIFO Watermark Level */ @@ -600,13 +592,9 @@ /* Bit masks for PIXC_INTRSTAT */ #define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */ -#define nOVR_INT_EN 0x0 #define FRM_INT_EN 0x2 /* Interrupt at End of Frame */ -#define nFRM_INT_EN 0x0 #define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */ -#define nOVR_INT_STAT 0x0 #define FRM_INT_STAT 0x8 /* Frame Interrupt Status */ -#define nFRM_INT_STAT 0x0 /* Bit masks for PIXC_RYCON */ @@ -614,7 +602,6 @@ #define A12 0xffc00 /* A12 in the Coefficient Matrix */ #define A13 0x3ff00000 /* A13 in the Coefficient Matrix */ #define RY_MULT4 0x40000000 /* Multiply Row by 4 */ -#define nRY_MULT4 0x0 /* Bit masks for PIXC_GUCON */ @@ -622,7 +609,6 @@ #define A22 0xffc00 /* A22 in the Coefficient Matrix */ #define A23 0x3ff00000 /* A23 in the Coefficient Matrix */ #define GU_MULT4 0x40000000 /* Multiply Row by 4 */ -#define nGU_MULT4 0x0 /* Bit masks for PIXC_BVCON */ @@ -630,7 +616,6 @@ #define A32 0xffc00 /* A32 in the Coefficient Matrix */ #define A33 0x3ff00000 /* A33 in the Coefficient Matrix */ #define BV_MULT4 0x40000000 /* Multiply Row by 4 */ -#define nBV_MULT4 0x0 /* Bit masks for PIXC_CCBIAS */ @@ -647,48 +632,28 @@ /* Bit masks for HOST_CONTROL */ #define HOST_EN 0x1 /* Host Enable */ -#define nHOST_EN 0x0 #define HOST_END 0x2 /* Host Endianess */ -#define nHOST_END 0x0 #define DATA_SIZE 0x4 /* Data Size */ -#define nDATA_SIZE 0x0 #define HOST_RST 0x8 /* Host Reset */ -#define nHOST_RST 0x0 #define HRDY_OVR 0x20 /* Host Ready Override */ -#define nHRDY_OVR 0x0 #define INT_MODE 0x40 /* Interrupt Mode */ -#define nINT_MODE 0x0 #define BT_EN 0x80 /* Bus Timeout Enable */ -#define nBT_EN 0x0 #define EHW 0x100 /* Enable Host Write */ -#define nEHW 0x0 #define EHR 0x200 /* Enable Host Read */ -#define nEHR 0x0 #define BDR 0x400 /* Burst DMA Requests */ -#define nBDR 0x0 /* Bit masks for HOST_STATUS */ #define READY 0x1 /* DMA Ready */ -#define nREADY 0x0 #define FIFOFULL 0x2 /* FIFO Full */ -#define nFIFOFULL 0x0 #define FIFOEMPTY 0x4 /* FIFO Empty */ -#define nFIFOEMPTY 0x0 #define COMPLETE 0x8 /* DMA Complete */ -#define nCOMPLETE 0x0 #define HSHK 0x10 /* Host Handshake */ -#define nHSHK 0x0 #define TIMEOUT 0x20 /* Host Timeout */ -#define nTIMEOUT 0x0 #define HIRQ 0x40 /* Host Interrupt Request */ -#define nHIRQ 0x0 #define ALLOW_CNFG 0x80 /* Allow New Configuration */ -#define nALLOW_CNFG 0x0 #define DMA_DIR 0x100 /* DMA Direction */ -#define nDMA_DIR 0x0 #define BTE 0x200 /* Bus Timeout Enabled */ -#define nBTE 0x0 /* Bit masks for HOST_TIMEOUT */ @@ -697,67 +662,42 @@ /* Bit masks for TIMER_ENABLE1 */ #define TIMEN8 0x1 /* Timer 8 Enable */ -#define nTIMEN8 0x0 #define TIMEN9 0x2 /* Timer 9 Enable */ -#define nTIMEN9 0x0 #define TIMEN10 0x4 /* Timer 10 Enable */ -#define nTIMEN10 0x0 /* Bit masks for TIMER_DISABLE1 */ #define TIMDIS8 0x1 /* Timer 8 Disable */ -#define nTIMDIS8 0x0 #define TIMDIS9 0x2 /* Timer 9 Disable */ -#define nTIMDIS9 0x0 #define TIMDIS10 0x4 /* Timer 10 Disable */ -#define nTIMDIS10 0x0 /* Bit masks for TIMER_STATUS1 */ #define TIMIL8 0x1 /* Timer 8 Interrupt */ -#define nTIMIL8 0x0 #define TIMIL9 0x2 /* Timer 9 Interrupt */ -#define nTIMIL9 0x0 #define TIMIL10 0x4 /* Timer 10 Interrupt */ -#define nTIMIL10 0x0 #define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */ -#define nTOVF_ERR8 0x0 #define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */ -#define nTOVF_ERR9 0x0 #define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */ -#define nTOVF_ERR10 0x0 #define TRUN8 0x1000 /* Timer 8 Slave Enable Status */ -#define nTRUN8 0x0 #define TRUN9 0x2000 /* Timer 9 Slave Enable Status */ -#define nTRUN9 0x0 #define TRUN10 0x4000 /* Timer 10 Slave Enable Status */ -#define nTRUN10 0x0 /* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */ /* Bit masks for HMDMAx_CONTROL */ #define HMDMAEN 0x1 /* Handshake MDMA Enable */ -#define nHMDMAEN 0x0 #define REP 0x2 /* Handshake MDMA Request Polarity */ -#define nREP 0x0 #define UTE 0x8 /* Urgency Threshold Enable */ -#define nUTE 0x0 #define OIE 0x10 /* Overflow Interrupt Enable */ -#define nOIE 0x0 #define BDIE 0x20 /* Block Done Interrupt Enable */ -#define nBDIE 0x0 #define MBDI 0x40 /* Mask Block Done Interrupt */ -#define nMBDI 0x0 #define DRQ 0x300 /* Handshake MDMA Request Type */ #define RBC 0x1000 /* Force Reload of BCOUNT */ -#define nRBC 0x0 #define PS 0x2000 /* Pin Status */ -#define nPS 0x0 #define OI 0x4000 /* Overflow Interrupt Generated */ -#define nOI 0x0 #define BDI 0x8000 /* Block Done Interrupt Generated */ -#define nBDI 0x0 /* ******************************************* */ /* MULTI BIT MACRO ENUMERATIONS */ |