diff options
Diffstat (limited to 'include/asm-arm/arch-iop13xx')
| -rw-r--r-- | include/asm-arm/arch-iop13xx/iop13xx.h | 43 | ||||
| -rw-r--r-- | include/asm-arm/arch-iop13xx/system.h | 34 | ||||
| -rw-r--r-- | include/asm-arm/arch-iop13xx/uncompress.h | 3 |
3 files changed, 46 insertions, 34 deletions
diff --git a/include/asm-arm/arch-iop13xx/iop13xx.h b/include/asm-arm/arch-iop13xx/iop13xx.h index d4e4f828577..52b7fab7ef6 100644 --- a/include/asm-arm/arch-iop13xx/iop13xx.h +++ b/include/asm-arm/arch-iop13xx/iop13xx.h @@ -19,6 +19,39 @@ static inline int iop13xx_cpu_id(void) return id; } +/* WDTCR CP6 R7 Page 9 */ +static inline u32 read_wdtcr(void) +{ + u32 val; + asm volatile("mrc p6, 0, %0, c7, c9, 0":"=r" (val)); + return val; +} +static inline void write_wdtcr(u32 val) +{ + asm volatile("mcr p6, 0, %0, c7, c9, 0"::"r" (val)); +} + +/* WDTSR CP6 R8 Page 9 */ +static inline u32 read_wdtsr(void) +{ + u32 val; + asm volatile("mrc p6, 0, %0, c8, c9, 0":"=r" (val)); + return val; +} +static inline void write_wdtsr(u32 val) +{ + asm volatile("mcr p6, 0, %0, c8, c9, 0"::"r" (val)); +} + +/* RCSR - Reset Cause Status Register */ +static inline u32 read_rcsr(void) +{ + u32 val; + asm volatile("mrc p6, 0, %0, c0, c1, 0":"=r" (val)); + return val; +} + +extern unsigned long get_iop_tick_rate(void); #endif /* @@ -480,4 +513,14 @@ static inline int iop13xx_cpu_id(void) #define IOP13XX_PBI_LR1 IOP13XX_PBI_OFFSET(0x14) #define IOP13XX_PROCESSOR_FREQ IOP13XX_REG_ADDR32(0x2180) + +/* Watchdog timer definitions */ +#define IOP_WDTCR_EN_ARM 0x1e1e1e1e +#define IOP_WDTCR_EN 0xe1e1e1e1 +#define IOP_WDTCR_DIS_ARM 0x1f1f1f1f +#define IOP_WDTCR_DIS 0xf1f1f1f1 +#define IOP_RCSR_WDT (1 << 5) /* reset caused by watchdog timer */ +#define IOP13XX_WDTSR_WRITE_EN (1 << 31) /* used to speed up reset requests */ +#define IOP13XX_WDTCR_IB_RESET (1 << 0) + #endif /* _IOP13XX_HW_H_ */ diff --git a/include/asm-arm/arch-iop13xx/system.h b/include/asm-arm/arch-iop13xx/system.h index 127827058e1..8575af8db78 100644 --- a/include/asm-arm/arch-iop13xx/system.h +++ b/include/asm-arm/arch-iop13xx/system.h @@ -13,43 +13,13 @@ static inline void arch_idle(void) cpu_do_idle(); } -/* WDTCR CP6 R7 Page 9 */ -static inline u32 read_wdtcr(void) -{ - u32 val; - asm volatile("mrc p6, 0, %0, c7, c9, 0":"=r" (val)); - return val; -} -static inline void write_wdtcr(u32 val) -{ - asm volatile("mcr p6, 0, %0, c7, c9, 0"::"r" (val)); -} - -/* WDTSR CP6 R8 Page 9 */ -static inline u32 read_wdtsr(void) -{ - u32 val; - asm volatile("mrc p6, 0, %0, c8, c9, 0":"=r" (val)); - return val; -} -static inline void write_wdtsr(u32 val) -{ - asm volatile("mcr p6, 0, %0, c8, c9, 0"::"r" (val)); -} - -#define IOP13XX_WDTCR_EN_ARM 0x1e1e1e1e -#define IOP13XX_WDTCR_EN 0xe1e1e1e1 -#define IOP13XX_WDTCR_DIS_ARM 0x1f1f1f1f -#define IOP13XX_WDTCR_DIS 0xf1f1f1f1 -#define IOP13XX_WDTSR_WRITE_EN (1 << 31) -#define IOP13XX_WDTCR_IB_RESET (1 << 0) static inline void arch_reset(char mode) { /* * Reset the internal bus (warning both cores are reset) */ - write_wdtcr(IOP13XX_WDTCR_EN_ARM); - write_wdtcr(IOP13XX_WDTCR_EN); + write_wdtcr(IOP_WDTCR_EN_ARM); + write_wdtcr(IOP_WDTCR_EN); write_wdtsr(IOP13XX_WDTSR_WRITE_EN | IOP13XX_WDTCR_IB_RESET); write_wdtcr(0x1000); diff --git a/include/asm-arm/arch-iop13xx/uncompress.h b/include/asm-arm/arch-iop13xx/uncompress.h index b9525d59b7a..dd9c2934190 100644 --- a/include/asm-arm/arch-iop13xx/uncompress.h +++ b/include/asm-arm/arch-iop13xx/uncompress.h @@ -1,7 +1,6 @@ #include <asm/types.h> #include <linux/serial_reg.h> #include <asm/hardware.h> -#include <asm/processor.h> #define UART_BASE ((volatile u32 *)IOP13XX_UART1_PHYS) #define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE) @@ -9,7 +8,7 @@ static inline void putc(char c) { while ((UART_BASE[UART_LSR] & TX_DONE) != TX_DONE) - cpu_relax(); + barrier(); UART_BASE[UART_TX] = c; } |