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-rw-r--r--drivers/misc/Kconfig41
-rw-r--r--drivers/misc/ab8500.c43
2 files changed, 76 insertions, 8 deletions
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index bd851088099..4b9cb1a5d6b 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -336,6 +336,47 @@ config AB8500
chip. This connects to U8500 on the SSP/SPI bus and exports
read/write functions for the devices to get access to this chip.
This chip embeds various other multimedia funtionalities as well.
+choice
+ prompt "AB8500 Access Method"
+ depends on AB8500
+ default AB8500_ACCESS_CONFIG3
+
+ config AB8500_ACCESS_CONFIG1
+ depends on AB8500
+ bool "CONFIG_1"
+ help
+ Select this option to enable AB8500 accesses via PRCMU I2C for
+ all register banks
+
+ config AB8500_ACCESS_CONFIG2
+ depends on AB8500
+ bool "CONFIG_2"
+ help
+ Select this option to enable AB8500 accesses via PRCMU I2C for
+ all register banks except SIM control which happens via Modem I2C
+
+ config AB8500_ACCESS_CONFIG3
+ depends on AB8500
+ bool "CONFIG_3"
+ help
+ Select this option to enable AB8500 accesses via SPI for
+ all register banks except SIM control which happens via Modem I2C
+
+ config AB8500_ACCESS_CONFIG4
+ depends on AB8500
+ bool "CONFIG_4"
+ help
+ Select this option to enable AB8500 accesses via SPI for
+ all register banks
+
+ config AB8500_ACCESS_CONFIG5
+ depends on AB8500
+ bool "CONFIG_5"
+ help
+ Select this option to enable AB8500 voltage regulator bank access via
+ PRCMU I2C, SIM control access via Modem I2C and rest of banks accessed
+ via SPI
+endchoice
config AB8500_GPADC
bool "AB8500 GPADC driver"
diff --git a/drivers/misc/ab8500.c b/drivers/misc/ab8500.c
index fc8a813a819..0ebd51aaa29 100644
--- a/drivers/misc/ab8500.c
+++ b/drivers/misc/ab8500.c
@@ -504,12 +504,25 @@ int ab8500_write(u8 block, u32 adr, u8 data)
if (!ab8500)
return -ENODEV;
-#if 0
- /* disabled as prcmu i2c not tested */
+#if defined(CONFIG_AB8500_ACCESS_CONFIG1) || \
+ defined(CONFIG_AB8500_ACCESS_CONFIG2)
if (!u8500_is_earlydrop()) {
- if ( block == AB8500_REGU_CTRL2 )
- return prcmu_i2c_write(block, adr, data);
+ down(&(ab8500->ab8500_sem));
+ error = prcmu_i2c_write(block, adr, data);
+ up(&(ab8500->ab8500_sem));
+ return error;
}
+#else
+#ifdef CONFIG_AB8500_ACCESS_CONFIG5
+ if (!u8500_is_earlydrop()) {
+ if (block == AB8500_REGU_CTRL2) {
+ down(&(ab8500->ab8500_sem));
+ error = prcmu_i2c_write(block, adr, data);
+ up(&(ab8500->ab8500_sem));
+ return error;
+ }
+ }
+#endif
#endif
/**
@@ -568,12 +581,26 @@ int ab8500_read(u8 block, u32 adr)
*/
if (!ab8500)
return -ENODEV;
-#if 0
- /* disabled as prcmu i2c not tested */
+
+#if defined(CONFIG_AB8500_ACCESS_CONFIG1) || \
+ defined(CONFIG_AB8500_ACCESS_CONFIG2)
if (!u8500_is_earlydrop()) {
- if ( block == AB8500_REGU_CTRL2 )
- return prcmu_i2c_read(block, adr);
+ down(&(ab8500->ab8500_sem));
+ retval = prcmu_i2c_read(block, adr);
+ up(&(ab8500->ab8500_sem));
+ return retval;
}
+#else
+#ifdef CONFIG_AB8500_ACCESS_CONFIG5
+ if (!u8500_is_earlydrop()) {
+ if (block == AB8500_REGU_CTRL2) {
+ down(&(ab8500->ab8500_sem));
+ retval = prcmu_i2c_read(block, adr);
+ up(&(ab8500->ab8500_sem));
+ return retval;
+ }
+ }
+#endif
#endif
data = 1 << 23 | block << 18 | adr << 10;