diff options
Diffstat (limited to 'arch/arm/mach-ux500')
91 files changed, 32816 insertions, 0 deletions
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig new file mode 100755 index 00000000000..a84e5b6463a --- /dev/null +++ b/arch/arm/mach-ux500/Kconfig @@ -0,0 +1,70 @@ +if ARCH_U8500 + +config UX500_SOC_DB8500 + bool + depends on (MACH_U8500_MOP || MACH_U8500_SIMULATOR) + default y + +config UX500_SOC_DB5500 + bool + default y + depends on MACH_U5500_SIMULATOR + +choice + prompt "Ux500 target platform" + default MACH_U8500_MOP + +config MACH_U8500_SIMULATOR + bool "U8500 Simulator (SVP8500)" + select CPU_V7 + select ARM_GIC + select SMP + help + Supports Simulation for u8500 platform + +config MACH_U5500_SIMULATOR + bool "U5500 Simulator (SVP5500)" + select CPU_V7 + select ARM_GIC + select SMP + help + Supports Simulation for u5500(FairBanks) platform + +config MACH_U8500_MOP + bool "U8500 MOP500/HREF" + select CPU_V7 + select ARM_GIC + select SMP + help + Supports MOP500 target board + +endchoice + +config U8500_CPUIDLE + tristate "CPUIdle support" + depends on UX500_SOC_DB8500 && CPU_IDLE + select GENERIC_CLOCKEVENTS_BROADCAST + help + Add support for CPUIdle for U8500 + +config U8500_CPUFREQ + tristate "CPUFreq support" + depends on UX500_SOC_DB8500 && CPU_FREQ + default y + help + Add support for CPU Frequency scaling for U8500 + +config U8500_PM + bool + depends on UX500_SOC_DB8500 && PM + +config ARCH_HAS_CPU_IDLE_WAIT + def_bool y + +source "arch/arm/mach-ux500/Kconfig-arch" + +config FORCE_MAX_ZONEORDER + int "Maximum zone order" + default "12" + +endif diff --git a/arch/arm/mach-ux500/Kconfig-arch b/arch/arm/mach-ux500/Kconfig-arch new file mode 100755 index 00000000000..82aeebabd57 --- /dev/null +++ b/arch/arm/mach-ux500/Kconfig-arch @@ -0,0 +1,690 @@ +config MCDE_ENABLE_FEATURE_HW_V1_SUPPORT + bool "MCDE HW V1 support" + default n + help + Say yes here if V1 HW + +config GPIO_STM + bool "STM GPIO driver support" + default y + help + Say yes here to support the STM GPIO device + +config STM_DMA + tristate "STM DMA SUPPORT" + default y + help + STM DMA low level driver for standrd DMA interface + +config U8500_SECURE + bool "Support for running in Secure mode" + default n + help + Build the kernel to run in Secure mode. + +menu "Debug level for STM drivers" +config STM_ACODEC_DEBUG + int "STM ACODEC Debug Level" + depends on U8500_ACODEC + default 0 + help + Sets the ACODEC debug ON/OFF for U8500 SoC + * 0 OFF + * 1 ON + +config STM_ALSA_DEBUG + int "STM ALSA Debug Level" + depends on SND_U8500_ALSA || SND_U8500_ALSA_AB8500 + default 0 + help + Sets the ALSA debug ON/OFF for U8500 SoC + * 0 OFF + * 1 ON +endmenu +#Configuration for MCDE setup + +menu "Display Channel Selection" + +menuconfig FB_U8500_MCDE_CHANNELA + depends on FB + bool "MCDE Channel A configuration" + default y + help + If you want to connect your panel to MCDE channel A then configure this option + +choice + prompt "Display Panel Type" + depends on FB && FB_U8500_MCDE_CHANNELA + default FB_U8500_MCDE_CHANNELA_DISPLAY_HDMI + +config FB_U8500_MCDE_CHANNELA_DISPLAY_WVGA + bool "CLCD WVGA" + +config FB_U8500_MCDE_CHANNELA_DISPLAY_VGA + bool "CLCD VGA" + +config FB_U8500_MCDE_CHANNELA_DISPLAY_CRT + bool "CRT VGA" + +config FB_U8500_MCDE_CHANNELA_DISPLAY_SDTV + bool "SDTV" + +config FB_U8500_MCDE_CHANNELA_DISPLAY_HDMI + depends on MCDE_ENABLE_FEATURE_HW_V1_SUPPORT && FB_HDMI + bool "HDMI A" + +config FB_U8500_MCDE_CHANNELA_DISPLAY_QVGA_PORTRAIT + bool "CLCD QVGA Portrait" + +config FB_U8500_MCDE_CHANNELA_DISPLAY_QVGA_LANDSCAPE + bool "CLCD QVGA Landscape" + +endchoice + + +choice + prompt "HDMI resolution" + depends on FB && FB_U8500_MCDE_CHANNELA && FB_U8500_MCDE_CHANNELA_DISPLAY_HDMI + default FB_U8500_MCDE_HDMI_1280x720P60 + +config FB_U8500_MCDE_HDMI_1920x1080P30 + bool "1920x1080P@30Hz" + +config FB_U8500_MCDE_HDMI_1280x720P60 + bool "1280x720P@60Hz" + +#config FB_U8500_MCDE_HDMI_720x480P60 +# bool "720x480P@60Hz" + +#config FB_U8500_MCDE_HDMI_640x480P60 +# bool "640x480P@60Hz" + +endchoice + + +choice + prompt "InputSource BPP" + depends on FB && FB_U8500_MCDE_CHANNELA + default FB_U8500_MCDE_CHANNELA_INPUT_16BPP_RGB + + +config FB_U8500_MCDE_CHANNELA_INPUT_16BPP_IRGB + bool "16 BPP IRGB" + +config FB_U8500_MCDE_CHANNELA_INPUT_8BPP + bool "8 BPP" + +config FB_U8500_MCDE_CHANNELA_INPUT_12BPP + bool "12 BPP" + +config FB_U8500_MCDE_CHANNELA_INPUT_16BPP_ARGB + bool "16 BPP ARGB" + +config FB_U8500_MCDE_CHANNELA_INPUT_16BPP_RGB + bool "16 BPP RGB" + +config FB_U8500_MCDE_CHANNELA_INPUT_24BPP + bool "24 BPP" + +config FB_U8500_MCDE_CHANNELA_INPUT_24BPP_PACKED + bool "24 BPP Packed" + +config FB_U8500_MCDE_CHANNELA_INPUT_32BPP + bool "32 BPP" + +config FB_U8500_MCDE_CHANNELA_INPUT_YCBCR + bool "YCbCr422" + + +endchoice + + +choice + prompt "OutputPanel BPP" + depends on FB && FB_U8500_MCDE_CHANNELA + default FB_U8500_MCDE_CHANNELA_OUTPUT_16BPP + +config FB_U8500_MCDE_CHANNELA_OUTPUT_12BPP + bool "12 BPP" + +config FB_U8500_MCDE_CHANNELA_OUTPUT_16BPP + bool "16 BPP" + +config FB_U8500_MCDE_CHANNELA_OUTPUT_18BPP + bool "18 BPP" + +config FB_U8500_MCDE_CHANNELA_OUTPUT_24BPP + bool "24 BPP" + + +endchoice + +config FB_U8500_MCDE_CHANNELA_INPUT_BGRDATA + bool "BGR Input data" + depends on FB && FB_U8500_MCDE_CHANNELA + default no + help + Select this option if your input data is in BGR format + + +config FB_U8500_MCDE_CHANNELA_INPUT_BPP + int + default 16 if !FB + default 8 if FB_U8500_MCDE_CHANNELA_INPUT_8BPP + default 16 if FB_U8500_MCDE_CHANNELA_INPUT_12BPP + default 16 if FB_U8500_MCDE_CHANNELA_INPUT_16BPP_ARGB + default 16 if FB_U8500_MCDE_CHANNELA_INPUT_16BPP_IRGB + default 16 if FB_U8500_MCDE_CHANNELA_INPUT_16BPP_RGB + default 25 if FB_U8500_MCDE_CHANNELA_INPUT_24BPP + default 24 if FB_U8500_MCDE_CHANNELA_INPUT_24BPP_PACKED + default 32 if FB_U8500_MCDE_CHANNELA_INPUT_32BPP + default 11 if FB_U8500_MCDE_CHANNELA_INPUT_YCBCR + + +config FB_U8500_MCDE_CHANNELA_INPUT_16BPP_TYPE + int + default 0 if ((!FB_U8500_MCDE_CHANNELA_INPUT_12BPP) && (!FB_U8500_MCDE_CHANNELA_INPUT_16BPP_RGB) && (!FB_U8500_MCDE_CHANNELA_INPUT_16BPP_IRGB) && (!FB_U8500_MCDE_CHANNELA_INPUT_16BPP_ARGB)) + default 35 if FB_U8500_MCDE_CHANNELA_INPUT_16BPP_RGB + default 36 if FB_U8500_MCDE_CHANNELA_INPUT_16BPP_IRGB + default 37 if FB_U8500_MCDE_CHANNELA_INPUT_16BPP_ARGB + default 38 if FB_U8500_MCDE_CHANNELA_INPUT_12BPP + + +config FB_U8500_MCDE_CHANNELA_DISPLAY_TYPE + string + default "VGA" if !FB + default "WVGA" if FB_U8500_MCDE_CHANNELA_DISPLAY_WVGA + default "VGA" if FB_U8500_MCDE_CHANNELA_DISPLAY_VGA + default "CRT" if FB_U8500_MCDE_CHANNELA_DISPLAY_CRT + default "SDTV" if FB_U8500_MCDE_CHANNELA_DISPLAY_SDTV + default "HDMI A" if FB_U8500_MCDE_CHANNELA_DISPLAY_HDMI + default "QVGA_Portrait" if FB_U8500_MCDE_CHANNELA_DISPLAY_QVGA_PORTRAIT + default "QVGA_Landscape" if FB_U8500_MCDE_CHANNELA_DISPLAY_QVGA_LANDSCAPE + +config FB_U8500_MCDE_CHANNELA_OUTPUT_BPP + hex + default 0x2 if !FB + default 0x1 if FB_U8500_MCDE_CHANNELA_OUTPUT_12BPP + default 0x2 if FB_U8500_MCDE_CHANNELA_OUTPUT_16BPP + default 0x3 if FB_U8500_MCDE_CHANNELA_OUTPUT_18BPP + default 0x4 if FB_U8500_MCDE_CHANNELA_OUTPUT_24BPP + +config FB_U8500_MCDE_CHANNELA_INPUT_BGR + hex + default 0x0 if !FB || !FB_U8500_MCDE_CHANNELA_INPUT_BGRDATA + default 0x1 if FB_U8500_MCDE_CHANNELA_INPUT_BGRDATA + + +menuconfig FB_U8500_MCDE_CHANNELB + depends on FB + bool "MCDE Channel B configuration" + default n + help + If you want to connect your panel to MCDE channel B then configure this option + +choice + prompt "Display Panel Type" + depends on FB && FB_U8500_MCDE_CHANNELB + default FB_U8500_MCDE_CHANNELB_DISPLAY_SDTV + +config FB_U8500_MCDE_CHANNELB_DISPLAY_WVGA + bool "CLCD WVGA" + +config FB_U8500_MCDE_CHANNELB_DISPLAY_VGA + bool "CLCD VGA" + +config FB_U8500_MCDE_CHANNELB_DISPLAY_CRT + bool "CRT VGA" + +config FB_U8500_MCDE_CHANNELB_DISPLAY_SDTV + depends on !FB_U8500_MCDE_CHANNELA_DISPLAY_HDMI + bool "SDTV" + +config FB_U8500_MCDE_CHANNELB_DISPLAY_QVGA_PORTRAIT + bool "CLCD QVGA Portrait" + +config FB_U8500_MCDE_CHANNELB_DISPLAY_QVGA_LANDSCAPE + bool "CLCD QVGA Landscape" + +config FB_U8500_MCDE_CHANNELB_DISPLAY_VUIB_WVGA + bool "VUIB WVGA" + +endchoice + + +choice + prompt "InputDataFormat BPP" + depends on FB && FB_U8500_MCDE_CHANNELB + default FB_U8500_MCDE_CHANNELB_INPUT_16BPP_RGB + + +config FB_U8500_MCDE_CHANNELB_INPUT_16BPP_IRGB + bool "16 BPP IRGB" + +config FB_U8500_MCDE_CHANNELB_INPUT_8BPP + bool "8 BPP" + +config FB_U8500_MCDE_CHANNELB_INPUT_12BPP + bool "12 BPP" + +config FB_U8500_MCDE_CHANNELB_INPUT_16BPP_ARGB + bool "16 BPP ARGB" + +config FB_U8500_MCDE_CHANNELB_INPUT_16BPP_RGB + bool "16 BPP RGB" + +config FB_U8500_MCDE_CHANNELB_INPUT_24BPP + bool "24 BPP" + +config FB_U8500_MCDE_CHANNELB_INPUT_24BPP_PACKED + bool "24 BPP Packed" + +config FB_U8500_MCDE_CHANNELB_INPUT_32BPP + bool "32 BPP" + +config FB_U8500_MCDE_CHANNELB_INPUT_YCBCR + bool "YCbCr422" + +endchoice + + +choice + prompt "OutputPanel BPP" + depends on FB && FB_U8500_MCDE_CHANNELB + default FB_U8500_MCDE_CHANNELB_OUTPUT_24BPP if FB_U8500_MCDE_CHANNELB_DISPLAY_SDTV + default FB_U8500_MCDE_CHANNELB_OUTPUT_16BPP + +config FB_U8500_MCDE_CHANNELB_OUTPUT_12BPP + bool "12 BPP" + +config FB_U8500_MCDE_CHANNELB_OUTPUT_16BPP + bool "16 BPP" + +config FB_U8500_MCDE_CHANNELB_OUTPUT_18BPP + bool "18 BPP" + +config FB_U8500_MCDE_CHANNELB_OUTPUT_24BPP + bool "24 BPP" + + +endchoice + + + +config FB_U8500_MCDE_CHANNELB_INPUT_BGRDATA + bool "BGR Input data" + depends on FB && FB_U8500_MCDE_CHANNELB + default no + help + Select this option if your input data is in BGR format + + +config FB_U8500_MCDE_CHANNELB_INPUT_BPP + int + default 16 if !FB + default 8 if FB_U8500_MCDE_CHANNELB_INPUT_8BPP + default 16 if FB_U8500_MCDE_CHANNELB_INPUT_12BPP + default 16 if FB_U8500_MCDE_CHANNELB_INPUT_16BPP_ARGB + default 16 if FB_U8500_MCDE_CHANNELB_INPUT_16BPP_IRGB + default 16 if FB_U8500_MCDE_CHANNELB_INPUT_16BPP_RGB + default 25 if FB_U8500_MCDE_CHANNELB_INPUT_24BPP + default 24 if FB_U8500_MCDE_CHANNELB_INPUT_24BPP_PACKED + default 32 if FB_U8500_MCDE_CHANNELB_INPUT_32BPP + default 11 if FB_U8500_MCDE_CHANNELB_INPUT_YCBCR + + +config FB_U8500_MCDE_CHANNELB_INPUT_16BPP_TYPE + int + default 0 if ((!FB_U8500_MCDE_CHANNELB_INPUT_12BPP) && (!FB_U8500_MCDE_CHANNELB_INPUT_16BPP_RGB) && (!FB_U8500_MCDE_CHANNELB_INPUT_16BPP_IRGB) && (!FB_U8500_MCDE_CHANNELB_INPUT_16BPP_ARGB)) + default 1 if FB_U8500_MCDE_CHANNELB_INPUT_16BPP_RGB + default 2 if FB_U8500_MCDE_CHANNELB_INPUT_16BPP_IRGB + default 3 if FB_U8500_MCDE_CHANNELB_INPUT_16BPP_ARGB + default 4 if FB_U8500_MCDE_CHANNELB_INPUT_12BPP + + +config FB_U8500_MCDE_CHANNELB_DISPLAY_TYPE + string + default "VGA" if !FB + default "WVGA" if FB_U8500_MCDE_CHANNELB_DISPLAY_WVGA + default "VGA" if FB_U8500_MCDE_CHANNELB_DISPLAY_VGA + default "CRT" if FB_U8500_MCDE_CHANNELB_DISPLAY_CRT + default "PAL" if FB_U8500_MCDE_CHANNELB_DISPLAY_SDTV + default "QVGA_Portrait" if FB_U8500_MCDE_CHANNELB_DISPLAY_QVGA_PORTRAIT + default "QVGA_Landscape" if FB_U8500_MCDE_CHANNELB_DISPLAY_QVGA_LANDSCAPE + default "VUIB WVGA" if FB_U8500_MCDE_CHANNELB_DISPLAY_VUIB_WVGA + +config FB_U8500_MCDE_CHANNELB_OUTPUT_BPP + hex + default 0x2 if !FB + default 0x1 if FB_U8500_MCDE_CHANNELB_OUTPUT_12BPP + default 0x2 if FB_U8500_MCDE_CHANNELB_OUTPUT_16BPP + default 0x3 if FB_U8500_MCDE_CHANNELB_OUTPUT_18BPP + default 0x4 if FB_U8500_MCDE_CHANNELB_OUTPUT_24BPP + +config FB_U8500_MCDE_CHANNELB_INPUT_BGR + hex + default 0x0 if !FB || !FB_U8500_MCDE_CHANNELB_INPUT_BGRDATA + default 0x1 if FB_U8500_MCDE_CHANNELB_INPUT_BGRDATA + +config U8500_MCDE_DHO_LBW_SWAPPED + bool "SDTV-MCDE: Swap LBW and DHO fields" + depends on FB_U8500_MCDE_CHANNELB_DISPLAY_SDTV || FB_U8500_MCDE_CHANNEL + default y + help + In early development the MCDE register fields DHO and LBW are sw + +config U8500_TVOUT_DDR_MODE + bool "SDTV: use Dual Data Rate" + depends on FB_U8500_MCDE_CHANNELB_DISPLAY_SDTV || FB_U8500_MCDE_CHANNEL + default y + help + Set to use dual data rate (using 4 data lines instead of 8) + +config TVOUT_TEST_PATTERN + bool "SDTV: Generate Test Pattern" + depends on FB_U8500_MCDE_CHANNELB_DISPLAY_SDTV || FB_U8500_MCDE_CHANNEL + default n + help + Only generate a test pattern (MCDE is not used) + +menuconfig FB_U8500_MCDE_CHANNELC0 + depends on FB + bool "MCDE Channel C0 configuration" + default n + help + If you want to connect your panel to MCDE channel C then configure this option + +choice + prompt "Display Panel Type" + depends on FB && FB_U8500_MCDE_CHANNELC0 + default FB_U8500_MCDE_CHANNELC0_DISPLAY_WVGA + +config FB_U8500_MCDE_CHANNELC0_DISPLAY_WVGA_PORTRAIT +# depends on MCDE_ENABLE_FEATURE_HW_V1_SUPPORT + bool "CLCD WVGA Portrait" + +config FB_U8500_MCDE_CHANNELC0_DISPLAY_WVGA + bool "CLCD WVGA" + +config FB_U8500_MCDE_CHANNELC0_DISPLAY_VGA + bool "CLCD VGA" + +config FB_U8500_MCDE_CHANNELC0_DISPLAY_CRT + bool "CRT VGA" + +config FB_U8500_MCDE_CHANNELC0_DISPLAY_SDTV + bool "SDTV" + +config FB_U8500_MCDE_CHANNELC0_DISPLAY_QVGA_PORTRAIT + bool "CLCD QVGA Portrait" + +config FB_U8500_MCDE_CHANNELC0_DISPLAY_QVGA_LANDSCAPE + bool "CLCD QVGA Landscape" + +endchoice + + +choice + prompt "InputDataFormat BPP" + depends on FB && FB_U8500_MCDE_CHANNELC0 + default FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_RGB + + +config FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_IRGB + bool "16 BPP IRGB" + +config FB_U8500_MCDE_CHANNELC0_INPUT_8BPP + bool "8 BPP" + +config FB_U8500_MCDE_CHANNELC0_INPUT_12BPP + bool "12 BPP" + +config FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_ARGB + bool "16 BPP ARGB" + +config FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_RGB + bool "16 BPP RGB" + +config FB_U8500_MCDE_CHANNELC0_INPUT_24BPP + bool "24 BPP" + +config FB_U8500_MCDE_CHANNELC0_INPUT_24BPP_PACKED + bool "24 BPP Packed" + +config FB_U8500_MCDE_CHANNELC0_INPUT_32BPP + bool "32 BPP" + +config FB_U8500_MCDE_CHANNELC0_INPUT_YCBCR + bool "YCbCr422" + +endchoice + + +choice + prompt "OutputPanel BPP" + depends on FB && FB_U8500_MCDE_CHANNELC0 + default FB_U8500_MCDE_CHANNELC0_OUTPUT_16BPP + +config FB_U8500_MCDE_CHANNELC0_OUTPUT_12BPP + bool "12 BPP" + +config FB_U8500_MCDE_CHANNELC0_OUTPUT_16BPP + bool "16 BPP" + +config FB_U8500_MCDE_CHANNELC0_OUTPUT_18BPP + bool "18 BPP" + +config FB_U8500_MCDE_CHANNELC0_OUTPUT_24BPP + bool "24 BPP" + + +endchoice + + + +config FB_U8500_MCDE_CHANNELC0_INPUT_BGRDATA + bool "BGR Input data" + depends on FB && FB_U8500_MCDE_CHANNELC0 + default no + help + Select this option if your input data is in BGR format + + +config FB_U8500_MCDE_CHANNELC0_INPUT_BPP + int + default 16 if !FB + default 8 if FB_U8500_MCDE_CHANNELC0_INPUT_8BPP + default 16 if FB_U8500_MCDE_CHANNELC0_INPUT_12BPP + default 16 if FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_ARGB + default 16 if FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_IRGB + default 16 if FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_RGB + default 25 if FB_U8500_MCDE_CHANNELC0_INPUT_24BPP + default 24 if FB_U8500_MCDE_CHANNELC0_INPUT_24BPP_PACKED + default 32 if FB_U8500_MCDE_CHANNELC0_INPUT_32BPP + default 11 if FB_U8500_MCDE_CHANNELC0_INPUT_YCBCR + + +config FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_TYPE + int + default 0 if ((!FB_U8500_MCDE_CHANNELC0_INPUT_12BPP) && (!FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_RGB) && (!FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_IRGB) && (!FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_ARGB)) + default 1 if FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_RGB + default 2 if FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_IRGB + default 3 if FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_ARGB + default 4 if FB_U8500_MCDE_CHANNELC0_INPUT_12BPP + + +config FB_U8500_MCDE_CHANNELC0_DISPLAY_TYPE + string + default "VGA" if !FB + default "WVGA_Portrait" if FB_U8500_MCDE_CHANNELC0_DISPLAY_WVGA_PORTRAIT + default "WVGA" if FB_U8500_MCDE_CHANNELC0_DISPLAY_WVGA + default "VGA" if FB_U8500_MCDE_CHANNELC0_DISPLAY_VGA + default "CRT" if FB_U8500_MCDE_CHANNELC0_DISPLAY_CRT + default "SDTV" if FB_U8500_MCDE_CHANNELC0_DISPLAY_SDTV + default "QVGA_Portrait" if FB_U8500_MCDE_CHANNELC0_DISPLAY_QVGA_PORTRAIT + default "QVGA_Landscape" if FB_U8500_MCDE_CHANNELC0_DISPLAY_QVGA_LANDSCAPE + +config FB_U8500_MCDE_CHANNELC0_OUTPUT_BPP + hex + default 0x2 if !FB + default 0x1 if FB_U8500_MCDE_CHANNELC0_OUTPUT_12BPP + default 0x2 if FB_U8500_MCDE_CHANNELC0_OUTPUT_16BPP + default 0x3 if FB_U8500_MCDE_CHANNELC0_OUTPUT_18BPP + default 0x4 if FB_U8500_MCDE_CHANNELC0_OUTPUT_24BPP + +config FB_U8500_MCDE_CHANNELC0_INPUT_BGR + hex + default 0x0 if !FB || !FB_U8500_MCDE_CHANNELC0_INPUT_BGRDATA + default 0x1 if FB_U8500_MCDE_CHANNELC0_INPUT_BGRDATA + +menuconfig FB_U8500_MCDE_CHANNELC1 + depends on FB + bool "MCDE Channel C1 configuration" + default n + help + If you want to connect your panel to MCDE channel C then configure this option + +choice + prompt "Display Panel Type" + depends on FB && FB_U8500_MCDE_CHANNELC1 + default FB_U8500_MCDE_CHANNELC1_DISPLAY_WVGA_PORTRAIT + +config FB_U8500_MCDE_CHANNELC1_DISPLAY_WVGA_PORTRAIT + bool "CLCD WVGA Portrait" + +config FB_U8500_MCDE_CHANNELC1_DISPLAY_WVGA + bool "CLCD WVGA" + +config FB_U8500_MCDE_CHANNELC1_DISPLAY_VGA + bool "CLCD VGA" + +config FB_U8500_MCDE_CHANNELC1_DISPLAY_CRT + bool "CRT VGA" + +config FB_U8500_MCDE_CHANNELC1_DISPLAY_SDTV + bool "SDTV" + +config FB_U8500_MCDE_CHANNELC1_DISPLAY_QVGA_PORTRAIT + bool "CLCD QVGA Portrait" + +config FB_U8500_MCDE_CHANNELC1_DISPLAY_QVGA_LANDSCAPE + bool "CLCD QVGA Landscape" + +endchoice + + +choice + prompt "InputDataFormat BPP" + depends on FB && FB_U8500_MCDE_CHANNELC1 + default FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_RGB + + +config FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_IRGB + bool "16 BPP IRGB" + +config FB_U8500_MCDE_CHANNELC1_INPUT_8BPP + bool "8 BPP" + +config FB_U8500_MCDE_CHANNELC1_INPUT_12BPP + bool "12 BPP" + +config FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_ARGB + bool "16 BPP ARGB" + +config FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_RGB + bool "16 BPP RGB" + +config FB_U8500_MCDE_CHANNELC1_INPUT_24BPP + bool "24 BPP" + +config FB_U8500_MCDE_CHANNELC1_INPUT_24BPP_PACKED + bool "24 BPP Packed" + +config FB_U8500_MCDE_CHANNELC1_INPUT_32BPP + bool "32 BPP" + +config FB_U8500_MCDE_CHANNELC1_INPUT_YCBCR + bool "YCbCr422" + +endchoice + + +choice + prompt "OutputPanel BPP" + depends on FB && FB_U8500_MCDE_CHANNELC1 + default FB_U8500_MCDE_CHANNELC1_OUTPUT_16BPP + +config FB_U8500_MCDE_CHANNELC1_OUTPUT_12BPP + bool "12 BPP" + +config FB_U8500_MCDE_CHANNELC1_OUTPUT_16BPP + bool "16 BPP" + +config FB_U8500_MCDE_CHANNELC1_OUTPUT_18BPP + bool "18 BPP" + +config FB_U8500_MCDE_CHANNELC1_OUTPUT_24BPP + bool "24 BPP" + + +endchoice + + + +config FB_U8500_MCDE_CHANNELC1_INPUT_BGRDATA + bool "BGR Input data" + depends on FB && FB_U8500_MCDE_CHANNELC1 + default no + help + Select this option if your input data is in BGR format + + +config FB_U8500_MCDE_CHANNELC1_INPUT_BPP + int + default 16 if !FB + default 8 if FB_U8500_MCDE_CHANNELC1_INPUT_8BPP + default 16 if FB_U8500_MCDE_CHANNELC1_INPUT_12BPP + default 16 if FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_ARGB + default 16 if FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_IRGB + default 16 if FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_RGB + default 25 if FB_U8500_MCDE_CHANNELC1_INPUT_24BPP + default 24 if FB_U8500_MCDE_CHANNELC1_INPUT_24BPP_PACKED + default 32 if FB_U8500_MCDE_CHANNELC1_INPUT_32BPP + default 11 if FB_U8500_MCDE_CHANNELC1_INPUT_YCBCR + + +config FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_TYPE + int + default 0 if ((!FB_U8500_MCDE_CHANNELC1_INPUT_12BPP) && (!FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_RGB) && (!FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_IRGB) && (!FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_ARGB)) + default 1 if FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_RGB + default 2 if FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_IRGB + default 3 if FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_ARGB + default 4 if FB_U8500_MCDE_CHANNELC1_INPUT_12BPP + + +config FB_U8500_MCDE_CHANNELC1_DISPLAY_TYPE + string + default "VGA" if !FB + default "WVGA_Portrait" if FB_U8500_MCDE_CHANNELC1_DISPLAY_WVGA_PORTRAIT + default "WVGA" if FB_U8500_MCDE_CHANNELC1_DISPLAY_WVGA + default "VGA" if FB_U8500_MCDE_CHANNELC1_DISPLAY_VGA + default "CRT" if FB_U8500_MCDE_CHANNELC1_DISPLAY_CRT + default "SDTV" if FB_U8500_MCDE_CHANNELC1_DISPLAY_SDTV + default "QVGA_Portrait" if FB_U8500_MCDE_CHANNELC1_DISPLAY_QVGA_PORTRAIT + default "QVGA_Landscape" if FB_U8500_MCDE_CHANNELC1_DISPLAY_QVGA_LANDSCAPE + +config FB_U8500_MCDE_CHANNELC1_OUTPUT_BPP + hex + default 0x2 if !FB + default 0x1 if FB_U8500_MCDE_CHANNELC1_OUTPUT_12BPP + default 0x2 if FB_U8500_MCDE_CHANNELC1_OUTPUT_16BPP + default 0x3 if FB_U8500_MCDE_CHANNELC1_OUTPUT_18BPP + default 0x4 if FB_U8500_MCDE_CHANNELC1_OUTPUT_24BPP + +config FB_U8500_MCDE_CHANNELC1_INPUT_BGR + hex + default 0x0 if !FB || !FB_U8500_MCDE_CHANNELC1_INPUT_BGRDATA + default 0x1 if FB_U8500_MCDE_CHANNELC1_INPUT_BGRDATA +endmenu + + diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile new file mode 100755 index 00000000000..adb63af8991 --- /dev/null +++ b/arch/arm/mach-ux500/Makefile @@ -0,0 +1,26 @@ +# +# Makefile for the linux kernel, U8500 machine. +# +# + +obj-y := clock.o timer.o timer-rtt.o +obj-$(CONFIG_REGULATOR) += regulator.o +obj-$(CONFIG_ARCH_U8500) += devices.o +obj-$(CONFIG_STM_DMA) += dma_40.o #part1 no. of dma is 0x40 +obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o +obj-$(CONFIG_MACH_U8500_MOP) += mop500_devices.o mop500-sdi.o +obj-$(CONFIG_UX500_SOC_DB5500) += db5500-devices.o cpu-db5500.o +obj-$(CONFIG_UX500_SOC_DB8500) += db8500-devices.o hsi.o mcde.o \ + cpu-db8500.o prcmu-fw.o +obj-$(CONFIG_MACH_U8500_SIMULATOR) += mop500_devices.o mop500-sdi.o +obj-$(CONFIG_MACH_U5500_SIMULATOR) += board-u5500.o +obj-$(CONFIG_SMP) += platsmp.o headsmp.o localtimer.o +obj-$(CONFIG_U8500_CPUIDLE) += cpuidle.o +obj-$(CONFIG_U8500_CPUFREQ) += cpufreq.o +obj-$(CONFIG_U8500_PM) += pm.o + +ifeq ($(CONFIG_MFD_STE_CONN), m) +obj-y += ste_conn_devices.o +else +obj-$(CONFIG_MFD_STE_CONN) += ste_conn_devices.o +endif diff --git a/arch/arm/mach-ux500/Makefile.boot b/arch/arm/mach-ux500/Makefile.boot new file mode 100755 index 00000000000..c7e75acfe6c --- /dev/null +++ b/arch/arm/mach-ux500/Makefile.boot @@ -0,0 +1,4 @@ + zreladdr-y := 0x00008000 +params_phys-y := 0x00000100 +initrd_phys-y := 0x00800000 + diff --git a/arch/arm/mach-ux500/board-u5500.c b/arch/arm/mach-ux500/board-u5500.c new file mode 100644 index 00000000000..3dcbde07aba --- /dev/null +++ b/arch/arm/mach-ux500/board-u5500.c @@ -0,0 +1,115 @@ +/* + * Copyright (C) 2010 ST-Ericsson + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + */ + +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/amba/bus.h> +#include <linux/gpio.h> + +#include <asm/mach/arch.h> +#include <asm/mach-types.h> + +#include <mach/i2c-stm.h> +#include <mach/devices.h> +#include <mach/setup.h> + +#ifdef CONFIG_FB_MCDE +/* + * This is only for MCDE to build. Remove this once MCDE is fixed to not + * depend on this variable. + */ +int platform_id; +#endif + +/* + * I2C + */ + +static struct i2c_platform_data u8500_i2c1_data = { + .gpio_alt_func = GPIO_ALT_I2C_1, + .name = "i2c1", + .own_addr = I2C1_LP_OWNADDR, + .mode = I2C_FREQ_MODE_STANDARD, + .clk_freq = 100000, + .slave_addressing_mode = I2C_7_BIT_ADDRESS, + .digital_filter_control = I2C_DIGITAL_FILTERS_OFF, + .dma_sync_logic_control = I2C_DISABLED, + .start_byte_procedure = I2C_DISABLED, + .slave_data_setup_time = 0xE, + .bus_control_mode = I2C_BUS_MASTER_MODE, + .i2c_loopback_mode = I2C_DISABLED, + .xfer_mode = I2C_TRANSFER_MODE_INTERRUPT, + .high_speed_master_code = 0, + .i2c_tx_int_threshold = 1, + .i2c_rx_int_threshold = 1 +}; + +static struct i2c_platform_data u8500_i2c2_data = { + .gpio_alt_func = GPIO_ALT_I2C_2, + .name = "i2c2", + .own_addr = I2C2_LP_OWNADDR, + .mode = I2C_FREQ_MODE_STANDARD, + .clk_freq = 100000, + .slave_addressing_mode = I2C_7_BIT_ADDRESS, + .digital_filter_control = I2C_DIGITAL_FILTERS_OFF, + .dma_sync_logic_control = I2C_DISABLED, + .start_byte_procedure = I2C_DISABLED, + .slave_data_setup_time = 0xE, + .bus_control_mode = I2C_BUS_MASTER_MODE, + .i2c_loopback_mode = I2C_DISABLED, + .xfer_mode = I2C_TRANSFER_MODE_INTERRUPT, + .high_speed_master_code = 0, + .i2c_tx_int_threshold = 1, + .i2c_rx_int_threshold = 1 +}; + +static struct i2c_platform_data u8500_i2c3_data = { + .gpio_alt_func = GPIO_ALT_I2C_3, + .name = "i2c3", + .own_addr = I2C3_LP_OWNADDR, + .mode = I2C_FREQ_MODE_STANDARD, + .clk_freq = 100000, + .slave_addressing_mode = I2C_7_BIT_ADDRESS, + .digital_filter_control = I2C_DIGITAL_FILTERS_OFF, + .dma_sync_logic_control = I2C_DISABLED, + .start_byte_procedure = I2C_DISABLED, + .slave_data_setup_time = 0xE, + .bus_control_mode = I2C_BUS_MASTER_MODE, + .i2c_loopback_mode = I2C_DISABLED, + .xfer_mode = I2C_TRANSFER_MODE_INTERRUPT, + .high_speed_master_code = 0, + .i2c_tx_int_threshold = 1, + .i2c_rx_int_threshold = 1 +}; + +static struct amba_device *amba_board_devs[] __initdata = { + &ux500_uart0_device, + &ux500_uart1_device, + &ux500_uart2_device, +}; + +static void __init u5500_init_machine(void) +{ + u5500_init_devices(); + + amba_add_devices(amba_board_devs, ARRAY_SIZE(amba_board_devs)); + + u8500_register_device(&ux500_i2c1_device, &u8500_i2c1_data); + u8500_register_device(&ux500_i2c2_device, &u8500_i2c2_data); + u8500_register_device(&ux500_i2c3_device, &u8500_i2c3_data); +} + +MACHINE_START(NOMADIK, "ST-Ericsson U5500 Platform") + .phys_io = UX500_UART0_BASE, + .io_pg_offst = (IO_ADDRESS(UX500_UART0_BASE) >> 18) & 0xfffc, + .boot_params = 0x00000100, + .map_io = u5500_map_io, + .init_irq = u8500_init_irq, + .timer = &u8500_timer, + .init_machine = u5500_init_machine, +MACHINE_END diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c new file mode 100755 index 00000000000..5f84994e3ab --- /dev/null +++ b/arch/arm/mach-ux500/clock.c @@ -0,0 +1,724 @@ +/* + * linux/arch/arm/mach-u8500/clock.c + * + * Copyright (C) ST Ericsson + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/list.h> +#include <linux/errno.h> +#include <linux/err.h> +#include <linux/clk.h> +#include <linux/mutex.h> + +#include <asm/clkdev.h> +#include <asm/io.h> + +#include <mach/hardware.h> +#include <mach/prcmu-regs.h> +#include "clock.h" + +static DEFINE_SPINLOCK(clocks_lock); + +static void __clk_enable(struct clk *clk) +{ + if (clk->enabled++ == 0) { + if (clk->parent_cluster) + __clk_enable(clk->parent_cluster); + + if (clk->parent_periph) + __clk_enable(clk->parent_periph); + + if (clk->ops && clk->ops->enable) + clk->ops->enable(clk); + } +} + +int clk_enable(struct clk *clk) +{ + unsigned long flags; + + if (!clk || IS_ERR(clk)) + return -EINVAL; + + spin_lock_irqsave(&clocks_lock, flags); + __clk_enable(clk); + spin_unlock_irqrestore(&clocks_lock, flags); + + return 0; +} +EXPORT_SYMBOL(clk_enable); + +static void __clk_disable(struct clk *clk) +{ + if (--clk->enabled == 0) { + if (clk->ops && clk->ops->disable) + clk->ops->disable(clk); + + if (clk->parent_periph) + __clk_disable(clk->parent_periph); + + if (clk->parent_cluster) + __clk_disable(clk->parent_cluster); + } +} + +void clk_disable(struct clk *clk) +{ + unsigned long flags; + + if (!clk || IS_ERR(clk)) + return; + + WARN_ON(!clk->enabled); + + spin_lock_irqsave(&clocks_lock, flags); + __clk_disable(clk); + spin_unlock_irqrestore(&clocks_lock, flags); +} +EXPORT_SYMBOL(clk_disable); + +unsigned long clk_get_rate(struct clk *clk) +{ + unsigned long rate; + + if (clk->ops && clk->ops->get_rate) + return clk->ops->get_rate(clk); + + rate = clk->rate; + if (!rate) { + if (clk->parent_periph) + rate = clk_get_rate(clk->parent_periph); + else if (clk->parent_cluster) + rate = clk_get_rate(clk->parent_cluster); + } + + return rate; +} +EXPORT_SYMBOL(clk_get_rate); + +static void clk_prcmu_enable(struct clk *clk) +{ + void __iomem *cg_set_reg = (void __iomem *)PRCM_YYCLKEN0_MGT_SET + + clk->prcmu_cg_off; + + writel(1 << clk->prcmu_cg_bit, cg_set_reg); +} + +static void clk_prcmu_disable(struct clk *clk) +{ + void __iomem *cg_clr_reg = (void __iomem *)PRCM_YYCLKEN0_MGT_CLR + + clk->prcmu_cg_off; + + writel(1 << clk->prcmu_cg_bit, cg_clr_reg); +} + +/* ED doesn't have the combined set/clr registers */ + +static void clk_prcmu_ed_enable(struct clk *clk) +{ + unsigned int val = readl(clk->prcmu_cg_mgt); + + val |= 1 << 8; + writel(val, clk->prcmu_cg_mgt); +} + +static void clk_prcmu_ed_disable(struct clk *clk) +{ + unsigned int val = readl(clk->prcmu_cg_mgt); + + val &= ~(1 << 8); + writel(val, clk->prcmu_cg_mgt); +} + +static struct clkops clk_prcmu_ops = { + .enable = clk_prcmu_enable, + .disable = clk_prcmu_disable, +}; + +static void clk_prcc_enable(struct clk *clk) +{ + if (clk->prcc_kernel != -1) + writel(1 << (clk->prcc_kernel), clk->prcc_base + 0x8); + + if (clk->prcc_bus != -1) + writel(1 << (clk->prcc_bus), clk->prcc_base + 0x0); +} + +static void clk_prcc_disable(struct clk *clk) +{ + if (clk->prcc_bus != -1) + writel(1 << (clk->prcc_bus), clk->prcc_base + 0x4); + + if (clk->prcc_kernel != -1) + writel(1 << (clk->prcc_kernel), clk->prcc_base + 0xc); +} + +static struct clkops clk_prcc_ops = { + .enable = clk_prcc_enable, + .disable = clk_prcc_disable, +}; + +static struct clk clk_32khz = { + .rate = 32000, +}; + +/* + * PRCMU level clock gating + */ + +/* Bank 0 */ +static DEFINE_PRCMU_CLK(svaclk, 0x0, 2, SVAMMDSPCLK); +static DEFINE_PRCMU_CLK(siaclk, 0x0, 3, SIAMMDSPCLK); +static DEFINE_PRCMU_CLK(sgaclk, 0x0, 4, SGACLK); +static DEFINE_PRCMU_CLK_RATE(uartclk, 0x0, 5, UARTCLK, 38400000); +static DEFINE_PRCMU_CLK(msp02clk, 0x0, 6, MSP02CLK); +static DEFINE_PRCMU_CLK(msp1clk, 0x0, 7, MSP1CLK); /* v1 */ +static DEFINE_PRCMU_CLK_RATE(i2cclk, 0x0, 8, I2CCLK, 48000000); +static DEFINE_PRCMU_CLK_RATE(sdmmcclk, 0x0, 9, SDMMCCLK, 50000000); +static DEFINE_PRCMU_CLK(slimclk, 0x0, 10, SLIMCLK); +static DEFINE_PRCMU_CLK(per1clk, 0x0, 11, PER1CLK); +static DEFINE_PRCMU_CLK(per2clk, 0x0, 12, PER2CLK); +static DEFINE_PRCMU_CLK(per3clk, 0x0, 13, PER3CLK); +static DEFINE_PRCMU_CLK(per5clk, 0x0, 14, PER5CLK); +static DEFINE_PRCMU_CLK_RATE(per6clk, 0x0, 15, PER6CLK, 133330000); +static DEFINE_PRCMU_CLK_RATE(per7clk, 0x0, 16, PER7CLK, 100000000); +static DEFINE_PRCMU_CLK(lcdclk, 0x0, 17, LCDCLK); +static DEFINE_PRCMU_CLK(bmlclk, 0x0, 18, BMLCLK); +static DEFINE_PRCMU_CLK(hsitxclk, 0x0, 19, HSITXCLK); +static DEFINE_PRCMU_CLK(hsirxclk, 0x0, 20, HSIRXCLK); +static DEFINE_PRCMU_CLK(hdmiclk, 0x0, 21, HDMICLK); +static DEFINE_PRCMU_CLK(apeatclk, 0x0, 22, APEATCLK); +static DEFINE_PRCMU_CLK(apetraceclk, 0x0, 23, APETRACECLK); +static DEFINE_PRCMU_CLK(mcdeclk, 0x0, 24, MCDECLK); +static DEFINE_PRCMU_CLK(ipi2clk, 0x0, 25, IPI2CCLK); +static DEFINE_PRCMU_CLK(dsialtclk, 0x0, 26, DSIALTCLK); /* v1 */ +static DEFINE_PRCMU_CLK(dmaclk, 0x0, 27, DMACLK); +static DEFINE_PRCMU_CLK(b2r2clk, 0x0, 28, B2R2CLK); +static DEFINE_PRCMU_CLK(tvclk, 0x0, 29, TVCLK); +static DEFINE_PRCMU_CLK(uniproclk, 0x0, 30, UNIPROCLK); /* v1 */ +static DEFINE_PRCMU_CLK(sspclk, 0x0, 31, SSPCLK); /* v1 */ + +/* Bank 1 */ +static DEFINE_PRCMU_CLK(rngclk, 0x4, 0, RNGCLK); /* v1 */ +static DEFINE_PRCMU_CLK(uiccclk, 0x4, 1, UICCCLK); /* v1 */ + +/* + * PRCC level clock gating + * Format: per#, clk, PCKEN bit, KCKEN bit, parent + */ + +/* Peripheral Cluster #1 */ +static DEFINE_PRCC_CLK(1, i2c4, 10, 9, &clk_i2cclk); +static DEFINE_PRCC_CLK(1, gpio0, 9, -1, NULL); +static DEFINE_PRCC_CLK(1, slimbus0, 8, 8, &clk_slimclk); +static DEFINE_PRCC_CLK(1, spi3_ed, 7, 7, NULL); +static DEFINE_PRCC_CLK(1, spi3_v1, 7, -1, NULL); +static DEFINE_PRCC_CLK(1, i2c2, 6, 6, &clk_i2cclk); +static DEFINE_PRCC_CLK(1, sdi0, 5, 5, &clk_sdmmcclk); +static DEFINE_PRCC_CLK(1, msp1_ed, 4, 4, &clk_msp02clk); +static DEFINE_PRCC_CLK(1, msp1_v1, 4, 4, &clk_msp1clk); +static DEFINE_PRCC_CLK(1, msp0, 3, 3, &clk_msp02clk); +static DEFINE_PRCC_CLK(1, i2c1, 2, 2, &clk_i2cclk); +static DEFINE_PRCC_CLK(1, uart1, 1, 1, &clk_uartclk); +static DEFINE_PRCC_CLK(1, uart0, 0, 0, &clk_uartclk); + +/* Peripheral Cluster #2 */ + +static DEFINE_PRCC_CLK(2, gpio1_ed, 12, -1, NULL); +static DEFINE_PRCC_CLK(2, ssitx_ed, 11, -1, NULL); +static DEFINE_PRCC_CLK(2, ssirx_ed, 10, -1, NULL); +static DEFINE_PRCC_CLK(2, spi0_ed, 9, -1, NULL); +static DEFINE_PRCC_CLK(2, sdi3_ed, 8, 6, &clk_sdmmcclk); +static DEFINE_PRCC_CLK(2, sdi1_ed, 7, 5, &clk_sdmmcclk); +static DEFINE_PRCC_CLK(2, msp2_ed, 6, 4, &clk_msp02clk); +static DEFINE_PRCC_CLK(2, sdi4_ed, 4, 2, &clk_sdmmcclk); +static DEFINE_PRCC_CLK(2, pwl_ed, 3, 1, NULL); +static DEFINE_PRCC_CLK(2, spi1_ed, 2, -1, NULL); +static DEFINE_PRCC_CLK(2, spi2_ed, 1, -1, NULL); +static DEFINE_PRCC_CLK(2, i2c3_ed, 0, 0, &clk_i2cclk); + +static DEFINE_PRCC_CLK(2, gpio1_v1, 11, -1, NULL); +static DEFINE_PRCC_CLK(2, ssitx_v1, 10, 7, NULL); +static DEFINE_PRCC_CLK(2, ssirx_v1, 9, 6, NULL); +static DEFINE_PRCC_CLK(2, spi0_v1, 8, -1, NULL); +static DEFINE_PRCC_CLK(2, sdi3_v1, 7, 5, &clk_sdmmcclk); +static DEFINE_PRCC_CLK(2, sdi1_v1, 6, 4, &clk_sdmmcclk); +static DEFINE_PRCC_CLK(2, msp2_v1, 5, 3, &clk_msp02clk); +static DEFINE_PRCC_CLK(2, sdi4_v1, 4, 2, &clk_sdmmcclk); +static DEFINE_PRCC_CLK(2, pwl_v1, 3, 1, NULL); +static DEFINE_PRCC_CLK(2, spi1_v1, 2, -1, NULL); +static DEFINE_PRCC_CLK(2, spi2_v1, 1, -1, NULL); +static DEFINE_PRCC_CLK(2, i2c3_v1, 0, 0, &clk_i2cclk); + +/* Peripheral Cluster #3 */ +static DEFINE_PRCC_CLK(3, gpio2, 8, -1, NULL); +static DEFINE_PRCC_CLK(3, sdi5, 7, 7, &clk_sdmmcclk); +static DEFINE_PRCC_CLK(3, uart2, 6, 6, &clk_uartclk); +static DEFINE_PRCC_CLK(3, ske, 5, 5, &clk_32khz); +static DEFINE_PRCC_CLK(3, sdi2, 4, 4, &clk_sdmmcclk); +static DEFINE_PRCC_CLK(3, i2c0, 3, 3, &clk_i2cclk); +static DEFINE_PRCC_CLK(3, ssp1_ed, 2, 2, &clk_i2cclk); +static DEFINE_PRCC_CLK(3, ssp0_ed, 1, 1, &clk_i2cclk); +static DEFINE_PRCC_CLK(3, ssp1_v1, 2, 2, &clk_sspclk); +static DEFINE_PRCC_CLK(3, ssp0_v1, 1, 1, &clk_sspclk); +static DEFINE_PRCC_CLK(3, fsmc, 0, -1, NULL); + +/* Peripheral Cluster #4 is in the always on domain */ + +/* Peripheral Cluster #5 */ +static DEFINE_PRCC_CLK(5, gpio3, 1, -1, NULL); +static DEFINE_PRCC_CLK(5, usb_ed, 0, 0, &clk_i2cclk); +static DEFINE_PRCC_CLK(5, usb_v1, 0, 0, NULL); + +/* Peripheral Cluster #6 */ + +static DEFINE_PRCC_CLK(6, mtu1_v1, 8, -1, NULL); +static DEFINE_PRCC_CLK(6, mtu0_v1, 7, -1, NULL); +static DEFINE_PRCC_CLK(6, cfgreg_v1, 6, 6, NULL); +static DEFINE_PRCC_CLK(6, dmc_ed, 6, 6, NULL); +static DEFINE_PRCC_CLK(6, hash1, 5, -1, NULL); +static DEFINE_PRCC_CLK(6, unipro_v1, 4, 1, &clk_uniproclk); +static DEFINE_PRCC_CLK(6, cryp1_ed, 4, -1, NULL); +static DEFINE_PRCC_CLK(6, pka, 3, -1, NULL); +static DEFINE_PRCC_CLK(6, hash0, 2, -1, NULL); +static DEFINE_PRCC_CLK(6, cryp0, 1, -1, NULL); +static DEFINE_PRCC_CLK(6, rng_ed, 0, 0, &clk_i2cclk); +static DEFINE_PRCC_CLK(6, rng_v1, 0, 0, &clk_rngclk); + +/* Peripheral Cluster #7 */ + +static DEFINE_PRCC_CLK(7, tzpc0_ed, 4, -1, NULL); +static DEFINE_PRCC_CLK(7, mtu1_ed, 3, -1, NULL); +static DEFINE_PRCC_CLK(7, mtu0_ed, 2, -1, NULL); +static DEFINE_PRCC_CLK(7, wdg_ed, 1, -1, NULL); +static DEFINE_PRCC_CLK(7, cfgreg_ed, 0, -1, NULL); + +/* + * TODO: Ensure names match with devices and then remove unnecessary entries + * when all drivers use the clk API. + */ + +static struct clk_lookup u8500_common_clkregs[] = { + /* Peripheral Cluster #1 */ + CLK(gpio0, "gpioblock0", NULL), + CLK(slimbus0, "slimbus0", NULL), + CLK(i2c2, "STM-I2C.2", NULL), + CLK(sdi0, NULL, "MMC"), /* remove */ + CLK(sdi0, "sdi0", NULL), + CLK(msp0, "msp0", NULL), + CLK(msp0, "MSP_I2S.0", NULL), + CLK(i2c1, "STM-I2C.1", NULL), + CLK(uart1, "uart1", NULL), + CLK(uart0, "uart0", NULL), + + /* Peripheral Cluster #3 */ + CLK(gpio2, "gpioblock2", NULL), + CLK(sdi5, "sdi5", NULL), + CLK(uart2, "uart2", NULL), + CLK(ske, "ske", NULL), + CLK(sdi2, "sdi2", NULL), + CLK(i2c0, "STM-I2C.0", NULL), + CLK(fsmc, "fsmc", NULL), + + /* Peripheral Cluster #5 */ + CLK(gpio3, "gpioblock3", NULL), + + /* Peripheral Cluster #6 */ + CLK(hash1, "hash1", NULL), + CLK(pka, "pka", NULL), + CLK(hash0, "hash0", NULL), + CLK(cryp0, "cryp0", NULL), + + /* + * PRCMU level clock gating + */ + + /* Bank 0 */ + CLK(svaclk, "sva", NULL), + CLK(siaclk, "sia", NULL), + CLK(sgaclk, "sga", NULL), + CLK(uartclk, "UART", NULL), + CLK(msp02clk, "MSP02", NULL), + CLK(i2cclk, "I2C", NULL), + CLK(sdmmcclk, "sdmmc", NULL), + CLK(slimclk, "SLIM", NULL), + CLK(per1clk, "PERIPH1", NULL), + CLK(per2clk, "PERIPH2", NULL), + CLK(per3clk, "PERIPH3", NULL), + CLK(per5clk, "PERIPH5", NULL), + CLK(per6clk, "PERIPH6", NULL), + CLK(per7clk, "PERIPH7", NULL), + CLK(lcdclk, "lcd", NULL), + CLK(bmlclk, "bml", NULL), + CLK(hsitxclk, "stm-hsi.0", NULL), + CLK(hsirxclk, "stm-hsi.1", NULL), + CLK(hdmiclk, "hdmi", NULL), + CLK(apeatclk, "apeat", NULL), + CLK(apetraceclk, "apetrace", NULL), + CLK(mcdeclk, "mcde", NULL), + CLK(ipi2clk, "ipi2", NULL), + CLK(dmaclk, "STM-DMA.0", NULL), + CLK(b2r2clk, "b2r2", NULL), + CLK(tvclk, "tv", NULL), + + /* With device names */ + + CLK(mcdeclk, "U8500-MCDE.0", "mcde"), + CLK(hdmiclk, "U8500-MCDE.0", "hdmi"), + CLK(tvclk, "U8500-MCDE.0", "tv"), + CLK(lcdclk, "U8500-MCDE.0", "lcd"), + CLK(mcdeclk, "U8500-MCDE.1", "mcde"), + CLK(hdmiclk, "U8500-MCDE.1", "hdmi"), + CLK(tvclk, "U8500-MCDE.1", "tv"), + CLK(lcdclk, "U8500-MCDE.1", "lcd"), + CLK(mcdeclk, "U8500-MCDE.2", "mcde"), + CLK(hdmiclk, "U8500-MCDE.2", "hdmi"), + CLK(tvclk, "U8500-MCDE.2", "tv"), + CLK(lcdclk, "U8500-MCDE.2", "lcd"), + CLK(mcdeclk, "U8500-MCDE.3", "mcde"), + CLK(hdmiclk, "U8500-MCDE.3", "hdmi"), + CLK(tvclk, "U8500-MCDE.3", "tv"), + CLK(lcdclk, "U8500-MCDE.3", "lcd"), + CLK(b2r2clk, "U8500-B2R2.0", NULL), +}; + +static struct clk_lookup u8500_ed_clkregs[] = { + /* Peripheral Cluster #1 */ + CLK(spi3_ed, "spi3", NULL), + CLK(msp1_ed, "msp1", NULL), + CLK(msp1_ed, "MSP_I2S.1", NULL), + + /* Peripheral Cluster #2 */ + CLK(gpio1_ed, "gpioblock1", NULL), + CLK(ssitx_ed, "ssitx", NULL), + CLK(ssirx_ed, "ssirx", NULL), + CLK(spi0_ed, "spi0", NULL), + CLK(sdi3_ed, "sdi3", NULL), + CLK(sdi1_ed, "sdi1", NULL), + CLK(msp2_ed, "msp2", NULL), + CLK(msp2_ed, "MSP_I2S.2", NULL), + CLK(sdi4_ed, NULL, "EMMC"), /* remove */ + CLK(sdi4_ed, "sdi4", NULL), + CLK(pwl_ed, "pwl", NULL), + CLK(spi1_ed, "spi1", NULL), + CLK(spi2_ed, "spi2", NULL), + CLK(i2c3_ed, "STM-I2C.3", NULL), + + /* Peripheral Cluster #3 */ + CLK(ssp1_ed, "ssp1", NULL), + CLK(ssp0_ed, "ssp0", NULL), + + /* Peripheral Cluster #5 */ + CLK(usb_ed, "musb_hdrc.0", "usb"), + + /* Peripheral Cluster #6 */ + CLK(dmc_ed, "dmc", NULL), + CLK(cryp1_ed, "cryp1", NULL), + CLK(rng_ed, "rng", NULL), + + /* Peripheral Cluster #7 */ + CLK(tzpc0_ed, "tzpc0", NULL), + CLK(mtu1_ed, "mtu1", NULL), + CLK(mtu0_ed, "mtu0", NULL), + CLK(wdg_ed, "wdg", NULL), + CLK(cfgreg_ed, "cfgreg", NULL), +}; + +static struct clk_lookup u8500_v1_clkregs[] = { + /* Peripheral Cluster #1 */ + CLK(i2c4, "STM-I2C.4", NULL), + CLK(spi3_v1, "spi3", NULL), + CLK(msp1_v1, "msp1", NULL), + CLK(msp1_v1, "MSP_I2S.1", NULL), + + /* Peripheral Cluster #2 */ + CLK(gpio1_v1, "gpioblock1", NULL), + CLK(ssitx_v1, "ssitx", NULL), + CLK(ssirx_v1, "ssirx", NULL), + CLK(spi0_v1, "spi0", NULL), + CLK(sdi3_v1, "sdi3", NULL), + CLK(sdi1_v1, "sdi1", NULL), + CLK(msp2_v1, "msp2", NULL), + CLK(msp2_v1, "MSP_I2S.2", NULL), + CLK(sdi4_v1, NULL, "EMMC"), /* remove */ + CLK(sdi4_v1, "sdi4", NULL), + CLK(pwl_v1, "pwl", NULL), + CLK(spi1_v1, "spi1", NULL), + CLK(spi2_v1, "spi2", NULL), + CLK(i2c3_v1, "STM-I2C.3", NULL), + + /* Peripheral Cluster #3 */ + CLK(ssp1_v1, "ssp1", NULL), + CLK(ssp0_v1, "ssp0", NULL), + + /* Peripheral Cluster #5 */ + CLK(usb_v1, "musb_hdrc.0", "usb"), + + /* Peripheral Cluster #6 */ + CLK(mtu1_v1, "mtu1", NULL), + CLK(mtu0_v1, "mtu0", NULL), + CLK(cfgreg_v1, "cfgreg", NULL), + CLK(hash1, "hash1", NULL), + CLK(unipro_v1, "unipro", NULL), + CLK(rng_v1, "rng", NULL), + + /* + * PRCMU level clock gating + */ + + /* Bank 0 */ + CLK(msp1clk, "MSP1", NULL), + CLK(uniproclk, "uniproclk", NULL), + CLK(sspclk, "SSP", NULL), + CLK(dsialtclk, "dsialt", NULL), + + /* Bank 1 */ + CLK(rngclk, "rng", NULL), + CLK(uiccclk, "uicc", NULL), +}; + +static void clk_register(struct clk *clk); + +static void clks_register(struct clk_lookup *clks, size_t num) +{ + int i; + + for (i = 0; i < num; i++) { + clkdev_add(&clks[i]); + clk_register(clks[i].clk); + } +} + +/* these are the clocks which are default from the bootloader */ +static const char *u8500_boot_clk[] = { + "uart0", + "uart1", + "uart2", + "gpio0", + "gpio1", + "gpio2", + "gpio3", + "mtu0", + "mtu1", + "ssp0", + "ssp1", + "spi0", + "spi1", + "spi2", + "spi3", + "msp0", + "msp1", + "msp2", + "msp3", + "i2c0", + "i2c1", + "i2c2", + "i2c3", + "i2c4" +}; + +struct clk *boot_clks[ARRAY_SIZE(u8500_boot_clk)]; + +/* we disable a majority of peripherals enabled by default + * but without drivers + */ +static void __init u8500_boot_clk_disable(void) +{ + int i = 0; + for (i = 0; i < ARRAY_SIZE(u8500_boot_clk); i++) { + clk_disable(boot_clks[i]); + clk_put(boot_clks[i]); + } +} +late_initcall_sync(u8500_boot_clk_disable); + +static void u8500_amba_clk_enable(void) +{ + int i = 0; + + writel(~0x0 & ~(1 << 9), IO_ADDRESS(U8500_PER1_BASE + 0xF000 + 0x04)); + writel(~0x0, IO_ADDRESS(U8500_PER1_BASE + 0xF000 + 0x0C)); + + writel(~0x0 & ~(1 << 11), IO_ADDRESS(U8500_PER2_BASE + 0xF000 + 0x04)); + writel(~0x0, IO_ADDRESS(U8500_PER2_BASE + 0xF000 + 0x0C)); + + /*GPIO,UART2 are enabled for booting*/ + writel(0xBF, IO_ADDRESS(U8500_PER3_BASE + 0xF000 + 0x04)); + writel(~0x0 & ~(1 << 6), IO_ADDRESS(U8500_PER3_BASE + 0xF000 + 0x0C)); + + /* enable AMBA configuration clock ONLY */ + writel(~0x0, IO_ADDRESS(U8500_PER6_BASE + 0xF000 + 0x04)); + writel(~0x0, IO_ADDRESS(U8500_PER6_BASE + 0xF000 + 0x0C)); + + for (i = 0; i < ARRAY_SIZE(u8500_boot_clk); i++) { + boot_clks[i] = clk_get_sys(u8500_boot_clk[i], NULL); + clk_enable(boot_clks[i]); + } +} + +int __init clk_init(void) +{ + if (cpu_is_u8500ed()) { + clk_prcmu_ops.enable = clk_prcmu_ed_enable; + clk_prcmu_ops.disable = clk_prcmu_ed_disable; + } else if (cpu_is_u8500v1()) { + void __iomem *sdmmclkmgt = (void __iomem *) PRCM_SDMMCCLK_MGT; + unsigned int val; + + /* Switch SDMMCCLK to 52Mhz instead of 104Mhz */ + val = readl(sdmmclkmgt); + val = (val & ~0x1f) | 16; + writel(val, sdmmclkmgt); + } else if (cpu_is_u5500()) { + clk_prcmu_ops.enable = NULL; + clk_prcmu_ops.disable = NULL; + clk_prcc_ops.enable = NULL; + clk_prcc_ops.disable = NULL; + } + + clks_register(u8500_common_clkregs, ARRAY_SIZE(u8500_common_clkregs)); + + if (cpu_is_u8500ed()) + clks_register(u8500_ed_clkregs, ARRAY_SIZE(u8500_ed_clkregs)); + else + clks_register(u8500_v1_clkregs, ARRAY_SIZE(u8500_v1_clkregs)); + + if (cpu_is_u8500() && !cpu_is_u8500ed()) + u8500_amba_clk_enable(); + + return 0; +} + +#ifdef CONFIG_DEBUG_FS +#include <linux/debugfs.h> +#include <linux/seq_file.h> + +static LIST_HEAD(clocks); +static DEFINE_MUTEX(clocks_mutex); + +static void clk_register(struct clk *clk) +{ + mutex_lock(&clocks_mutex); + + /* Ignore duplicate clocks */ + if (clk->list.prev != NULL || clk->list.next != NULL) { + mutex_unlock(&clocks_mutex); + return; + } + + list_add(&clk->list, &clocks); + mutex_unlock(&clocks_mutex); +} + +/* + * The following makes it possible to view the status (especially reference + * count and reset status) for the clocks in the platform by looking into the + * special file <debugfs>/u8500_clocks + */ +static void *u8500_clocks_start(struct seq_file *m, loff_t *pos) +{ + return *pos < 1 ? (void *)1 : NULL; +} + +static void *u8500_clocks_next(struct seq_file *m, void *v, loff_t *pos) +{ + ++*pos; + return NULL; +} + +static void u8500_clocks_stop(struct seq_file *m, void *v) +{ +} + +static int u8500_clocks_show(struct seq_file *m, void *v) +{ + struct clk *clk; + + list_for_each_entry(clk, &clocks, list) { + struct clk *child; + bool first = true; + + seq_printf(m, "%-11s %d", clk->name, clk->enabled); + + list_for_each_entry(child, &clocks, list) { + if (!child->enabled) + continue; + + if (child->parent_cluster == clk || + child->parent_periph == clk) { + if (first) { + first = false; + seq_printf(m, "\t[active children:"); + } + + seq_printf(m, " %s", child->name); + } + } + + seq_printf(m, "%s\n", first ? "" : "]"); + } + + printk(KERN_INFO "Periph1 PCKEN : 0x%x\n", + readl(IO_ADDRESS(U8500_PER1_BASE + 0xF000 + 0x10))); + printk(KERN_INFO "Periph1 KCKEN : 0x%x\n", + readl(IO_ADDRESS(U8500_PER1_BASE + 0xF000 + 0x14))); + printk(KERN_INFO "Periph2 PCKEN : 0x%x\n", + readl(IO_ADDRESS(U8500_PER2_BASE + 0xF000 + 0x10))); + printk(KERN_INFO "Periph2 KCKEN : 0x%x\n", + readl(IO_ADDRESS(U8500_PER2_BASE + 0xF000 + 0x14))); + printk(KERN_INFO "Periph3 PCKEN : 0x%x\n", + readl(IO_ADDRESS(U8500_PER3_BASE + 0xF000 + 0x10))); + printk(KERN_INFO "Periph3 KCKEN : 0x%x\n", + readl(IO_ADDRESS(U8500_PER3_BASE + 0xF000 + 0x14))); + printk(KERN_INFO "Periph5 PCKEN : 0x%x\n", + readl(IO_ADDRESS(U8500_PER5_BASE + 0x1F000 + 0x10))); + printk(KERN_INFO "Periph5 KCKEN : 0x%x\n", + readl(IO_ADDRESS(U8500_PER5_BASE + 0x1F000 + 0x14))); + printk(KERN_INFO "Periph6 PCKEN : 0x%x\n", + readl(IO_ADDRESS(U8500_PER6_BASE + 0xF000 + 0x10))); + printk(KERN_INFO "Periph6 KCKEN : 0x%x\n", + readl(IO_ADDRESS(U8500_PER6_BASE + 0xF000 + 0x14))); + + return 0; +} + +static const struct seq_operations u8500_clocks_op = { + .start = u8500_clocks_start, + .next = u8500_clocks_next, + .stop = u8500_clocks_stop, + .show = u8500_clocks_show +}; + +static int u8500_clocks_open(struct inode *inode, struct file *file) +{ + return seq_open(file, &u8500_clocks_op); +} + +static const struct file_operations u8500_clocks_operations = { + .open = u8500_clocks_open, + .read = seq_read, + .llseek = seq_lseek, + .release = seq_release, +}; + +static int __init init_clk_read_debugfs(void) +{ + /* Expose a simple debugfs interface to view all clocks */ + (void) debugfs_create_file("u8500_clocks", S_IFREG | S_IRUGO, + NULL, NULL, &u8500_clocks_operations); + return 0; +} +/* + * This needs to come in after the arch_initcall() for the + * overall clocks, because debugfs is not available until + * the subsystems come up. + */ +module_init(init_clk_read_debugfs); +#else +static void clk_register(struct clk *clk) { } +#endif diff --git a/arch/arm/mach-ux500/clock.h b/arch/arm/mach-ux500/clock.h new file mode 100755 index 00000000000..bcf246dcfa4 --- /dev/null +++ b/arch/arm/mach-ux500/clock.h @@ -0,0 +1,76 @@ +/* + * Copyright (C) ST Ericsson + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +extern int __init clk_init(void); + +struct clkops { + void (*enable) (struct clk *); + void (*disable) (struct clk *); + unsigned long (*get_rate) (struct clk *); +}; + +struct clk { + const struct clkops *ops; + const char *name; + unsigned int enabled; + + unsigned long rate; + struct list_head list; + + /* These three are only for PRCMU clks */ + + unsigned int prcmu_cg_off; + unsigned int prcmu_cg_bit; + void __iomem *prcmu_cg_mgt; + + /* The rest are only for PRCC clks */ + + void __iomem *prcc_base; + unsigned int prcc_bus; + unsigned int prcc_kernel; + + struct clk *parent_cluster; + struct clk *parent_periph; +}; + +#define DEFINE_PRCMU_CLK(_name, _cg_off, _cg_bit, _reg) \ +struct clk clk_##_name = { \ + .name = #_name, \ + .ops = &clk_prcmu_ops, \ + .prcmu_cg_off = _cg_off, \ + .prcmu_cg_bit = _cg_bit, \ + .prcmu_cg_mgt = (void __iomem *)PRCM_##_reg##_MGT \ + } + +#define DEFINE_PRCMU_CLK_RATE(_name, _cg_off, _cg_bit, _reg, _rate) \ +struct clk clk_##_name = { \ + .name = #_name, \ + .ops = &clk_prcmu_ops, \ + .prcmu_cg_off = _cg_off, \ + .prcmu_cg_bit = _cg_bit, \ + .rate = _rate, \ + .prcmu_cg_mgt = (void __iomem *)PRCM_##_reg##_MGT \ + } + +#define DEFINE_PRCC_CLK(_pclust, _name, _bus_en, _kernel_en, _kernclk) \ +struct clk clk_##_name = { \ + .name = #_name, \ + .ops = &clk_prcc_ops, \ + .prcc_base = (void __iomem *)IO_ADDRESS(U8500_CLKRST##_pclust##_BASE), \ + .prcc_bus = _bus_en, \ + .prcc_kernel = _kernel_en, \ + .parent_cluster = &clk_per##_pclust##clk, \ + .parent_periph = _kernclk \ + } + +#define CLK(_clk, _devname, _conname) \ + { \ + .clk = &clk_##_clk, \ + .dev_id = _devname, \ + .con_id = _conname, \ + } diff --git a/arch/arm/mach-ux500/cpu-db5500.c b/arch/arm/mach-ux500/cpu-db5500.c new file mode 100644 index 00000000000..3c4adac835b --- /dev/null +++ b/arch/arm/mach-ux500/cpu-db5500.c @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2010 ST-Ericsson + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + */ + +#include <linux/platform_device.h> +#include <linux/amba/bus.h> +#include <linux/io.h> + +#include <asm/mach/map.h> + +#include <mach/hardware.h> +#include <mach/devices.h> +#include <mach/setup.h> + +static struct map_desc u5500_io_desc[] __initdata = { + __IO_DEV_DESC(U5500_GPIO0_BASE, SZ_4K), + __IO_DEV_DESC(U5500_GPIO1_BASE, SZ_4K), + __IO_DEV_DESC(U5500_GPIO2_BASE, SZ_4K), + __IO_DEV_DESC(U5500_GPIO3_BASE, SZ_4K), + __IO_DEV_DESC(U5500_GPIO4_BASE, SZ_4K), +}; + +static struct amba_device *u5500_amba_devs[] __initdata = { + &u5500_gpio0_device, + &u5500_gpio1_device, + &u5500_gpio2_device, + &u5500_gpio3_device, + &u5500_gpio4_device, +}; + +void __init u5500_map_io(void) +{ + ux500_map_io(); + + iotable_init(u5500_io_desc, ARRAY_SIZE(u5500_io_desc)); +} + +void __init u5500_init_devices(void) +{ + ux500_init_devices(); + + amba_add_devices(u5500_amba_devs, ARRAY_SIZE(u5500_amba_devs)); +} diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c new file mode 100644 index 00000000000..fb7def59b22 --- /dev/null +++ b/arch/arm/mach-ux500/cpu-db8500.c @@ -0,0 +1,79 @@ +/* + * Copyright (C) 2010 ST-Ericsson + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + */ + +#include <linux/platform_device.h> +#include <linux/amba/bus.h> +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/io.h> + +#include <asm/mach/map.h> + +#include <mach/hardware.h> +#include <mach/devices.h> +#include <mach/setup.h> + +static struct map_desc u8500_io_desc[] __initdata = { + __IO_DEV_DESC(U8500_MSP0_BASE, SZ_4K), + __IO_DEV_DESC(U8500_MSP1_BASE, SZ_4K), + __IO_DEV_DESC(U8500_MSP2_BASE, SZ_4K), + __IO_DEV_DESC(U8500_GPIO0_BASE, SZ_4K), + __IO_DEV_DESC(U8500_GPIO1_BASE, SZ_4K), + __IO_DEV_DESC(U8500_GPIO2_BASE, SZ_4K), + __IO_DEV_DESC(U8500_GPIO3_BASE, SZ_4K), + __IO_DEV_DESC(U8500_PRCMU_BASE, SZ_4K), + __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K), +}; + +static struct map_desc u8500_ed_io_desc[] __initdata = { + __IO_DEV_DESC(U8500_CLKRST7_BASE, SZ_4K), + __IO_DEV_DESC(U8500_MTU0_BASE_ED, SZ_4K), + __IO_DEV_DESC(U8500_MTU1_BASE_ED, SZ_4K), +}; + +static struct amba_device *u8500_amba_devs[] __initdata = { + &u8500_gpio0_device, + &u8500_gpio1_device, + &u8500_gpio2_device, + &u8500_gpio3_device, +}; + +void __init u8500_map_io(void) +{ + ux500_map_io(); + + iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc)); + if (cpu_is_u8500ed()) + iotable_init(u8500_ed_io_desc, ARRAY_SIZE(u8500_ed_io_desc)); +} + +static void __init u8500_earlydrop_fixup(void) +{ + ux500_dma_device.resource[0].start = U8500_DMA_BASE_ED; + ux500_dma_device.resource[0].end = U8500_DMA_BASE_ED + SZ_4K - 1; + u8500_shrm_device.resource[1].start = IRQ_CA_WAKE_REQ_ED; + u8500_shrm_device.resource[1].end = IRQ_CA_WAKE_REQ_ED; + u8500_shrm_device.resource[2].start = IRQ_AC_READ_NOTIFICATION_0_ED; + u8500_shrm_device.resource[2].end = IRQ_AC_READ_NOTIFICATION_0_ED; + u8500_shrm_device.resource[3].start = IRQ_AC_READ_NOTIFICATION_1_ED; + u8500_shrm_device.resource[3].end = IRQ_AC_READ_NOTIFICATION_1_ED; + u8500_shrm_device.resource[4].start = IRQ_CA_MSG_PEND_NOTIFICATION_0_ED; + u8500_shrm_device.resource[4].end = IRQ_CA_MSG_PEND_NOTIFICATION_0_ED; + u8500_shrm_device.resource[5].start = IRQ_CA_MSG_PEND_NOTIFICATION_1_ED; + u8500_shrm_device.resource[5].end = IRQ_CA_MSG_PEND_NOTIFICATION_1_ED; +} + +void __init u8500_init_devices(void) +{ + if (u8500_is_earlydrop()) + u8500_earlydrop_fixup(); + + ux500_init_devices(); + + amba_add_devices(u8500_amba_devs, ARRAY_SIZE(u8500_amba_devs)); +} diff --git a/arch/arm/mach-ux500/cpufreq.c b/arch/arm/mach-ux500/cpufreq.c new file mode 100755 index 00000000000..54f37e30c4c --- /dev/null +++ b/arch/arm/mach-ux500/cpufreq.c @@ -0,0 +1,163 @@ +/* + * CPU frequency module for U8500 + * + * Copyright 2009 STMicroelectronics. + * Copyright 2009 ST-Ericsson + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + */ +#include <linux/cpufreq.h> +#include <linux/delay.h> + +#include <mach/prcmu-fw-api.h> +#include <mach/prcmu-regs.h> + +static struct cpufreq_frequency_table freq_table[] = { + { + .index = 0, + .frequency = 200000, + }, + { + .index = 1, + .frequency = 300000, + }, + { + .index = 2, + .frequency = 600000, + }, + { + .index = 3, + .frequency = CPUFREQ_TABLE_END + } +}; + +static struct freq_attr *u8500_cpufreq_attr[] = { + &cpufreq_freq_attr_scaling_available_freqs, + NULL, +}; + +int u8500_verify_speed(struct cpufreq_policy *policy) +{ + return cpufreq_frequency_table_verify(policy, freq_table); +} + +static int u8500_target(struct cpufreq_policy *policy, unsigned int target_freq, + unsigned int relation) +{ + struct cpufreq_freqs freqs; + unsigned int idx; + enum arm_opp_t op; + + + /* scale the target frequency to one of the extremes supported */ + if (target_freq < policy->cpuinfo.min_freq) + target_freq = policy->cpuinfo.min_freq; + if (target_freq > policy->cpuinfo.max_freq) + target_freq = policy->cpuinfo.max_freq; + + /* Lookup the next frequency */ + if (cpufreq_frequency_table_target + (policy, freq_table, target_freq, relation, &idx)) { + return -EINVAL; + } + + freqs.old = policy->cur; + freqs.new = freq_table[idx].frequency; + freqs.cpu = policy->cpu; + + /* pre-change notification */ + cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); + + switch (idx) { + case 0: + op = ARM_EXTCLK; break; + case 1: + op = ARM_50_OPP; break; + case 2: + op = ARM_100_OPP; break; + default: + printk(KERN_INFO "u8500-cpufreq : Error in OPP\n"); + return -EINVAL; + } + + /* request the PRCM unit for opp change */ + if (prcmu_set_arm_opp(op)) + return -EINVAL; + + /* post change notification */ + cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); + + return 0; +} + +unsigned int u8500_getspeed(unsigned int cpu) +{ + /* request the prcm to get the current ARM opp */ + enum arm_opp_t opp = prcmu_get_arm_opp(); + + switch (opp) { + case ARM_EXTCLK: return freq_table[0].frequency; + case ARM_50_OPP: return freq_table[1].frequency; + case ARM_100_OPP: return freq_table[2].frequency; + default: + return -EINVAL; + } + return 0; +} + +static int __cpuinit u8500_cpu_init(struct cpufreq_policy *policy) +{ + int res; + + /* get policy fields based on the table */ + res = cpufreq_frequency_table_cpuinfo(policy, freq_table); + if (!res) + cpufreq_frequency_table_get_attr(freq_table, policy->cpu); + else { + printk(KERN_INFO "u8500-cpufreq : Null CPUFreq Tables!!!\n"); + return -EINVAL; + } + + policy->min = policy->cpuinfo.min_freq; + policy->max = policy->cpuinfo.max_freq; + policy->cur = u8500_getspeed(policy->cpu); + + policy->governor = CPUFREQ_DEFAULT_GOVERNOR; + + /* FIXME : Need to take time measurement across the target() + * function with no/some/all drivers in the notification + * list. + */ + policy->cpuinfo.transition_latency = 200 * 1000; /* in ns */ + + /* policy->cpus = cpu_possible_map; TODO will cpufreq.c do this? */ + + policy->shared_type = CPUFREQ_SHARED_TYPE_ALL; + + return res; +} + +static int u8500_cpu_exit(struct cpufreq_policy *policy) +{ + return 0; +} + +static struct cpufreq_driver u8500_driver = { + .flags = CPUFREQ_STICKY, + .verify = u8500_verify_speed, + .target = u8500_target, + .get = u8500_getspeed, + .init = u8500_cpu_init, + .exit = u8500_cpu_exit, + .name = "U8500", + .attr = u8500_cpufreq_attr, +}; + +static int __init u8500_cpufreq_init(void) +{ + return cpufreq_register_driver(&u8500_driver); +} + +device_initcall(u8500_cpufreq_init); diff --git a/arch/arm/mach-ux500/cpuidle.c b/arch/arm/mach-ux500/cpuidle.c new file mode 100755 index 00000000000..98409ea1c43 --- /dev/null +++ b/arch/arm/mach-ux500/cpuidle.c @@ -0,0 +1,246 @@ +/* + * CPU idle module for U8500 + * + * Copyright 2009 STMicroelectronics. + * Copyright 2009 ST-Ericsson. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + */ + +/* CPUIdle driver for U8500 */ + +#include <linux/module.h> +#include <linux/hrtimer.h> +#include <linux/sched.h> +#include <linux/clockchips.h> +#include <mach/prcmu-fw-api.h> +#include "cpuidle.h" + +struct u8500_cstate u8500_cstates[U8500_NUM_CSTATES] = { + { + .type = U8500_CSTATE_C0, + .sleep_latency = 0, + .wakeup_latency = 0, + .threshold = 0, + .power_usage = -1, + .flags = CPUIDLE_FLAG_SHALLOW | CPUIDLE_FLAG_TIME_VALID, + .desc = "C0 - running", + }, + { + .type = U8500_CSTATE_C1, + .sleep_latency = 10, + .wakeup_latency = 10, + .threshold = 10, + .power_usage = 10, + .flags = CPUIDLE_FLAG_SHALLOW | CPUIDLE_FLAG_TIME_VALID, + .desc = "C1 - wait for interrupt", + }, + { + .type = U8500_CSTATE_C2, + .sleep_latency = 50, + .wakeup_latency = 50, + .threshold = 20000, + .power_usage = 5, + .flags = CPUIDLE_FLAG_SHALLOW | CPUIDLE_FLAG_TIME_VALID, + .desc = "C2 - WFI-Retention", + }, +}; + +DEFINE_PER_CPU(struct cpuidle_device, u8500_cpuidle_dev); +DEFINE_PER_CPU(int, u8500_cpu_in_wfi) = {0}; + +struct cpuidle_driver u8500_cpuidle_drv = { + .name = "U8500_CPUIdle", + .owner = THIS_MODULE, +}; + +static void do_nothing(void *unused) +{ +} + +/* + * cpu_idle_wait - Used to ensure that all the CPUs discard old value of + * pm_idle and update to new pm_idle value. Required while changing pm_idle + * handler on SMP systems. + * + * Caller must have changed pm_idle to the new value before the call. Old + * pm_idle value will not be used by any CPU after the return of this function. + */ +void cpu_idle_wait(void) +{ + smp_mb(); + /* kick all the CPUs so that they exit out of pm_idle */ + smp_call_function(do_nothing, NULL, 1); +} +EXPORT_SYMBOL_GPL(cpu_idle_wait); + +static int poll_idle(struct cpuidle_device *dev, struct cpuidle_state *state) +{ + ktime_t t1, t2; + s64 diff; + int ret; + t1 = ktime_get(); + local_irq_enable(); + while (!need_resched()) + cpu_relax(); + + t2 = ktime_get(); + diff = ktime_to_us(ktime_sub(t2, t1)); + if (diff > INT_MAX) + diff = INT_MAX; + + ret = (int)diff; + return ret; +} + +static int wfi_idle(struct cpuidle_device *dev, struct cpuidle_state *state) +{ + ktime_t t1, t2; + s64 diff; + int ret; + + t1 = ktime_get(); + + __asm__ __volatile__("dsb\n\t" "wfi\n\t" : : : "memory"); + + t2 = ktime_get(); + diff = ktime_to_us(ktime_sub(t2, t1)); + if (diff > INT_MAX) + diff = INT_MAX; + + ret = (int)diff; + return ret; +} + +static int wfi_retention_idle(struct cpuidle_device *dev, + struct cpuidle_state *state) +{ + ktime_t t1, t2; + s64 diff; + int ret, cpu, i = 0; + + t1 = ktime_get(); + + per_cpu(u8500_cpu_in_wfi, smp_processor_id()) = 1; + smp_wmb(); + + cpu = smp_processor_id(); + clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu); + + for_each_online_cpu(cpu) + if (per_cpu(u8500_cpu_in_wfi, cpu) == 1) + i++; + + if (i == num_online_cpus()) + prcmu_apply_ap_state_transition(APEXECUTE_TO_APIDLE, + DDR_PWR_STATE_UNCHANGED, 0); + else { + __asm__ __volatile__("dsb\n\t" "wfi\n\t" : : : "memory"); + } + + local_irq_disable(); + clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu); + local_irq_enable(); + + per_cpu(u8500_cpu_in_wfi, smp_processor_id()) = 0; + smp_wmb(); + + t2 = ktime_get(); + diff = ktime_to_us(ktime_sub(t2, t1)); + if (diff > INT_MAX) + diff = INT_MAX; + + ret = (int)diff; + return ret; + +} + +static int u8500_enter_idle(struct cpuidle_device *dev, + struct cpuidle_state *state) +{ + struct u8500_cstate *cstate; + int ret = 0; + cstate = cpuidle_get_statedata(state); + + if (cstate->type == U8500_CSTATE_C1) + ret = wfi_idle(dev, state); + + if (cstate->type == U8500_CSTATE_C2) + ret = wfi_retention_idle(dev, state); + + if (cstate->type == U8500_CSTATE_C0) + ret = poll_idle(dev, state); + + return ret; +} + +static void u8500_cpu_cstate_init(unsigned int cpu) +{ + struct cpuidle_device *dev; + struct u8500_cstate *cstate; + struct cpuidle_state *state; + int i; + + printk("Initializing CPUIdle for CPU%d...\n", cpu); + dev = &per_cpu(u8500_cpuidle_dev, cpu); + dev->cpu = cpu; + for (i = 0; i < U8500_NUM_CSTATES; i++) { + cstate = &u8500_cstates[i]; + state = &dev->states[i]; + + cpuidle_set_statedata(state, cstate); + + state->exit_latency = + cstate->sleep_latency + cstate->wakeup_latency; + state->target_residency = cstate->threshold; + state->flags = cstate->flags; + state->enter = u8500_enter_idle; + state->power_usage = cstate->power_usage; + snprintf(state->name, CPUIDLE_NAME_LEN, "C%d", i); + strncpy(state->desc, cstate->desc, CPUIDLE_DESC_LEN); + } + + dev->state_count = U8500_NUM_CSTATES; + + if (dev->state_count >= 2) + dev->safe_state = &dev->states[1]; + else + dev->safe_state = &dev->states[0]; + + if (cpuidle_register_device(dev)) { + printk(KERN_ERR "%s: CPUidle register device failed\n", + __func__); + } + +} + +static int __init u8500_cpuidle_init(void) +{ + int result = 0; + unsigned int cpu; + + result = cpuidle_register_driver(&u8500_cpuidle_drv); + if (result < 0) + goto out; + + /* TODO: pass a per-cpu var to get the return value of + cpuidle_register_device */ + /* on_each_cpu(u8500_cpu_cstate_init, NULL, 0); */ + for_each_online_cpu(cpu) + u8500_cpu_cstate_init(cpu); + out: + return result; +} +static void __exit u8500_cpuidle_exit(void) +{ + /* TODO: disable cpuidle devices & unregister driver */ +} + +module_init(u8500_cpuidle_init); +module_exit(u8500_cpuidle_exit); + +MODULE_DESCRIPTION("U8500 CPUIdle driver"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("STMicroelectronics"); diff --git a/arch/arm/mach-ux500/cpuidle.h b/arch/arm/mach-ux500/cpuidle.h new file mode 100755 index 00000000000..bfa5221a718 --- /dev/null +++ b/arch/arm/mach-ux500/cpuidle.h @@ -0,0 +1,34 @@ +/* + * CPU frequency module for U8500 + * + * Copyright 2009 STMicroelectronics. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + */ +#ifndef __U8500_CPUIDLE_H +#define __U8500_CPUIDLE_H + +#include <linux/cpuidle.h> + +#define U8500_NUM_CSTATES 3 + +#define U8500_CSTATE_C0 0 /* running */ +#define U8500_CSTATE_C1 1 /* wfi */ +#define U8500_CSTATE_C2 2 /* wfi or wfi retention */ + +/* this is the c-state template structure used to populate the cpuidle + * c-states for all cpu's */ + +struct u8500_cstate { + u8 type; + u32 sleep_latency; + u32 wakeup_latency; + u32 threshold; + u32 power_usage; + u32 flags; + char desc[CPUIDLE_DESC_LEN]; +}; + +#endif diff --git a/arch/arm/mach-ux500/db5500-devices.c b/arch/arm/mach-ux500/db5500-devices.c new file mode 100644 index 00000000000..8ba9fb86cb4 --- /dev/null +++ b/arch/arm/mach-ux500/db5500-devices.c @@ -0,0 +1,240 @@ +/* + * Copyright (C) 2010 ST-Ericsson + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + */ + +#include <linux/platform_device.h> +#include <linux/interrupt.h> +#include <linux/amba/bus.h> +#include <linux/platform_device.h> +#include <linux/gpio.h> +#include <linux/io.h> + +/* gpio alternate funtions on this platform */ +#define __GPIO_ALT(_fun, _start, _end, _cont, _type, _name) { \ + .altfun = _fun, \ + .start = _start, \ + .end = _end, \ + .cont = _cont, \ + .type = _type, \ + .dev_name = _name } + +static struct gpio_altfun_data gpio_altfun_table[] = { + __GPIO_ALT(GPIO_ALT_I2C_4, 4, 5, 0, GPIO_ALTF_B, "i2c4"), + __GPIO_ALT(GPIO_ALT_I2C_1, 16, 17, 0, GPIO_ALTF_B, "i2c1"), + __GPIO_ALT(GPIO_ALT_I2C_2, 8, 9, 0, GPIO_ALTF_B, "i2c2"), + __GPIO_ALT(GPIO_ALT_I2C_0, 147, 148, 0, GPIO_ALTF_A, "i2c0"), + __GPIO_ALT(GPIO_ALT_I2C_3, 229, 230, 0, GPIO_ALTF_C, "i2c3"), + __GPIO_ALT(GPIO_ALT_UART_2, 177, 180, 0, GPIO_ALTF_A, "uart2"), + __GPIO_ALT(GPIO_ALT_SSP_0, 143, 146, 0, GPIO_ALTF_A, "ssp0"), + __GPIO_ALT(GPIO_ALT_SSP_1, 139, 142, 0, GPIO_ALTF_A, "ssp1"), + __GPIO_ALT(GPIO_ALT_USB_OTG, 256, 267, 0, GPIO_ALTF_A, "usb"), + __GPIO_ALT(GPIO_ALT_UART_1, 200, 203, 0, GPIO_ALTF_A, "uart1"), + __GPIO_ALT(GPIO_ALT_UART_0_NO_MODEM, 28, 29, 0, GPIO_ALTF_A, "uart0"), + __GPIO_ALT(GPIO_ALT_MSP_0, 12, 15, 0, GPIO_ALTF_A, "msp0"), + __GPIO_ALT(GPIO_ALT_MSP_1, 33, 36, 0, GPIO_ALTF_A, "msp1"), + __GPIO_ALT(GPIO_ALT_MSP_2, 192, 196, 0, GPIO_ALTF_A, "msp2"), + __GPIO_ALT(GPIO_ALT_HSIR, 219, 221, 0, GPIO_ALTF_A, "hsir"), + __GPIO_ALT(GPIO_ALT_HSIT, 222, 224, 0, GPIO_ALTF_A, "hsit"), + __GPIO_ALT(GPIO_ALT_EMMC, 197, 207, 0, GPIO_ALTF_A, "emmc"), + __GPIO_ALT(GPIO_ALT_SDMMC, 18, 28, 0, GPIO_ALTF_A, "sdmmc"), + __GPIO_ALT(GPIO_ALT_SDIO, 208, 214, 0, GPIO_ALTF_A, "sdio"), + __GPIO_ALT(GPIO_ALT_TRACE, 70, 74, 0, GPIO_ALTF_C, "stm"), + __GPIO_ALT(GPIO_ALT_SDMMC2, 128, 138, 0, GPIO_ALTF_A, "mmc2"), +#ifndef CONFIG_FB_NOMADIK_MCDE_CHANNELB_DISPLAY_VUIB_WVGA + __GPIO_ALT(GPIO_ALT_LCD_PANELB_ED, 78, 85, 1, GPIO_ALTF_A, "mcde tvout"), + __GPIO_ALT(GPIO_ALT_LCD_PANELB_ED, 150, 150, 0, GPIO_ALTF_B, "mcde tvout"), + __GPIO_ALT(GPIO_ALT_LCD_PANELB, 78, 81, 1, GPIO_ALTF_A, "mcde tvout"), + __GPIO_ALT(GPIO_ALT_LCD_PANELB, 150, 150, 0, GPIO_ALTF_B, "mcde tvout"), +#else + __GPIO_ALT(GPIO_ALT_LCD_PANELB, 153, 171, 1, GPIO_ALTF_B, "mcde tvout"), + __GPIO_ALT(GPIO_ALT_LCD_PANELB, 64, 77, 0, GPIO_ALTF_A, "mcde tvout"), +#endif + __GPIO_ALT(GPIO_ALT_LCD_PANELA, 68, 68, 0, GPIO_ALTF_A, "mcde tvout"), + __GPIO_ALT(GPIO_ALT_MMIO_INIT_BOARD, 141, 142, 0, GPIO_ALTF_B, "mmio"), + __GPIO_ALT(GPIO_ALT_MMIO_CAM_SET_I2C, 8, 9, 0, GPIO_ALTF_A, "mmio"), + __GPIO_ALT(GPIO_ALT_MMIO_CAM_SET_EXT_CLK, 227, 228, 0, GPIO_ALTF_A, "mmio"), +#ifdef CONFIG_TOUCHP_EXT_CLK + __GPIO_ALT(GPIO_ALT_TP_SET_EXT_CLK, 228, 228, 0, GPIO_ALTF_A, "u8500_tp1"), +#endif +}; + +static struct gpio_block_data gpio0_block_data[] = { + { + .irq = IRQ_GPIO0, + .base_offset = 0x0, + .blocks_per_irq = 1, + .block_base = 0, + .block_size = 32, + }, + { + .irq = IRQ_GPIO1, + .base_offset = 0x080, + .blocks_per_irq = 1, + .block_base = 32, + .block_size = 4, + }, +}; + +static struct gpio_platform_data gpio0_platform_data = { + .gpio_data = gpio0_block_data, + .gpio_block_size = ARRAY_SIZE(gpio0_block_data), + .altfun_table = gpio_altfun_table, + .altfun_table_size = ARRAY_SIZE(gpio_altfun_table) +}; + +struct amba_device u5500_gpio0_device = { + .dev = { + .bus_id = "gpioblock0", + .platform_data = &gpio0_platform_data, + }, + .res = { + .start = U5500_GPIO0_BASE, + .end = U5500_GPIO0_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + .periphid = GPIO_PER_ID, + .irq = {IRQ_GPIO0, NO_IRQ}, +}; + +static struct gpio_block_data gpio1_block_data[] = { + { + .irq = IRQ_GPIO2, + .base_offset = 0x0, + .blocks_per_irq = 1, + .block_base = 64, + .block_size = 19, + } +}; + +static struct gpio_platform_data gpio1_platform_data = { + .gpio_data = gpio1_block_data, + .gpio_block_size = ARRAY_SIZE(gpio1_block_data), + .altfun_table = gpio_altfun_table, + .altfun_table_size = ARRAY_SIZE(gpio_altfun_table) + +}; + +struct amba_device u5500_gpio1_device = { + .dev = { + .bus_id = "gpioblock1", + .platform_data = &gpio1_platform_data, + }, + .res = { + .start = U5500_GPIO1_BASE, + .end = U5500_GPIO1_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + .periphid = GPIO_PER_ID, + .irq = {IRQ_GPIO2, NO_IRQ}, +}; + +static struct gpio_block_data gpio2_block_data[] = { + { + .irq = IRQ_GPIO3, + .base_offset = 0x0, + .blocks_per_irq = 1, + .block_base = 96, + .block_size = 6, + } +}; + +static struct gpio_platform_data gpio2_platform_data = { + .gpio_data = gpio2_block_data, + .gpio_block_size = ARRAY_SIZE(gpio2_block_data), + .altfun_table = gpio_altfun_table, + .altfun_table_size = ARRAY_SIZE(gpio_altfun_table) +}; + +struct amba_device u5500_gpio2_device = { + .dev = { + .bus_id = "gpioblock2", + .platform_data = &gpio2_platform_data, + }, + .res = { + .start = U5500_GPIO2_BASE, + .end = U5500_GPIO2_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + .periphid = GPIO_PER_ID, + .irq = {IRQ_GPIO3, NO_IRQ}, +}; + +static struct gpio_block_data gpio3_block_data[] = { + { + .irq = IRQ_GPIO4, + .base_offset = 0x0, + .blocks_per_irq = 1, + .block_base = 128, + .block_size = 21, + } +}; + +static struct gpio_platform_data gpio3_platform_data = { + .gpio_data = gpio3_block_data, + .gpio_block_size = ARRAY_SIZE(gpio3_block_data), + .altfun_table = gpio_altfun_table, + .altfun_table_size = ARRAY_SIZE(gpio_altfun_table) + +}; + +struct amba_device u5500_gpio3_device = { + .dev = { + .bus_id = "gpioblock3", + .platform_data = &gpio3_platform_data, + }, + .res = { + .start = U5500_GPIO3_BASE, + .end = U5500_GPIO3_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + .periphid = GPIO_PER_ID, + .irq = {IRQ_GPIO4, NO_IRQ}, +}; + +static struct gpio_block_data gpio4_block_data[] = { + { + .irq = IRQ_GPIO5, + .base_offset = 0x0, + .blocks_per_irq = 1, + .block_base = 160, + .block_size = 32, + }, + { + .irq = IRQ_GPIO6, + .base_offset = 0x80, + .blocks_per_irq = 1, + .block_base = 192, + .block_size = 32, + }, + { + .irq = IRQ_GPIO7, + .base_offset = 0x100, + .blocks_per_irq = 1, + .block_base = 224, + .block_size = 4, + } +}; +static struct gpio_platform_data gpio4_platform_data = { + .gpio_data = gpio4_block_data, + .gpio_block_size = ARRAY_SIZE(gpio4_block_data), + .altfun_table = gpio_altfun_table, + .altfun_table_size = ARRAY_SIZE(gpio_altfun_table) + +}; +struct amba_device u5500_gpio4_device = { + .dev = { + .bus_id = "gpioblock4", + .platform_data = &gpio4_platform_data, + }, + .res = { + .start = U5500_GPIO4_BASE, + .end = U5500_GPIO4_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + .periphid = GPIO_PER_ID, + .irq = {IRQ_GPIO5, NO_IRQ}, +}; diff --git a/arch/arm/mach-ux500/db8500-devices.c b/arch/arm/mach-ux500/db8500-devices.c new file mode 100644 index 00000000000..4bba6684bbb --- /dev/null +++ b/arch/arm/mach-ux500/db8500-devices.c @@ -0,0 +1,327 @@ +/* + * Copyright (C) 2010 ST-Ericsson + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + */ + +#include <linux/platform_device.h> +#include <linux/interrupt.h> +#include <linux/amba/bus.h> +#include <linux/platform_device.h> +#include <linux/gpio.h> +#include <linux/io.h> +#include <linux/dma-mapping.h> +#include <linux/spi/spi.h> + +#include <mach/dma.h> +#include <linux/spi/spi-stm.h> + +/* gpio alternate funtions on this platform */ +#define __GPIO_ALT(_fun, _start, _end, _cont, _type, _name) { \ + .altfun = _fun, \ + .start = _start, \ + .end = _end, \ + .cont = _cont, \ + .type = _type, \ + .dev_name = _name } + +static struct gpio_altfun_data gpio_altfun_table[] = { + __GPIO_ALT(GPIO_ALT_I2C_4, 4, 5, 0, GPIO_ALTF_B, "i2c4"), + __GPIO_ALT(GPIO_ALT_I2C_1, 16, 17, 0, GPIO_ALTF_B, "i2c1"), + __GPIO_ALT(GPIO_ALT_I2C_2, 8, 9, 0, GPIO_ALTF_B, "i2c2"), + __GPIO_ALT(GPIO_ALT_I2C_0, 147, 148, 0, GPIO_ALTF_A, "i2c0"), + __GPIO_ALT(GPIO_ALT_I2C_3, 229, 230, 0, GPIO_ALTF_C, "i2c3"), + __GPIO_ALT(GPIO_ALT_UART_2, 29, 32, 0, GPIO_ALTF_C, "uart2"), + __GPIO_ALT(GPIO_ALT_SSP_0, 143, 146, 0, GPIO_ALTF_A, "ssp0"), + __GPIO_ALT(GPIO_ALT_SSP_1, 139, 142, 0, GPIO_ALTF_A, "ssp1"), + __GPIO_ALT(GPIO_ALT_USB_OTG, 256, 267, 0, GPIO_ALTF_A, "usb"), + __GPIO_ALT(GPIO_ALT_UART_1, 4, 7, 0, GPIO_ALTF_A, "uart1"), + __GPIO_ALT(GPIO_ALT_UART_0_NO_MODEM, 0, 3, 0, GPIO_ALTF_A, "uart0"), + __GPIO_ALT(GPIO_ALT_UART_0_MODEM, 0, 3, 1, GPIO_ALTF_A, "uart0"), + __GPIO_ALT(GPIO_ALT_UART_0_MODEM, 33, 36, 0, GPIO_ALTF_C, "uart0"), + __GPIO_ALT(GPIO_ALT_MSP_0, 12, 15, 0, GPIO_ALTF_A, "msp0"), + __GPIO_ALT(GPIO_ALT_MSP_1, 33, 36, 0, GPIO_ALTF_A, "msp1"), + __GPIO_ALT(GPIO_ALT_MSP_2, 192, 196, 0, GPIO_ALTF_A, "msp2"), + __GPIO_ALT(GPIO_ALT_HSIR, 219, 221, 0, GPIO_ALTF_A, "hsir"), + __GPIO_ALT(GPIO_ALT_HSIT, 222, 224, 0, GPIO_ALTF_A, "hsit"), + __GPIO_ALT(GPIO_ALT_EMMC, 197, 207, 0, GPIO_ALTF_A, "emmc"), + __GPIO_ALT(GPIO_ALT_SDMMC, 18, 28, 0, GPIO_ALTF_A, "sdmmc"), + __GPIO_ALT(GPIO_ALT_SDIO, 208, 214, 0, GPIO_ALTF_A, "sdio"), + __GPIO_ALT(GPIO_ALT_TRACE, 70, 74, 0, GPIO_ALTF_C, "stm"), + __GPIO_ALT(GPIO_ALT_SDMMC2, 128, 138, 0, GPIO_ALTF_A, "mmc2"), +#ifndef CONFIG_FB_NOMADIK_MCDE_CHANNELB_DISPLAY_VUIB_WVGA + __GPIO_ALT(GPIO_ALT_LCD_PANELB_ED, 78, 85, 1, GPIO_ALTF_A, "mcde tvout"), + __GPIO_ALT(GPIO_ALT_LCD_PANELB_ED, 150, 150, 0, GPIO_ALTF_B, "mcde tvout"), + __GPIO_ALT(GPIO_ALT_LCD_PANELB, 78, 81, 1, GPIO_ALTF_A, "mcde tvout"), + __GPIO_ALT(GPIO_ALT_LCD_PANELB, 150, 150, 0, GPIO_ALTF_B, "mcde tvout"), +#else + __GPIO_ALT(GPIO_ALT_LCD_PANELB, 153, 171, 1, GPIO_ALTF_B, "mcde tvout"), + __GPIO_ALT(GPIO_ALT_LCD_PANELB, 64, 77, 0, GPIO_ALTF_A, "mcde tvout"), +#endif + __GPIO_ALT(GPIO_ALT_LCD_PANELA, 68, 68, 0, GPIO_ALTF_A, "mcde tvout"), + __GPIO_ALT(GPIO_ALT_MMIO_INIT_BOARD, 141, 142, 0, GPIO_ALTF_B, "mmio"), + __GPIO_ALT(GPIO_ALT_MMIO_CAM_SET_I2C, 8, 9, 0, GPIO_ALTF_A, "mmio"), + __GPIO_ALT(GPIO_ALT_MMIO_CAM_SET_EXT_CLK, 227, 228, 0, GPIO_ALTF_A, "mmio"), +#ifdef CONFIG_TOUCHP_EXT_CLK + __GPIO_ALT(GPIO_ALT_TP_SET_EXT_CLK, 228, 228, 0, GPIO_ALTF_A, "u8500_tp1"), +#endif +}; + +static struct gpio_block_data gpio0_block_data[] = { + { + .irq = IRQ_GPIO0, + .base_offset = 0x0, + .blocks_per_irq = 1, + .block_base = 0, + .block_size = 32, + }, + { + .irq = IRQ_GPIO1, + .base_offset = 0x080, + .blocks_per_irq = 1, + .block_base = 32, + .block_size = 5, + } +}; + +static struct gpio_platform_data gpio0_platform_data = { + .gpio_data = gpio0_block_data, + .gpio_block_size = ARRAY_SIZE(gpio0_block_data), + .altfun_table = gpio_altfun_table, + .altfun_table_size = ARRAY_SIZE(gpio_altfun_table), +}; + +struct amba_device u8500_gpio0_device = { + .dev = { + .bus_id = "gpioblock0", + .platform_data = &gpio0_platform_data, + }, + .res = { + .start = U8500_GPIO0_BASE, + .end = U8500_GPIO0_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + .periphid = GPIO_PER_ID, + .irq = {IRQ_GPIO0, NO_IRQ}, +}; + +static struct gpio_block_data gpio1_block_data[] = { + { + .irq = IRQ_GPIO2, + .base_offset = 0x0, + .blocks_per_irq = 1, + .block_base = 64, + .block_size = 32, + }, + { + .irq = IRQ_GPIO3, + .base_offset = 0x080, + .blocks_per_irq = 1, + .block_base = 96, + .block_size = 2, + }, + { + .irq = IRQ_GPIO4, + .base_offset = 0x100, + .blocks_per_irq = 1, + .block_base = 128, + .block_size = 32, + }, + { + .irq = IRQ_GPIO5, + .base_offset = 0x180, + .blocks_per_irq = 1, + .block_base = 160, + .block_size = 12, + } +}; +static struct gpio_platform_data gpio1_platform_data = { + .gpio_data = gpio1_block_data, + .gpio_block_size = ARRAY_SIZE(gpio1_block_data), + .altfun_table = gpio_altfun_table, + .altfun_table_size = ARRAY_SIZE(gpio_altfun_table) +}; + +struct amba_device u8500_gpio1_device = { + .dev = { + .bus_id = "gpioblock1", + .platform_data = &gpio1_platform_data, + }, + .res = { + .start = U8500_GPIO1_BASE, + .end = U8500_GPIO1_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + .periphid = GPIO_PER_ID, + .irq = {IRQ_GPIO2, NO_IRQ}, +}; + +static struct gpio_block_data gpio2_block_data[] = { + { + .irq = IRQ_GPIO6, + .base_offset = 0x0, + .blocks_per_irq = 1, + .block_base = 192, + .block_size = 32, + }, + { + .irq = IRQ_GPIO7, + .base_offset = 0x080, + .blocks_per_irq = 1, + .block_base = 224, + .block_size = 7, + } +}; + +static struct gpio_platform_data gpio2_platform_data = { + .gpio_data = gpio2_block_data, + .gpio_block_size = ARRAY_SIZE(gpio2_block_data), + .altfun_table = gpio_altfun_table, + .altfun_table_size = ARRAY_SIZE(gpio_altfun_table) +}; + +struct amba_device u8500_gpio2_device = { + .dev = { + .bus_id = "gpioblock2", + .platform_data = &gpio2_platform_data, + }, + .res = { + .start = U8500_GPIO2_BASE, + .end = U8500_GPIO2_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + .periphid = GPIO_PER_ID, + .irq = {IRQ_GPIO6, NO_IRQ}, +}; + +static struct gpio_block_data gpio3_block_data[] = { + { + .irq = IRQ_GPIO8, + .base_offset = 0x0, + .blocks_per_irq = 1, + .block_base = 256, + .block_size = 12, + } +}; + +static struct gpio_platform_data gpio3_platform_data = { + .gpio_data = gpio3_block_data, + .gpio_block_size = ARRAY_SIZE(gpio3_block_data), + .altfun_table = gpio_altfun_table, + .altfun_table_size = ARRAY_SIZE(gpio_altfun_table) + +}; + +struct amba_device u8500_gpio3_device = { + .dev = { + .bus_id = "gpioblock3", + .platform_data = &gpio3_platform_data, + }, + .res = { + .start = U8500_GPIO3_BASE, + .end = U8500_GPIO3_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + .periphid = GPIO_PER_ID, + .irq = {IRQ_GPIO8, NO_IRQ}, +}; + +static struct resource u8500_i2c0_resources[] = { + [0] = { + .start = U8500_I2C0_BASE, + .end = U8500_I2C0_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_I2C0, + .end = IRQ_I2C0, + .flags = IORESOURCE_IRQ, + } +}; + +struct platform_device u8500_i2c0_device = { + .name = "STM-I2C", + .id = 0, + .resource = u8500_i2c0_resources, + .num_resources = ARRAY_SIZE(u8500_i2c0_resources), +}; + +static struct resource u8500_i2c4_resources[] = { + [0] = { + .start = U8500_I2C4_BASE, + .end = U8500_I2C4_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_I2C4, + .end = IRQ_I2C4, + .flags = IORESOURCE_IRQ, + } +}; + +struct platform_device u8500_i2c4_device = { + .name = "STM-I2C", + .id = 4, + .resource = u8500_i2c4_resources, + .num_resources = ARRAY_SIZE(u8500_i2c4_resources), +}; + +#define NUM_SSP_CLIENTS 10 + +static struct nmdk_spi_master_cntlr ssp0_platform_data = { + .enable_dma = 1, + .id = SSP_0_CONTROLLER, + .num_chipselect = NUM_SSP_CLIENTS, + .base_addr = U8500_SSP0_BASE, + .rx_fifo_addr = U8500_SSP0_BASE + SSP_TX_RX_REG_OFFSET, + .rx_fifo_dev_type = DMA_DEV_SSP0_RX, + .tx_fifo_addr = U8500_SSP0_BASE + SSP_TX_RX_REG_OFFSET, + .tx_fifo_dev_type = DMA_DEV_SSP0_TX, + .gpio_alt_func = GPIO_ALT_SSP_0, + .device_name = "ssp0", +}; + +struct amba_device u8500_ssp0_device = { + .dev = { + .bus_id = "ssp0", + .platform_data = &ssp0_platform_data, + }, + .res = { + .start = U8500_SSP0_BASE, + .end = U8500_SSP0_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + .dma_mask = DMA_BIT_MASK(32), + .irq = {IRQ_SSP0, NO_IRQ}, + .periphid = SSP_PER_ID, +}; + +static struct nmdk_spi_master_cntlr ssp1_platform_data = { + .enable_dma = 1, + .id = SSP_1_CONTROLLER, + .num_chipselect = NUM_SSP_CLIENTS, + .base_addr = U8500_SSP1_BASE, + .rx_fifo_addr = U8500_SSP1_BASE + SSP_TX_RX_REG_OFFSET, + .rx_fifo_dev_type = DMA_DEV_SSP1_RX, + .tx_fifo_addr = U8500_SSP1_BASE + SSP_TX_RX_REG_OFFSET, + .tx_fifo_dev_type = DMA_DEV_SSP1_TX, + .gpio_alt_func = GPIO_ALT_SSP_1, + .device_name = "ssp1", +}; + +struct amba_device u8500_ssp1_device = { + .dev = { + .bus_id = "ssp1", + .platform_data = &ssp1_platform_data, + }, + .res = { + .start = U8500_SSP1_BASE, + .end = U8500_SSP1_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + .dma_mask = DMA_BIT_MASK(32), + .irq = {IRQ_SSP1, NO_IRQ}, + .periphid = SSP_PER_ID, +}; diff --git a/arch/arm/mach-ux500/devices.c b/arch/arm/mach-ux500/devices.c new file mode 100644 index 00000000000..98c906ecd7f --- /dev/null +++ b/arch/arm/mach-ux500/devices.c @@ -0,0 +1,1094 @@ +/* + * Copyright (C) 2009 ST Ericsson. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + */ +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/sysdev.h> +#include <linux/amba/bus.h> +#include <linux/amba/serial.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/i2s/i2s.h> +#include <linux/i2c.h> +#include <linux/gpio.h> +#include <linux/usb/musb.h> +#include <linux/regulator/machine.h> +#include <linux/dma-mapping.h> + +#include <asm/irq.h> + +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/hardware/cache-l2x0.h> +#include <mach/irqs.h> +#include <mach/hardware.h> +#include <mach/devices.h> +#include <asm/dma.h> +#include <mach/dma.h> +#include <linux/spi/spi.h> +#include <linux/spi/spi-stm.h> +#include <linux/mmc/host.h> +#include <asm/setup.h> +#include <linux/android_pmem.h> +#include <mach/msp.h> +#include <mach/i2c-stm.h> +#include <mach/shrm.h> +#include <mach/mmc.h> +#include <mach/ab8500.h> +#include <mach/stmpe2401.h> +#include <mach/tc35892.h> +#include <mach/uart.h> +#include <mach/setup.h> + +void __init u8500_register_device(struct platform_device *dev, void *data) +{ + int ret; + + dev->dev.platform_data = data; + + ret = platform_device_register(dev); + if (ret) + dev_err(&dev->dev, "unable to register device: %d\n", ret); +} + +void __init u8500_register_amba_device(struct amba_device *dev, void *data) +{ + int ret; + + dev->dev.platform_data = data; + + ret = amba_device_register(dev, &iomem_resource); + if (ret) + dev_err(&dev->dev, "unable to register device: %d\n", ret); +} + +#ifdef CONFIG_UX500_SOC_DB8500 +/* MSP is being used as a platform device because the perif id of all MSPs + * is same & hence probe would be called for + * 2 drivers namely: msp-spi & msp-i2s. + * Inorder to avoid this & bind a set of MSPs to each driver a platform + * bus is being used- binding based on name. + */ +static int msp_i2s_init(gpio_alt_function gpio) +{ + return stm_gpio_altfuncenable(gpio); +} + +static int msp_i2s_exit(gpio_alt_function gpio) +{ + return stm_gpio_altfuncdisable(gpio); +} + +static struct msp_i2s_platform_data msp0_platform_data = { + .id = MSP_0_I2S_CONTROLLER, + .gpio_alt_func = GPIO_ALT_MSP_0, + .msp_tx_dma_addr = DMA_DEV_MSP0_TX, + .msp_rx_dma_addr = DMA_DEV_MSP0_RX, + .msp_base_addr = U8500_MSP0_BASE, + .msp_i2s_init = msp_i2s_init, + .msp_i2s_exit = msp_i2s_exit, +}; +static struct resource u8500_msp_0_resources[] = { + [0] = { + .start = U8500_MSP0_BASE, + .end = U8500_MSP0_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_MSP0, + .end = IRQ_MSP0, + .flags = IORESOURCE_IRQ} +}; +struct platform_device u8500_msp0_device = { + .name = "MSP_I2S", + .id = 0, + .num_resources = 2, + .resource = u8500_msp_0_resources, + .dev = { + .bus_id = "msp0", + .platform_data = &msp0_platform_data, + }, + +}; +static struct msp_i2s_platform_data msp1_platform_data = { + .id = MSP_1_I2S_CONTROLLER, + .gpio_alt_func = GPIO_ALT_MSP_1, + .msp_tx_dma_addr = DMA_DEV_MSP1_TX, + .msp_rx_dma_addr = DMA_DEV_MSP1_RX, + .msp_base_addr = U8500_MSP1_BASE, + .msp_i2s_init = msp_i2s_init, + .msp_i2s_exit = msp_i2s_exit, +}; +static struct resource u8500_msp_1_resources[] = { + [0] = { + .start = U8500_MSP1_BASE, + .end = U8500_MSP1_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_MSP1, + .end = IRQ_MSP1, + .flags = IORESOURCE_IRQ} +}; +struct platform_device u8500_msp1_device = { + .name = "MSP_I2S", + .id = 1, + .num_resources = 2, + .resource = u8500_msp_1_resources, + .dev = { + .bus_id = "msp1", + .platform_data = &msp1_platform_data, + }, + +}; +static struct msp_i2s_platform_data msp2_platform_data = { + .id = MSP_2_I2S_CONTROLLER, + .gpio_alt_func = GPIO_ALT_MSP_2, + .msp_tx_dma_addr = DMA_DEV_MSP2_TX, + .msp_rx_dma_addr = DMA_DEV_MSP2_RX, + .msp_base_addr = U8500_MSP2_BASE, + .msp_i2s_init = msp_i2s_init, + .msp_i2s_exit = msp_i2s_exit, +}; + +static struct resource u8500_msp_2_resources[] = { + [0] = { + .start = U8500_MSP2_BASE, + .end = U8500_MSP2_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_MSP2, + .end = IRQ_MSP2, + .flags = IORESOURCE_IRQ + } +}; + +struct platform_device u8500_msp2_device = { + .name = "MSP_I2S", + .id = 2, + .num_resources = 2, + .resource = u8500_msp_2_resources, + .dev = { + .bus_id = "msp2", + .platform_data = &msp2_platform_data, + }, +}; +#endif + +#define NUM_MSP_CLIENTS 10 + +static struct nmdk_spi_master_cntlr msp2_spi_platform_data = { + .enable_dma = 1, + .id = MSP_2_CONTROLLER, + .num_chipselect = NUM_MSP_CLIENTS, + .base_addr = U8500_MSP2_BASE, + .rx_fifo_addr = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET, + .rx_fifo_dev_type = DMA_DEV_MSP2_RX, + .tx_fifo_addr = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET, + .tx_fifo_dev_type = DMA_DEV_MSP2_TX, + .gpio_alt_func = GPIO_ALT_MSP_2, + .device_name = "msp2", +}; + +struct amba_device u8500_msp2_spi_device = { + .dev = { + .bus_id = "msp2", + .platform_data = &msp2_spi_platform_data, + }, + .res = { + .start = U8500_MSP2_BASE, + .end = U8500_MSP2_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + .dma_mask = ~0, + .irq = {IRQ_MSP2, NO_IRQ}, + .periphid = MSP_PER_ID, +}; + +static struct resource ux500_i2c1_resources[] = { + [0] = { + .start = UX500_I2C1_BASE, + .end = UX500_I2C1_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_I2C1, + .end = IRQ_I2C1, + .flags = IORESOURCE_IRQ + } +}; + +struct platform_device ux500_i2c1_device = { + .name = "STM-I2C", + .id = 1, + .resource = ux500_i2c1_resources, + .num_resources = ARRAY_SIZE(ux500_i2c1_resources), +}; + +static struct resource ux500_i2c2_resources[] = { + [0] = { + .start = UX500_I2C2_BASE, + .end = UX500_I2C2_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_I2C2, + .end = IRQ_I2C2, + .flags = IORESOURCE_IRQ, + } +}; + +struct platform_device ux500_i2c2_device = { + .name = "STM-I2C", + .id = 2, + .resource = ux500_i2c2_resources, + .num_resources = ARRAY_SIZE(ux500_i2c2_resources), +}; + +static struct resource ux500_i2c3_resources[] = { + [0] = { + .start = UX500_I2C3_BASE, + .end = UX500_I2C3_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_I2C3, + .end = IRQ_I2C3, + .flags = IORESOURCE_IRQ, + } +}; + +struct platform_device ux500_i2c3_device = { + .name = "STM-I2C", + .id = 3, + .resource = ux500_i2c3_resources, + .num_resources = ARRAY_SIZE(ux500_i2c3_resources), +}; + +static struct shrm_plat_data shrm_platform_data = { + + .pshm_dev_data = 0 +}; + +static struct resource u8500_shrm_resources[] = { + [0] = { + .start = U8500_SHRM_GOP_INTERRUPT_BASE, + .end = U8500_SHRM_GOP_INTERRUPT_BASE + ((4*4)-1), + .name = "shrm_gop_register_base", + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_CA_WAKE_REQ_V1, + .end = IRQ_CA_WAKE_REQ_V1, + .name = "ca_irq_wake_req", + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = IRQ_AC_READ_NOTIFICATION_0_V1, + .end = IRQ_AC_READ_NOTIFICATION_0_V1, + .name = "ac_read_notification_0_irq", + .flags = IORESOURCE_IRQ, + }, + [3] = { + .start = IRQ_AC_READ_NOTIFICATION_1_V1, + .end = IRQ_AC_READ_NOTIFICATION_1_V1, + .name = "ac_read_notification_1_irq", + .flags = IORESOURCE_IRQ, + }, + [4] = { + .start = IRQ_CA_MSG_PEND_NOTIFICATION_0_V1, + .end = IRQ_CA_MSG_PEND_NOTIFICATION_0_V1, + .name = "ca_msg_pending_notification_0_irq", + .flags = IORESOURCE_IRQ, + }, + [5] = { + .start = IRQ_CA_MSG_PEND_NOTIFICATION_1_V1, + .end = IRQ_CA_MSG_PEND_NOTIFICATION_1_V1, + .name = "ca_msg_pending_notification_1_irq", + .flags = IORESOURCE_IRQ, + } +}; + +struct platform_device u8500_shrm_device = { + .name = "u8500_shrm", + .id = 0, + .dev = { + .bus_id = "shrm_bus", + .coherent_dma_mask = ~0, + .platform_data = &shrm_platform_data, + }, + + .num_resources = ARRAY_SIZE(u8500_shrm_resources), + .resource = u8500_shrm_resources +}; + +static struct resource b2r2_resources[] = { + [0] = { + .start = UX500_B2R2_BASE, + .end = UX500_B2R2_BASE + ((4*1024)-1), + .name = "b2r2_base", + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = PRCM_B2R2CLK_MGT_REG, + .end = PRCM_B2R2CLK_MGT_REG + (sizeof(u32) - 1), + .name = "prcm_b2r2_clk", + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device ux500_b2r2_device = { + .name = "U8500-B2R2", + .id = 0, + .dev = { + .bus_id = "b2r2_bus", + .coherent_dma_mask = ~0, + }, + .num_resources = ARRAY_SIZE(b2r2_resources), + .resource = b2r2_resources, +}; + +static void __init early_pmem_generic_parse(char **p, struct android_pmem_platform_data * data) +{ + data->size = memparse(*p, p); + if (**p == '@') + data->start = memparse(*p + 1, p); +} + +/******************************************************************************** + * Pmem device used by surface flinger + ********************************************************************************/ + +static struct android_pmem_platform_data pmem_pdata = { + .name = "pmem", + .no_allocator = 1, /* MemoryHeapBase is having an allocator */ + .cached = 1, + .start = 0, + .size = 0, +}; + +static void __init early_pmem(char **p) +{ + early_pmem_generic_parse(p, &pmem_pdata); +} +__early_param("pmem=", early_pmem); + +struct platform_device u8500_pmem_device = { + .name = "android_pmem", + .id = 0, + .dev = { + .platform_data = &pmem_pdata, + }, +}; + +/******************************************************************************** + * Pmem device used by PV video output node + ********************************************************************************/ + +static struct android_pmem_platform_data pmem_mio_pdata = { + .name = "pmem_mio", + .no_allocator = 1, /* We'll manage allocation */ + .cached = 1, + .start = 0, + .size = 0, +}; + +static void __init early_pmem_mio(char **p) +{ + early_pmem_generic_parse(p, &pmem_mio_pdata); +} +__early_param("pmem_mio=", early_pmem_mio); + +struct platform_device u8500_pmem_mio_device = { + .name = "android_pmem", + .id = 1, + .dev = { + .platform_data = &pmem_mio_pdata, + }, +}; + +/******************************************************************************** + * Pmem device used by OMX components allocating buffers + ********************************************************************************/ + +static struct android_pmem_platform_data pmem_hwb_pdata = { + .name = "pmem_hwb", + .no_allocator = 1, /* We'll manage allocation */ + .cached = 1, + .start = 0, + .size = 0, +}; + +static void __init early_pmem_hwb(char **p) +{ + early_pmem_generic_parse(p, &pmem_hwb_pdata); +} +__early_param("pmem_hwb=", early_pmem_hwb); + +struct platform_device u8500_pmem_hwb_device = { + .name = "android_pmem", + .id = 2, + .dev = { + .platform_data = &pmem_hwb_pdata, + }, +}; + +struct amba_device ux500_rtc_device = { + .dev = { + .bus_id = "mb:15", + }, + .res = { + .start = UX500_RTC_BASE, + .end = UX500_RTC_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + .irq = {IRQ_RTC_RTT, NO_IRQ}, + .periphid = RTC_PER_ID, +}; + +#include "clock.h" + +static struct map_desc ux500_io_desc[] __initdata = { + __IO_DEV_DESC(U8500_RTC_BASE, SZ_4K), + + __IO_DEV_DESC(U8500_MSP0_BASE, SZ_4K), + __IO_DEV_DESC(U8500_MSP1_BASE, SZ_4K), + __IO_DEV_DESC(U8500_MSP2_BASE, SZ_4K), + + __IO_DEV_DESC(UX500_UART0_BASE, SZ_4K), + __IO_DEV_DESC(UX500_UART1_BASE, SZ_4K), + __IO_DEV_DESC(UX500_UART2_BASE, SZ_4K), + + __IO_DEV_DESC(UX500_GIC_CPU_BASE, SZ_4K), + __IO_DEV_DESC(UX500_GIC_DIST_BASE, SZ_4K), + __IO_DEV_DESC(UX500_L2CC_BASE, SZ_4K), + + __IO_DEV_DESC(UX500_CLKRST1_BASE, SZ_4K), + __IO_DEV_DESC(UX500_CLKRST2_BASE, SZ_4K), + __IO_DEV_DESC(UX500_CLKRST3_BASE, SZ_4K), + __IO_DEV_DESC(UX500_CLKRST5_BASE, SZ_4K), + __IO_DEV_DESC(UX500_CLKRST6_BASE, SZ_4K), + + __IO_DEV_DESC(UX500_MTU0_BASE, SZ_4K), + __IO_DEV_DESC(UX500_MTU1_BASE, SZ_4K), + + __IO_DEV_DESC(UX500_BACKUPRAM0_BASE, SZ_8K), +}; + +static struct platform_device *ux500_platform_devs[] __initdata = { + &ux500_dma_device, +}; + +static struct amba_device *ux500_amba_devs[] __initdata = { + &ux500_rtc_device, +}; + +void __init ux500_init_devices(void) +{ + platform_add_devices(ux500_platform_devs, + ARRAY_SIZE(ux500_platform_devs)); + amba_add_devices(ux500_amba_devs, ARRAY_SIZE(ux500_amba_devs)); +} + +static struct resource ux500_dma_resources[] = { + [0] = { + .start = UX500_DMA_BASE, + .end = UX500_DMA_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_DMA, + .end = IRQ_DMA, + .flags = IORESOURCE_IRQ + }, +}; + +struct platform_device ux500_dma_device = { + .name = "STM-DMA", + .id = 0, + .num_resources = ARRAY_SIZE(ux500_dma_resources), + .resource = ux500_dma_resources +}; + +#define NUM_SPI023_CLIENTS 10 +static struct nmdk_spi_master_cntlr spi0_platform_data = { + .enable_dma = 1, + .id = SPI023_0_CONTROLLER, + .num_chipselect = NUM_SPI023_CLIENTS, + .base_addr = UX500_SPI0_BASE, + .rx_fifo_addr = UX500_SPI0_BASE + SPI_TX_RX_REG_OFFSET, + .rx_fifo_dev_type = DMA_DEV_SPI0_RX, + .tx_fifo_addr = UX500_SPI0_BASE + SPI_TX_RX_REG_OFFSET, + .tx_fifo_dev_type = DMA_DEV_SPI0_TX, + .gpio_alt_func = GPIO_ALT_SSP_0, + .device_name = "spi0", +}; + +struct amba_device ux500_spi0_device = { + .dev = { + .bus_id = "spi0", + .platform_data = &spi0_platform_data, + }, + .res = { + .start = UX500_SPI0_BASE, + .end = UX500_SPI0_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + .dma_mask = DMA_BIT_MASK(32), + .irq = {IRQ_SPI0, NO_IRQ}, + .periphid = SPI_PER_ID, +}; + +struct amba_device ux500_sdi0_device = { + .dev = { + .init_name = "sdi0", + }, + .res = { + .start = UX500_SDI0_BASE, + .end = UX500_SDI0_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + .irq = {IRQ_SDMMC0, NO_IRQ}, + .periphid = SDI_PER_ID, +}; + +struct amba_device ux500_sdi1_device = { + .dev = { + .init_name = "sdi1", + }, + .res = { + .start = UX500_SDI1_BASE, + .end = UX500_SDI1_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + .irq = {IRQ_SDMMC1, NO_IRQ}, + .periphid = SDI_PER_ID, +}; + +struct amba_device ux500_sdi2_device = { + .dev = { + .init_name = "sdi2", + }, + .res = { + .start = UX500_SDI2_BASE, + .end = UX500_SDI2_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + .irq = {IRQ_SDMMC2, NO_IRQ}, + .periphid = SDI_PER_ID, +}; + +struct amba_device ux500_sdi4_device = { + .dev = { + .init_name = "sdi4", + }, + .res = { + .start = UX500_SDI4_BASE, + .end = UX500_SDI4_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + .irq = {IRQ_SDMMC4, NO_IRQ}, + .periphid = SDI_PER_ID, +}; + +static struct resource ab8500_resources[] = { + [0] = { + .start = STW4500_IRQ, + .end = STW4500_IRQ, + .flags = IORESOURCE_IRQ + } +}; + +/** + * ab8500_spi_cs_enable - disables the chip select for STw4500 + */ +void ab8500_spi_cs_enable(void) +{ + +} + +/** + * ab8500_spi_cs_disable - enables the chip select for STw4500 + */ +void ab8500_spi_cs_disable(void) +{ + +} + +static struct ab8500_device ab8500_board = { + .cs_en = ab8500_spi_cs_enable, + .cs_dis = ab8500_spi_cs_disable, + .ssp_controller = SSP_0_CONTROLLER, +}; + +struct platform_device u8500_ab8500_device = { + .name = "ab8500", + .id = 0, + .dev = { + .platform_data = &ab8500_board, + }, + .num_resources = 1, + .resource = ab8500_resources, +}; + +#if defined(CONFIG_USB_MUSB_HOST) +#define MUSB_MODE MUSB_HOST +#elif defined(CONFIG_USB_MUSB_PERIPHERAL) +#define MUSB_MODE MUSB_PERIPHERAL +#elif defined(CONFIG_USB_MUSB_OTG) +#define MUSB_MODE MUSB_OTG +#else +#define MUSB_MODE MUSB_UNDEFINED +#endif +static struct musb_hdrc_config musb_hdrc_hs_otg_config = { + .multipoint = true, /* multipoint device */ + .dyn_fifo = true, /* supports dynamic fifo sizing */ + .num_eps = 16, /* number of endpoints _with_ ep0 */ + .ram_bits = 16, /* ram address size */ +}; + +static struct musb_hdrc_platform_data musb_hdrc_hs_otg_platform_data = { + .mode = MUSB_MODE, + .clock = "usb", /* for clk_get() */ + .config = &musb_hdrc_hs_otg_config, +}; + +static struct resource usb_resources[] = { + [0] = { + .name = "usb-mem", + .start = UX500_USBOTG_BASE, + .end = (UX500_USBOTG_BASE + SZ_64K - 1), + .flags = IORESOURCE_MEM, + }, + + [1] = { + .name = "usb-irq", + .start = IRQ_USBOTG, + .end = IRQ_USBOTG, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device ux500_musb_device = { + .name = "musb_hdrc", + .id = 0, + .dev = { + .bus_id = "musb_hdrc.0", /* for clk_get() */ + .platform_data = &musb_hdrc_hs_otg_platform_data, + .dma_mask = (u64 *)0xFFFFFFFF, + .coherent_dma_mask = (u64)0xFFFFFFFF + }, + .num_resources = ARRAY_SIZE(usb_resources), + .resource = usb_resources, +}; + +void __init ux500_map_io(void) +{ + iotable_init(ux500_io_desc, ARRAY_SIZE(ux500_io_desc)); +} + +void __init u8500_init_irq(void) +{ + gic_dist_init(0, (void __iomem *)IO_ADDRESS(UX500_GIC_DIST_BASE), 29); + gic_cpu_init(0, (void __iomem *)IO_ADDRESS(UX500_GIC_CPU_BASE)); + + /* + * Init clocks here so that they are available for system timer + * initialization. + */ + clk_init(); +} + +static void uart0_init(void) +{ + stm_gpio_altfuncenable(GPIO_ALT_UART_0_NO_MODEM); +} + +static void uart0_exit(void) +{ + stm_gpio_altfuncdisable(GPIO_ALT_UART_0_NO_MODEM); +} + +struct uart_amba_plat_data uart0_plat = { + .init = uart0_init, + .exit = uart0_exit, +}; + +static void uart1_init(void) +{ + stm_gpio_altfuncenable(GPIO_ALT_UART_1); +} + +static void uart1_exit(void) +{ + stm_gpio_altfuncdisable(GPIO_ALT_UART_1); +} + +struct uart_amba_plat_data uart1_plat = { + .init = uart1_init, + .exit = uart1_exit, +}; + +static void uart2_init(void) +{ + stm_gpio_altfuncenable(GPIO_ALT_UART_2); +} + +static void uart2_exit(void) +{ + stm_gpio_altfuncdisable(GPIO_ALT_UART_2); +} + +struct uart_amba_plat_data uart2_plat = { + .init = uart2_init, + .exit = uart2_exit, +}; + +#define __MEM_4K_RESOURCE(x) \ + .res = {.start = (x), .end = (x) + SZ_4K - 1, .flags = IORESOURCE_MEM} + +/* These are active devices on this board, FIXME + * move this to board file + */ +#if defined(CONFIG_MACH_U5500_SIMULATOR) +/* Remap of uart0 and uart2 when using SVP5500 + * remove this when uart2 problem solved in SVP5500 + */ +struct amba_device ux500_uart2_device = { + .dev = {.bus_id = "uart2", .platform_data = &uart0_plat, }, + __MEM_4K_RESOURCE(UX500_UART0_BASE), + .irq = {IRQ_UART0, NO_IRQ}, +}; + +struct amba_device ux500_uart1_device = { + .dev = {.bus_id = "uart1", .platform_data = &uart1_plat, }, + __MEM_4K_RESOURCE(UX500_UART1_BASE), + .irq = {IRQ_UART1, NO_IRQ}, +}; + +struct amba_device ux500_uart0_device = { + .dev = {.bus_id = "uart0", .platform_data = &uart2_plat, }, + __MEM_4K_RESOURCE(UX500_UART2_BASE), + .irq = {IRQ_UART2, NO_IRQ}, +}; +#else +struct amba_device ux500_uart0_device = { + .dev = {.bus_id = "uart0", .platform_data = &uart0_plat, }, + __MEM_4K_RESOURCE(UX500_UART0_BASE), + .irq = {IRQ_UART0, NO_IRQ}, +}; + +struct amba_device ux500_uart1_device = { + .dev = {.bus_id = "uart1", .platform_data = &uart1_plat, }, + __MEM_4K_RESOURCE(UX500_UART1_BASE), + .irq = {IRQ_UART1, NO_IRQ}, +}; + +struct amba_device ux500_uart2_device = { + .dev = {.bus_id = "uart2", .platform_data = &uart2_plat, }, + __MEM_4K_RESOURCE(UX500_UART2_BASE), + .irq = {IRQ_UART2, NO_IRQ}, +}; + +#endif + +#ifdef CONFIG_CACHE_L2X0 +static int __init u8500_l2x0_init(void) +{ + l2x0_init((void *)IO_ADDRESS(UX500_L2CC_BASE), 0x3e060000, 0x3e060000); + return 0; +} +early_initcall(u8500_l2x0_init); +#endif + +void __init amba_add_devices(struct amba_device *devs[], int num) +{ + int i; + + for (i = 0; i < num; i++) { + struct amba_device *d = devs[i]; + amba_device_register(d, &iomem_resource); + } +} + +/* U8500 Power section */ +#ifdef CONFIG_REGULATOR + +#define U8500_VAPE_REGULATOR_MIN_VOLTAGE (1800000) +#define U8500_VAPE_REGULATOR_MAX_VOLTAGE (2000000) + +static int db8500_vape_regulator_init(void) +{ return 0; } + +/* tying VAPE regulator to symbolic consumer devices */ +static struct regulator_consumer_supply db8500_vape_consumers[] = { + { + .supply = "v-ape", + }, +}; + +/* VAPE supply, for interconnect */ +static struct regulator_init_data db8500_vape_init = { + .supply_regulator_dev = NULL, + .constraints = { + .name = "DB8500-VAPE", + .min_uV = U8500_VAPE_REGULATOR_MIN_VOLTAGE, + .max_uV = U8500_VAPE_REGULATOR_MAX_VOLTAGE, + .input_uV = 1, /* notional, for set_mode* */ + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE| + REGULATOR_CHANGE_MODE|REGULATOR_CHANGE_DRMS, + .valid_modes_mask = REGULATOR_MODE_NORMAL|REGULATOR_MODE_IDLE, + }, + .num_consumer_supplies = ARRAY_SIZE(db8500_vape_consumers), + .regulator_init = db8500_vape_regulator_init, + .consumer_supplies = db8500_vape_consumers, +}; + +static struct platform_device db8500_vape_regulator_dev = { + .name = "db8500-regulator", + .id = 0, + .dev = { + .platform_data = &db8500_vape_init, + }, +}; + +/* VANA Supply, for analogue part of displays */ +#define U8500_VANA_REGULATOR_MIN_VOLTAGE (0) +#define U8500_VANA_REGULATOR_MAX_VOLTAGE (1200000) + +static int db8500_vana_regulator_init(void) { return 0; } + +static struct regulator_consumer_supply db8500_vana_consumers[] = { +#ifdef CONFIG_FB_U8500_MCDE_CHANNELA + { + .dev = &u8500_mcde0_device.dev, + .supply = "v-ana", + }, +#endif +#ifdef CONFIG_FB_U8500_MCDE_CHANNELB + { + .dev = &u8500_mcde1_device.dev, + .supply = "v-ana", + }, +#endif +#ifdef CONFIG_FB_U8500_MCDE_CHANNELC0 + { + .dev = &u8500_mcde2_device.dev, + .supply = "v-ana", + }, +#endif +#ifdef CONFIG_FB_U8500_MCDE_CHANNELC1 + { + .dev = &u8500_mcde3_device.dev, + .supply = "v-ana", + }, +#endif +}; + +static struct regulator_init_data db8500_vana_init = { + .supply_regulator_dev = NULL, + .constraints = { + .name = "VANA", + .min_uV = U8500_VANA_REGULATOR_MIN_VOLTAGE, + .max_uV = U8500_VANA_REGULATOR_MAX_VOLTAGE, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_MODE, + .valid_modes_mask = REGULATOR_MODE_NORMAL | + REGULATOR_MODE_IDLE, + }, + .num_consumer_supplies = ARRAY_SIZE(db8500_vana_consumers), + .regulator_init = db8500_vana_regulator_init, + .consumer_supplies = db8500_vana_consumers, +}; + +static struct platform_device db8500_vana_regulator_dev = { + .name = "db8500-regulator", + .id = 1, + .dev = { + .platform_data = &db8500_vana_init, + }, +}; + +/* VAUX1 supply */ +#define AB8500_VAUXN_LDO_MIN_VOLTAGE (1100000) +#define AB8500_VAUXN_LDO_MAX_VOLTAGE (3300000) + +static int ab8500_vaux1_regulator_init(void) { return 0; } + +static struct regulator_consumer_supply ab8500_vaux1_consumers[] = { +#ifdef CONFIG_FB_U8500_MCDE_CHANNELA + { + .dev = &u8500_mcde0_device.dev, + .supply = "v-mcde", + }, +#endif +#ifdef CONFIG_FB_U8500_MCDE_CHANNELB + { + .dev = &u8500_mcde1_device.dev, + .supply = "v-mcde", + }, +#endif +#ifdef CONFIG_FB_U8500_MCDE_CHANNELC0 + { + .dev = &u8500_mcde2_device.dev, + .supply = "v-mcde", + }, +#endif +#ifdef CONFIG_FB_U8500_MCDE_CHANNELC1 + { + .dev = &u8500_mcde3_device.dev, + .supply = "v-mcde", + }, +#endif +}; + +static struct regulator_init_data ab8500_vaux1_init = { + .supply_regulator_dev = NULL, + .constraints = { + .name = "AB8500-VAUX1", + .min_uV = AB8500_VAUXN_LDO_MIN_VOLTAGE, + .max_uV = AB8500_VAUXN_LDO_MIN_VOLTAGE, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE| + REGULATOR_CHANGE_MODE, + .valid_modes_mask = REGULATOR_MODE_NORMAL|REGULATOR_MODE_IDLE, + }, + .num_consumer_supplies = ARRAY_SIZE(ab8500_vaux1_consumers), + .regulator_init = ab8500_vaux1_regulator_init, + .consumer_supplies = ab8500_vaux1_consumers, +}; + +/* as the vaux2 is not a u8500 specific regulator, it is named + * as the ab8500 series */ +static struct platform_device ab8500_vaux1_regulator_dev = { + .name = "ab8500-regulator", + .id = 0, + .dev = { + .platform_data = &ab8500_vaux1_init, + }, +}; + +/* VAUX2 supply */ +static int ab8500_vaux2_regulator_init(void) { return 0; } + +/* supply for on-board eMMC */ +static struct regulator_consumer_supply ab8500_vaux2_consumers[] = { + { + .dev = &u8500_sdi4_device.dev, + .supply = "v-eMMC", + } +}; + +static struct regulator_init_data ab8500_vaux2_init = { + .supply_regulator_dev = NULL, + .constraints = { + .name = "AB8500-VAUX2", + .min_uV = AB8500_VAUXN_LDO_MIN_VOLTAGE, + .max_uV = AB8500_VAUXN_LDO_MAX_VOLTAGE, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE| + REGULATOR_CHANGE_MODE, + .valid_modes_mask = REGULATOR_MODE_NORMAL|REGULATOR_MODE_IDLE, + }, + .num_consumer_supplies = ARRAY_SIZE(ab8500_vaux2_consumers), + .regulator_init = ab8500_vaux2_regulator_init, + .consumer_supplies = ab8500_vaux2_consumers, +}; + +static struct platform_device ab8500_vaux2_regulator_dev = { + .name = "ab8500-regulator", + .id = 1, + .dev = { + .platform_data = &ab8500_vaux2_init, + }, +}; + +/* supply for tvout, gpadc, TVOUT LDO */ +#define AB8500_VTVOUT_LDO_MIN_VOLTAGE (0) +#define AB8500_VTVOUT_LDO_MAX_VOLTAGE (2000000) + +static int ab8500_vtvout_regulator_init(void) { return 0; } + +static struct regulator_consumer_supply ab8500_vtvout_consumers[] = { +}; + +static struct regulator_init_data ab8500_vtvout_init = { + .supply_regulator_dev = NULL, + .constraints = { + .name = "AB8500-VTVOUT", + .min_uV = AB8500_VTVOUT_LDO_MIN_VOLTAGE, + .max_uV = AB8500_VTVOUT_LDO_MAX_VOLTAGE, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE| + REGULATOR_CHANGE_MODE, + .valid_modes_mask = REGULATOR_MODE_NORMAL|REGULATOR_MODE_IDLE, + }, + .num_consumer_supplies = ARRAY_SIZE(ab8500_vtvout_consumers), + .regulator_init = ab8500_vtvout_regulator_init, + .consumer_supplies = ab8500_vtvout_consumers, +}; + +static struct platform_device ab8500_vtvout_regulator_dev = { + .name = "ab8500-regulator", + .id = 2, + .dev = { + .platform_data = &ab8500_vtvout_init, + }, +}; + +/* supply for usb, VBUS LDO */ +#define AB8500_VBUS_REGULATOR_MIN_VOLTAGE (0) +#define AB8500_VBUS_REGULATOR_MAX_VOLTAGE (5000000) + +static int ab8500_vbus_regulator_init(void) { return 0; } + +static struct regulator_consumer_supply ab8500_vbus_consumers[] = { + { + .supply = "v-bus", + } +}; + +static struct regulator_init_data ab8500_vbus_init = { + .supply_regulator_dev = NULL, + .constraints = { + .name = "AB8500-VBUS", + .min_uV = AB8500_VBUS_REGULATOR_MIN_VOLTAGE, + .max_uV = AB8500_VBUS_REGULATOR_MAX_VOLTAGE, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE| + REGULATOR_CHANGE_MODE, + .valid_modes_mask = REGULATOR_MODE_NORMAL|REGULATOR_MODE_IDLE, + }, + .num_consumer_supplies = ARRAY_SIZE(ab8500_vbus_consumers), + .regulator_init = ab8500_vbus_regulator_init, + .consumer_supplies = ab8500_vbus_consumers, +}; + +static struct platform_device ab8500_vbus_regulator_dev = { + .name = "ab8500-regulator", + .id = 3, + .dev = { + .platform_data = &ab8500_vbus_init, + }, +}; + +static struct platform_device *u8500_regulators[] = { + &db8500_vape_regulator_dev, + &db8500_vana_regulator_dev, + &ab8500_vaux1_regulator_dev, + &ab8500_vaux2_regulator_dev, + &ab8500_vtvout_regulator_dev, + &ab8500_vbus_regulator_dev, +}; + +#endif + +/* FIXME: move this to the appropriate file */ +void __init u8500_init_regulators(void) +{ +#ifdef CONFIG_REGULATOR + /* we want the on-chip regulator before any device registration */ + platform_add_devices(u8500_regulators, ARRAY_SIZE(u8500_regulators)); +#endif +} diff --git a/arch/arm/mach-ux500/dma_40.c b/arch/arm/mach-ux500/dma_40.c new file mode 100755 index 00000000000..b1b84a9e25c --- /dev/null +++ b/arch/arm/mach-ux500/dma_40.c @@ -0,0 +1,3903 @@ +/*----------------------------------------------------------------------------*/ +/* Copyright STMicroelectronics, 2008. */ +/* */ +/* This program is free software; you can redistribute it and/or modify it */ +/* under the terms of the GNU General Public License as published by the Free */ +/* Software Foundation; either version 2.1 of the License, or (at your option)*/ +/* any later version. */ +/* */ +/* This program is distributed in the hope that it will be useful, but */ +/* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY */ +/* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public */ +/* License for more details. */ +/* */ +/* You should have received a copy of the GNU General Public License */ +/* along with this program. If not, see <http://www.gnu.org/licenses/>. */ +/*----------------------------------------------------------------------------*/ + +#include <linux/module.h> +#include <linux/init.h> +#include <linux/delay.h> +#include <linux/interrupt.h> +#include <linux/errno.h> +#include <linux/sched.h> +#include <linux/mm.h> +#include <linux/platform_device.h> +#include <linux/cpufreq.h> +#include <linux/dma-mapping.h> +#include <linux/spinlock.h> +#include <linux/scatterlist.h> +#include <linux/uaccess.h> +#include <linux/clk.h> +#include <asm/page.h> +#include <asm/fiq.h> +#include <asm/irq.h> +#include <mach/hardware.h> +#include <mach/memory.h> +#include <mach/debug.h> + +#include <mach/dma.h> + +#ifndef CONFIG_U8500_SECURE +/* Define this macro if in non-secure mode */ +#define CONFIG_STM_SECURITY +#endif + +#define DRIVER_NAME "DRIVER DMA" + +/* enables/disables debug msgs */ +#define DRIVER_DEBUG 0 +#define DRIVER_DEBUG_PFX DRIVER_NAME +#define DRIVER_DBG KERN_ERR + +#define MAX_BACKUP_REGS 24 + +struct dma_addr { + dma_addr_t phys_addr; + void *log_addr; +}; + +/** + * struct elem_pool - Structure of element pool + * @name: Name of the Element pool + * @allocation_map: Whether a pool element is allocated or not + * @lchan_allocation_map: Pool allocation map for Logical channels, + * (for each phy res) + * @num_blocks: Number of elements in the pool + * @block_size: Size of each element in the pool + * @allocation_size: Total memory allocated for the pool + * @unalign_base: Unaligned Base address of pool + * @base_addr: Aligned base address of pool + * + * + **/ +struct elem_pool { + char name[20]; + spinlock_t pool_lock; + u32 allocation_map; + u32 lchan_allocation_map[MAX_PHYSICAL_CHANNELS]; + int num_blocks; + int block_size; + int allocation_size; + struct dma_addr unalign_base; + struct dma_addr base_addr; +}; + +/** + * struct dma_driver_data - DMA driver private data structure + * @reg_base: pointer to DMA controller Register area + * @dma_chan_info: Array of pointer to channel info structure. + * It is used by DMA driver internally to access information + * of each channel (Physical or Logical). It is accessed in + * the interrupt handler also. + * @pipe_info: Array of pointers to channel info structure, used + * access channel info structure when client makes a request. + * pipe_id used by client in all requests is an entry + * in this array. + * @pipe_id_map: Map from where we allocate ID's to client drivers. + * If a particular bit is set in this map, it means that + * particular id can be given to a client. + * @pipe_id_lock: Mutex to provide access to pipe_id_map + * @pr_info: stores current status of all physical resources + * whether physical channel or Logical channel. + * If Logical then count of how many channels are there + * @pr_info_lock: Lock to synchronise access to pr_info + * @cfg_lock: Lock to synchronize access to write on DMA registers + * @lchan_params_base: Base address where logical channel params are + * stored. + * @pchan_lli_pool: Pool from where LLI's are allocated for phy channels + * @sg_pool: Pool from where SG blocks are allocated to keep SG info + * @lchan_lli_pool: Pool from where LLI's are allocated for Log channels + * @backup_regs: Used to store and restore DMA regs during suspend resume. + * + **/ + +struct dma_driver_data { + void __iomem *reg_base; + struct clk *clk; + struct dma_channel_info *dma_chan_info[NUM_CHANNELS]; + struct dma_channel_info *pipe_info[NUM_CHANNELS]; + DECLARE_BITMAP(pipe_id_map, NUM_CHANNELS); + spinlock_t pipe_id_lock; + struct phy_res_info pr_info[MAX_AVAIL_PHY_CHANNELS]; + spinlock_t pr_info_lock; + struct dma_addr lchan_params_base; + struct elem_pool *pchan_lli_pool; + struct elem_pool *sg_pool; + struct elem_pool *lchan_lli_pool; + spinlock_t cfg_ch_lock[MAX_AVAIL_PHY_CHANNELS]; + u32 backup_regs[MAX_BACKUP_REGS]; +}; +static struct dma_driver_data *dma_drv_data; + +static inline void __iomem *io_addr(unsigned int offset) +{ + return dma_drv_data->reg_base + offset; +} + +static inline void __iomem *cio_addr(unsigned int phys_chan_id, + unsigned int offset) +{ + return dma_drv_data->reg_base + 0x400 + (phys_chan_id * (8 * 4)) + + offset; +} + +/** + * print_sg_info() - To Print info of the scatter gather list items + * @sg: Pointer to sg List which you want to print + * @nents: Number of elements in the list + * + **/ +static void print_sg_info(struct scatterlist *sg, int nents) +{ + int i = 0; + stm_dbg(DBG_ST.dma, "Scatter Gather info........\n"); + for (i = 0; i < nents; i++) { + stm_dbg(DBG_ST.dma, "SG[%d] , dma_addr = %x\n", i, + sg[i].dma_address); + stm_dbg(DBG_ST.dma, "SG[%d] , length = %d\n", i, sg[i].length); + stm_dbg(DBG_ST.dma, "SG[%d] , offset = %d\n", i, sg[i].offset); + } +} + +/** + * print_dma_lli() - To Print the Information that we stored in LLI Struct + * @idx: LLI number whose info we are printing + * @lli: LLI structure whose value would be printed + * + **/ +static void print_dma_lli(int idx, struct dma_lli_info *lli) +{ + stm_dbg(DBG_ST.dma, "---------------------------------\n"); + stm_dbg(DBG_ST.dma, "##### %x\n", (u32) lli); + stm_dbg(DBG_ST.dma, "LLI[%d]:: Link Register\t %x\n", idx, + lli->reg_lnk); + stm_dbg(DBG_ST.dma, "LLI[%d]:: Pointer Register\t %x\n", idx, + lli->reg_ptr); + stm_dbg(DBG_ST.dma, "LLI[%d]:: Element Register\t %x\n", idx, + lli->reg_elt); + stm_dbg(DBG_ST.dma, "LLI[%d]:: Config Register\t %x\n", idx, + lli->reg_cfg); + stm_dbg(DBG_ST.dma, "---------------------------------\n"); +} + +/** + * print_allocation_map() - To print Allocation map of Pipe Ids given to client + * + */ +static void print_allocation_map(void) +{ + stm_dbg(DBG_ST.dma, + "==================================================\n"); + stm_dbg(DBG_ST.dma, "=====pipe_id_map(0) = %x\n", + (u32) dma_drv_data->pipe_id_map[0]); + stm_dbg(DBG_ST.dma, "=====pipe_id_map(1) = %x\n", + (u32) dma_drv_data->pipe_id_map[1]); + stm_dbg(DBG_ST.dma, "=====pipe_id_map(2) = %x\n", + (u32) dma_drv_data->pipe_id_map[2]); + stm_dbg(DBG_ST.dma, "=====pipe_id_map(3) = %x\n", + (u32) dma_drv_data->pipe_id_map[3]); + stm_dbg(DBG_ST.dma, "=====pipe_id_map(4) = %x\n", + (u32) dma_drv_data->pipe_id_map[4]); + stm_dbg(DBG_ST.dma, + "==================================================\n"); +} + +/** + * initialize_dma_regs() - To Initialize the DMA global registers + * + */ +static inline void initialize_dma_regs(void) +{ + /* + * Some registers can only be touched in secure mode. Normally, we + * will not modify these registers, as xloader would initialize these + * registers for us. + * + * It appears that we are allowed a write if we don't change the value + * of the register. + */ + +#ifndef CONFIG_STM_SECURITY + REG_WR_BITS(io_addr(DREG_GCC), 0xff01, FULL32_MASK, NO_SHIFT); +#else + REG_WR_BITS(io_addr(DREG_GCC), 0x0, FULL32_MASK, NO_SHIFT); +#endif + + /*All resources are standard */ + REG_WR_BITS(io_addr(DREG_PRTYP), 0x55555555, FULL32_MASK, NO_SHIFT); + /*All in non secure mode */ + REG_WR_BITS(io_addr(DREG_PRSME), 0xaaaaaaaa, FULL32_MASK, NO_SHIFT); + REG_WR_BITS(io_addr(DREG_PRSMO), 0xaaaaaaaa, FULL32_MASK, NO_SHIFT); + /*Basic mode */ + REG_WR_BITS(io_addr(DREG_PRMSE), 0x55555555, FULL32_MASK, NO_SHIFT); + /*Basic mode */ + REG_WR_BITS(io_addr(DREG_PRMSO), 0x55555555, FULL32_MASK, NO_SHIFT); + /*Basic mode */ + REG_WR_BITS(io_addr(DREG_PRMOE), 0x55555555, FULL32_MASK, NO_SHIFT); + /*Basic mode */ + REG_WR_BITS(io_addr(DREG_PRMOO), 0x55555555, FULL32_MASK, NO_SHIFT); + /***************************************************************/ + /*Currently dont modify as we are only using basic mode and not logical */ + REG_WR_BITS(io_addr(DREG_LCPA), 0x0, FULL32_MASK, NO_SHIFT); + REG_WR_BITS(io_addr(DREG_LCLA), 0x0, FULL32_MASK, NO_SHIFT); + REG_WR_BITS(io_addr(DREG_SLCPA), 0x0, FULL32_MASK, NO_SHIFT); + REG_WR_BITS(io_addr(DREG_SLCLA), 0x0, FULL32_MASK, NO_SHIFT); + /***************************************************************/ + /*Registers to activate channels */ + REG_WR_BITS(io_addr(DREG_ACTIVE), 0x0, FULL32_MASK, NO_SHIFT); + REG_WR_BITS(io_addr(DREG_ACTIVO), 0x0, FULL32_MASK, NO_SHIFT); + /***************************************************************/ + REG_WR_BITS(io_addr(DREG_FSEB1), 0x0, FULL32_MASK, NO_SHIFT); + REG_WR_BITS(io_addr(DREG_FSEB2), 0x0, FULL32_MASK, NO_SHIFT); + /***************************************************************/ + /*Allow all interrupts */ + REG_WR_BITS(io_addr(DREG_PCMIS), 0xFFFFFFFF, FULL32_MASK, NO_SHIFT); + /*Clear all interrupts */ + REG_WR_BITS(io_addr(DREG_PCICR), 0xFFFFFFFF, FULL32_MASK, NO_SHIFT); + + REG_WR_BITS(io_addr(DREG_SPCMIS), 0xFFFFFFFF, FULL32_MASK, NO_SHIFT); + REG_WR_BITS(io_addr(DREG_SPCICR), 0xFFFFFFFF, FULL32_MASK, NO_SHIFT); + + REG_WR_BITS(io_addr(DREG_LCMIS(0)), 0xFFFFFFFF, FULL32_MASK, NO_SHIFT); + REG_WR_BITS(io_addr(DREG_LCMIS(1)), 0xFFFFFFFF, FULL32_MASK, NO_SHIFT); + REG_WR_BITS(io_addr(DREG_LCMIS(2)), 0xFFFFFFFF, FULL32_MASK, NO_SHIFT); + REG_WR_BITS(io_addr(DREG_LCMIS(3)), 0xFFFFFFFF, FULL32_MASK, NO_SHIFT); + + REG_WR_BITS(io_addr(DREG_LCICR(0)), 0xFFFFFFFF, FULL32_MASK, NO_SHIFT); + REG_WR_BITS(io_addr(DREG_LCICR(1)), 0xFFFFFFFF, FULL32_MASK, NO_SHIFT); + REG_WR_BITS(io_addr(DREG_LCICR(2)), 0xFFFFFFFF, FULL32_MASK, NO_SHIFT); + REG_WR_BITS(io_addr(DREG_LCICR(3)), 0xFFFFFFFF, FULL32_MASK, NO_SHIFT); + + REG_WR_BITS(io_addr(DREG_LCTIS(0)), 0xFFFFFFFF, FULL32_MASK, NO_SHIFT); + REG_WR_BITS(io_addr(DREG_LCTIS(1)), 0xFFFFFFFF, FULL32_MASK, NO_SHIFT); + REG_WR_BITS(io_addr(DREG_LCTIS(2)), 0xFFFFFFFF, FULL32_MASK, NO_SHIFT); + REG_WR_BITS(io_addr(DREG_LCTIS(3)), 0xFFFFFFFF, FULL32_MASK, NO_SHIFT); +} + +/** + * print_channel_reg_params() - To print Channel registers of the physical + * channel for debug + * @channel: Physical channel whose register values to be printed + * + */ +static inline void print_channel_reg_params(int channel) +{ + if ((channel < 0) || (channel > MAX_AVAIL_PHY_CHANNELS)) { + stm_dbg(DBG_ST.dma, "Invalid channel number...."); + return; + } + stm_dbg(DBG_ST.dma, + "\n===================================================\n"); + stm_dbg(DBG_ST.dma, "\t\tChannel params %d\n", channel); + stm_dbg(DBG_ST.dma, + "\n===================================================\n"); + stm_dbg(DBG_ST.dma, "CHANNEL_params_regs (CHAN_REG_sscfg_excfg)=%x\n", + ioread32(cio_addr(channel, CHAN_REG_SSCFG))); + stm_dbg(DBG_ST.dma, "CHANNEL_params_regs (CHAN_REG_sselt_exelt)=%x\n", + ioread32(cio_addr(channel, CHAN_REG_SSELT))); + stm_dbg(DBG_ST.dma, "CHANNEL_params_regs (CHAN_REG_ssptr_exptr)=%x\n", + ioread32(cio_addr(channel, CHAN_REG_SSPTR))); + stm_dbg(DBG_ST.dma, "CHANNEL_params_regs (CHAN_REG_sslnk_exlnk)=%x\n", + ioread32(cio_addr(channel, CHAN_REG_SSLNK))); + stm_dbg(DBG_ST.dma, "CHANNEL_params_regs (CHAN_REG_sdcfg_exexc)=%x\n", + ioread32(cio_addr(channel, CHAN_REG_SDCFG))); + stm_dbg(DBG_ST.dma, "CHANNEL_params_regs (CHAN_REG_sdelt_exfrm)=%x\n", + ioread32(cio_addr(channel, CHAN_REG_SDELT))); + stm_dbg(DBG_ST.dma, "CHANNEL_params_regs (CHAN_REG_sdptr_exrld)=%x\n", + ioread32(cio_addr(channel, CHAN_REG_SDPTR))); + stm_dbg(DBG_ST.dma, "CHANNEL_params_regs (CHAN_REG_sdlnk_exblk)=%x\n", + ioread32(cio_addr(channel, CHAN_REG_SDLNK))); + stm_dbg(DBG_ST.dma, + "\n=================================================\n"); +} + +/** + * print_dma_regs() - To print DMA global registers + * + */ +static void print_dma_regs(void) +{ + stm_dbg(DBG_ST.dma, + "\n=====================================================\n"); + stm_dbg(DBG_ST.dma, "\t\tGLOBAL DMA REGISTERS"); + stm_dbg(DBG_ST.dma, + "\n=====================================================\n"); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_gcc)=%x\n", + ioread32(io_addr(DREG_GCC))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_prtyp)=%x\n", + ioread32(io_addr(DREG_PRTYP))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_prsme)=%x\n", + ioread32(io_addr(DREG_PRSME))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_prsmo)=%x\n", + ioread32(io_addr(DREG_PRSMO))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_prmse)=%x\n", + ioread32(io_addr(DREG_PRMSE))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_prmso)=%x\n", + ioread32(io_addr(DREG_PRMSO))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_prmoe)=%x\n", + ioread32(io_addr(DREG_PRMOE))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_prmoo)=%x\n", + ioread32(io_addr(DREG_PRMOO))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_lcpa)=%x\n", + ioread32(io_addr(DREG_LCPA))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_lcla)=%x\n", + ioread32(io_addr(DREG_LCLA))); +#ifndef CONFIG_STM_SECURITY + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_slcpa)=%x\n", + ioread32(io_addr(DREG_SLCPA))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_slcla) =%x\n", + ioread32(io_addr(DREG_SLCLA))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_sseg[0])=%x\n", + ioread32(io_addr(DREG_SSEG(0)))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_sseg[1])=%x\n", + ioread32(io_addr(DREG_SSEG(1)))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_sseg[2])=%x\n", + ioread32(io_addr(DREG_SSEG(2)))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_sseg[3])=%x\n", + ioread32(io_addr(DREG_SSEG(3)))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_sceg[0])=%x\n", + ioread32(io_addr(DREG_SCEG(0)))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_sceg[1])=%x\n", + ioread32(io_addr(DREG_SCEG(1)))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_sceg[2])=%x\n", + ioread32(io_addr(DREG_SCEG(2)))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_sceg[3])=%x\n", + ioread32(io_addr(DREG_SCEG(3)))); +#endif + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_active)=%x\n", + ioread32(io_addr(DREG_ACTIVE))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_activo)=%x\n", + ioread32(io_addr(DREG_ACTIVO))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_fsebs1)=%x\n", + ioread32(io_addr(DREG_FSEB1))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_fsebs2)=%x\n", + ioread32(io_addr(DREG_FSEB2))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_pcmis)=%x\n", + ioread32(io_addr(DREG_PCMIS))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_pcicr)=%x\n", + ioread32(io_addr(DREG_PCICR))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_pctis)=%x\n", + ioread32(io_addr(DREG_PCTIS))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_pceis)=%x\n", + ioread32(io_addr(DREG_PCEIS))); +#ifndef CONFIG_STM_SECURITY + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_spcmis)=%x\n", + ioread32(io_addr(DREG_SPCMIS))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_spcicr)=%x\n", + ioread32(io_addr(DREG_SPCICR))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_spctis)=%x\n", + ioread32(io_addr(DREG_SPCTIS))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_spceis)=%x\n", + ioread32(io_addr(DREG_SPCEIS))); +#endif + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_lcmis[0])=%x\n", + ioread32(io_addr(DREG_LCMIS(0)))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_lcmis[1])=%x\n", + ioread32(io_addr(DREG_LCMIS(1)))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_lcmis[2])=%x\n", + ioread32(io_addr(DREG_LCMIS(2)))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_lcmis[3])=%x\n", + ioread32(io_addr(DREG_LCMIS(3)))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_lcicr[0])=%x\n", + ioread32(io_addr(DREG_LCICR(0)))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_lcicr[1])=%x\n", + ioread32(io_addr(DREG_LCICR(1)))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_lcicr[2])=%x\n", + ioread32(io_addr(DREG_LCICR(2)))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_lcicr[3])=%x\n", + ioread32(io_addr(DREG_LCICR(3)))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_lctis[0])=%x\n", + ioread32(io_addr(DREG_LCTIS(0)))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_lctis[1])=%x\n", + ioread32(io_addr(DREG_LCTIS(1)))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_lctis[2])=%x\n", + ioread32(io_addr(DREG_LCTIS(2)))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_lctis[3])=%x\n", + ioread32(io_addr(DREG_LCTIS(3)))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_lceis[0])=%x\n", + ioread32(io_addr(DREG_LCEIS(0)))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_lceis[1])=%x\n", + ioread32(io_addr(DREG_LCEIS(1)))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_lceis[2])=%x\n", + ioread32(io_addr(DREG_LCEIS(2)))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_lceis[3])=%x\n", + ioread32(io_addr(DREG_LCEIS(3)))); +#ifndef CONFIG_STM_SECURITY + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_slcmis[0])=%x\n", + ioread32(io_addr(DREG_SLCMIS(0)))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_slcmis[1])=%x\n", + ioread32(io_addr(DREG_SLCMIS(1)))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_slcmis[2])=%x\n", + ioread32(io_addr(DREG_SLCMIS(2)))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_slcmis[3])=%x\n", + ioread32(io_addr(DREG_SLCMIS(3)))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_slcicr[0])=%x\n", + ioread32(io_addr(DREG_SLCICR(0)))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_slcicr[1])=%x\n", + ioread32(io_addr(DREG_SLCICR(1)))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_slcicr[2])=%x\n", + ioread32(io_addr(DREG_SLCICR(2)))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_slcicr[3])=%x\n", + ioread32(io_addr(DREG_SLCICR(3)))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_slctis[0])=%x\n", + ioread32(io_addr(DREG_SLCTIS(0)))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_slctis[1])=%x\n", + ioread32(io_addr(DREG_SLCTIS(1)))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_slctis[2])=%x\n", + ioread32(io_addr(DREG_SLCTIS(2)))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_slctis[3])=%x\n", + ioread32(io_addr(DREG_SLCTIS(3)))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_slceis[0])=%x\n", + ioread32(io_addr(DREG_SLCEIS(0)))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_slceis[1])=%x\n", + ioread32(io_addr(DREG_SLCEIS(1)))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_slceis[2])=%x\n", + ioread32(io_addr(DREG_SLCEIS(2)))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_slceis[3])=%x\n", + ioread32(io_addr(DREG_SLCEIS(3)))); +#endif + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_stfu)=%x\n", + ioread32(io_addr(DREG_STFU))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_icfg)=%x\n", + ioread32(io_addr(DREG_ICFG))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_mplug[0])=%x\n", + ioread32(io_addr(DREG_MPLUG(0)))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_mplug[1])=%x\n", + ioread32(io_addr(DREG_MPLUG(1)))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_mplug[2])=%x\n", + ioread32(io_addr(DREG_MPLUG(2)))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dmac_mplug[3])=%x\n", + ioread32(io_addr(DREG_MPLUG(3)))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dma_periphid0)=%x\n", + ioread32(io_addr(DREG_PERIPHID(0)))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dma_periphid1)=%x\n", + ioread32(io_addr(DREG_PERIPHID(1)))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dma_periphid2)=%x\n", + ioread32(io_addr(DREG_PERIPHID(2)))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dma_periphid3)=%x\n", + ioread32(io_addr(DREG_PERIPHID(2)))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dma_cellid0)=%x\n", + ioread32(io_addr(DREG_CELLID(0)))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dma_cellid1)=%x\n", + ioread32(io_addr(DREG_CELLID(1)))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dma_cellid2)=%x\n", + ioread32(io_addr(DREG_CELLID(2)))); + stm_dbg(DBG_ST.dma, "DMA_REGS (dma_cellid3)=%x\n", + ioread32(io_addr(DREG_CELLID(3)))); + stm_dbg(DBG_ST.dma, + "\n===================================================\n"); +} + +/** + * print_dma_channel_info() - To print DMA channel info that is maintained by + * DMA driver internally + * @info: Info structure where information is maintained + * + */ +static void print_dma_channel_info(struct dma_channel_info *info) +{ + stm_dbg(DBG_ST.dma, " info->phys_chan_id = %d \n", info->phys_chan_id); + stm_dbg(DBG_ST.dma, " info->dir = %d \n", info->dir); + stm_dbg(DBG_ST.dma, " info->security = %d \n", info->security); + stm_dbg(DBG_ST.dma, " info->ch_status = %d \n", info->ch_status); + stm_dbg(DBG_ST.dma, " info->src_info.endianess = %d \n", + info->src_info.endianess); + stm_dbg(DBG_ST.dma, " info->src_info.data_width = %d \n", + info->src_info.data_width); + stm_dbg(DBG_ST.dma, " info->src_info.burst_size = %d \n", + info->src_info.burst_size); + stm_dbg(DBG_ST.dma, " info->src_info.buffer_type = %d \n", + info->src_info.buffer_type); + if (info->src_addr) + stm_dbg(DBG_ST.dma, " info->src_addr = %x \n", + (u32) info->src_addr); + stm_dbg(DBG_ST.dma, " info->dst_info.endianess = %d \n", + info->dst_info.endianess); + stm_dbg(DBG_ST.dma, " info->dst_info.data_width = %d \n", + info->dst_info.data_width); + stm_dbg(DBG_ST.dma, " info->dst_info.burst_size = %d \n", + info->dst_info.burst_size); + stm_dbg(DBG_ST.dma, " info->dst_info.buffer_type = %d \n", + info->dst_info.buffer_type); + if (info->dst_addr) + stm_dbg(DBG_ST.dma, " info->dst_addr = %x \n", + (u32) info->dst_addr); +} + +/** + * is_pipeid_invalid() - To check validity of client pipe_id + * @pipe_id: pipe_id whose validity needs to be checked + * + * It will return -1 if pipe_id is invalid and 0 if valid + **/ +static inline int is_pipeid_invalid(int pipe_id) +{ + if ((pipe_id < 0) + || (pipe_id > (MAX_LOGICAL_CHANNELS + MAX_PHYSICAL_CHANNELS))) + return -1; + else { + if (test_bit(pipe_id, dma_drv_data->pipe_id_map)) + return 0; + else + return -1; + } +} + +/** + * get_xfer_len() - To get the length of the transfer + * @info: Information struct of the channel parameters. + * + */ +static inline int get_xfer_len(struct dma_channel_info *info) +{ + return info->xfer_len; +} + +/** + * allocate_pipe_id() - To mark allocation of free pipe id. + * + * This function searches the pipe_id_map to find first free zero. + * Presence of zero means we can use this position number as a pipe id. + * After finding a position we mark it as unavailable, by writting a 1 + * at that position in the map. This function returns -1 if it + * cannot find a free pipe_id, or it returns pipe_id (>=0) + * + */ +static int allocate_pipe_id(void) +{ + int id = 0; + unsigned long flags; + spin_lock_irqsave(&dma_drv_data->pipe_id_lock, flags); + id = find_first_zero_bit((const unsigned long + *)(dma_drv_data->pipe_id_map), NUM_CHANNELS); + if (id >= 0 && id < NUM_CHANNELS) { + test_and_set_bit((id % BITS_PER_LONG), + &(dma_drv_data->pipe_id_map[BIT_WORD(id)])); + stm_dbg(DBG_ST.dma, + "allocate_pipe_id():: Client Id allocated = %d\n", id); + } else { + stm_error("Unable to allocate free channel....\n"); + id = -1; + } + spin_unlock_irqrestore(&dma_drv_data->pipe_id_lock, flags); + return id; +} + +/** + * deallocate_pipe_id() - Function to deallocate already allocated pipe_id + * @pipe_id: Pipe id which needs to be deallocated. + * + * This function deallocates the pipe_id by clearing the corresponding + * bit position in the pipe_id_map which is the allocation map for + * DMA pipes. + * + */ +static void deallocate_pipe_id(int pipe_id) +{ + unsigned long flags; + spin_lock_irqsave(&dma_drv_data->pipe_id_lock, flags); + test_and_clear_bit((pipe_id % BITS_PER_LONG), + &(dma_drv_data->pipe_id_map[BIT_WORD(pipe_id)])); + spin_unlock_irqrestore(&dma_drv_data->pipe_id_lock, flags); + print_allocation_map(); +} + +/** + * get_phys_res_security() - Returns security type of the Physical resource. + * @pr: Physical resource whose security has to be returned + * + */ +enum dma_chan_security get_phys_res_security(int pr) +{ +#ifndef CONFIG_STM_SECURITY + if (pr % 2) + return REG_RD_BITS(io_addr(DREG_PRSMO), + PHYSICAL_RESOURCE_SECURE_MODE_MASK(pr), + PHYSICAL_RESOURCE_SECURE_MODE_POS(pr)); + else + return REG_RD_BITS(io_addr(DREG_PRSME), + PHYSICAL_RESOURCE_SECURE_MODE_MASK(pr), + PHYSICAL_RESOURCE_SECURE_MODE_POS(pr)); +#else + return DMA_NONSECURE_CHAN; +#endif + +} + +/** + * dma_channel_get_status() - To check the activation status of a physical channel + * @channel: Channel whose activation status is to be checked + * + */ +static inline int dma_channel_get_status(int channel) +{ + + if (channel % 2 == 0) + return REG_RD_BITS(io_addr(DREG_ACTIVE), + ACT_PHY_RES_MASK + (channel), ACT_PHY_RES_POS(channel)); + else + return REG_RD_BITS(io_addr(DREG_ACTIVO), + ACT_PHY_RES_MASK + (channel), ACT_PHY_RES_POS(channel)); +} + +/** + * dma_channel_execute_command() - To execute cmds like run, stop, + * suspend on phy channels + * @command: Command to be executed(run, stop, suspend, etc...) + * @channel: Channel on which these commands have to be executed + * + */ +static int dma_channel_execute_command(int command, int channel) +{ + int status = 0; + int iter = 0; + + if (get_phys_res_security(channel) == DMA_NONSECURE_CHAN) { + switch (command) { + case DMA_RUN: + { + if (channel % 2 == 0) + REG_WR_BITS_1(io_addr + (DREG_ACTIVE), + DMA_RUN, + ACT_PHY_RES_MASK + (channel), + ACT_PHY_RES_POS(channel)); + else + REG_WR_BITS_1(io_addr + (DREG_ACTIVO), + DMA_RUN, + ACT_PHY_RES_MASK + (channel), + ACT_PHY_RES_POS(channel)); + return 0; + } + case DMA_STOP: + { + if (channel % 2 == 0) + REG_WR_BITS_1(io_addr + (DREG_ACTIVE), + DMA_STOP, + ACT_PHY_RES_MASK + (channel), + ACT_PHY_RES_POS(channel)); + else + REG_WR_BITS_1(io_addr + (DREG_ACTIVO), + DMA_STOP, + ACT_PHY_RES_MASK + (channel), + ACT_PHY_RES_POS(channel)); + return 0; + } + case DMA_SUSPEND_REQ: + { + status = dma_channel_get_status(channel); + if ((status == DMA_SUSPENDED) + || (status == DMA_STOP)) + return 0; + if (channel % 2 == 0) + REG_WR_BITS_1(io_addr + (DREG_ACTIVE), + DMA_SUSPEND_REQ, + ACT_PHY_RES_MASK + (channel), + ACT_PHY_RES_POS(channel)); + else + REG_WR_BITS_1(io_addr + (DREG_ACTIVO), + DMA_SUSPEND_REQ, + ACT_PHY_RES_MASK + (channel), + ACT_PHY_RES_POS(channel)); + status = dma_channel_get_status(channel); + while ((status != DMA_STOP) + && (status != DMA_SUSPENDED)) { + if (iter == MAX_ITERATIONS) { + stm_error("Unable to suspend \ + the Channel \ + %d\n", channel); + return -1; + } + udelay(2); + status = + dma_channel_get_status(channel); + iter++; + } + return 0; + } + default: + { + stm_error("dma_channel_execute_command(): \ + Unknown command \n"); + return -1; + } + } + } else { + stm_error("Secure mode not activated yet!!\n"); + + } + return 0; +} + +/** + * get_phy_res_usage_count() - To find how many clients are sharing + * this phy res. + * @pchan: id of Physical resource whose usage count has to be returned + * This function returns the number of clients sharing a physical resource. + * Count > 1 means, this is a logical resource. + * + */ +static inline int get_phy_res_usage_count(int pchan) +{ + int count; + count = dma_drv_data->pr_info[pchan].count; + return count; +} + +/** + * release_phys_resource() - Function to deallocate a physical resource. + * @info: dma info staructure + * This function deallocates a physical resource + * + */ + +static int release_phys_resource(struct dma_channel_info *info) +{ + int phy_channel = info->phys_chan_id; + unsigned long flags; + + spin_lock_irqsave(&dma_drv_data->pr_info_lock, flags); + if (dma_drv_data->pr_info[phy_channel].status == RESOURCE_LOGICAL) { + if (--dma_drv_data->pr_info[phy_channel].count == 0) { + if (dma_channel_execute_command + (DMA_SUSPEND_REQ, phy_channel) == -1) { + stm_error("Unable to suspend the Channel %d\n", + phy_channel); + goto error_release; + } + if (dma_channel_execute_command(DMA_STOP, phy_channel) + == -1) { + stm_error("Unable to stop the Channel %d\n", + phy_channel); + goto error_release; + } + dma_drv_data->pr_info[phy_channel].status = + RESOURCE_FREE; + /*Resource is clean now */ + dma_drv_data->pr_info[phy_channel].dirty = 0; + } + } else if (dma_drv_data->pr_info[phy_channel].status == + RESOURCE_PHYSICAL) { + dma_drv_data->pr_info[phy_channel].status = RESOURCE_FREE; + /*Resource is clean now */ + dma_drv_data->pr_info[phy_channel].dirty = 0; + } else { + stm_error("\n Already freed"); + goto error_release; + } + spin_unlock_irqrestore(&dma_drv_data->pr_info_lock, flags); + return 0; +error_release: + spin_unlock_irqrestore(&dma_drv_data->pr_info_lock, flags); + return -1; +} + +/** + * allocate_free_dma_channel() - To allocate free Physical channel for a + * dma xfer. + * @info: client id for which channel allocation has to be done + * This function allocates free Physical channel for a dma xfer. + * Allocation is done based on requirement of client and + * availability of channels. + * Logical channels would be used only for mem-periph, periph-mem. + * mem-mem, periph-periph would used Physical mode only. + * If a physical channel wants to reserve, a flag would mark + * the physical resource. + * If a logical channel has been requested, but corresponding + * Physical resource(based on event line of Logical channel)is + * reserved, request would be rejected straightaway. + * + */ +static int allocate_free_dma_channel(struct dma_channel_info *info) +{ + int i, j, tmp; + int event_group; + unsigned long flags; + if (info->dir == PERIPH_TO_PERIPH && + (info->src_info.event_group != info->dst_info.event_group)) + return -EINVAL; + if (info->dir == MEM_TO_PERIPH) + event_group = info->dst_info.event_group; + else + event_group = info->src_info.event_group; + + spin_lock_irqsave(&dma_drv_data->pr_info_lock, flags); + if (info->chan_mode == DMA_CHAN_IN_PHYS_MODE) { + if (info->dir == MEM_TO_MEM) { + for (i = 0; i < MAX_AVAIL_PHY_CHANNELS; i++) { + if (dma_drv_data->pr_info[i].status == + RESOURCE_FREE) { + info->phys_chan_id = i; + dma_drv_data->pr_info[i].status = + RESOURCE_PHYSICAL; + info->channel_id = + (MAX_LOGICAL_CHANNELS + + info->phys_chan_id); + goto done; + } + } + } else { + for (i = 0; i < MAX_AVAIL_PHY_CHANNELS; i += 8) { + tmp = i * 8 + event_group * 2; + for (j = tmp; j < tmp + 2; j++) { + if (dma_drv_data->pr_info[j].status == + RESOURCE_FREE) { + info->phys_chan_id = j; + info->channel_id = + (MAX_LOGICAL_CHANNELS + + info->phys_chan_id); + dma_drv_data-> + pr_info[j].status = + RESOURCE_PHYSICAL; + goto done; + } + } + } + } + } else { /* Logical mode */ + if (info->dir == MEM_TO_PERIPH) + info->channel_id = 2 * (info->dst_dev_type) + 1; + else + info->channel_id = 2 * (info->src_dev_type); + if (info->dir == MEM_TO_MEM) { + spin_unlock_irqrestore(&dma_drv_data->pr_info_lock, + flags); + return -EINVAL; + } else { + for (i = 0; i < MAX_AVAIL_PHY_CHANNELS; i += 8) { + tmp = i * 8 + event_group * 2; + for (j = tmp; j < tmp + 2; j++) { + if (dma_drv_data->pr_info[j].status == + RESOURCE_FREE + || dma_drv_data-> + pr_info[j].status == + RESOURCE_LOGICAL) { + if (dma_drv_data-> + pr_info[j].count >= 16) + continue; + else { + dma_drv_data->pr_info + [j].count++; + info->phys_chan_id = j; + dma_drv_data->pr_info + [j].status = + RESOURCE_LOGICAL; + goto done; + } + } + } + + } + } + } + spin_unlock_irqrestore(&dma_drv_data->pr_info_lock, flags); + return -EBUSY; +done: + spin_unlock_irqrestore(&dma_drv_data->pr_info_lock, flags); + return 0; + +} + +/** + * get_phys_res_type() - returns Type of a Physical resource + * (standard or extended) + * @pr: Physical resource whose type will be returned + * + */ +static inline enum dma_phys_res_type get_phys_res_type(int pr) +{ + return REG_RD_BITS(io_addr(DREG_PRTYP), + PHYSICAL_RESOURCE_TYPE_MASK(pr), + PHYSICAL_RESOURCE_TYPE_POS(pr)); +} + +/** + * set_phys_res_type() - To set Type of a Phys resource(standard or extended) + * @pr: Physical resource whose type is to be set + * @type: standard or extended + * + */ +static inline void set_phys_res_type(int pr, enum dma_phys_res_type type) +{ + REG_WR_BITS(io_addr(DREG_PRTYP), type, + PHYSICAL_RESOURCE_TYPE_MASK(pr), + PHYSICAL_RESOURCE_TYPE_POS(pr)); +} + +/** + * set_phys_res_security() - To set security type of the Physical resource. + * @pr: Physical resource whose security has to be set + * @type: type (secure, non secure) + * + */ +static inline void set_phys_res_security(int pr, + enum dma_chan_security type) +{ + if (pr % 2) + REG_WR_BITS(io_addr(DREG_PRSMO), type, + PHYSICAL_RESOURCE_SECURE_MODE_MASK(pr), + PHYSICAL_RESOURCE_SECURE_MODE_POS(pr)); + else + REG_WR_BITS(io_addr(DREG_PRSME), type, + PHYSICAL_RESOURCE_SECURE_MODE_MASK(pr), + PHYSICAL_RESOURCE_SECURE_MODE_POS(pr)); +} + +/** + * get_phys_res_mode() - To read the mode of the physical resource. + * @pr: Physical resource whose mode is to be retrieved. + * This function returns the current mode of the physical resources + * by reading the DMA control registers. It returns enum + * dma_channel_mode which is either DMA_CHAN_IN_PHYS_MODE, + * DMA_CHAN_IN_LOG_MODE ,DMA_CHAN_IN_OPERATION_MODE. + * + */ +static inline enum dma_channel_mode get_phys_res_mode(int pr) +{ + if (pr % 2) + return REG_RD_BITS(io_addr(DREG_PRMSO), + PHYSICAL_RESOURCE_CHANNEL_MODE_MASK + (pr), + PHYSICAL_RESOURCE_CHANNEL_MODE_POS(pr)); + else + return REG_RD_BITS(io_addr(DREG_PRMSE), + PHYSICAL_RESOURCE_CHANNEL_MODE_MASK + (pr), + PHYSICAL_RESOURCE_CHANNEL_MODE_POS(pr)); +} + +/** + * set_phys_res_mode() - To set the mode of the Physical resource + * @pr: Physical resource whose mode has to be set + * @mode: The mode in which the physical resource is to be set. + * + */ +static inline void set_phys_res_mode(int pr, enum dma_channel_mode mode) +{ +#if 0 + if (pr % 2) + REG_WR_BITS(io_addr(DREG_PRMSO), mode, + PHYSICAL_RESOURCE_CHANNEL_MODE_MASK(pr), + PHYSICAL_RESOURCE_CHANNEL_MODE_POS(pr)); + else + REG_WR_BITS(io_addr(DREG_PRMSE), mode, + PHYSICAL_RESOURCE_CHANNEL_MODE_MASK(pr), + PHYSICAL_RESOURCE_CHANNEL_MODE_POS(pr)); +#endif + + if (get_phys_res_security(pr) == DMA_NONSECURE_CHAN) { + if (pr % 2) + REG_WR_BITS(io_addr(DREG_PRMSO), mode, + PHYSICAL_RESOURCE_CHANNEL_MODE_MASK + (pr), + PHYSICAL_RESOURCE_CHANNEL_MODE_POS(pr)); + else + REG_WR_BITS(io_addr(DREG_PRMSE), mode, + PHYSICAL_RESOURCE_CHANNEL_MODE_MASK + (pr), + PHYSICAL_RESOURCE_CHANNEL_MODE_POS(pr)); + + } else { + stm_error("DMA Driver: Secure register not touched\n"); + } +} + +/** + * set_phys_res_mode_option() - To set the mode option of physical resource. + * @pr: Physical resource whose mode option needs to be set. + * @option: enum dma_channel_mode_option + * + */ +static inline void set_phys_res_mode_option(int pr, + enum dma_channel_mode_option + option) +{ +#if 0 + if (pr % 2) + REG_WR_BITS(io_addr(DREG_PRMOO), option, + PHYSICAL_RESOURCE_CHANNEL_MODE_OPTION_MASK + (pr), + PHYSICAL_RESOURCE_CHANNEL_MODE_OPTION_POS(pr)); + else + REG_WR_BITS(io_addr(DREG_PRMOE), option, + PHYSICAL_RESOURCE_CHANNEL_MODE_OPTION_MASK + (pr), + PHYSICAL_RESOURCE_CHANNEL_MODE_OPTION_POS(pr)); +#endif + if (get_phys_res_security(pr) == DMA_NONSECURE_CHAN) { + if (pr % 2) + REG_WR_BITS(io_addr(DREG_PRMOO), option, + PHYSICAL_RESOURCE_CHANNEL_MODE_OPTION_MASK + (pr), + PHYSICAL_RESOURCE_CHANNEL_MODE_OPTION_POS + (pr)); + else + REG_WR_BITS(io_addr(DREG_PRMOE), option, + PHYSICAL_RESOURCE_CHANNEL_MODE_OPTION_MASK + (pr), + PHYSICAL_RESOURCE_CHANNEL_MODE_OPTION_POS + (pr)); + } else { + stm_error + ("DMA Driver:Secure reg not touched for mode option\n"); + } + +} + +enum dma_channel_mode_option get_phys_res_mode_option(int pr) +{ + if (pr % 2) + return REG_RD_BITS(io_addr(DREG_PRMOO), + PHYSICAL_RESOURCE_CHANNEL_MODE_OPTION_MASK + (pr), + PHYSICAL_RESOURCE_CHANNEL_MODE_OPTION_POS + (pr)); + else + return REG_RD_BITS(io_addr(DREG_PRMOE), + PHYSICAL_RESOURCE_CHANNEL_MODE_OPTION_MASK + (pr), + PHYSICAL_RESOURCE_CHANNEL_MODE_OPTION_POS + (pr)); +} + +/** + * set_event_line_security() - To set event line security + * @line: Event line whose security has to be set + * @event_group: Event group of the event line + * @security: Type of security(enum dma_chan_security) to set + * + */ +static inline void set_event_line_security(int line, + enum dma_event_group + event_group, + enum dma_chan_security security) +{ + u32 tmp; + if (security == DMA_SECURE_CHAN) { + tmp = + REG_RD_BITS(io_addr(DREG_SSEG(event_group)), + FULL32_MASK, NO_SHIFT); + tmp |= (0x1 << line); + REG_WR_BITS(io_addr(DREG_SSEG(event_group)), tmp, + FULL32_MASK, NO_SHIFT); + } else { + tmp = + REG_RD_BITS(io_addr(DREG_SCEG(event_group)), + FULL32_MASK, NO_SHIFT); + tmp |= (0x1 << line); + REG_WR_BITS(io_addr(DREG_SCEG(event_group)), tmp, + FULL32_MASK, NO_SHIFT); + } +} + +/** + * create_elem_pool() - To create pool of elements + * @name: Name of the Element pool created + * @block_size: Number of bytes in one element + * @num_block: Number of elements. + * @allignment_bits: Allignment of memory allocated in terms of bit position + * This function creates a pool of "num_block" blocks with fixed + * block size of "block_size" It returns a logical address or null if + * allocation fails. It uses dma_alloc_coherent() for allocation of pool memory. + * The memory allocated would be alligned as given by allignment_bits argument. + * For e.g if allignment_bits = 16, then last 16 bits of alligned + * memory would be 0. + * This function returns pointer to the element pool created , or NULL on error + * + */ +static struct elem_pool *create_elem_pool(char *name, int block_size, + int num_block, int allignment_bits) +{ + int allignment_size; + int alloc_size; + struct elem_pool *pool = kzalloc(sizeof(struct elem_pool), GFP_KERNEL); + if (!pool) { + stm_error("Could not allocate memory for pool"); + return NULL; + } + + pool->num_blocks = num_block; + pool->block_size = block_size; + pool->allocation_map = 0; + spin_lock_init(&pool->pool_lock); + strcpy(pool->name, name); + + if (allignment_bits <= PAGE_SHIFT) { + /*Because dma_alloc_coherent is already page_aligned */ + void *ptr = dma_alloc_coherent(NULL, + num_block * block_size, + &pool->unalign_base.phys_addr, + GFP_KERNEL | GFP_DMA); + pool->unalign_base.log_addr = ptr; + pool->base_addr = pool->unalign_base; + pool->allocation_size = num_block * block_size; + } else { + void *ptr; + + allignment_size = (0x1 << allignment_bits); + alloc_size = + num_block * block_size + allignment_size + sizeof(void *); + + pool->allocation_size = alloc_size; + ptr = dma_alloc_coherent(NULL, + alloc_size, + &pool->unalign_base.phys_addr, + GFP_KERNEL | GFP_DMA); + pool->unalign_base.log_addr = ptr; + if ((pool->unalign_base.phys_addr % allignment_size + + pool->unalign_base.phys_addr) == + pool->unalign_base.phys_addr) { + pool->base_addr.log_addr = pool->unalign_base.log_addr; + pool->base_addr.phys_addr = + pool->unalign_base.phys_addr; + stm_dbg(DBG_ST.dma, "No need to Allign.............\n"); + goto complete_pool; + } + + pool->base_addr.log_addr = + (char *)pool->unalign_base.log_addr + + sizeof(void *) + allignment_size; + pool->base_addr.log_addr = + (char *)pool->base_addr.log_addr - + ((unsigned long)pool->base_addr.log_addr) % allignment_size; + + pool->base_addr.phys_addr = pool->unalign_base.phys_addr + + sizeof(void *) + allignment_size; + pool->base_addr.phys_addr = pool->base_addr.phys_addr + - + ((unsigned long)pool->base_addr.phys_addr) % + allignment_size; + + pool->base_addr.log_addr = pool->unalign_base.log_addr + + ((unsigned long)pool->base_addr.phys_addr + - (unsigned long)pool->unalign_base.phys_addr); + } +complete_pool: + stm_dbg(DBG_ST.dma, + "UNALLIGNED BASE ADDRESS :: LOGICAL = %x, PHYSICAL = %x\n", + (u32) pool->unalign_base.log_addr, + (u32) pool->unalign_base.phys_addr); + stm_dbg(DBG_ST.dma, + "ALLIGNED BASE ADDRESS :: LOGICAL = %x, PHYSICAL = %x\n", + (u32) pool->base_addr.log_addr, + (u32) pool->base_addr.phys_addr); + return pool; +} + +static struct elem_pool *create_elem_pool_fixed_mem(char *name, int block_size, + int num_block, u32 mem_base, + int max_avail_mem) +{ + struct elem_pool *pool = kzalloc(sizeof(struct elem_pool), GFP_KERNEL); + if (!pool) { + stm_error("Could not allocate memory for pool"); + return NULL; + } + + pool->num_blocks = num_block; + pool->block_size = block_size; + pool->allocation_map = 0; + spin_lock_init(&pool->pool_lock); + strcpy(pool->name, name); + + if ((block_size * num_block) > max_avail_mem) { + stm_error("Too much memory requested\n"); + kfree(pool); + return NULL; + } + pool->unalign_base.log_addr = ioremap(mem_base, max_avail_mem); + if (!(pool->unalign_base.log_addr)) { + stm_error("Could not ioremap the LCLA memory\n"); + kfree(pool); + return NULL; + } + + pool->unalign_base.phys_addr = mem_base; + pool->base_addr = pool->unalign_base; + pool->allocation_size = num_block * block_size; + + stm_dbg(DBG_ST.dma, + "UNALLIGNED BASE ADDRESS :: LOGICAL = %x, PHYSICAL = %x\n", + (u32) pool->unalign_base.log_addr, + (u32) pool->unalign_base.phys_addr); + stm_dbg(DBG_ST.dma, + "ALLIGNED BASE ADDRESS :: LOGICAL = %x, PHYSICAL = %x\n", + (u32) pool->base_addr.log_addr, + (u32) pool->base_addr.phys_addr); + return pool; +} + +/** + * destroy_elem_pool() - To destroy the Element pool created + * @pool: Pointer to pool which needs to be destroyed + * + */ +static void destroy_elem_pool(struct elem_pool *pool) +{ + if (pool) { + dma_free_coherent(NULL, pool->allocation_size, + pool->unalign_base.log_addr, + pool->unalign_base.phys_addr); + kfree(pool); + } +} + +/** + * get_free_block() - To allocate a Free block from an element pool + * @pool: Pointer to pool from which free block is required + * This function checks in the allocation bitmap of the pool + * and returns a free block after setting corresponding bit in the + * allocation map of the pool. + * It will return block id(>=0) on success and -1 on failure. + */ +static int get_free_block(struct elem_pool *pool) +{ + int i; + stm_dbg(DBG_ST.dma, "%s :: Allocation Map: %d\n", pool->name, + pool->allocation_map); + spin_lock(&pool->pool_lock); + for (i = 0; i < pool->num_blocks; i++) { + if (!(pool->allocation_map & (0x1 << i))) { + pool->allocation_map |= (0x1 << i); + spin_unlock(&pool->pool_lock); + return i; + } + } + spin_unlock(&pool->pool_lock); + return -1; +} + +/** + * get_free_log_lli_block() - To allocate a Free block for a Logical channel + * @pool: Element pool from where allocation has to be done + * @pchan: Physical resource corresponding to the Logical channel + * There are a fixed number of blocks for Logical LLI per physical channel. + * Hence allocation is done by searching free blocks for a particular + * physical channel. It will return block id(>=0) on success and -1 on failure. + * + */ +static int get_free_log_lli_block(struct elem_pool *pool, int pchan) +{ + int i = 0; + int num_log_lli_blocks; + num_log_lli_blocks = 126 / NUM_LLI_PER_LOG_CHANNEL; + + stm_dbg(DBG_ST.dma, "NAME:%s :: Phys_chan:: %d :: Allocation Map: %d\n", + pool->name, pchan, pool->lchan_allocation_map[pchan]); + spin_lock(&pool->pool_lock); + for (i = 0; i < num_log_lli_blocks; i++) { + if (!(pool->lchan_allocation_map[pchan] & (0x1 << i))) { + pool->lchan_allocation_map[pchan] |= (0x1 << i); + spin_unlock(&pool->pool_lock); + return i; + } + } + spin_unlock(&pool->pool_lock); + return -1; +} + +/** + * rel_free_log_lli_block() - To release a Free block for a Logical channel + * @pool: Element pool from where relese has to be done + * @pchan: Physical resource corresponding to this Logical channel + * @idx: index of the block to be released + * + */ +static void rel_free_log_lli_block(struct elem_pool *pool, int pchan, int idx) +{ + int num_log_lli_blocks; + num_log_lli_blocks = 126 / NUM_LLI_PER_LOG_CHANNEL; + + stm_dbg(DBG_ST.dma, "NAME:%s :: Phys_chan:: %d :: Allocation Map: %d\n", + pool->name, pchan, pool->lchan_allocation_map[pchan]); + spin_lock(&pool->pool_lock); + pool->lchan_allocation_map[pchan] &= (~(0x1 << idx)); + spin_unlock(&pool->pool_lock); +} + +/** + * release_block() - To release a Free block + * @idx: index of the block to be released + * @pool: Pool from which block is to be released + * + */ +static void release_block(int idx, struct elem_pool *pool) +{ + if (idx < pool->num_blocks) { + spin_lock(&pool->pool_lock); + pool->allocation_map &= (~(0x1 << idx)); + spin_unlock(&pool->pool_lock); + } +} + +int calculate_lli_required(struct dma_channel_info *info, + int *lli_size_req) +{ + int lli_count = 0; + int lli_size = 0; + int xfer_len = get_xfer_len(info); + + u32 src_data_width = (0x1 << info->src_info.data_width); + u32 dst_data_width = (0x1 << info->dst_info.data_width); + + lli_size = ((SIXTY_FOUR_KB - 4) * + ((dst_data_width > + src_data_width) ? src_data_width : dst_data_width)); + + lli_count = xfer_len / lli_size; + if (xfer_len % lli_size) + lli_count++; + *lli_size_req = lli_size; + stm_dbg(DBG_ST.dma, "LLI_size = %d LLI Count = %d\n", lli_size, + lli_count); + return lli_count; +} + +/** + * generate_sg_list() - To Generate a sg list if DMA xfer len > 64K elems + * @info: Information of the channel parameters. + * @type: Whether Source or Destination half channel. + * @lli_size: Max size of each LLI to be generated. + * @lli_count: Number of LLI's to be generated. + * This function generates a sg list by breaking current length into + * length of size lli_size. It will generate lli_count lli's. It will + * finally return the sg list. + * + */ +struct scatterlist *generate_sg_list(struct dma_channel_info *info, + enum dma_half_chan type, int lli_size, + int lli_count) +{ + struct scatterlist *sg = NULL; + struct scatterlist *temp_sg = NULL; + int i = 0; + void *temp_addr; + + if (type == DMA_SRC_HALF_CHANNEL) { + if (info->sg_block_id_src < 0) + info->sg_block_id_src = + get_free_block(dma_drv_data->sg_pool); + sg = ((struct scatterlist *)((u32) dma_drv_data->sg_pool-> + base_addr.log_addr + + info->sg_block_id_src * + dma_drv_data->sg_pool-> + block_size)); + info->sgcount_src = lli_count; + info->sg_src = sg; + temp_addr = info->src_addr; + } else { + if (info->sg_block_id_dest < 0) + info->sg_block_id_dest = + get_free_block(dma_drv_data->sg_pool); + sg = ((struct scatterlist *)((u32) dma_drv_data->sg_pool-> + base_addr.log_addr + + info->sg_block_id_dest * + dma_drv_data->sg_pool-> + block_size)); + info->sgcount_dest = lli_count; + info->sg_dest = sg; + temp_addr = info->dst_addr; + } + + sg_init_table(sg, lli_count); + for_each_sg(sg, temp_sg, lli_count, i) { + if ((type == DMA_SRC_HALF_CHANNEL) + && ((info->dir == PERIPH_TO_MEM) + || (info->dir == PERIPH_TO_PERIPH))) + temp_sg->dma_address = (dma_addr_t) temp_addr; + else if ((type == DMA_DEST_HALF_CHANNEL) + && ((info->dir == MEM_TO_PERIPH) + || (info->dir == PERIPH_TO_PERIPH))) + temp_sg->dma_address = (dma_addr_t) temp_addr; + else + temp_sg->dma_address = + (dma_addr_t) (temp_addr + i * (lli_size)); + + temp_sg->length = lli_size; + temp_sg->offset = 0; + if (i == (lli_count - 1)) { + int len = get_xfer_len(info) % lli_size; + if (len) + temp_sg->length = len; + } + } + return sg; +} + +/** + * map_lli_info_log_chan() - To Map the SG info into LLI's for Log channels. + * @info: Information of the channel parameters. + * @type: Whether source or destination half channel. + * @params: Memory location pointer where standard Logical channel register + * parameters are Loaded. + * This function maps the SG info into LLI's for the Logical channels. + * A free block of LLI's is allocated for a particular physical + * channel and SG info is mapped in that memory block. For a particular + * physical channel 1Kb of memory is there for LLI's which has to be + * shared by all Logical channels running on it. + * It returns 0 on success, -1 on failure. + * + */ +static int map_lli_info_log_chan(struct dma_channel_info *info, int type, + struct std_log_memory_param *params) +{ + int idx = 0; + struct scatterlist *sg; + u32 step_size = 0; + u32 lli_count = 0; + void *base = + dma_drv_data->lchan_lli_pool->base_addr.log_addr + + info->phys_chan_id * 1024; + + stm_dbg(DBG_ST.dma, "Setting LLI for %s\n", + (type == + DMA_SRC_HALF_CHANNEL) ? "DMA_SRC_HALF_CHANNEL" : + "DMA_DEST_HALF_CHANNEL"); + + if (type == DMA_SRC_HALF_CHANNEL) { + struct dma_logical_src_lli_info *lli_ptr = NULL; + u32 slos; + step_size = (0x1 << info->src_info.data_width); + sg = info->sg_src; + lli_count = info->sgcount_src; + if (info->lli_block_id_src < 0) + info->lli_block_id_src = + get_free_log_lli_block(dma_drv_data->lchan_lli_pool, + info->phys_chan_id); + if (info->lli_block_id_src < 0) { + stm_error("Free LLI's not available\n"); + return -1; + } + + slos = info->lli_block_id_src * NUM_LLI_PER_LOG_CHANNEL + 1; + /*********************************************************/ + /*Use first SG item to fill params register */ + REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SSELT), + info->phys_chan_id, SREG_ELEM_LOG_LIDX_MASK, + SREG_ELEM_LOG_LIDX_POS); + MEM_WRITE_BITS(params->dmac_lcsp0, + (sg_dma_len(sg) >> info->src_info.data_width), + MEM_LCSP0_ECNT_MASK, MEM_LCSP0_ECNT_POS); + MEM_WRITE_BITS(params->dmac_lcsp1, slos, MEM_LCSP1_SLOS_MASK, + MEM_LCSP1_SLOS_POS); + MEM_WRITE_BITS(params->dmac_lcsp0, + (0x0000FFFFUL & (u32) (sg_dma_address(sg))), + MEM_LCSP0_SPTR_MASK, MEM_LCSP0_SPTR_POS); + MEM_WRITE_BITS(params->dmac_lcsp1, + (0xFFFF0000 & (u32) (sg_dma_address(sg))) >> 16, + MEM_LCSP1_SPTR_MASK, MEM_LCSP1_SPTR_POS); + if ((info->lli_interrupt == 1) && (info->dir == PERIPH_TO_MEM)) + MEM_WRITE_BITS(params->dmac_lcsp1, DMA_TRUE, + MEM_LCSP1_SCFG_TIM_MASK, + MEM_LCSP1_SCFG_TIM_POS); + else + MEM_WRITE_BITS(params->dmac_lcsp1, DMA_FALSE, + MEM_LCSP1_SCFG_TIM_MASK, + MEM_LCSP1_SCFG_TIM_POS); + sg++; + lli_count--; + /***********************************************************/ + lli_ptr = (struct dma_logical_src_lli_info *)base + slos; + + for (idx = 0; idx < lli_count; idx++) { + lli_ptr[idx].dmac_lcsp1 = params->dmac_lcsp1; + MEM_WRITE_BITS(lli_ptr[idx].dmac_lcsp0, + (sg_dma_len(sg) >> info-> + src_info.data_width), + MEM_LCSP0_ECNT_MASK, MEM_LCSP0_ECNT_POS); + MEM_WRITE_BITS(lli_ptr[idx].dmac_lcsp0, + (0x0000FFFFUL & + (u32) (sg_dma_address(sg))), + MEM_LCSP0_SPTR_MASK, MEM_LCSP0_SPTR_POS); + MEM_WRITE_BITS(lli_ptr[idx].dmac_lcsp1, + (0xFFFF0000UL & + (u32) (sg_dma_address(sg))) >> 16, + MEM_LCSP1_SPTR_MASK, MEM_LCSP1_SPTR_POS); + MEM_WRITE_BITS(lli_ptr[idx].dmac_lcsp1, + (slos + idx + 1), MEM_LCSP1_SLOS_MASK, + MEM_LCSP1_SLOS_POS); + if ((info->lli_interrupt == 1) + && (info->dir == PERIPH_TO_MEM)) + MEM_WRITE_BITS(lli_ptr[idx].dmac_lcsp1, + DMA_TRUE, + MEM_LCSP1_SCFG_TIM_MASK, + MEM_LCSP1_SCFG_TIM_POS); + else + MEM_WRITE_BITS(lli_ptr[idx].dmac_lcsp1, + DMA_FALSE, + MEM_LCSP1_SCFG_TIM_MASK, + MEM_LCSP1_SCFG_TIM_POS); + sg++; + } + MEM_WRITE_BITS(lli_ptr[idx - 1].dmac_lcsp1, 0x0, + MEM_LCSP1_SLOS_MASK, MEM_LCSP1_SLOS_POS); + MEM_WRITE_BITS(lli_ptr[idx - 1].dmac_lcsp1, DMA_TRUE, + MEM_LCSP1_SCFG_TIM_MASK, MEM_LCSP1_SCFG_TIM_POS); + } else { + struct dma_logical_dest_lli_info *lli_ptr = NULL; + u32 dlos; + step_size = (0x1 << info->dst_info.data_width); + lli_count = info->sgcount_dest; + sg = info->sg_dest; + info->current_sg = sg; + if (info->lli_block_id_dest < 0) + info->lli_block_id_dest = + get_free_log_lli_block(dma_drv_data->lchan_lli_pool, + info->phys_chan_id); + if (info->lli_block_id_dest < 0) { + stm_error("Free LLI's not available\n"); + return -1; + } + dlos = info->lli_block_id_dest * NUM_LLI_PER_LOG_CHANNEL + 1; + /**********************************************************/ + /*Use first SG item to fill params register */ + REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SDELT), + info->phys_chan_id, SREG_ELEM_LOG_LIDX_MASK, + SREG_ELEM_LOG_LIDX_POS); + MEM_WRITE_BITS(params->dmac_lcsp2, + (sg_dma_len(sg) >> info->dst_info.data_width), + MEM_LCSP2_ECNT_MASK, MEM_LCSP2_ECNT_POS); + MEM_WRITE_BITS(params->dmac_lcsp3, dlos, MEM_LCSP3_DLOS_MASK, + MEM_LCSP3_DLOS_POS); + MEM_WRITE_BITS(params->dmac_lcsp2, + (0x0000FFFFUL & (u32) (sg_dma_address(sg))), + MEM_LCSP2_DPTR_MASK, MEM_LCSP2_DPTR_POS); + MEM_WRITE_BITS(params->dmac_lcsp3, + (0xFFFF0000UL & (u32) (sg_dma_address(sg))) >> + 16, MEM_LCSP3_DPTR_MASK, MEM_LCSP3_DPTR_POS); + if (info->lli_interrupt == 1) + MEM_WRITE_BITS(params->dmac_lcsp3, DMA_TRUE, + MEM_LCSP3_DCFG_TIM_MASK, + MEM_LCSP3_DCFG_TIM_POS); + else + MEM_WRITE_BITS(params->dmac_lcsp3, DMA_FALSE, + MEM_LCSP3_DCFG_TIM_MASK, + MEM_LCSP3_DCFG_TIM_POS); + sg++; + lli_count--; + /************************************************************/ + lli_ptr = (struct dma_logical_dest_lli_info *)base + dlos; + + for (idx = 0; idx < lli_count; idx++) { + lli_ptr[idx].dmac_lcsp3 = params->dmac_lcsp3; + MEM_WRITE_BITS(lli_ptr[idx].dmac_lcsp2, + (sg_dma_len(sg) >> info-> + dst_info.data_width), + MEM_LCSP2_ECNT_MASK, MEM_LCSP2_ECNT_POS); + MEM_WRITE_BITS(lli_ptr[idx].dmac_lcsp2, + (0x0000FFFFUL & + (u32) (sg_dma_address(sg))), + MEM_LCSP2_DPTR_MASK, MEM_LCSP2_DPTR_POS); + MEM_WRITE_BITS(lli_ptr[idx].dmac_lcsp3, + (0xFFFF0000UL & + (u32) (sg_dma_address(sg))) >> 16, + MEM_LCSP3_DPTR_MASK, MEM_LCSP3_DPTR_POS); + MEM_WRITE_BITS(lli_ptr[idx].dmac_lcsp3, + (dlos + idx + 1), MEM_LCSP3_DLOS_MASK, + MEM_LCSP3_DLOS_POS); + if (info->lli_interrupt == 1) + MEM_WRITE_BITS(lli_ptr[idx].dmac_lcsp3, + DMA_TRUE, + MEM_LCSP3_DCFG_TIM_MASK, + MEM_LCSP3_DCFG_TIM_POS); + else + MEM_WRITE_BITS(lli_ptr[idx].dmac_lcsp3, + DMA_FALSE, + MEM_LCSP3_DCFG_TIM_MASK, + MEM_LCSP3_DCFG_TIM_POS); + sg++; + } + MEM_WRITE_BITS(lli_ptr[idx - 1].dmac_lcsp3, 0x0, + MEM_LCSP3_DLOS_MASK, MEM_LCSP3_DLOS_POS); + MEM_WRITE_BITS(lli_ptr[idx - 1].dmac_lcsp3, DMA_TRUE, + MEM_LCSP3_DCFG_TIM_MASK, MEM_LCSP3_DCFG_TIM_POS); + } + return 0; +} + +/** + * map_lli_info_phys_chan() - To Map the SG info into LLI's for Phys channels. + * @info: Information of the channel parameters. + * @type: Whether source or destination half channel. + * This function maps the SG info into LLI's for the Physical channels. + * A free block of LLI's is allocated for a particular physical + * channel and SG info is mapped in that memory block. + * This function returns 0 on success and -1 on failure + * + */ +static int map_lli_info_phys_chan(struct dma_channel_info *info, int type) +{ + int idx = 0; + struct dma_lli_info *lli_ptr = NULL; + u32 temp; + dma_addr_t phys_lli_addr = 0; + struct scatterlist *sg; + u32 lli_count = 0; + u32 fifo_ptr_incr = 0; + stm_dbg(DBG_ST.dma, "map_lli_info_phys_chan():: Setting LLI for %s\n", + (type == + DMA_SRC_HALF_CHANNEL) ? "DMA_SRC_HALF_CHANNEL" : + "DMA_DEST_HALF_CHANNEL"); + + if (type == DMA_SRC_HALF_CHANNEL) { + sg = info->sg_src; + lli_count = info->sgcount_src; + if (info->src_info.addr_inc) + fifo_ptr_incr = (0x1 << info->src_info.data_width); + if (info->lli_block_id_src < 0) + info->lli_block_id_src = + get_free_block(dma_drv_data->pchan_lli_pool); + if (info->lli_block_id_src < 0) { + stm_error("Free LLI's not available\n"); + return -1; + } + temp = ((u32) dma_drv_data->pchan_lli_pool->base_addr.log_addr + + info->lli_block_id_src * + dma_drv_data->pchan_lli_pool->block_size); + lli_ptr = (struct dma_lli_info *)temp; + temp = (u32) (dma_drv_data->pchan_lli_pool->base_addr.phys_addr + + + info->lli_block_id_src + * dma_drv_data->pchan_lli_pool->block_size); + phys_lli_addr = (dma_addr_t) temp; + if (info->link_type == POSTLINK) { + REG_WR_BITS(cio_addr + (info->phys_chan_id, CHAN_REG_SSELT), + (sg_dma_len(sg) >> info-> + src_info.data_width), + SREG_ELEM_PHY_ECNT_MASK, + SREG_ELEM_PHY_ECNT_POS); + REG_WR_BITS(cio_addr + (info->phys_chan_id, CHAN_REG_SSELT), + fifo_ptr_incr, SREG_ELEM_PHY_EIDX_MASK, + SREG_ELEM_PHY_EIDX_POS); + REG_WR_BITS(cio_addr + (info->phys_chan_id, CHAN_REG_SSPTR), + sg_dma_address(sg), FULL32_MASK, NO_SHIFT); + sg++; + lli_count--; + } + + REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SSLNK), + (u32) (phys_lli_addr), FULL32_MASK, NO_SHIFT); + REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SSLNK), + info->link_type, SREG_LNK_PHYS_PRE_MASK, + SREG_LNK_PHY_PRE_POS); + + for (idx = 0; idx < lli_count; idx++) { + lli_ptr[idx].reg_cfg = + REG_RD_BITS(cio_addr + (info->phys_chan_id, + CHAN_REG_SSCFG), FULL32_MASK, + NO_SHIFT); + lli_ptr[idx].reg_elt = + REG_RD_BITS(cio_addr + (info->phys_chan_id, + CHAN_REG_SSELT), FULL32_MASK, + NO_SHIFT); + MEM_WRITE_BITS(lli_ptr[idx].reg_elt, + (sg_dma_len(sg) >> info-> + src_info.data_width), + SREG_ELEM_PHY_ECNT_MASK, + SREG_ELEM_PHY_ECNT_POS); + MEM_WRITE_BITS(lli_ptr[idx].reg_elt, fifo_ptr_incr, + SREG_ELEM_PHY_EIDX_MASK, + SREG_ELEM_PHY_EIDX_POS); + lli_ptr[idx].reg_ptr = sg_dma_address(sg); + lli_ptr[idx].reg_lnk = + (u32) (phys_lli_addr + + (idx + 1) * sizeof(struct dma_lli_info)); + MEM_WRITE_BITS(lli_ptr[idx].reg_lnk, info->link_type, + SREG_LNK_PHYS_PRE_MASK, + SREG_LNK_PHY_PRE_POS); + + sg++; + print_dma_lli(idx, &lli_ptr[idx]); + } + lli_ptr[idx - 1].reg_lnk = 0x0; + MEM_WRITE_BITS(lli_ptr[idx - 1].reg_lnk, info->link_type, + SREG_LNK_PHYS_PRE_MASK, SREG_LNK_PHY_PRE_POS); + MEM_WRITE_BITS(lli_ptr[idx - 1].reg_lnk, DMA_TRUE, + SREG_LNK_PHYS_TCP_MASK, SREG_LNK_PHY_TCP_POS); + MEM_WRITE_BITS(lli_ptr[idx - 1].reg_cfg, DMA_TRUE, + SREG_CFG_PHY_TIM_MASK, SREG_CFG_PHY_TIM_POS); + + } else { + sg = info->sg_dest; + info->current_sg = sg; + lli_count = info->sgcount_dest; + if ((info->dst_info.addr_inc)) + fifo_ptr_incr = (0x1 << info->dst_info.data_width); + info->lli_block_id_dest = + get_free_block(dma_drv_data->pchan_lli_pool); + if (info->lli_block_id_dest < 0) { + stm_error("Free LLI's not available\n"); + return -1; + } + + lli_ptr = (struct dma_lli_info *) + (dma_drv_data->pchan_lli_pool->base_addr.log_addr + + info->lli_block_id_dest * + dma_drv_data->pchan_lli_pool->block_size); + phys_lli_addr = (dma_addr_t) (((u32) + dma_drv_data->pchan_lli_pool-> + base_addr.phys_addr + + info->lli_block_id_dest * + dma_drv_data->pchan_lli_pool-> + block_size)); + + if (info->link_type == POSTLINK) { + if ((info->dir != MEM_TO_MEM) + && (info->lli_interrupt == 1)) + REG_WR_BITS(cio_addr + (info->phys_chan_id, + CHAN_REG_SDCFG), + DMA_TRUE, + SREG_CFG_PHY_TIM_MASK, + SREG_CFG_PHY_TIM_POS); + else + REG_WR_BITS(cio_addr + (info->phys_chan_id, + CHAN_REG_SDCFG), + DMA_FALSE, + SREG_CFG_PHY_TIM_MASK, + SREG_CFG_PHY_TIM_POS); + REG_WR_BITS(cio_addr + (info->phys_chan_id, CHAN_REG_SDELT), + (sg_dma_len(sg)) >> info-> + dst_info.data_width, + SREG_ELEM_PHY_ECNT_MASK, + SREG_ELEM_PHY_ECNT_POS); + REG_WR_BITS(cio_addr + (info->phys_chan_id, CHAN_REG_SDELT), + fifo_ptr_incr, SREG_ELEM_PHY_EIDX_MASK, + SREG_ELEM_PHY_EIDX_POS); + REG_WR_BITS(cio_addr + (info->phys_chan_id, CHAN_REG_SDPTR), + sg_dma_address(sg), FULL32_MASK, NO_SHIFT); + sg++; + lli_count--; + } + + REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SDLNK), + (u32) (phys_lli_addr), FULL32_MASK, NO_SHIFT); + REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SDLNK), + info->link_type, SREG_LNK_PHYS_PRE_MASK, + SREG_LNK_PHY_PRE_POS); + + for (idx = 0; idx < lli_count; idx++) { + lli_ptr[idx].reg_cfg = + REG_RD_BITS(cio_addr + (info->phys_chan_id, + CHAN_REG_SDCFG), FULL32_MASK, + NO_SHIFT); + lli_ptr[idx].reg_lnk = + (u32) (phys_lli_addr + + (idx + 1) * sizeof(struct dma_lli_info)); + MEM_WRITE_BITS(lli_ptr[idx].reg_lnk, info->link_type, + SREG_LNK_PHYS_PRE_MASK, + SREG_LNK_PHY_PRE_POS); + lli_ptr[idx].reg_elt = + REG_RD_BITS(cio_addr + (info->phys_chan_id, + CHAN_REG_SDELT), FULL32_MASK, + NO_SHIFT); + MEM_WRITE_BITS(lli_ptr[idx].reg_elt, + (sg_dma_len(sg) >> info-> + dst_info.data_width), + SREG_ELEM_PHY_ECNT_MASK, + SREG_ELEM_PHY_ECNT_POS); + MEM_WRITE_BITS(lli_ptr[idx].reg_elt, fifo_ptr_incr, + SREG_ELEM_PHY_EIDX_MASK, + SREG_ELEM_PHY_EIDX_POS); + lli_ptr[idx].reg_ptr = sg_dma_address(sg); + if ((info->dir != MEM_TO_MEM) + && (info->lli_interrupt == 1)) + MEM_WRITE_BITS(lli_ptr[idx].reg_cfg, + DMA_TRUE, + SREG_CFG_PHY_TIM_MASK, + SREG_CFG_PHY_TIM_POS); + else + MEM_WRITE_BITS(lli_ptr[idx].reg_cfg, + DMA_FALSE, + SREG_CFG_PHY_TIM_MASK, + SREG_CFG_PHY_TIM_POS); + print_dma_lli(idx, &lli_ptr[idx]); + sg++; + } + MEM_WRITE_BITS(lli_ptr[idx - 1].reg_cfg, DMA_TRUE, + SREG_CFG_PHY_TIM_MASK, SREG_CFG_PHY_TIM_POS); + lli_ptr[idx - 1].reg_lnk = 0x0; + MEM_WRITE_BITS(lli_ptr[idx - 1].reg_lnk, info->link_type, + SREG_LNK_PHYS_PRE_MASK, SREG_LNK_PHY_PRE_POS); + MEM_WRITE_BITS(lli_ptr[idx - 1].reg_lnk, DMA_TRUE, + SREG_LNK_PHYS_TCP_MASK, SREG_LNK_PHY_TCP_POS); + } + return 0; +} + +/** + * set_std_phy_src_half_channel_params() - set params for src phy half channel + * @info: Information of the channel parameters. + * This function sets the channel Parameters for standard source half channel. + * Channel is configured as Physical channel. It maps sg info by calling + * map_lli_info_phys_chan() for src channel. If transfer length is more than + * 64K elements, it calls calculate_lli_required() and generate_sg_list() + * API's to create LLI's. + * It returns 0 on success and -1 on failure + * + */ +static int set_std_phy_src_half_channel_params(struct dma_channel_info + *info) +{ + u32 num_elems; + u32 step_size = 0; + if (info->src_info.addr_inc) + step_size = (0x1 << info->src_info.data_width); + + num_elems = info->src_xfer_elem; + REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SSCFG), + info->src_cfg, FULL32_MASK, NO_SHIFT); + REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SSPTR), 0x0, + FULL32_MASK, NO_SHIFT); + REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SSELT), 0x0, + FULL32_MASK, NO_SHIFT); + REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SSLNK), 0x0, + FULL32_MASK, NO_SHIFT); + + if ((num_elems >= MAX_NUM_OF_ELEM_IN_A_XFER) || (info->sg_src)) { + u32 lli_size; + u32 lli_count; + REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SSCFG), + DMA_FALSE, SREG_CFG_PHY_TIM_MASK, + SREG_CFG_PHY_TIM_POS); + if (!info->sg_src) { + lli_count = calculate_lli_required(info, &lli_size); + if (lli_count > NUM_SG_PER_REQUEST) { + stm_error("Insufficient LLI's, \ + lli count very high = %d\n", lli_count); + return -1; + } + if (!generate_sg_list + (info, DMA_SRC_HALF_CHANNEL, lli_size, lli_count)) { + stm_error("cannot generate sg list\n"); + return -1; + } + } + print_sg_info(info->sg_src, info->sgcount_src); + if (map_lli_info_phys_chan(info, DMA_SRC_HALF_CHANNEL)) { + stm_error("Unable to map SG info to LLI...."); + return -1; + } + } else { + REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SSELT), + num_elems, SREG_ELEM_PHY_ECNT_MASK, + SREG_ELEM_PHY_ECNT_POS); + REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SSELT), + step_size, SREG_ELEM_PHY_EIDX_MASK, + SREG_ELEM_PHY_EIDX_POS); + + REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SSPTR), + (u32) info->src_addr, FULL32_MASK, NO_SHIFT); + REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SSLNK), + 0x1, FULL32_MASK, NO_SHIFT); + } + return 0; +} + +static int set_std_phy_src_half_channel_params_mem(struct dma_channel_info + *info) +{ + + enum dma_master_id master_id; + enum dma_half_chan_sync sync_type; + + info->src_cfg = 0; + + if ((info->dir == PERIPH_TO_MEM) || (info->dir == PERIPH_TO_PERIPH)) { + master_id = DMA_MASTER_1; + sync_type = DMA_PACKET_SYNC; + info->src_info.addr_inc = DMA_ADR_NOINC; + } else { + master_id = DMA_MASTER_0; + sync_type = DMA_NO_SYNC; + } + + MEM_WRITE_BITS(info->src_cfg, master_id, + SREG_CFG_PHY_MST_MASK, SREG_CFG_PHY_MST_POS); + MEM_WRITE_BITS(info->src_cfg, DMA_FALSE, + SREG_CFG_PHY_TIM_MASK, SREG_CFG_PHY_TIM_POS); + MEM_WRITE_BITS(info->src_cfg, DMA_TRUE, + SREG_CFG_PHY_EIM_MASK, SREG_CFG_PHY_EIM_POS); + MEM_WRITE_BITS(info->src_cfg, DMA_TRUE, + SREG_CFG_PHY_PEN_MASK, SREG_CFG_PHY_PEN_POS); + MEM_WRITE_BITS(info->src_cfg, info->src_info.burst_size, + SREG_CFG_PHY_PSIZE_MASK, SREG_CFG_PHY_PSIZE_POS); + MEM_WRITE_BITS(info->src_cfg, info->src_info.data_width, + SREG_CFG_PHY_ESIZE_MASK, SREG_CFG_PHY_ESIZE_POS); + MEM_WRITE_BITS(info->src_cfg, info->priority, + SREG_CFG_PHY_PRI_MASK, SREG_CFG_PHY_PRI_POS); + MEM_WRITE_BITS(info->src_cfg, info->src_info.endianess, + SREG_CFG_PHY_LBE_MASK, SREG_CFG_PHY_LBE_POS); + MEM_WRITE_BITS(info->src_cfg, sync_type, + SREG_CFG_PHY_TM_MASK, SREG_CFG_PHY_TM_POS); + MEM_WRITE_BITS(info->src_cfg, info->src_info.event_line, + SREG_CFG_PHY_EVTL_MASK, SREG_CFG_PHY_EVTL_POS); + return 0; + +} + +/** + * set_std_phy_dst_half_channel_params() - set params for dst phy half channel + * @info: Information of the channel parameters. + * This function sets the channel Parameters for standard dest half channel. + * Channel is configured as Physical channel. It maps sg info by calling + * map_lli_info_phys_chan() for dst channel. If transfer length is more than + * 64K elements, it calls calculate_lli_required() and generate_sg_list() + * API's to create LLI's. + * It returns 0 on success and -1 on failure + * + */ +static int set_std_phy_dst_half_channel_params(struct dma_channel_info + *info) +{ + u32 step_size = 0; + u32 num_elems; + num_elems = info->dst_xfer_elem; + if (info->dst_info.addr_inc) + step_size = (0x1 << info->dst_info.data_width); + REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SDCFG), + info->dst_cfg, FULL32_MASK, NO_SHIFT); + REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SDELT), 0x0, + FULL32_MASK, NO_SHIFT); + REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SDPTR), 0x0, + FULL32_MASK, NO_SHIFT); + REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SDLNK), 0x0, + FULL32_MASK, NO_SHIFT); + + if ((num_elems >= MAX_NUM_OF_ELEM_IN_A_XFER) || (info->sg_dest)) { + u32 lli_size; + u32 lli_count; + REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SDCFG), + DMA_FALSE, SREG_CFG_PHY_TIM_MASK, + SREG_CFG_PHY_TIM_POS); + if (!info->sg_dest) { + lli_count = calculate_lli_required(info, &lli_size); + if (lli_count > NUM_SG_PER_REQUEST) { + stm_error("Insufficient LLI's, \ + lli count very high = %d\n", lli_count); + return -1; + } + if (!generate_sg_list + (info, DMA_DEST_HALF_CHANNEL, lli_size, + lli_count)) { + stm_error("cannot generate sg list\n"); + return -1; + } + } + print_sg_info(info->sg_dest, info->sgcount_dest); + if (map_lli_info_phys_chan(info, DMA_DEST_HALF_CHANNEL)) + return -1; + } else { + REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SDELT), + num_elems, SREG_ELEM_PHY_ECNT_MASK, + SREG_ELEM_PHY_ECNT_POS); + REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SDELT), + step_size, SREG_ELEM_PHY_EIDX_MASK, + SREG_ELEM_PHY_EIDX_POS); + REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SDPTR), + (u32) info->dst_addr, FULL32_MASK, NO_SHIFT); + REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SDLNK), + 0x1, FULL32_MASK, NO_SHIFT); + } + return 0; +} + +static int set_std_phy_dst_half_channel_params_mem(struct dma_channel_info + *info) +{ + enum dma_master_id master_id; + enum dma_half_chan_sync sync_type; + + info->dst_cfg = 0; + + if ((info->dir == MEM_TO_PERIPH) || (info->dir == PERIPH_TO_PERIPH)) { + master_id = DMA_MASTER_1; + sync_type = DMA_PACKET_SYNC; + info->dst_info.addr_inc = DMA_ADR_NOINC; + } else { + master_id = DMA_MASTER_0; + sync_type = DMA_NO_SYNC; + } + + MEM_WRITE_BITS(info->dst_cfg, master_id, + SREG_CFG_PHY_MST_MASK, SREG_CFG_PHY_MST_POS); + MEM_WRITE_BITS(info->dst_cfg, DMA_TRUE, + SREG_CFG_PHY_TIM_MASK, SREG_CFG_PHY_TIM_POS); + MEM_WRITE_BITS(info->dst_cfg, DMA_TRUE, + SREG_CFG_PHY_EIM_MASK, SREG_CFG_PHY_EIM_POS); + MEM_WRITE_BITS(info->dst_cfg, DMA_TRUE, + SREG_CFG_PHY_PEN_MASK, SREG_CFG_PHY_PEN_POS); + MEM_WRITE_BITS(info->dst_cfg, info->dst_info.burst_size, + SREG_CFG_PHY_PSIZE_MASK, SREG_CFG_PHY_PSIZE_POS); + MEM_WRITE_BITS(info->dst_cfg, info->dst_info.data_width, + SREG_CFG_PHY_ESIZE_MASK, SREG_CFG_PHY_ESIZE_POS); + MEM_WRITE_BITS(info->dst_cfg, info->priority, + SREG_CFG_PHY_PRI_MASK, SREG_CFG_PHY_PRI_POS); + MEM_WRITE_BITS(info->dst_cfg, info->dst_info.endianess, + SREG_CFG_PHY_LBE_MASK, SREG_CFG_PHY_LBE_POS); + MEM_WRITE_BITS(info->dst_cfg, sync_type, + SREG_CFG_PHY_TM_MASK, SREG_CFG_PHY_TM_POS); + MEM_WRITE_BITS(info->dst_cfg, info->dst_info.event_line, + SREG_CFG_PHY_EVTL_MASK, SREG_CFG_PHY_EVTL_POS); + + return 0; + +} + +/** + * set_std_phy_channel_params() - maps the cfg params for std phy channel + * @info: Information of the channel parameters. + * This function maps the configuration parameters of source and dest + * half channels on to the registers by calling function + * set_std_phy_src_half_channel_params() for source half channel and + * set_std_phy_dst_half_channel_params() for dest half channel. + * This function returns 0 on success and -1 on failure. + * + */ +static int set_std_phy_channel_params(struct dma_channel_info *info) +{ + if (set_std_phy_src_half_channel_params(info)) { + stm_error("Unable to map source half channel params"); + return -1; + } + if (set_std_phy_dst_half_channel_params(info)) { + stm_error("Unable to map destination half channel params"); + return -1; + } + return 0; +} + +static int set_std_phy_channel_params_mem(struct dma_channel_info *info) +{ + if (set_std_phy_src_half_channel_params_mem(info)) { + stm_error("Unable to map source half channel params"); + return -1; + } + if (set_std_phy_dst_half_channel_params_mem(info)) { + stm_error("Unable to map destination half channel params"); + return -1; + } + return 0; +} + +/** + * set_std_log_dst_half_channel_params() - map channel params for dest + * logical half channel + * @info: Information of the channel parameters. + * This function sets the channel Parameters for standard Destination + * half channel. + * Channel is configured as Logical channel. It maps sg info by calling + * map_lli_info_log_chan() for destination half channel. If transfer + * length is more than 64K elements, it calls calculate_lli_required() + * and generate_sg_list() API's to create LLI's. Activate Event Line + * if destination is a peripheral. + * This function returns 0 on success and -1 on failure. + * + */ +static int set_std_log_dst_half_channel_params(struct dma_channel_info + *info) +{ + u32 num_elems; + struct std_log_memory_param *params; + + num_elems = info->dst_xfer_elem; + + if (info->dir == MEM_TO_PERIPH) { + params = + (struct std_log_memory_param + *)((void *)(dma_drv_data->lchan_params_base.log_addr) + + (info->dst_dev_type * 32) + 16); + REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SDLNK), + ACTIVATE_EVENTLINE, + EVENTLINE_MASK(info->dst_info.event_line), + EVENTLINE_POS(info->dst_info.event_line)); + } else { + params = + (struct std_log_memory_param + *)((void *)(dma_drv_data->lchan_params_base.log_addr) + + (info->src_dev_type * 32)); + } + params->dmac_lcsp3 = info->dmac_lcsp3; + if (info->invalid) { + REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SDCFG), + info->priority, SREG_CFG_LOG_PRI_MASK, + SREG_CFG_LOG_PRI_POS); + REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SDCFG), + info->dst_info.endianess, + SREG_CFG_LOG_LBE_MASK, SREG_CFG_LOG_LBE_POS); + REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SDCFG), + 0x1, SREG_CFG_LOG_GIM_MASK, SREG_CFG_LOG_GIM_POS); + REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SDCFG), + DMA_MASTER_0, SREG_CFG_LOG_MFU_MASK, + SREG_CFG_LOG_MFU_POS); + } + + if ((num_elems >= MAX_NUM_OF_ELEM_IN_A_XFER) || (info->sg_dest)) { + u32 lli_size; + u32 lli_count; + MEM_WRITE_BITS(params->dmac_lcsp3, DMA_FALSE, + MEM_LCSP3_DCFG_TIM_MASK, MEM_LCSP3_DCFG_TIM_POS); + if (!info->sg_dest) { + lli_count = calculate_lli_required(info, &lli_size); + if (lli_count > NUM_LLI_PER_LOG_CHANNEL + 1) { + stm_error("Insufficient LLI's, \ + lli count very high = %d\n", lli_count); + return -1; + } + if (!generate_sg_list + (info, DMA_DEST_HALF_CHANNEL, lli_size, + lli_count)) { + stm_error("cannot generate sg list\n"); + return -1; + } + } + print_sg_info(info->sg_dest, info->sgcount_dest); + if (map_lli_info_log_chan(info, DMA_DEST_HALF_CHANNEL, params)) + return -1; + } else { + MEM_WRITE_BITS(params->dmac_lcsp2, num_elems, + MEM_LCSP2_ECNT_MASK, MEM_LCSP2_ECNT_POS); + MEM_WRITE_BITS(params->dmac_lcsp2, + (0x0000FFFFUL & (u32) (info->dst_addr)), + MEM_LCSP2_DPTR_MASK, MEM_LCSP2_DPTR_POS); + MEM_WRITE_BITS(params->dmac_lcsp3, + (0xFFFF0000UL & (u32) (info->dst_addr)) >> 16, + MEM_LCSP3_DPTR_MASK, MEM_LCSP3_DPTR_POS); + MEM_WRITE_BITS(params->dmac_lcsp3, 0x1, MEM_LCSP3_DTCP_MASK, + MEM_LCSP3_DTCP_POS); + } + return 0; +} + +static int set_std_log_dst_half_channel_params_mem(struct dma_channel_info + *info) +{ + + enum dma_master_id master_id; + int tim; + int increment_addr; + if (info->dir == MEM_TO_PERIPH) { + master_id = DMA_MASTER_1; + tim = DMA_TRUE; + increment_addr = DMA_FALSE; + } else { + master_id = DMA_MASTER_0; + tim = DMA_TRUE; + increment_addr = DMA_TRUE; + } + MEM_WRITE_BITS(info->dmac_lcsp3, master_id, MEM_LCSP3_DCFG_MST_MASK, + MEM_LCSP3_DCFG_MST_POS); + MEM_WRITE_BITS(info->dmac_lcsp3, tim, MEM_LCSP3_DCFG_TIM_MASK, + MEM_LCSP3_DCFG_TIM_POS); + MEM_WRITE_BITS(info->dmac_lcsp3, DMA_TRUE, + MEM_LCSP3_DCFG_EIM_MASK, MEM_LCSP3_DCFG_EIM_POS); + MEM_WRITE_BITS(info->dmac_lcsp3, increment_addr, + MEM_LCSP3_DCFG_INCR_MASK, MEM_LCSP3_DCFG_INCR_POS); + MEM_WRITE_BITS(info->dmac_lcsp3, info->dst_info.burst_size, + MEM_LCSP3_DCFG_PSIZE_MASK, MEM_LCSP3_DCFG_PSIZE_POS); + MEM_WRITE_BITS(info->dmac_lcsp3, info->dst_info.data_width, + MEM_LCSP3_DCFG_ESIZE_MASK, MEM_LCSP3_DCFG_ESIZE_POS); + MEM_WRITE_BITS(info->dmac_lcsp3, 0x0, MEM_LCSP3_DLOS_MASK, + MEM_LCSP3_DLOS_POS); + MEM_WRITE_BITS(info->dmac_lcsp3, 0x1, MEM_LCSP3_DTCP_MASK, + MEM_LCSP3_DTCP_POS); + + return 0; + +} + +/** + * set_std_log_src_half_channel_params() - map channel params for src + * logical half channel + * @info: Information of the channel parameters. + * This function sets the channel Parameters for standard src half channel. + * Channel is configured as Logical channel. It maps sg info by calling + * map_lli_info_log_chan() for source half channel. If transfer + * length is more than 64K elements, it calls calculate_lli_required() + * and generate_sg_list() API's to create LLI's. Activate Event Line + * if source is a peripheral. + * This function returns 0 on success and -1 on failure. + * + */ +static int set_std_log_src_half_channel_params(struct dma_channel_info + *info) +{ + u32 num_elems; + struct std_log_memory_param *params = NULL; + + num_elems = info->src_xfer_elem; + + if (info->dir == PERIPH_TO_MEM) { + params = + (struct std_log_memory_param + *)((void *)(dma_drv_data->lchan_params_base.log_addr) + + (info->src_dev_type * 32)); + stm_dbg(DBG_ST.dma, "Params address : %x dev_indx = %d \n", + (u32) params, info->src_dev_type); + REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SSLNK), + ACTIVATE_EVENTLINE, + EVENTLINE_MASK(info->src_info.event_line), + EVENTLINE_POS(info->src_info.event_line)); + } else { + params = + (struct std_log_memory_param + *)((void *)(dma_drv_data->lchan_params_base.log_addr) + + (info->dst_dev_type * 32) + 16); + } + params->dmac_lcsp1 = info->dmac_lcsp1; + if (info->invalid) { + REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SSCFG), + info->priority, SREG_CFG_LOG_PRI_MASK, + SREG_CFG_LOG_PRI_POS); + REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SSCFG), + info->src_info.endianess, + SREG_CFG_LOG_LBE_MASK, SREG_CFG_LOG_LBE_POS); + REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SSCFG), + 0x1, SREG_CFG_LOG_GIM_MASK, SREG_CFG_LOG_GIM_POS); + REG_WR_BITS(cio_addr(info->phys_chan_id, CHAN_REG_SSCFG), + DMA_MASTER_0, SREG_CFG_LOG_MFU_MASK, + SREG_CFG_LOG_MFU_POS); + } + if ((num_elems >= MAX_NUM_OF_ELEM_IN_A_XFER) || (info->sg_src)) { + u32 lli_size; + u32 lli_count; + MEM_WRITE_BITS(params->dmac_lcsp1, DMA_FALSE, + MEM_LCSP1_SCFG_TIM_MASK, MEM_LCSP1_SCFG_TIM_POS); + if (!info->sg_src) { + lli_count = calculate_lli_required(info, &lli_size); + if (lli_count > NUM_LLI_PER_LOG_CHANNEL + 1) { + stm_error("Insufficient LLI's, \ + lli count very high = %d\n", lli_count); + return -1; + } + if (!generate_sg_list + (info, DMA_SRC_HALF_CHANNEL, lli_size, lli_count)) { + stm_error("cannot generate sg list\n"); + return -1; + } + } + print_sg_info(info->sg_src, info->sgcount_src); + if (map_lli_info_log_chan(info, DMA_SRC_HALF_CHANNEL, params)) { + stm_error("Unable to map SG info on \ + LLI for src half channel"); + return -1; + } + } else { + MEM_WRITE_BITS(params->dmac_lcsp0, num_elems, + MEM_LCSP0_ECNT_MASK, MEM_LCSP0_ECNT_POS); + MEM_WRITE_BITS(params->dmac_lcsp0, + (0x0000FFFFUL & (u32) (info->src_addr)), + MEM_LCSP0_SPTR_MASK, MEM_LCSP0_SPTR_POS); + MEM_WRITE_BITS(params->dmac_lcsp1, + (0xFFFF0000 & (u32) (info->src_addr)) >> 16, + MEM_LCSP1_SPTR_MASK, MEM_LCSP1_SPTR_POS); + } + return 0; +} + +static int set_std_log_src_half_channel_params_mem(struct dma_channel_info + *info) +{ + + enum dma_master_id master_id; + int tim; + int increment_addr; + if (info->dir == PERIPH_TO_MEM) { + master_id = DMA_MASTER_1; + tim = DMA_FALSE; + increment_addr = DMA_FALSE; + } else { + master_id = DMA_MASTER_0; + tim = DMA_FALSE; + increment_addr = DMA_TRUE; + } + MEM_WRITE_BITS(info->dmac_lcsp1, master_id, MEM_LCSP1_SCFG_MST_MASK, + MEM_LCSP1_SCFG_MST_POS); + MEM_WRITE_BITS(info->dmac_lcsp1, tim, MEM_LCSP1_SCFG_TIM_MASK, + MEM_LCSP1_SCFG_TIM_POS); + MEM_WRITE_BITS(info->dmac_lcsp1, DMA_TRUE, + MEM_LCSP1_SCFG_EIM_MASK, MEM_LCSP1_SCFG_EIM_POS); + MEM_WRITE_BITS(info->dmac_lcsp1, increment_addr, + MEM_LCSP1_SCFG_INCR_MASK, MEM_LCSP1_SCFG_INCR_POS); + MEM_WRITE_BITS(info->dmac_lcsp1, info->src_info.burst_size, + MEM_LCSP1_SCFG_PSIZE_MASK, MEM_LCSP1_SCFG_PSIZE_POS); + MEM_WRITE_BITS(info->dmac_lcsp1, info->src_info.data_width, + MEM_LCSP1_SCFG_ESIZE_MASK, MEM_LCSP1_SCFG_ESIZE_POS); + MEM_WRITE_BITS(info->dmac_lcsp1, 0x0, MEM_LCSP1_SLOS_MASK, + MEM_LCSP1_SLOS_POS); + MEM_WRITE_BITS(info->dmac_lcsp1, 0x1, MEM_LCSP1_STCP_MASK, + MEM_LCSP1_STCP_POS); + + return 0; + +} + +/** + * set_std_log_channel_params() - maps cfg params for std logical channel + * @info: Information of the channel parameters. + * + */ +static int set_std_log_channel_params(struct dma_channel_info *info) +{ + if (set_std_log_src_half_channel_params(info)) + return -1; + if (set_std_log_dst_half_channel_params(info)) + return -1; + return 0; +} + +static int set_std_log_channel_params_mem(struct dma_channel_info *info) +{ + if (set_std_log_src_half_channel_params_mem(info)) + return -1; + if (set_std_log_dst_half_channel_params_mem(info)) + return -1; + return 0; +} + +/** + * process_dma_pipe_info() - process the DMA channel info sent by user + * @pipe_id: Channel Id for which this information is to be set + * @pipe_info: Information struct of the given channel given by user + * This function processes info supplied by the client driver. It stores + * the required info in to it;s internal data structure. + * It returns 0 on success and -1 on failure + * + */ +static int process_dma_pipe_info(struct dma_channel_info *info, + struct stm_dma_pipe_info *pipe_info) +{ + unsigned long flags; + + if (info && pipe_info) { + info->invalid = 1; + spin_lock_irqsave(&info->cfg_lock, flags); + if (info->active) + stm_dbg(DBG_ST.dma, + "Modifying the info while channel active..\n"); + info->pr_type = + MEM_READ_BITS(pipe_info->channel_type, 0x3, + INFO_CH_TYPE_POS); + info->priority = + MEM_READ_BITS(pipe_info->channel_type, + (0x3 << INFO_PRIO_TYPE_POS), + INFO_PRIO_TYPE_POS); + info->security = + MEM_READ_BITS(pipe_info->channel_type, + (0x3 << INFO_SEC_TYPE_POS), + INFO_SEC_TYPE_POS); + info->chan_mode = + MEM_READ_BITS(pipe_info->channel_type, + (0x3 << INFO_CH_MODE_TYPE_POS), + INFO_CH_MODE_TYPE_POS); + info->mode_option = + MEM_READ_BITS(pipe_info->channel_type, + (0x3 << INFO_CH_MODE_OPTION_POS), + INFO_CH_MODE_OPTION_POS); + info->link_type = + MEM_READ_BITS(pipe_info->channel_type, + (0x1 << INFO_LINK_TYPE_POS), + INFO_LINK_TYPE_POS); + info->lli_interrupt = + MEM_READ_BITS(pipe_info->channel_type, + (0x1 << INFO_TIM_POS), INFO_TIM_POS); + info->dir = pipe_info->dir; + info->src_dev_type = pipe_info->src_dev_type; + info->dst_dev_type = pipe_info->dst_dev_type; + info->src_info.endianess = pipe_info->src_info.endianess; + info->src_info.data_width = pipe_info->src_info.data_width; + info->src_info.burst_size = pipe_info->src_info.burst_size; + info->src_info.buffer_type = pipe_info->src_info.buffer_type; + if (info->src_dev_type != DMA_DEV_SRC_MEMORY) { + info->src_info.event_group = info->src_dev_type / 16; + info->src_info.event_line = info->src_dev_type % 16; + } else { + info->src_info.event_group = 0; + info->src_info.event_line = 0; + } + info->dst_info.endianess = pipe_info->dst_info.endianess; + info->dst_info.data_width = pipe_info->dst_info.data_width; + info->dst_info.burst_size = pipe_info->dst_info.burst_size; + info->dst_info.buffer_type = pipe_info->dst_info.buffer_type; + if (info->dst_dev_type != DMA_DEV_DEST_MEMORY) { + info->dst_info.event_group = info->dst_dev_type / 16; + info->dst_info.event_line = info->dst_dev_type % 16; + } else { + info->dst_info.event_group = 0; + info->dst_info.event_line = 0; + } + + if (info->dir == MEM_TO_MEM) { + info->src_info.addr_inc = pipe_info->src_info.addr_inc; + info->dst_info.addr_inc = pipe_info->dst_info.addr_inc; + } + + print_dma_channel_info(info); + if (info->pr_type == DMA_STANDARD) { + if (info->chan_mode == DMA_CHAN_IN_PHYS_MODE) { + if (set_std_phy_channel_params_mem(info)) { + stm_error("Could not set parameters \ + for channel in phy mode\n"); + } + } else if (info->chan_mode == DMA_CHAN_IN_LOG_MODE) { + if (set_std_log_channel_params_mem(info)) { + stm_error + ("Could not set parameters for \ + channel in Log mode\n"); + } + } else { + stm_error("Operation Mode not yet supported"); + } + } else { /*DMA_EXTENDED */ + stm_error("Extended Channels not supported"); + } + spin_unlock_irqrestore(&info->cfg_lock, flags); + return 0; + } else { + stm_error("NULL info structure\n"); + return -1; + } +} + +static inline int validate_pipe_info(struct stm_dma_pipe_info *info) +{ + if (!info) { + stm_error("Info is Null"); + return -1; + } + if (0x0 == MEM_READ_BITS(info->channel_type, 0x3, INFO_CH_TYPE_POS)) { + stm_error("Configuration wrong:: \ + Physical resource type incorrect\n"); + return -1; + } + if (0x0 == MEM_READ_BITS(info->channel_type, + (0x3 << INFO_PRIO_TYPE_POS), + INFO_PRIO_TYPE_POS)) { + stm_error("Configuration wrong:: incorrect Priority...\n"); + return -1; + } + if (0x0 == MEM_READ_BITS(info->channel_type, + (0x3 << INFO_SEC_TYPE_POS), + INFO_SEC_TYPE_POS)) { + stm_error("Configuration wrong: incorrect security type\n"); + return -1; + } + if (0x0 == MEM_READ_BITS(info->channel_type, + (0x3 << INFO_CH_MODE_TYPE_POS), + INFO_CH_MODE_TYPE_POS)) { + stm_error("Configuration wrong:: Wrong channel mode\n"); + return -1; + } + if (0x0 == MEM_READ_BITS(info->channel_type, + (0x3 << INFO_CH_MODE_OPTION_POS), + INFO_CH_MODE_OPTION_POS)) { + stm_error("Configuration wrong:: incorrect mode option\n"); + + return -1; + } + return 0; +} + +/** + * get_inititalized_info_structure() - Allocate a new channel info structure + * Returns pointer inititalized info structure(struct dma_channel_info *), + * or NULL in case of error + */ +static struct dma_channel_info *get_inititalized_info_structure(void) +{ + struct dma_channel_info *info = NULL; + info = (struct dma_channel_info *) + kzalloc(sizeof(struct dma_channel_info), GFP_KERNEL); + if (!info) { + stm_error("Could not allocate memory for \ + info structure for new channel\n"); + return NULL; + } + info->phys_chan_id = DMA_CHAN_NOT_ALLOCATED; + info->channel_id = -1; + info->lli_block_id_src = -1; + info->lli_block_id_dest = -1; + info->sg_block_id_src = -1; + info->sg_block_id_dest = -1; + info->sg_dest = NULL; + info->sg_src = NULL; + info->current_sg = NULL; + info->active = 0; + info->invalid = 1; + info->dmac_lcsp3 = 0; + info->dmac_lcsp1 = 0; + info->src_info.addr_inc = DMA_ADR_INC; + info->dst_info.addr_inc = DMA_ADR_INC; + spin_lock_init(&info->cfg_lock); + return info; +} + +/** + * stm_request_dma() - API for requesting a DMA channel used by + * client driver + * @channel: Channel Id which is returned to client on succefull allocation + * @pipe_info: Information struct of the given channel given by user + * This API is called by the client driver to request for a channel. On + * successful allocation of channel 0 is returned. This API first allocates + * a new info structure for the channel(used by Driver to maintain internal + * state for this pipe). A new pipe_id is allocated for this request.The channel + * information as requested by client in pipe_info structure are then verified + * and copied in the info structure we allocated using process_dma_pipe_info(). + * If client requests to reserve channel, it is done at this point by calling + * acquire_physical_resource(). Reference for this info structure are then + * stored in pipe_info array. If channel has been reserved then entry is also + * stored in dma_chan_info array. + * + */ +int stm_request_dma(int *channel, struct stm_dma_pipe_info *pipe_info) +{ + struct dma_channel_info *new_info; + int pipe_id = -1; + int retval = 0; + + if (validate_pipe_info(pipe_info)) { + *channel = -1; + return -EINVAL; + } + + new_info = get_inititalized_info_structure(); + + if (!new_info) { + *channel = -1; + return -ENOMEM; + } + + pipe_id = allocate_pipe_id(); + + if (pipe_id >= 0) { + *channel = pipe_id; + new_info->pipe_id = pipe_id; + + if (process_dma_pipe_info(new_info, pipe_info)) { + retval = -EINVAL; + goto error_request; + } + if (pipe_info->reserve_channel) { + allocate_free_dma_channel(new_info); + if (new_info->phys_chan_id == -1) { + retval = -EINVAL; + goto error_request; + } + } + dma_drv_data->pipe_info[pipe_id] = new_info; + if (new_info->channel_id >= 0) { + /*i.e. for reserved channels only */ + dma_drv_data->dma_chan_info[new_info->channel_id] = + new_info; + } + + } else { + retval = -EAGAIN; + goto error_pipeid; + } + return retval; + +error_request: + deallocate_pipe_id(pipe_id); +error_pipeid: + *channel = -1; + kfree(new_info); + return retval; +} +EXPORT_SYMBOL(stm_request_dma); + +/** + * stm_set_callback_handler() - To set a callback handler for the + * given channel + * @pipe_id: pipe id allocated to client driver from the call + * stm_request_dma() + * @callback_handler: Callback function to be invoked in case of + * completion or error on xfer + * @data: Data pointer with which this callback function must be invoked. + * This function returns 0 on success, -1 on error. + * This callback handler you set here would be invoked when Xfer is complete. + * Calling this function is optional. + * If you do not call this function then you need to poll using + * stm_dma_residue() API to check whether you DMA xfer has completed or not + * + */ +int stm_set_callback_handler(int pipe_id, void *callback_handler, + void *data) +{ + struct dma_channel_info *info; + unsigned long flags; + + if (is_pipeid_invalid(pipe_id)) { + stm_error("Invalid pipe id"); + return -1; + } + info = dma_drv_data->pipe_info[pipe_id]; + if (info) { + if (info->active) + stm_dbg(DBG_ST.dma, + "Modifying the info while channel active..\n"); + spin_lock_irqsave(&info->cfg_lock, flags); + info->callback = callback_handler; + info->data = data; + spin_unlock_irqrestore(&info->cfg_lock, flags); + return 0; + } else { + stm_error("Info structure for this pipe is unavailable\n"); + return -EINVAL; + } +} +EXPORT_SYMBOL(stm_set_callback_handler); + +/** + * stm_configure_dma_channel() - To configure a DMA pipe after it + * has been requested + * @pipe_id: pipe id allocated to client driver from the call + * stm_request_dma() + * @pipe_info: Updated pipe information structure. + * This function returns 0 on success, negative value on error. + * Calling this function is optional if you have already configured + * your pipe during call to API stm_request_dma(). + * It is required only if you need to update params. + * + */ +int stm_configure_dma_channel(int pipe_id, + struct stm_dma_pipe_info *pipe_info) +{ + int retval = 0; + struct dma_channel_info *info; + + if (is_pipeid_invalid(pipe_id)) { + stm_error("Invalid pipe id"); + return -1; + } + info = dma_drv_data->pipe_info[pipe_id]; + if (!info) { + stm_error("Null Info structure...."); + return -1; + } + + retval = process_dma_pipe_info(info, pipe_info); + if (retval) + return -EINVAL; + else + return 0; +} +EXPORT_SYMBOL(stm_configure_dma_channel); + +/** + * stm_set_dma_addr() - To set source and destination address for + * the given DMA channel + * @pipe_id: pipe_id for which dma addresses have to be set + * @src_addr: Source address from where DMA will start + * @dst_addr: Dest address at which DMA controller will copy data + * + */ +void stm_set_dma_addr(int pipe_id, void *src_addr, void *dst_addr) +{ + struct dma_channel_info *info; + unsigned long flags = 0; + + if (is_pipeid_invalid(pipe_id)) { + stm_error("Invalid pipe id"); + return; + } + info = dma_drv_data->pipe_info[pipe_id]; + if (!info) { + stm_error("Null Info structure...."); + return; + } + if (info->active) + stm_dbg(DBG_ST.dma, + "Modifying the info while channel active..\n"); + + spin_lock_irqsave(&info->cfg_lock, flags); + info->src_addr = src_addr; + info->dst_addr = dst_addr; + spin_unlock_irqrestore(&info->cfg_lock, flags); +} +EXPORT_SYMBOL(stm_set_dma_addr); + +/** + * stm_set_dma_count() - To set dma count(number of bytes to transfer) + * @pipe_id: client Pipe id for which count to transfer has to be set + * @count: Number of bytes to xfer + * + */ +void stm_set_dma_count(int pipe_id, int count) +{ + struct dma_channel_info *info; + unsigned long flags = 0; + + if (is_pipeid_invalid(pipe_id)) { + stm_error("Invalid pipe id"); + return; + } + info = dma_drv_data->pipe_info[pipe_id]; + if (!info) { + stm_error("Null Info structure...."); + return; + } + if (info->active) + stm_dbg(DBG_ST.dma, + "Modifying the info while channel active..\n"); + spin_lock_irqsave(&info->cfg_lock, flags); + info->xfer_len = count; + info->src_xfer_elem = count >> info->src_info.data_width; + info->dst_xfer_elem = count >> info->dst_info.data_width; + spin_unlock_irqrestore(&info->cfg_lock, flags); +} +EXPORT_SYMBOL(stm_set_dma_count); + +/** + * stm_set_dma_sg() - To set the SG list for a given pipe id. + * @pipe_id: client Pipe id for which sg list has to be set + * @sg: sg List to be set + * @nr_sg: Number of items in SG list + * @type: Whether sg list is for src or destination(0 - src, 1 - dst) + * + */ +void stm_set_dma_sg(int pipe_id, struct scatterlist *sg, int nr_sg, + int type) +{ + struct dma_channel_info *info; + unsigned long flags = 0; + + if (is_pipeid_invalid(pipe_id)) { + stm_error("Invalid pipe id"); + return; + } + info = dma_drv_data->pipe_info[pipe_id]; + if (!info) { + stm_error("Null Info structure...."); + return; + } + if (info->active) + stm_dbg(DBG_ST.dma, + "Modifying the info while channel active..\n"); + spin_lock_irqsave(&info->cfg_lock, flags); + if (type == DMA_SRC_HALF_CHANNEL) { + info->sg_src = sg; + info->sgcount_src = nr_sg; + } else { + info->sg_dest = sg; + info->sgcount_dest = nr_sg; + } + spin_unlock_irqrestore(&info->cfg_lock, flags); +} +EXPORT_SYMBOL(stm_set_dma_sg); + +/** + * stm_enable_dma() - To enable a DMA channel + * @pipe_id: client Id whose DMA channel has to be enabled + * Unless DMA channel was reserved, at this point allocation for a + * physical resource is done on which this request would run. + * Once a physical resource is allocated, corresponding DMA channel + * parameters are loaded on to the DMA registers, and physical + * resource is put in a running state. + * It returns 0 on success, -1 on error + * + */ +int stm_enable_dma(int pipe_id) +{ + struct dma_channel_info *info = NULL; + unsigned long flags; + + if (is_pipeid_invalid(pipe_id)) { + stm_error("Invalid pipe id"); + return -1; + } + info = dma_drv_data->pipe_info[pipe_id]; + if (!info) { + stm_error("Null Info structure...."); + return -1; + } + if ((info->phys_chan_id) == DMA_CHAN_NOT_ALLOCATED) { + if (allocate_free_dma_channel(info)) { + stm_error("stm_enable_dma():: \ + No free DMA channel available.....\n"); + return -1; + } + dma_drv_data->dma_chan_info[info->channel_id] = info; + } + stm_dbg(DBG_ST.dma, "info->phys_chan_id Allocated = %d\n", + (info->phys_chan_id)); + + spin_lock_irqsave(&dma_drv_data->cfg_ch_lock[info->phys_chan_id], + flags); +#if 0 + if (dma_channel_execute_command + (DMA_SUSPEND_REQ, info->phys_chan_id) == -1) { + stm_error("Unable to suspend the Channel %d\n", + info->phys_chan_id); + goto error_enable_dma; + } + stm_error("--->suspending the Channel %d\n", info->phys_chan_id); + +#endif + if (info->invalid) { + if (info->chan_mode == DMA_CHAN_IN_LOG_MODE) { + if (!dma_drv_data->pr_info[info->phys_chan_id].dirty) { + set_phys_res_type(info->phys_chan_id, + info->pr_type); + set_phys_res_mode(info->phys_chan_id, + info->chan_mode); + set_phys_res_mode_option(info->phys_chan_id, + info->mode_option); + set_phys_res_security(info->phys_chan_id, + info->security); + /*Resource is Dirty now */ + dma_drv_data->pr_info[info-> + phys_chan_id].dirty = 1; + } + if ((info->dir == PERIPH_TO_PERIPH) + || (info->dir == PERIPH_TO_MEM)) { + set_event_line_security(info->src_info. + event_line, + info->src_info. + event_group, + info->security); + } + if ((info->dir == PERIPH_TO_PERIPH) + || (info->dir == MEM_TO_PERIPH)) + set_event_line_security((info->dst_info. + event_line + 16), + info->dst_info. + event_group, + info->security); + } else { /*Channel in Physical mode */ + + set_phys_res_type(info->phys_chan_id, info->pr_type); + set_phys_res_mode(info->phys_chan_id, info->chan_mode); + set_phys_res_mode_option(info->phys_chan_id, + info->mode_option); + set_phys_res_security(info->phys_chan_id, + info->security); + + if ((info->dir == PERIPH_TO_PERIPH) + || (info->dir == PERIPH_TO_MEM)) { + set_event_line_security(info->src_info. + event_line, + info->src_info. + event_group, + info->security); + } + if ((info->dir == PERIPH_TO_PERIPH) + || (info->dir == MEM_TO_PERIPH)) + set_event_line_security((info->dst_info. + event_line + 16), + info->dst_info. + event_group, + info->security); + + } + } + if (info->pr_type == DMA_STANDARD) { + if (info->chan_mode == DMA_CHAN_IN_PHYS_MODE) { + if (set_std_phy_channel_params(info)) { + stm_error("Could not set parameters \ + for channel in phy mode\n"); + goto error_enable_dma; + } + } else if (info->chan_mode == DMA_CHAN_IN_LOG_MODE) { + if (dma_channel_execute_command + (DMA_SUSPEND_REQ, info->phys_chan_id) == -1) { + stm_error("Unable to suspend the Channel %d\n", + info->phys_chan_id); + goto error_enable_dma; + } + if (set_std_log_channel_params(info)) { + stm_error("Could not set parameters \ + for channel in Log mode\n"); + goto error_enable_dma; + } + } else { + stm_error("Operation Mode not yet supported"); + goto error_enable_dma; + } + } else { /*DMA_EXTENDED */ + stm_error("Extended Channels not supported"); + goto error_enable_dma; + } + /*Now after doing all necessary settings put the channel in RUN state */ + info->active = 1; + info->invalid = 0; + dma_channel_execute_command(DMA_RUN, info->phys_chan_id); + spin_unlock_irqrestore(&dma_drv_data->cfg_ch_lock[info->phys_chan_id], + flags); + + return 0; + +error_enable_dma: + spin_unlock_irqrestore(&dma_drv_data->cfg_ch_lock[info->phys_chan_id], + flags); + return -1; +} +EXPORT_SYMBOL(stm_enable_dma); + +/** + * halt_dma_channel() - To halt a Running DMA channel. + * @pipe_id: client Id whose DMA channel has to be halted + * We suspend the channel first. For Physical channel we just + * stop it and return. For Logical channels, we check if some other + * Logical channel is still running(Other than one we halted), + * then we again put that physical resource in run state. + * + */ +static int halt_dma_channel(int pipe_id) +{ + struct dma_channel_info *info = NULL; + + info = dma_drv_data->pipe_info[pipe_id]; + if (dma_channel_execute_command(DMA_SUSPEND_REQ, info->phys_chan_id) == + -1) { + stm_error("Unable to suspend the Channel %d\n", + info->phys_chan_id); + return -1; + } + if (info->chan_mode == DMA_CHAN_IN_PHYS_MODE) { + if (dma_channel_execute_command(DMA_STOP, info->phys_chan_id) == + -1) { + stm_error("Unable to stop the Channel %d\n", + info->phys_chan_id); + return -1; + } + } else if (info->chan_mode == DMA_CHAN_IN_LOG_MODE) { + /*Deactivate the event line during + * the time physical res is suspended */ + print_channel_reg_params(info->phys_chan_id); + + if (info->dir == MEM_TO_PERIPH) { + REG_WR_BITS(cio_addr + (info->phys_chan_id, CHAN_REG_SDLNK), + DEACTIVATE_EVENTLINE, + EVENTLINE_MASK(info->dst_info.event_line), + EVENTLINE_POS(info->dst_info.event_line)); + } else if (info->dir == PERIPH_TO_MEM) { + REG_WR_BITS(cio_addr + (info->phys_chan_id, CHAN_REG_SSLNK), + DEACTIVATE_EVENTLINE, + EVENTLINE_MASK(info->src_info.event_line), + EVENTLINE_POS(info->src_info.event_line)); + } else { + stm_dbg(DBG_ST.dma, "Unknown request\n"); + } + print_channel_reg_params(info->phys_chan_id); + + if (get_phy_res_usage_count(info->phys_chan_id) <= 1) { + stm_dbg(DBG_ST.dma, + "Stopping the Logical channel..............\n"); + if (dma_channel_execute_command + (DMA_STOP, info->phys_chan_id) == -1) { + stm_error("Unable to stop the Channel %d\n", + info->phys_chan_id); + return -1; + } + /*info->chan_mode = DMA_CHAN_IN_PHYS_MODE; */ + } else { + stm_dbg(DBG_ST.dma, + "since some other Logical channel might " + "be using it" "putting " + "it to running state again..\n"); + dma_channel_execute_command(DMA_RUN, + info->phys_chan_id); + } + } else { + stm_error + ("stm_disable_dma()::Operation mode not supported\n"); + } + info->active = 0; + return 0; +} + +/** + * stm_disable_dma() - API to disable a DMA channel + * @pipe_id: client id whose channel has to be disabled + * This function halts the concerned DMA channel and returns. + * + */ +void stm_disable_dma(int pipe_id) +{ + struct dma_channel_info *info = NULL; + unsigned long flags; + + if (is_pipeid_invalid(pipe_id)) { + stm_error("Invalid pipe id"); + return; + } + + info = dma_drv_data->pipe_info[pipe_id]; + if (info->phys_chan_id != DMA_CHAN_NOT_ALLOCATED) { + spin_lock_irqsave(&dma_drv_data->cfg_ch_lock + [info->phys_chan_id], flags); + if (halt_dma_channel(pipe_id)) + stm_error("Unable to Halt DMA pipe_id :: %d\n", + pipe_id); + spin_unlock_irqrestore(&dma_drv_data->cfg_ch_lock + [info->phys_chan_id], flags); + } +} +EXPORT_SYMBOL(stm_disable_dma); + +/** + * stm_free_dma() - API to release a DMA channel + * @pipe_id: id whose channel has to be freed + * This function first halts the channel, then the resources + * held by the channel are released and pipe deallocated. + * + */ +void stm_free_dma(int pipe_id) +{ + struct dma_channel_info *info = NULL; + unsigned long flags; + + if (is_pipeid_invalid(pipe_id)) { + stm_error("Invalid pipe id %d", pipe_id); + return; + } + + info = dma_drv_data->pipe_info[pipe_id]; + if (!info) { + stm_error("Null Info structure...."); + return; + } + stm_dbg(DBG_ST.dma, "Trying to free DMA pipe_id %d\n", pipe_id); + + if (info->phys_chan_id != DMA_CHAN_NOT_ALLOCATED) { + spin_lock_irqsave(&dma_drv_data->cfg_ch_lock + [info->phys_chan_id], flags); + if (info->chan_mode == DMA_CHAN_IN_PHYS_MODE) { + if (halt_dma_channel(pipe_id)) { + stm_error("Unable to Halt DMA pipe_id :: %d\n", + pipe_id); + spin_unlock_irqrestore + (&dma_drv_data->cfg_ch_lock + [info->phys_chan_id], flags); + return; + } + if (info->lli_block_id_src >= 0) { + release_block(info->lli_block_id_src, + dma_drv_data->pchan_lli_pool); + info->lli_block_id_src = -1; + } + if (info->lli_block_id_dest >= 0) { + release_block(info->lli_block_id_dest, + dma_drv_data->pchan_lli_pool); + info->lli_block_id_dest = -1; + } + if (info->sg_block_id_src >= 0) { + release_block(info->sg_block_id_src, + dma_drv_data->sg_pool); + info->sg_block_id_src = -1; + } + if (info->sg_block_id_dest >= 0) { + release_block(info->sg_block_id_dest, + dma_drv_data->sg_pool); + info->sg_block_id_dest = -1; + } + if (release_phys_resource(info) == -1) { + stm_error + ("Unable to free Physical resource %d\n", + info->phys_chan_id); + BUG(); + } + } else { /*Logical */ + + halt_dma_channel(pipe_id); + if (release_phys_resource(info) == -1) { + stm_error + ("Unable to free Physical resource %d\n", + info->phys_chan_id); + BUG(); + } + if (info->lli_block_id_src >= 0) { + rel_free_log_lli_block + (dma_drv_data->lchan_lli_pool, + info->phys_chan_id, + info->lli_block_id_src); + info->lli_block_id_src = -1; + } + if (info->lli_block_id_dest >= 0) { + rel_free_log_lli_block + (dma_drv_data->lchan_lli_pool, + info->phys_chan_id, + info->lli_block_id_dest); + info->lli_block_id_dest = -1; + } + if (info->sg_block_id_src >= 0) { + release_block(info->sg_block_id_src, + dma_drv_data->sg_pool); + info->sg_block_id_src = -1; + } + if (info->sg_block_id_dest >= 0) { + release_block(info->sg_block_id_dest, + dma_drv_data->sg_pool); + info->sg_block_id_dest = -1; + } + } + spin_unlock_irqrestore(&dma_drv_data->cfg_ch_lock + [info->phys_chan_id], flags); + } + dma_drv_data->pipe_info[pipe_id] = NULL; + if (info->channel_id >= 0) + dma_drv_data->dma_chan_info[info->channel_id] = NULL; + kfree(info); + deallocate_pipe_id(pipe_id); + stm_dbg(DBG_ST.dma, "Succesfully freed DMA pipe_id %d\n", pipe_id); +} +EXPORT_SYMBOL(stm_free_dma); + +/** + * stm_dma_residue() - To Return remaining bytes of transfer + * @pipe_id: client id whose residue is to be returned + * + */ +int stm_dma_residue(int pipe_id) +{ + struct dma_channel_info *info = NULL; + unsigned long flags; + int remaining = 0; + if (is_pipeid_invalid(pipe_id)) { + stm_error("Invalid pipe id"); + return -1; + } + info = dma_drv_data->pipe_info[pipe_id]; + if (!info) { + stm_error("Null Info structure...."); + return -1; + } + + if (info->active == 0) { + stm_error("Channel callback done... no residue\n"); + return 0; + } + spin_lock_irqsave(&dma_drv_data->cfg_ch_lock[info->phys_chan_id], + flags); + if (dma_channel_execute_command(DMA_SUSPEND_REQ, info->phys_chan_id) == + -1) { + stm_error("Unable to suspend the Channel %d\n", + info->phys_chan_id); + spin_unlock_irqrestore(&dma_drv_data->cfg_ch_lock + [info->phys_chan_id], flags); + return -1; + } + + if (info->chan_mode == DMA_CHAN_IN_PHYS_MODE) { + remaining = + REG_RD_BITS(cio_addr + (info->phys_chan_id, CHAN_REG_SDELT), + SREG_ELEM_PHY_ECNT_MASK, + SREG_ELEM_PHY_ECNT_POS); + } else { + struct std_log_memory_param *params = NULL; + + if (info->dir == MEM_TO_PERIPH) + params = ((void *) + (dma_drv_data->lchan_params_base.log_addr) + + (info->dst_dev_type * 32) + 16); + else if (info->dir == PERIPH_TO_MEM) + params = ((void *) + (dma_drv_data->lchan_params_base.log_addr) + + (info->src_dev_type * 32)); + remaining = + MEM_READ_BITS(params->dmac_lcsp2, MEM_LCSP2_ECNT_MASK, + MEM_LCSP2_ECNT_POS); + } + if (remaining) + dma_channel_execute_command(DMA_RUN, info->phys_chan_id); + spin_unlock_irqrestore(&dma_drv_data->cfg_ch_lock[info->phys_chan_id], + flags); + return remaining * (0x1 << info->src_info.data_width); +} +EXPORT_SYMBOL(stm_dma_residue); + +/** + * stm_pause_dma() - To pause an ongoing transfer on a pipe + * @pipe_id: client id whose transfer has to be paused + * This function pauses the transfer on a pipe. + * + * + * + */ +int stm_pause_dma(int pipe_id) +{ + struct dma_channel_info *info = NULL; + unsigned long flags; + + if (is_pipeid_invalid(pipe_id)) { + stm_error("Invalid pipe id"); + return -1; + } + info = dma_drv_data->pipe_info[pipe_id]; + if (!info) { + stm_error("Null Info structure...."); + return -1; + } + if (info->active == 0) { + stm_dbg(DBG_ST.dma, "Channel is not active\n"); + return 0; + } + spin_lock_irqsave(&dma_drv_data->cfg_ch_lock[info->phys_chan_id], + flags); + if (dma_channel_execute_command(DMA_SUSPEND_REQ, info->phys_chan_id) == + -1) { + stm_error("Unable to suspend the Channel %d\n", + info->phys_chan_id); + if (dma_channel_execute_command + (DMA_SUSPEND_REQ, info->phys_chan_id) == -1) + goto error_pause; + } + + if (info->chan_mode == DMA_CHAN_IN_PHYS_MODE) { + if ((info->dir == PERIPH_TO_MEM) + || (info->dir == PERIPH_TO_PERIPH)) { + u32 tmp; + if (info->src_dev_type < 32) { + tmp = + REG_RD_BITS(io_addr(DREG_FSEB1), + FULL32_MASK, NO_SHIFT); + tmp |= (0x1 << info->src_dev_type); + REG_WR_BITS(io_addr(DREG_FSEB1), tmp, + FULL32_MASK, NO_SHIFT); + } else { + tmp = + REG_RD_BITS(io_addr(DREG_FSEB2), + FULL32_MASK, NO_SHIFT); + tmp |= (0x1 << info->src_dev_type) + 32; + REG_WR_BITS(io_addr(DREG_FSEB2), tmp, + FULL32_MASK, NO_SHIFT); + } + } + } else if (info->chan_mode == DMA_CHAN_IN_LOG_MODE) { + /*Deactivate the event line during the + *time physical res is suspended */ + if (info->dir == MEM_TO_PERIPH) { + REG_WR_BITS(cio_addr + (info->phys_chan_id, CHAN_REG_SDLNK), + DEACTIVATE_EVENTLINE, + EVENTLINE_MASK(info->dst_info.event_line), + EVENTLINE_POS(info->dst_info.event_line)); + } else if (info->dir == PERIPH_TO_MEM) { + REG_WR_BITS(cio_addr + (info->phys_chan_id, CHAN_REG_SSLNK), + DEACTIVATE_EVENTLINE, + EVENTLINE_MASK(info->src_info.event_line), + EVENTLINE_POS(info->src_info.event_line)); + } else { + stm_dbg(DBG_ST.dma, "Unknown request\n"); + goto error_pause; + } + if ((info->dir == PERIPH_TO_MEM) + || (info->dir == PERIPH_TO_PERIPH)) { + u32 tmp; + if (info->src_dev_type < 32) { + tmp = + REG_RD_BITS(io_addr(DREG_FSEB1), + FULL32_MASK, NO_SHIFT); + tmp |= (0x1 << info->src_dev_type); + REG_WR_BITS(io_addr(DREG_FSEB1), tmp, + FULL32_MASK, NO_SHIFT); + } else { + tmp = + REG_RD_BITS(io_addr(DREG_FSEB2), + FULL32_MASK, NO_SHIFT); + tmp |= (0x1 << info->src_dev_type) + 32; + REG_WR_BITS(io_addr(DREG_FSEB2), tmp, + FULL32_MASK, NO_SHIFT); + } + } + /*Restart the Physical resource */ + dma_channel_execute_command(DMA_RUN, info->phys_chan_id); + } else { + stm_error("Operation mode not supported\n"); + goto error_pause; + } + + spin_unlock_irqrestore(&dma_drv_data->cfg_ch_lock[info->phys_chan_id], + flags); + return 0; +error_pause: + spin_unlock_irqrestore(&dma_drv_data->cfg_ch_lock[info->phys_chan_id], + flags); + return -1; +} +EXPORT_SYMBOL(stm_pause_dma); + +void stm_unpause_dma(int pipe_id) +{ + struct dma_channel_info *info = NULL; + unsigned long flags; + + if (is_pipeid_invalid(pipe_id)) { + stm_error("Invalid pipe id"); + return; + } + info = dma_drv_data->pipe_info[pipe_id]; + if (!info) { + stm_error("Null Info structure...."); + return; + } + spin_lock_irqsave(&dma_drv_data->cfg_ch_lock[info->phys_chan_id], + flags); + if (dma_channel_execute_command(DMA_SUSPEND_REQ, info->phys_chan_id) == + -1) { + stm_error("Unable to suspend the Channel %d\n", + info->phys_chan_id); + spin_unlock_irqrestore(&dma_drv_data->cfg_ch_lock + [info->phys_chan_id], flags); + return; + } + if (info->chan_mode == DMA_CHAN_IN_LOG_MODE) { + /*activate the event line */ + int line_status = 0; + if (info->dir == MEM_TO_PERIPH) { + REG_WR_BITS(cio_addr + (info->phys_chan_id, CHAN_REG_SDLNK), + ACTIVATE_EVENTLINE, + EVENTLINE_MASK(info->dst_info.event_line), + EVENTLINE_POS(info->dst_info.event_line)); + line_status = + REG_RD_BITS(cio_addr + (info->phys_chan_id, + CHAN_REG_SDLNK), + EVENTLINE_MASK(info-> + dst_info.event_line), + EVENTLINE_POS(info-> + dst_info.event_line)); + print_channel_reg_params(info->phys_chan_id); + } else if (info->dir == PERIPH_TO_MEM) { + REG_WR_BITS(cio_addr + (info->phys_chan_id, CHAN_REG_SSLNK), + ACTIVATE_EVENTLINE, + EVENTLINE_MASK(info->src_info.event_line), + EVENTLINE_POS(info->src_info.event_line)); + line_status = + REG_RD_BITS(cio_addr + (info->phys_chan_id, + CHAN_REG_SSLNK), + EVENTLINE_MASK(info-> + src_info.event_line), + EVENTLINE_POS(info-> + src_info.event_line)); + } else { + stm_dbg(DBG_ST.dma, "Unknown request\n"); + } + } + dma_channel_execute_command(DMA_RUN, info->phys_chan_id); + spin_unlock_irqrestore(&dma_drv_data->cfg_ch_lock[info->phys_chan_id], + flags); +} +EXPORT_SYMBOL(stm_unpause_dma); + +#if 0 +static irqreturn_t stm_dma_secure_interrupt_handler(int irq, void *dev_id) +{ + u32 mask = 0x1; + int i = 0; + int k = 0; + unsigned long flags; + struct dma_channel_info *info = NULL; + dbg2("stm_dma_interrupt_handler22222 called...\n"); + + if (dma_drv_data->dma_regs->dmac_spcmis) { + for (mask = 1; mask != 0x80000000; mask = mask << 1, k++) { + if (dma_drv_data->dma_regs->dmac_spcmis & mask) { + dma_drv_data->dma_regs->dmac_spcicr |= mask; + spin_lock_irqsave(&dma_info_lock, flags); + info = + dma_drv_data->dma_chan_info + [MAX_LOGICAL_CHANNELS + k]; + info->callback(info->data, 0); + print_channel_reg_params(info->phys_chan_id); + spin_unlock_irqrestore(&dma_info_lock, flags); + } + i++; + } + } + return IRQ_HANDLED; +} +#endif + +void process_phy_channel_inerrupt(void) +{ + int k = 0; + struct dma_channel_info *info = NULL; + u32 tmp; + if (ioread32(io_addr(DREG_PCMIS))) { + // Search Physical Interrupt source(s) + for (k = 0; k < MAX_AVAIL_PHY_CHANNELS; k++) { + // Is it due to an Error ? + if (ioread32(io_addr(DREG_PCEIS)) & (0x1 << k)) { + info = + dma_drv_data->dma_chan_info + [MAX_LOGICAL_CHANNELS + k]; + stm_dbg(DBG_ST.dma, "Error interrupt\n"); + if ((info->active) && (info->callback)) + info->callback(info->data, XFER_ERROR); + } + + // Is it due to a Terminal Count ? + if (ioread32(io_addr(DREG_PCTIS)) & (0x1 << k)) { + info = + dma_drv_data->dma_chan_info + [MAX_LOGICAL_CHANNELS + k]; + stm_dbg(DBG_ST.dma, "TIS interrupt\n"); + if ((info->lli_interrupt == 1) + && (info->sg_dest) + && ((info->dir == PERIPH_TO_MEM) + || (info->dir == MEM_TO_PERIPH))) { + info->bytes_xfred += + sg_dma_len(info->current_sg); + stm_dbg(DBG_ST.dma, + "Channel(%d) :: Transfer " + "completed for %d bytes\n", + info->phys_chan_id, + info->bytes_xfred); + info->current_sg++; + if ((info->bytes_xfred == + get_xfer_len(info)) + && (info->active) + && (info->callback)) + info->callback(info->data, + XFER_COMPLETE); + } else { + if ((info->active) && (info->callback)) + info->callback(info->data, + XFER_COMPLETE); + } + } + // Acknoledge Interrupt + tmp = + REG_RD_BITS(io_addr(DREG_PCICR), + FULL32_MASK, NO_SHIFT); + tmp |= (0x1 << k); + REG_WR_BITS(io_addr(DREG_PCICR), tmp, + FULL32_MASK, NO_SHIFT); + } + } +} + +void process_logical_channel_inerrupt(void) +{ + int j = 0; + int k = 0; + struct dma_channel_info *info = NULL; + u32 tmp; + for (j = 0; j < 4; j++) { + if (ioread32(io_addr(DREG_LCEIS(j)))) { + for (k = 0; k < 32; k++) { + if (ioread32(io_addr(DREG_LCEIS(j))) & + (0x1 << k)) { + tmp = + REG_RD_BITS(io_addr + (DREG_LCICR(j)), + FULL32_MASK, NO_SHIFT); + tmp |= (0x1 << k); + REG_WR_BITS(io_addr + (DREG_LCICR(j)), tmp, + FULL32_MASK, NO_SHIFT); + stm_dbg(DBG_ST.dma, + "Error Logical " + "Interrupt Line :: %d\n", + (j * 32 + k)); + info = + dma_drv_data->dma_chan_info[j * 32 + + k]; + if ((info->active) && (info->callback)) + info->callback(info->data, + XFER_ERROR); + } + } + } + } + + for (j = 0; j < 4; j++) { + if (ioread32(io_addr(DREG_LCTIS(j)))) { + for (k = 0; k < 32; k++) { + if (ioread32(io_addr(DREG_LCTIS(j))) & + (0x1 << k)) { + tmp = + REG_RD_BITS(io_addr + (DREG_LCICR(j)), + FULL32_MASK, NO_SHIFT); + tmp |= (0x1 << k); + REG_WR_BITS(io_addr + (DREG_LCICR(j)), tmp, + FULL32_MASK, NO_SHIFT); + stm_dbg(DBG_ST.dma, + "TIS interrupt:::: Logical " + "Interrupt Line :: %d\n", + (j * 32 + k)); + info = + dma_drv_data->dma_chan_info[j * 32 + + k]; + if (!info) + continue; + + if ((info->lli_interrupt == 1) + && (info->sg_dest) + && ((info->dir == PERIPH_TO_MEM) + || (info->dir == + MEM_TO_PERIPH))) { + info->bytes_xfred += + sg_dma_len + (info->current_sg); + stm_dbg(DBG_ST.dma, + "Channel(%d) :: " + "Transfer completed " + "for %d bytes\n", + info->phys_chan_id, + info->bytes_xfred); + info->current_sg++; + if ((info->bytes_xfred == + get_xfer_len(info)) + && ((info->active) + && (info->callback))) + info-> + callback(info->data, + XFER_COMPLETE); + } else { + if ((info->active) + && (info->callback)) + info-> + callback(info->data, + XFER_COMPLETE); + } + } + } + } + } +} + +static irqreturn_t stm_dma_interrupt_handler(int irq, void *dev_id) +{ + + process_phy_channel_inerrupt(); + process_logical_channel_inerrupt(); + return IRQ_HANDLED; +} + +static int stm_dma_probe(struct platform_device *pdev) +{ + struct resource *res = NULL; + int status = 0, i; + stm_dbg(DBG_ST.dma, "stm_dma_probe called.....\n"); + printk(KERN_INFO "In DMA PROBE \n"); + dma_drv_data = kzalloc(sizeof(struct dma_driver_data), GFP_KERNEL); + + if (!dma_drv_data) { + stm_error("DMA driver structure cannot be allocated...\n"); + return -1; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + stm_error("IORESOURCE_MEM unavailable\n"); + goto driver_cleanup; + } + + dma_drv_data->reg_base = + (void __iomem *)ioremap(res->start, res->end - res->start + 1); + + if (!dma_drv_data->reg_base) { + stm_error("ioremap of DMA register memory failed\n"); + goto driver_cleanup; + } + stm_dbg(DBG_ST.dma, "DMA_REGS = %x\n", (u32) dma_drv_data->reg_base); + + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (!res) { + stm_error("IORESOURCE_IRQ unavailable\n"); + goto driver_ioremap_cleanup; + } + + status = + request_irq(res->start, stm_dma_interrupt_handler, 0, "DMA", + NULL); + if (status) { + stm_error("Unable to request IRQ\n"); + goto driver_ioremap_cleanup; + } + + dma_drv_data->clk = clk_get(&pdev->dev, NULL); + if (IS_ERR(dma_drv_data->clk)) { + stm_error("Unable to get clock\n"); + goto driver_ioremap_cleanup; + } + + clk_enable(dma_drv_data->clk); + +#ifndef CONFIG_STM_SECURITY + initialize_dma_regs(); + dma_drv_data->lchan_params_base.log_addr = + dma_alloc_coherent(NULL, 128 * 4 * sizeof(u32), + &dma_drv_data->lchan_params_base.phys_addr, + GFP_KERNEL | GFP_DMA); + if (!dma_drv_data->lchan_params_base.log_addr) { + stm_error("Request for Memory allocation for \ + Logical channel parameters failed\n"); + goto driver_clk_cleanup; + } + REG_WR_BITS(io_addr(DREG_LCPA), + dma_drv_data->lchan_params_base.phys_addr, + FULL32_MASK, NO_SHIFT); +#else + /* LCPA value cannot be programmed(we are in non-secure mode). + * We make use of ESRAM memory for this. + * (xloader programs this register with the value(ESRAM address) + * beforehand) + * */ + dma_drv_data->lchan_params_base.log_addr = + ioremap(U8500_DMA_LCPA_BASE, 4096); + dma_drv_data->lchan_params_base.phys_addr = U8500_DMA_LCPA_BASE; + + REG_WR_BITS(io_addr(DREG_LCPA), + U8500_DMA_LCPA_BASE, + FULL32_MASK, NO_SHIFT); +#endif + + dma_drv_data->pchan_lli_pool = create_elem_pool("PCHAN_LLI_POOL", + NUM_LLI_PER_REQUEST * + sizeof(struct + dma_lli_info), + NUM_PCHAN_LLI_BLOCKS, + 12); + if (!dma_drv_data->pchan_lli_pool) { + stm_error("Unable to allocate memory for Phys chan LLI pool"); + goto driver_chan_mem_cleanup; + } + dma_drv_data->sg_pool = create_elem_pool("SG_POOL", + NUM_SG_PER_REQUEST * + sizeof(struct scatterlist), + NUM_SG_BLOCKS, 12); + if (!dma_drv_data->sg_pool) { + stm_error("Unable to allocate memory for SG pool"); + goto pchan_lli_pool_cleanup; + } +#ifndef CONFIG_STM_SECURITY + /*Allocate 1Kb block for each physical channels */ + dma_drv_data->lchan_lli_pool = create_elem_pool("LCHAN_LLI_POOL", + 1024, + MAX_PHYSICAL_CHANNELS, + 18); + if (!dma_drv_data->lchan_lli_pool) { + stm_error("Unable to allocate memory for lchan_lli_pool"); + goto sg_pool_cleanup; + } + + REG_WR_BITS(io_addr(DREG_LCLA), + dma_drv_data->lchan_lli_pool->base_addr.phys_addr, + FULL32_MASK, NO_SHIFT); +#else + /* LCLA value cannot be programmed(we are in non-secure mode). + * We make use of ESRAM memory for this. + * (xloader programs this register with the value(ESRAM address) + * beforehand) + * */ + /*Allocate 1Kb block for each physical channels */ + dma_drv_data->lchan_lli_pool = + create_elem_pool_fixed_mem("LCHAN_LLI_POOL", 1024, + MAX_AVAIL_PHY_CHANNELS, + U8500_DMA_LCLA_BASE, 16 * 1024); + + if (!dma_drv_data->lchan_lli_pool) { + stm_error("Unable to allocate memory for lchan_lli_pool"); + goto sg_pool_cleanup; + } + REG_WR_BITS(io_addr(DREG_LCLA), + dma_drv_data->lchan_lli_pool->base_addr.phys_addr, + FULL32_MASK, NO_SHIFT); +#endif + + spin_lock_init(&dma_drv_data->pipe_id_lock); + spin_lock_init(&dma_drv_data->pr_info_lock); + for (i = 0; i < MAX_AVAIL_PHY_CHANNELS; i++) + spin_lock_init(&dma_drv_data->cfg_ch_lock[i]); + + /* Audio is using physical channels 2 and 3 from MMDSP */ + dma_drv_data->pr_info[2].status = RESOURCE_PHYSICAL; + dma_drv_data->pr_info[3].status = RESOURCE_PHYSICAL; + /* End of Audio */ + + print_dma_regs(); + return 0; +sg_pool_cleanup: + destroy_elem_pool(dma_drv_data->sg_pool); +pchan_lli_pool_cleanup: + destroy_elem_pool(dma_drv_data->pchan_lli_pool); +driver_chan_mem_cleanup: +#ifndef CONFIG_STM_SECURITY + dma_free_coherent(NULL, 128 * 4 * sizeof(u32), + dma_drv_data->lchan_params_base.log_addr, + dma_drv_data->lchan_params_base.phys_addr); +driver_clk_cleanup: +#endif + clk_disable(dma_drv_data->clk); + clk_put(dma_drv_data->clk); +driver_ioremap_cleanup: + iounmap(dma_drv_data->reg_base); +driver_cleanup: + kfree(dma_drv_data); + return -1; +} + +/* + * Clean up routine + */ +static int stm_dma_remove(struct platform_device *pdev) +{ + struct resource *res = NULL; + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); +#ifndef CONFIG_STM_SECURITY + /*Free Memory used for Storing Logical channel cfg params */ + dma_free_coherent(NULL, 128 * 4 * sizeof(u32), + dma_drv_data->lchan_params_base.log_addr, + dma_drv_data->lchan_params_base.phys_addr); +#endif + destroy_elem_pool(dma_drv_data->pchan_lli_pool); + destroy_elem_pool(dma_drv_data->sg_pool); +#ifndef CONFIG_STM_SECURITY + destroy_elem_pool(dma_drv_data->lchan_lli_pool); +#endif + free_irq(res->start, 0); + clk_disable(dma_drv_data->clk); + clk_put(dma_drv_data->clk); + iounmap(dma_drv_data->reg_base); + kfree(dma_drv_data); + return 0; +} + +#ifdef CONFIG_PM + +/** + * stm_dma_suspend() - Function registered with Kernel Power Mgmt framework + * @pdev: Platform device structure for the DMA controller + * @state: pm_message_t state sent by PM framework + * + * This function will be called by the Linux Kernel Power Mgmt Framework, while + * going to sleep. It is assumed that no active tranfer is in progress + * at this time. Client driver should make sure of this. + */ +int stm_dma_suspend(struct platform_device *pdev, pm_message_t state) +{ + /* + * writing back backed-up non-secure registers + * FIXME : DREG_GCC/FSEBn and few others are accesible + * only on a secure mode. this condition needs + * to be inserted before this operation + */ + dma_drv_data->backup_regs[0] = ioread32(io_addr(DREG_GCC)); + dma_drv_data->backup_regs[1] = ioread32(io_addr(DREG_PRTYP)); + dma_drv_data->backup_regs[2] = ioread32(io_addr(DREG_PRMSE)); + dma_drv_data->backup_regs[3] = ioread32(io_addr(DREG_PRMSO)); + dma_drv_data->backup_regs[4] = ioread32(io_addr(DREG_PRMOE)); + dma_drv_data->backup_regs[5] = ioread32(io_addr(DREG_PRMOO)); + dma_drv_data->backup_regs[6] = ioread32(io_addr(DREG_LCPA)); + dma_drv_data->backup_regs[7] = ioread32(io_addr(DREG_LCLA)); + dma_drv_data->backup_regs[8] = ioread32(io_addr(DREG_ACTIVE)); + dma_drv_data->backup_regs[9] = ioread32(io_addr(DREG_ACTIVO)); + dma_drv_data->backup_regs[10] = ioread32(io_addr(DREG_FSEB1)); + dma_drv_data->backup_regs[11] = ioread32(io_addr(DREG_FSEB2)); + dma_drv_data->backup_regs[12] = ioread32(io_addr(DREG_PCICR)); + + stm_dbg(DBG_ST.dma, "stm_dma_suspend: called......\n"); + return 0; +} + +/** + * stm_dma_resume() - Function registered with Kernel Power Mgmt framework + * @pdev: Platform device structure for the DMA controller + * + * This function will be called by the Linux Kernel Power Mgmt Framework, when + * System comes out of sleep. + * + * + */ +int stm_dma_resume(struct platform_device *pdev) +{ + /* + * writing back backed-up non-secure registers + * FIXME : DREG_GCC/FSEBn and few others are accesible + * only on a secure mode. this condition needs + * to be inserted before this operation + */ + iowrite32(dma_drv_data->backup_regs[0], (io_addr(DREG_GCC))); + iowrite32(dma_drv_data->backup_regs[1], (io_addr(DREG_PRTYP))); + iowrite32(dma_drv_data->backup_regs[2], (io_addr(DREG_PRMSE))); + iowrite32(dma_drv_data->backup_regs[3], (io_addr(DREG_PRMSO))); + iowrite32(dma_drv_data->backup_regs[4], (io_addr(DREG_PRMOE))); + iowrite32(dma_drv_data->backup_regs[5], (io_addr(DREG_PRMOO))); + iowrite32(dma_drv_data->backup_regs[6], (io_addr(DREG_LCPA))); + iowrite32(dma_drv_data->backup_regs[7], (io_addr(DREG_LCLA))); + iowrite32(dma_drv_data->backup_regs[8], (io_addr(DREG_ACTIVE))); + iowrite32(dma_drv_data->backup_regs[9], (io_addr(DREG_ACTIVO))); + iowrite32(dma_drv_data->backup_regs[10], (io_addr(DREG_FSEB1))); + iowrite32(dma_drv_data->backup_regs[11], (io_addr(DREG_FSEB2))); + iowrite32(dma_drv_data->backup_regs[12], (io_addr(DREG_PCICR))); + + + stm_dbg(DBG_ST.dma, "stm_dma_resume: called......\n"); + return 0; +} + +#else + +#define stm_dma_suspend NULL +#define stm_dma_resume NULL + +#endif + +static struct platform_driver stm_dma_driver = { + .probe = stm_dma_probe, + .remove = stm_dma_remove, + .driver = { + .owner = THIS_MODULE, + .name = "STM-DMA", + }, + .suspend = stm_dma_suspend, + .resume = stm_dma_resume, +}; + +static int __init stm_dma_init(void) +{ + return platform_driver_register(&stm_dma_driver); +} + +module_init(stm_dma_init); +static void __exit stm_dma_exit(void) +{ + platform_driver_unregister(&stm_dma_driver); + return; +} + +module_exit(stm_dma_exit); + +/* Module parameters */ + +MODULE_AUTHOR("ST Microelectronics"); +MODULE_DESCRIPTION("STM DMA Controller"); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/mach-ux500/headsmp.S b/arch/arm/mach-ux500/headsmp.S new file mode 100755 index 00000000000..1f9aee4675d --- /dev/null +++ b/arch/arm/mach-ux500/headsmp.S @@ -0,0 +1,38 @@ +/* + * Copyright (c) ST Ericsson + * based on ARM realview platform + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/linkage.h> +#include <linux/init.h> + + __INIT + +/* + * u8500 specific entry point for secondary CPUs. This provides + * a "holding pen" into which all secondary cores are held until we're + * ready for them to initialise. + */ +ENTRY(u8500_secondary_startup) + mrc p15, 0, r0, c0, c0, 5 + and r0, r0, #15 + adr r4, 1f + ldmia r4, {r5, r6} + sub r4, r4, r5 + add r6, r6, r4 + dsb +pen: ldr r7, [r6] + cmp r7, r0 + bne pen + + /* + * we've been released from the holding pen: secondary_stack + * should now contain the SVC stack for this core + */ + b secondary_startup + +1: .long . + .long pen_release diff --git a/arch/arm/mach-ux500/hotplug.c b/arch/arm/mach-ux500/hotplug.c new file mode 100755 index 00000000000..f0c9471519c --- /dev/null +++ b/arch/arm/mach-ux500/hotplug.c @@ -0,0 +1,141 @@ +/* + * linux/arch/arm/mach-realview/hotplug.c + * + * Copyright (C) 2002 ARM Ltd. + * All Rights Reserved + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/kernel.h> +#include <linux/errno.h> +#include <linux/smp.h> +#include <linux/completion.h> + +extern volatile int pen_release; + +static DECLARE_COMPLETION(cpu_killed); + +static inline void cpu_enter_lowpower(void) +{ + unsigned int v; + asm volatile("bl v7_flush_kern_cache_all\n" + " mcr p15, 0, %1, c7, c5, 0\n" + " dsb\n" + /* + * Turn off coherency + */ + " mrc p15, 0, %0, c1, c0, 1\n" + " bic %0, %0, #0x40\n" + " mcr p15, 0, %0, c1, c0, 1\n" + " mrc p15, 0, %0, c1, c0, 0\n" + " bic %0, %0, #0x04\n" + " mcr p15, 0, %0, c1, c0, 0\n" + : "=&r" (v) + : "r" (0) + : "cc"); + +} + +static inline void cpu_leave_lowpower(void) +{ + unsigned int v; + + asm volatile("mrc p15, 0, %0, c1, c0, 0\n" + " orr %0, %0, #0x04\n" + " mcr p15, 0, %0, c1, c0, 0\n" + " mrc p15, 0, %0, c1, c0, 1\n" + " orr %0, %0, #0x40\n" + " mcr p15, 0, %0, c1, c0, 1\n" + : "=&r" (v) + : + : "cc"); +} + +static inline void platform_do_lowpower(unsigned int cpu) +{ + /* + * there is no power-control hardware on this platform, so all + * we can do is put the core into WFI; this is safe as the calling + * code will have already disabled interrupts + */ + for (;;) { + + /* + * here's the WFI + */ + asm(".word 0xe320f003\n" + : + : + : "memory", "cc"); + + if (pen_release == cpu) { + /* + * OK, proper wakeup, we're done + */ + break; + } + + /* + * getting here, means that we have come out of WFI without + * having been woken up - this shouldn't happen + * + * The trouble is, letting people know about this is not really + * possible, since we are currently running incoherently, and + * therefore cannot safely call printk() or anything else + */ +#ifdef DEBUG + printk("CPU%u: spurious wakeup call\n", cpu); +#endif + } +} + +int platform_cpu_kill(unsigned int cpu) +{ + return wait_for_completion_timeout(&cpu_killed, 5000); +} + +/* + * platform-specific code to shutdown a CPU + * + * Called with IRQs disabled + */ +void platform_cpu_die(unsigned int cpu) +{ +#ifdef DEBUG + unsigned int this_cpu = hard_smp_processor_id(); + + if (cpu != this_cpu) { + printk(KERN_CRIT "Eek! platform_cpu_die running on %u, should be %u\n", + this_cpu, cpu); + BUG(); + } +#endif + + printk(KERN_NOTICE "CPU%u: shutdown\n", cpu); + complete(&cpu_killed); + + /* + * we're ready for shutdown now, so do it + */ + /* FIXME : skipping this for a temp hack */ + /* cpu_enter_lowpower(); */ + platform_do_lowpower(cpu); + + /* + * bring this CPU back into the world of cache + * coherency, and then restore interrupts + */ + /* FIXME : skipping this for a temp hack */ + /* cpu_leave_lowpower(); */ +} + +int mach_cpu_disable(unsigned int cpu) +{ + /* + * we don't allow CPU 0 to be shutdown (it is still too special + * e.g. clock tick interrupts) + */ + return cpu == 0 ? -EPERM : 0; +} diff --git a/arch/arm/mach-ux500/hsi.c b/arch/arm/mach-ux500/hsi.c new file mode 100644 index 00000000000..79d7f04f41a --- /dev/null +++ b/arch/arm/mach-ux500/hsi.c @@ -0,0 +1,336 @@ +/* + * Copyright (C) 2010 ST-Ericsson + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + */ + +#include <linux/platform_device.h> +#include <linux/io.h> + +#include <linux/hsi.h> +#include <linux/hsi-legacy.h> + +#include <mach/hsi-stm.h> +#include <mach/devices.h> +#include <mach/hardware.h> + +static struct hsi_plat_data hsit_platform_data = { + .dev_type = 0x0 /** transmitter */ , + .mode = 0x2 /** frame mode */ , + .divisor = 0x12 /** half HSIT freq */ , + .parity = 0x0 /** no parity */ , + .channels = 0x4 /** 4 channels */ , + .flushbits = 0x0 /** none */ , + .priority = 0x3 /** ch0,ch1 high while ch2,ch3 low */ , + .burstlen = 0x0 /** infinite b2b */ , + .preamble = 0x0 /** none */ , + .dataswap = 0x0 /** no swap */ , + .framelen = 0x1f /** 32 bits all channels */ , + .ch_base_span = {[0] = {.base = 0x0, .span = 0x3}, + [1] = {.base = 0x4, .span = 0x3}, + [2] = {.base = 0x8, .span = 0x7}, + [3] = {.base = 0x10, .span = 0x7} + }, +#ifdef CONFIG_STN8500_HSI_LEGACY + .currmode = CONFIG_STN8500_HSI_TRANSFER_MODE, +#else + .currmode = 1, +#endif + .hsi_dma_info = { + [0] = { + .reserve_channel = 0, + .dir = MEM_TO_PERIPH, + .flow_cntlr = DMA_IS_FLOW_CNTLR, + .channel_type = + (STANDARD_CHANNEL | CHANNEL_IN_LOGICAL_MODE + | LCHAN_SRC_LOG_DEST_LOG | NO_TIM_FOR_LINK + | NON_SECURE_CHANNEL | HIGH_PRIORITY_CHANNEL), + .dst_dev_type = DMA_DEV_SLIM0_CH0_TX_HSI_TX_CH0, + .src_dev_type = DMA_DEV_DEST_MEMORY, + .src_info = { + .endianess = DMA_LITTLE_ENDIAN, + .data_width = DMA_WORD_WIDTH, + .burst_size = DMA_BURST_SIZE_4, + .buffer_type = SINGLE_BUFFERED, + }, + .dst_info = { + .endianess = DMA_LITTLE_ENDIAN, + .data_width = DMA_WORD_WIDTH, + .burst_size = DMA_BURST_SIZE_4, + .buffer_type = SINGLE_BUFFERED, + } + }, + [1] = { + .reserve_channel = 0, + .dir = MEM_TO_PERIPH, + .flow_cntlr = DMA_IS_FLOW_CNTLR, + .channel_type = + (STANDARD_CHANNEL | CHANNEL_IN_LOGICAL_MODE + | LCHAN_SRC_LOG_DEST_LOG | NO_TIM_FOR_LINK + | NON_SECURE_CHANNEL | HIGH_PRIORITY_CHANNEL), + .dst_dev_type = DMA_DEV_SLIM0_CH1_TX_HSI_TX_CH1, + .src_dev_type = DMA_DEV_DEST_MEMORY, + .src_info = { + .endianess = DMA_LITTLE_ENDIAN, + .data_width = DMA_WORD_WIDTH, + .burst_size = DMA_BURST_SIZE_4, + .buffer_type = SINGLE_BUFFERED, + }, + .dst_info = { + .endianess = DMA_LITTLE_ENDIAN, + .data_width = DMA_WORD_WIDTH, + .burst_size = DMA_BURST_SIZE_4, + .buffer_type = SINGLE_BUFFERED, + } + }, + [2] = { + .reserve_channel = 0, + .dir = MEM_TO_PERIPH, + .flow_cntlr = DMA_IS_FLOW_CNTLR, + .channel_type = + (STANDARD_CHANNEL | CHANNEL_IN_LOGICAL_MODE + | LCHAN_SRC_LOG_DEST_LOG | NO_TIM_FOR_LINK + | NON_SECURE_CHANNEL | HIGH_PRIORITY_CHANNEL), + .dst_dev_type = DMA_DEV_SLIM0_CH2_TX_HSI_TX_CH2, + .src_dev_type = DMA_DEV_DEST_MEMORY, + .src_info = { + .endianess = DMA_LITTLE_ENDIAN, + .data_width = DMA_WORD_WIDTH, + .burst_size = DMA_BURST_SIZE_4, + .buffer_type = SINGLE_BUFFERED, + }, + .dst_info = { + .endianess = DMA_LITTLE_ENDIAN, + .data_width = DMA_WORD_WIDTH, + .burst_size = DMA_BURST_SIZE_4, + .buffer_type = SINGLE_BUFFERED, + } + }, + [3] = { + .reserve_channel = 0, + .dir = MEM_TO_PERIPH, + .flow_cntlr = DMA_IS_FLOW_CNTLR, + .channel_type = + (STANDARD_CHANNEL | CHANNEL_IN_LOGICAL_MODE + | LCHAN_SRC_LOG_DEST_LOG | NO_TIM_FOR_LINK + | NON_SECURE_CHANNEL | HIGH_PRIORITY_CHANNEL), + .dst_dev_type = DMA_DEV_SLIM0_CH3_TX_HSI_TX_CH3, + .src_dev_type = DMA_DEV_DEST_MEMORY, + .src_info = { + .endianess = DMA_LITTLE_ENDIAN, + .data_width = DMA_WORD_WIDTH, + .burst_size = DMA_BURST_SIZE_4, + .buffer_type = SINGLE_BUFFERED, + }, + .dst_info = { + .endianess = DMA_LITTLE_ENDIAN, + .data_width = DMA_WORD_WIDTH, + .burst_size = DMA_BURST_SIZE_4, + .buffer_type = SINGLE_BUFFERED, + } + }, + }, + .watermark = 0x2 /** 1 free entries for all channels */ , + .gpio_alt_func = GPIO_ALT_HSIT, +}; + +static struct hsi_plat_data hsir_platform_data = { + .dev_type = 0x1 /** receiver */ , + .mode = 0x3 /** pipelined */ , + .threshold = 0x22 /** 35 zero bits for break */ , + .parity = 0x0 /** no parity */ , + .detector = 0x0 /** oversampling */ , + .channels = 0x4 /** 4 channels */ , + .realtime = 0x0 /** disabled,no overwrite,all channels */ , + .framelen = 0x1f /** 32 bits all channels */ , + .preamble = 0x0 /** max timeout cycles */ , + .ch_base_span = {[0] = {.base = 0x0, .span = 0x3}, + [1] = {.base = 0x4, .span = 0x3}, + [2] = {.base = 0x8, .span = 0x7}, + [3] = {.base = 0x10, .span = 0x7} + }, +#ifdef CONFIG_STN8500_HSI_LEGACY + .currmode = CONFIG_STN8500_HSI_TRANSFER_MODE, +#else + .currmode = 1, +#endif + .timeout = 0x0 /** immediate updation of channel buffer */ , + .hsi_dma_info = { + [0] = { + .reserve_channel = 0, + .dir = PERIPH_TO_MEM, + .flow_cntlr = DMA_IS_FLOW_CNTLR, + .channel_type = + (STANDARD_CHANNEL | CHANNEL_IN_LOGICAL_MODE + | LCHAN_SRC_LOG_DEST_LOG | NO_TIM_FOR_LINK + | NON_SECURE_CHANNEL | HIGH_PRIORITY_CHANNEL), + .src_dev_type = DMA_DEV_SLIM0_CH0_RX_HSI_RX_CH0, + .dst_dev_type = DMA_DEV_DEST_MEMORY, + .src_info = { + .endianess = DMA_LITTLE_ENDIAN, + .data_width = DMA_WORD_WIDTH, + .burst_size = DMA_BURST_SIZE_4, + .buffer_type = SINGLE_BUFFERED, + }, + .dst_info = { + .endianess = DMA_LITTLE_ENDIAN, + .data_width = DMA_WORD_WIDTH, + .burst_size = DMA_BURST_SIZE_4, + .buffer_type = SINGLE_BUFFERED, + } + }, + [1] = { + .reserve_channel = 0, + .dir = PERIPH_TO_MEM, + .flow_cntlr = DMA_IS_FLOW_CNTLR, + .channel_type = + (STANDARD_CHANNEL | CHANNEL_IN_LOGICAL_MODE + | LCHAN_SRC_LOG_DEST_LOG | NO_TIM_FOR_LINK + | NON_SECURE_CHANNEL | HIGH_PRIORITY_CHANNEL), + .src_dev_type = DMA_DEV_SLIM0_CH1_RX_HSI_RX_CH1, + .dst_dev_type = DMA_DEV_DEST_MEMORY, + .src_info = { + .endianess = DMA_LITTLE_ENDIAN, + .data_width = DMA_WORD_WIDTH, + .burst_size = DMA_BURST_SIZE_4, + .buffer_type = SINGLE_BUFFERED, + }, + .dst_info = { + .endianess = DMA_LITTLE_ENDIAN, + .data_width = DMA_WORD_WIDTH, + .burst_size = DMA_BURST_SIZE_4, + .buffer_type = SINGLE_BUFFERED, + } + }, + [2] = { + .reserve_channel = 0, + .dir = PERIPH_TO_MEM, + .flow_cntlr = DMA_IS_FLOW_CNTLR, + .channel_type = + (STANDARD_CHANNEL | CHANNEL_IN_LOGICAL_MODE + | LCHAN_SRC_LOG_DEST_LOG | NO_TIM_FOR_LINK + | NON_SECURE_CHANNEL | HIGH_PRIORITY_CHANNEL), + .src_dev_type = DMA_DEV_SLIM0_CH2_RX_HSI_RX_CH2, + .dst_dev_type = DMA_DEV_DEST_MEMORY, + .src_info = { + .endianess = DMA_LITTLE_ENDIAN, + .data_width = DMA_WORD_WIDTH, + .burst_size = DMA_BURST_SIZE_4, + .buffer_type = SINGLE_BUFFERED, + }, + .dst_info = { + .endianess = DMA_LITTLE_ENDIAN, + .data_width = DMA_WORD_WIDTH, + .burst_size = DMA_BURST_SIZE_4, + .buffer_type = SINGLE_BUFFERED, + } + }, + [3] = { + .reserve_channel = 0, + .dir = PERIPH_TO_MEM, + .flow_cntlr = DMA_IS_FLOW_CNTLR, + .channel_type = + (STANDARD_CHANNEL | CHANNEL_IN_LOGICAL_MODE + | LCHAN_SRC_LOG_DEST_LOG | NO_TIM_FOR_LINK + | NON_SECURE_CHANNEL | HIGH_PRIORITY_CHANNEL), + .src_dev_type = DMA_DEV_SLIM0_CH3_RX_HSI_RX_CH3, + .dst_dev_type = DMA_DEV_DEST_MEMORY, + .src_info = { + .endianess = DMA_LITTLE_ENDIAN, + .data_width = DMA_WORD_WIDTH, + .burst_size = DMA_BURST_SIZE_4, + .buffer_type = SINGLE_BUFFERED, + }, + .dst_info = { + .endianess = DMA_LITTLE_ENDIAN, + .data_width = DMA_WORD_WIDTH, + .burst_size = DMA_BURST_SIZE_4, + .buffer_type = SINGLE_BUFFERED, + } + }, + }, + .watermark = 0x2 /** 1 'occupated' entry for all channels */ , + .gpio_alt_func = GPIO_ALT_HSIR, +}; + +static struct resource u8500_hsit_resource[] = { + [0] = { + .start = U8500_HSIT_BASE, + .end = U8500_HSIT_BASE + (SZ_4K - 1), + .name = "hsit_iomem_base", + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_HSITD0, + .end = IRQ_HSITD1, + .name = "hsit_irq", + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource u8500_hsir_resource[] = { + [0] = { + .start = U8500_HSIR_BASE, + .end = U8500_HSIR_BASE + (SZ_4K - 1), + .name = "hsir_iomem_base", + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_HSIRD0, + .end = IRQ_HSIRD1, + .name = "hsir_irq", + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = IRQ_HSIR_EXCEP, + .end = IRQ_HSIR_EXCEP, + .name = "hsir_irq_excep", + .flags = IORESOURCE_IRQ, + }, + [3] = { + .start = IRQ_HSIR_CH0_OVRRUN, + .end = IRQ_HSIR_CH0_OVRRUN, + .name = "hsir_irq_ch0_overrun", + .flags = IORESOURCE_IRQ, + }, + [4] = { + .start = IRQ_HSIR_CH1_OVRRUN, + .end = IRQ_HSIR_CH1_OVRRUN, + .name = "hsir_irq_ch1_overrun", + .flags = IORESOURCE_IRQ, + }, + [5] = { + .start = IRQ_HSIR_CH2_OVRRUN, + .end = IRQ_HSIR_CH2_OVRRUN, + .name = "hsir_irq_ch2_overrun", + .flags = IORESOURCE_IRQ, + }, + [6] = { + .start = IRQ_HSIR_CH3_OVRRUN, + .end = IRQ_HSIR_CH3_OVRRUN, + .name = "hsir_irq_ch3_overrun", + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device u8500_hsit_device = { + .name = "stm-hsi", + .id = 0, + .dev = { + .platform_data = &hsit_platform_data, + }, + .num_resources = ARRAY_SIZE(u8500_hsit_resource), + .resource = u8500_hsit_resource, +}; + +struct platform_device u8500_hsir_device = { + .name = "stm-hsi", + .id = 1, + .dev = { + .platform_data = &hsir_platform_data, + }, + .num_resources = ARRAY_SIZE(u8500_hsir_resource), + .resource = u8500_hsir_resource, +}; diff --git a/arch/arm/mach-ux500/include/mach/ab8500-dev.h b/arch/arm/mach-ux500/include/mach/ab8500-dev.h new file mode 100755 index 00000000000..8b4d69f5d2e --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/ab8500-dev.h @@ -0,0 +1,30 @@ +/* + * ab8500-dev.c - simple userspace interface to ab8500 + * + * Copyright (C) 2009 STEricsson + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + */ + +/* + * struct ab8500dev_data - AB8500 /dev structure + * @block: bank address + * @addr: register address + * @data: data to be read/write to + * + * This supports access to AB8500 chip using normal userspace I/O calls. + */ +struct ab8500dev_data { + unsigned char block; + unsigned char addr; + unsigned char data; + unsigned char int_no; + unsigned char sig_no; +}; + +#define AB8500_IOC_MAGIC 'S' +#define AB8500_GET_REGISTER _IOWR(AB8500_IOC_MAGIC, 1, struct ab8500dev_data) +#define AB8500_SET_REGISTER _IOW(AB8500_IOC_MAGIC, 2, struct ab8500dev_data) +#define SET_INT_SIGNAL _IOW(AB8500_IOC_MAGIC, 3, struct ab8500dev_data) diff --git a/arch/arm/mach-ux500/include/mach/ab8500.h b/arch/arm/mach-ux500/include/mach/ab8500.h new file mode 100755 index 00000000000..9dc62278731 --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/ab8500.h @@ -0,0 +1,586 @@ +/* + * Copyright ST-Ericsson 2009. + * + * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> + * Licensed under GPLv2. + */ +#ifndef _AB8500_H +#define _AB8500_H + +#include <linux/types.h> +#include <linux/interrupt.h> +#include <linux/gpio.h> +#include <mach/hardware.h> +#include <asm/dma.h> +#include <mach/dma.h> +#include <linux/spi/spi.h> +#include <linux/spi/spi-stm.h> +#include <mach/prcmu-fw-api.h> +/* + * AB8500 bank addresses + */ +#define AB8500_SYS_CTRL1_BLOCK 0x1 +#define AB8500_SYS_CTRL2_BLOCK 0x2 +#define AB8500_REGU_CTRL1 0x3 +#define AB8500_REGU_CTRL2 0x4 +#define AB8500_USB 0x5 +#define AB8500_TVOUT 0x6 +#define AB8500_DBI 0x7 +#define AB8500_ECI_AV_ACC 0x8 +#define AB8500_RESERVED 0x9 +#define STw4550_GPADC 0xA +#define AB8500_GPADC 0xA +#define AB8500_CHARGER 0xB +#define AB8500_GAS_GAUGE 0xC +#define AB8500_AUDIO 0xD +#define AB8500_INTERRUPT 0xE +#define AB8500_RTC 0xF +#define AB8500_MISC 0x10 +#define AB8500_DEBUG 0x12 +#define AB8500_PROD_TEST 0x13 +#define AB8500_OTP_EMUL 0x15 + +/* + * System control 1 register offsets. + * Bank = 0x01 + */ +#define AB8500_TURNON_STAT_REG 0x0100 +#define AB8500_RESET_STAT_REG 0x0101 +#define AB8500_PONKEY1_PRESS_STAT_REG 0x0102 + +#define AB8500_FSM_STAT1_REG 0x0140 +#define AB8500_FSM_STAT2_REG 0x0141 +#define AB8500_SYSCLK_REQ_STAT_REG 0x0142 +#define AB8500_USB_STAT1_REG 0x0143 +#define AB8500_USB_STAT2_REG 0x0144 +#define AB8500_STATUS_SPARE1_REG 0x0145 +#define AB8500_STATUS_SPARE2_REG 0x0146 + +#define AB8500_CTRL1_REG 0x0180 +#define AB8500_CTRL2_REG 0x0181 + +/* + * System control 2 register offsets. + * bank = 0x02 + */ +#define AB8500_CTRL3_REG 0x0200 +#define AB8500_CTRL3_RST_DENC_MASK 0x4 +#define AB8500_CTRL3_RST_DENC_SHIFT 2 +#define AB8500_CTRL3_RST_AUD_MASK 0x2 +#define AB8500_CTRL3_RST_AUD_SHIFT 1 +#define AB8500_MAIN_WDOG_CTRL_REG 0x0201 +#define AB8500_MAIN_WDOG_TIMER_REG 0x0202 +#define AB8500_LOW_BAT_REG 0x0203 +#define AB8500_BATT_OK_REG 0x0204 +#define AB8500_SYSCLK_TIMER_REG 0x0205 +#define AB8500_SMPSCLK_CTRL_REG 0x0206 +#define AB8500_SMPSCLK_SEL1_REG 0x0207 +#define AB8500_SMPSCLK_SEL2_REG 0x0208 +#define AB8500_SMPSCLK_SEL3_REG 0x0209 +#define AB8500_SYSULPCLK_CONF_REG 0x020A +#define AB8500_SYSULPCLK_CTRL1_REG 0x020B +#define AB8500_SYSCLK_CTRL_REG 0x020C +#define AB8500_SYSCLK_REQ1_VALID_REG 0x020D +#define AB8500_SYSCLK_REQ_VALID_REG 0x020E +#define AB8500_SYSCTRL_SPARE_REG 0x020F +#define AB8500_PAD_CONF_REG 0x0210 + +/* + * Regu control1 register offsets (SPI) + * Bank = 0x03 + */ +#define AB8500_REGU_SERIAL_CTRL1_REG 0x0300 +#define AB8500_REGU_SERIAL_CTRL2_REG 0x0301 +#define AB8500_REGU_SERIAL_CTRL3_REG 0x0302 +#define AB8500_REGU_REQ_CTRL1_REG 0x0303 +#define AB8500_REGU_REQ_CTRL2_REG 0x0304 +#define AB8500_REGU_REQ_CTRL3_REG 0x0305 +#define AB8500_REGU_REQ_CTRL4_REG 0x0306 +#define AB8500_REGU_SYSCLK_REQ1HP_VALID1_REG 0x0307 +#define AB8500_REGU_SYSCLK_REQ1HP_VALID2_REG 0x0308 +#define AB8500_REGU_HWHPREQ1_VALID1_REG 0x0309 +#define AB8500_REGU_HWHPREQ1_VALID2_REG 0x030A +#define AB8500_REGU_HWHPREQ2_VALID1_REG 0x030B +#define AB8500_REGU_HWHPREQ2_VALID2_REG 0x030C +#define AB8500_REGU_SWHPREQ_VALID1_REG 0x030D +#define AB8500_REGU_SWHPREQ_VALID2_REG 0x030E + +#define AB8500_REGU_SYSCLK_REQ1_VALID_REG 0x030F /* only for ED*/ +#define AB8500_REGU_SYSCLK_REQ2_VALID_REG 0x0310 /*only for ED*/ + +#define AB8500_REGU_MISC1_REG 0x0380 +#define AB8500_REGU_OTGSUPPLY_CTRL_REG 0x0381 +#define AB8500_REGU_VUSB_CTRL_REG 0x0382 /* see reg manaul*/ +#define AB8500_REGU_VAUDIO_SUPPLY_REG 0x0383 +#define AB8500_REGU_CTRL1_SPARE_REG 0x0384 + + /* + * Regu control2 register offsets (SPI/APE I2C) + * Bank = 0x04 + */ +#define AB8500_REGU_ARM_REGU1_REG 0x0400 +#define AB8500_REGU_ARM_REGU2_REG 0x0401 +#define AB8500_REGU_VAPE_REGU_REG 0x0402 +#define AB8500_REGU_VSMPS1_REGU_REG 0x0403 +#define AB8500_REGU_VSMPS2_REGU_REG 0x0404 +#define AB8500_REGU_VSMPS3_REGU_REG 0x0405 +#define AB8500_REGU_VPLLVANA_REGU_REG 0x0406 +#define AB8500_REGU_VREF_DDR_REG 0x0407 +#define AB8500_REGU_EXTSUPPLY_REGU_REG 0x0408 +#define AB8500_REGU_VAUX12_REGU_REG 0x0409 +#define AB8500_REGU_VAUX12_REGU_VAUX1_MASK 0x3 +#define AB8500_REGU_VAUX12_REGU_VAUX1_SHIFT 0 +#define AB8500_REGU_VAUX12_REGU_VAUX1_FORCE_HP 0x1 +#define AB8500_REGU_VRF1VAUX3_REGU_REG 0x040A +#define AB8500_REGU_VARM_SEL1_REG 0x040B +#define AB8500_REGU_VARM_SEL2_REG 0x040C +#define AB8500_REGU_VARM_SEL3_REG 0x040D +#define AB8500_REGU_VAPE_SEL1_REG 0x040E +#define AB8500_REGU_VAPE_SEL2_REG 0x040F +#define AB8500_REGU_VAPE_SEL3_REG 0x0410 +#define AB8500_REGU_VBB_SEL2_REG 0x0412 +#define AB8500_REGU_VSMPS1_SEL1_REG 0x0413 +#define AB8500_REGU_VSMPS1_SEL2_REG 0x0414 +#define AB8500_REGU_VSMPS1_SEL3_REG 0x0415 +#define AB8500_REGU_VSMPS2_SEL1_REG 0x0417 +#define AB8500_REGU_VSMPS2_SEL2_REG 0x0418 +#define AB8500_REGU_VSMPS2_SEL3_REG 0x0419 +#define AB8500_REGU_VSMPS3_SEL1_REG 0x041B +#define AB8500_REGU_VSMPS3_SEL2_REG 0x041C +#define AB8500_REGU_VSMPS3_SEL3_REG 0x041D +#define AB8500_REGU_VAUX1_SEL_REG 0x041F +#define AB8500_REGU_VAUX1_SEL_MASK 0xf +#define AB8500_REGU_VAUX1_SEL_SHIFT 0 +#define AB8500_REGU_VAUX1_SEL_1_5V 0x4 +#define AB8500_REGU_VAUX1_SEL_2_5V 0x8 +#define AB8500_REGU_VAUX2_SEL_REG 0x0420 +#define AB8500_REGU_VRF1VAUX3_SEL_REG 0x0421 +#define AB8500_REGU_CTRL2_SPARE_REG 0x0422 + +/* + * Regu control2 Vmod register offsets + */ +#define AB8500_REGU_VMOD_REGU_REG 0x0440 +#define AB8500_REGU_VMOD_SEL1_REG 0x0441 +#define AB8500_REGU_VMOD_SEL2_REG 0x0442 +#define AB8500_REGU_CTRL_DISCH_REG 0x0443 +#define AB8500_REGU_CTRL_DISCH2_REG 0x0444 + +/* + * Sim control register offsets + * Bank:0x4 + */ +#define AB8500_SIM_REG1_SGR1L_REG 0x0480 +#define AB8500_SIM_REG1_SGR1U_REG 0x0481 +#define AB8500_SIM_REG2_SCR1L_REG 0x0482 +#define AB8500_SIM_REG2_SCR1U_REG 0x0483 +#define AB8500_SIM_REG3_SCTRLRL_REG 0x0484 +#define AB8500_SIM_REG3_SCTRLRU_REG 0x0485 +#define AB8500_SIM_ISOUICCINT_SRC_REG 0x0486 +#define AB8500_SIM_ISOUICCINT_LATCH_REG 0x0487 +#define AB8500_SIM_ISOUICCINT_MASK_REG 0x0488 +#define AB8500_SIM_REG4_USBUICC_REG 0x0489 +#define AB8500_SIM_SDELAYSEL_REG 0x048A +#define AB8500_SIM_USBUICC_CTRL 0x048B /* bit 3 only for ED */ + +/* + * USB/ULPI register offsets + * Bank : 0x5 + */ +#define AB8500_USB_LINE_STAT_REG 0x0580 +#define AB8500_USB_LINE_CTRL1_REG 0x0581 +#define AB8500_USB_LINE_CTRL2_REG 0x0582 +#define AB8500_USB_LINE_CTRL3_REG 0x0583 +#define AB8500_USB_LINE_CTRL4_REG 0x0584 +#define AB8500_USB_LINE_CTRL5_REG 0x0585 +#define AB8500_USB_OTG_CTRL_REG 0x0587 +#define AB8500_USB_OTG_STAT_REG 0x0588 +#define AB8500_USB_OTG_STAT_REG 0x0588 +#define AB8500_USB_CTRL_SPARE_REG 0x0589 +#define AB8500_USB_PHY_CTRL_REG 0x058A /*only in Cut1.0*/ + +/* + * TVOUT / CTRL register offsets + * Bank : 0x06 + */ +#define AB8500_DENC_CONF0_REG 0x0600 +#define AB8500_DENC_CONF1_REG 0x0601 +#define AB8500_DENC_CONF2_REG 0x0602 +#define AB8500_DENC_CONF3_REG 0x0603 +#define AB8500_DENC_CONF4_REG 0x0604 +#define AB8500_DENC_CONF5_REG 0x0605 +#define AB8500_DENC_CONF6_REG 0x0606 +#define AB8500_DENC_CONF6_SOFT_RST_MASK 0x80 +#define AB8500_DENC_CONF6_SOFT_RST_SHIFT 7 +#define AB8500_DENC_CONF6_SOFT_RST_OFF 0x0 +#define AB8500_DENC_CONF6_SOFT_RST_ON 0x1 +#define AB8500_DENC_CONF7_REG 0x0607 +#define AB8500_DENC_CONF8_REG 0x0608 +#define AB8500_TVOUT_CTRL_REG 0x0680 +#define AB8500_TVOUT_CTRL2_REG 0x0681 +/* + * DBI register offsets + * Bank : 0x07 + */ +#define AB8500_DBI_REG1_REG 0x0700 +#define AB8500_DBI_REG2_REG 0x0701 +/* + * ECI regsiter offsets + * Bank : 0x08 + */ +#define AB8500_ECI_CTRL_REG 0x0800 +#define AB8500_ECI_HOOKLEVEL_REG 0x0801 +#define AB8500_ECI_DATAOUT_REG 0x0802 +#define AB8500_ECI_DATAIN_REG 0x0803 +/* + * AV Connector register offsets + * Bank : 0x08 + */ +#define AB8500_AV_CONN_REG 0x0840 +/* + * Accessory detection register offsets + * Bank : 0x08 + */ +#define AB8500_ACC_DET_DB1_REG 0x0880 +#define AB8500_ACC_DET_DB2_REG 0x0881 +/* + * GPADC register offsets + * Bank : 0x0A + */ +#define AB8500_GPADC_CTRL1_REG 0x0A00 +#define AB8500_GPADC_CTRL2_REG 0x0A01 +#define AB8500_GPADC_CTRL3_REG 0x0A02 +#define AB8500_GPADC_AUTO_TIMER_REG 0x0A03 +#define AB8500_GPADC_STAT_REG 0x0A04 +#define AB8500_GPADC_MANDATAL_REG 0x0A05 +#define AB8500_GPADC_MANDATAH_REG 0x0A06 +#define AB8500_GPADC_AUTODATAL_REG 0x0A07 +#define AB8500_GPADC_AUTODATAH_REG 0x0A08 +#define AB8500_GPADC_MUX_CTRL_REG 0x0A09 +/* + * Charger / status register offfsets + * Bank : 0x0B + */ +#define AB8500_CH_STATUS1_REG 0x0B00 +#define AB8500_CH_STATUS2_REG 0x0B01 +#define AB8500_CH_USBCH_STAT1_REG 0x0B02 +#define AB8500_CH_USBCH_STAT2_REG 0x0B03 +#define AB8500_CH_FSM_STAT_REG 0x0B04 +#define AB8500_CH_STAT_REG 0x0B05 +/* + * Charger / control register offfsets + * Bank : 0x0B + */ +#define AB8500_CH_VOLT_LVL_REG 0x0B40 +#define AB8500_CH_VOLT_LVL_MAX_REG 0x0B41 /*Only in Cut1.0*/ +#define AB8500_CH_OPT_CRNTLVL_REG 0x0B42 /*Only in Cut1.0*/ +#define AB8500_CH_OPT_CRNTLVL_MAX_REG 0x0B43 /*Only in Cut1.0*/ +#define AB8500_CH_WD_TIMER_REG 0x0B44 /*Only in Cut1.0*/ +#define AB8500_CH_WD_CTRL_REG 0x0B45 /*Only in Cut1.0*/ +#define AB8500_CHARG_WD_CTRL 0x0B51 +#define AB8500_LED_INDICATOR_PWM_CTRL 0x0B53 +#define AB8500_LED_INDICATOR_PWM_DUTY 0x0B54 +#define AB8500_BATT_OVV 0x0B55 +/* + * Charger / main control register offfsets + * Bank : 0x0B + */ +#define AB8500_MCH_CTRL1 0x0B80 +#define AB8500_MCH_CTRL2 0x0B81 +#define AB8500_MCH_IPT_CURLVL_REG 0x0B82 +#define AB8500_CH_WD_REG 0x0B83 +/* + * Charger / USB control register offsets + * Bank : 0x0B + */ +#define AB8500_USBCH_CTRL1_REG 0x0BC0 +#define AB8500_USBCH_CTRL2_REG 0x0BC1 +#define AB8500_USBCH_IPT_CRNTLVL_REG 0x0BC2 +/* + * Gas Gauge register offsets + * Bank : 0x0C + */ +#define AB8500_GASG_CC_CTRL_REG 0x0C00 +#define AB8500_GASG_CC_ACCU1_REG 0x0C01 +#define AB8500_GASG_CC_ACCU2_REG 0x0C02 +#define AB8500_GASG_CC_ACCU3_REG 0x0C03 +#define AB8500_GASG_CC_ACCU4_REG 0x0C04 +#define AB8500_GASG_CC_SMPL_CNTRL_REG 0x0C05 +#define AB8500_GASG_CC_SMPL_CNTRH_REG 0x0C06 +#define AB8500_GASG_CC_SMPL_CNVL_REG 0x0C07 +#define AB8500_GASG_CC_SMPL_CNVH_REG 0x0C08 +#define AB8500_GASG_CC_CNTR_AVGOFF_REG 0x0C09 +#define AB8500_GASG_CC_OFFSET_REG 0x0C0A +/* + * Audio + * Bank : 0x0D + * Not a part of this file. Should be part of Audio codec driver + */ + +/* + * Interrupt register offsets + * Bank : 0x0E + */ +#define AB8500_IT_SOURCE1_REG 0x0E00 +#define AB8500_IT_SOURCE2_REG 0x0E01 +#define AB8500_IT_SOURCE3_REG 0x0E02 +#define AB8500_IT_SOURCE4_REG 0x0E03 +#define AB8500_IT_SOURCE5_REG 0x0E04 +#define AB8500_IT_SOURCE6_REG 0x0E05 + +/* available only in 1.0 */ +#define AB8500_IT_SOURCE7_REG 0x0E06 +#define AB8500_IT_SOURCE8_REG 0x0E07 +#define AB8500_IT_SOURCE19_REG 0x0E12 + +#define AB8500_IT_SOURCE20_REG 0x0E13 +#define AB8500_IT_SOURCE21_REG 0x0E14 +#define AB8500_IT_SOURCE22_REG 0x0E15 +#define AB8500_IT_SOURCE23_REG 0x0E16 +#define AB8500_IT_SOURCE24_REG 0x0E17 + +/* + * latch registers + */ +#define AB8500_IT_LATCH1_REG 0x0E20 +#define AB8500_IT_LATCH2_REG 0x0E21 +#define AB8500_IT_LATCH3_REG 0x0E22 +#define AB8500_IT_LATCH4_REG 0x0E23 +#define AB8500_IT_LATCH5_REG 0x0E24 +#define AB8500_IT_LATCH6_REG 0x0E25 + +/* available only in 1.0 */ +#define AB8500_IT_LATCH7_REG 0x0E26 +#define AB8500_IT_LATCH8_REG 0x0E27 +#define AB8500_IT_LATCH9_REG 0x0E28 +#define AB8500_IT_LATCH10_REG 0x0E29 +#define AB8500_IT_LATCH19_REG 0x0E32 + +#define AB8500_IT_LATCH20_REG 0x0E33 +#define AB8500_IT_LATCH21_REG 0x0E34 +#define AB8500_IT_LATCH22_REG 0x0E35 +#define AB8500_IT_LATCH23_REG 0x0E36 +#define AB8500_IT_LATCH24_REG 0x0E37 + +/* + * mask registers + */ + +#define AB8500_IT_MASK1_REG 0x0E40 +#define AB8500_IT_MASK2_REG 0x0E41 +#define AB8500_IT_MASK3_REG 0x0E42 +#define AB8500_IT_MASK4_REG 0x0E43 +#define AB8500_IT_MASK5_REG 0x0E44 +#define AB8500_IT_MASK6_REG 0x0E45 + + +/* available only in 1.0 */ +#define AB8500_IT_MASK7_REG 0x0E46 +#define AB8500_IT_MASK8_REG 0x0E47 +#define AB8500_IT_MASK9_REG 0x0E48 +#define AB8500_IT_MASK10_REG 0x0E49 +#define AB8500_IT_MASK11_REG 0x0E4A +#define AB8500_IT_MASK12_REG 0x0E4B +#define AB8500_IT_MASK13_REG 0x0E4C +#define AB8500_IT_MASK14_REG 0x0E4D +#define AB8500_IT_MASK15_REG 0x0E4E +#define AB8500_IT_MASK16_REG 0x0E4F +#define AB8500_IT_MASK17_REG 0x0E50 +#define AB8500_IT_MASK18_REG 0x0E51 +#define AB8500_IT_MASK19_REG 0x0E52 + +#define AB8500_IT_MASK20_REG 0x0E53 +#define AB8500_IT_MASK21_REG 0x0E54 +#define AB8500_IT_MASK22_REG 0x0E55 +#define AB8500_IT_MASK23_REG 0x0E56 +#define AB8500_IT_MASK24_REG 0x0E57 + +/* + * RTC bank register offsets + * Bank : 0xF + */ +#define AB8500_RTC_SWITCHOFF_STAT_REG 0x0F00 +#define AB8500_RTC_CC_CONF_REG 0x0F01 +#define AB8500_RTC_READ_REQ_REG 0x0F02 +#define AB8500_RTC_WATCH_TSECMID_REG 0x0F03 +#define AB8500_RTC_WATCH_TSECHI_REG 0x0F04 +#define AB8500_RTC_WATCH_TMIN_LOW_REG 0x0F05 +#define AB8500_RTC_WATCH_TMIN_MID_REG 0x0F06 +#define AB8500_RTC_WATCH_TMIN_HI_REG 0x0F07 +#define AB8500_RTC_ALRM_MIN_LOW_REG 0x0F08 +#define AB8500_RTC_ALRM_MIN_MID_REG 0x0F09 +#define AB8500_RTC_ALRM_MIN_HI_REG 0x0F0A +#define AB8500_RTC_STAT_REG 0x0F0B +#define AB8500_RTC_BKUP_CHG_REG 0x0F0C +#define AB8500_RTC_FORCE_BKUP_REG 0x0F0D +#define AB8500_RTC_CALIB_REG 0x0F0E +#define AB8500_RTC_SWITCH_STAT_REG 0x0F0F + +/* + * Misc block GPIO register offsets - Not for ED + * Bank : 0x10 + */ +/* available only in 1.0 */ +#define AB8500_GPIO_SEL1_REG 0x01000 +#define AB8500_GPIO_SEL2_REG 0x01001 +#define AB8500_GPIO_SEL3_REG 0x01002 +#define AB8500_GPIO_SEL4_REG 0x01003 +#define AB8500_GPIO_SEL5_REG 0x01004 +#define AB8500_GPIO_SEL6_REG 0x01005 +#define AB8500_GPIO_DIR1_REG 0x01010 +#define AB8500_GPIO_DIR2_REG 0x01011 +#define AB8500_GPIO_DIR3_REG 0x01012 +#define AB8500_GPIO_DIR4_REG 0x01013 +#define AB8500_GPIO_DIR5_REG 0x01014 +#define AB8500_GPIO_DIR6_REG 0x01015 + +#define AB8500_GPIO_OUT1_REG 0x01020 +#define AB8500_GPIO_OUT2_REG 0x01021 +#define AB8500_GPIO_OUT3_REG 0x01022 +#define AB8500_GPIO_OUT4_REG 0x01023 +#define AB8500_GPIO_OUT5_REG 0x01024 +#define AB8500_GPIO_OUT6_REG 0x01025 + +#define AB8500_GPIO_PUD1_REG 0x01030 +#define AB8500_GPIO_PUD2_REG 0x01031 +#define AB8500_GPIO_PUD3_REG 0x01032 +#define AB8500_GPIO_PUD4_REG 0x01033 +#define AB8500_GPIO_PUD5_REG 0x01034 +#define AB8500_GPIO_PUD6_REG 0x01035 + +#define AB8500_GPIO_IN1_REG 0x01040 +#define AB8500_GPIO_IN2_REG 0x01041 +#define AB8500_GPIO_IN3_REG 0x01042 +#define AB8500_GPIO_IN4_REG 0x01043 +#define AB8500_GPIO_IN5_REG 0x01044 +#define AB8500_GPIO_IN6_REG 0x01045 +#define AB8500_GPIO_ALT_FUNC 0x01050 + +/* + * PWM Out generators + * Bank: 0x10 + */ +#define AB8500_PWM_OUT_CTRL1_REG 0x1060 +#define AB8500_PWM_OUT_CTRL2_REG 0x1061 +#define AB8500_PWM_OUT_CTRL3_REG 0x1062 +#define AB8500_PWM_OUT_CTRL4_REG 0x1063 +#define AB8500_PWM_OUT_CTRL5_REG 0x1064 +#define AB8500_PWM_OUT_CTRL6_REG 0x1065 +#define AB8500_PWM_OUT_CTRL7_REG 0x1066 + +#define AB8500_I2C_PAD_CTRL_REG 0x1067 +#define AB8500_REV_REG 0x1080 + +/* + * Misc, Debug Test Configuration register + * Bank : 0x11 + */ +#define AB8500_DEBUG_TESTMODE_REG 0x01100 + +/* only in 1.0 */ +#define AB8500_I2C_TRIG1_ADR_REG 0x1101 +#define AB8500_I2C_TRIG1_ID_REG 0x1102 +#define AB8500_I2C_TRIG2_ADR_REG 0x1103 +#define AB8500_I2C_TRIG3_ID_REG 0x1104 +#define AB8500_I2C_NOACCESS_SUP_REG 0x1105 + +/* Offsets in TurnOnstatus register + */ + +#define AB8500_MAX_INT 192 +#define AB8500_MAX_FUTURE_USE 105 + +#define AB8500_MAX_INT_SOURCE 11 +#define AB8500_MAX_INT_LATCH 13 +#define AB8500_MAX_INT_MASK 21 + +/** + * struct ab8500_device - Stw4500 device structure + * @cs_en: pointer chip select enable + * @cs_dis: pointer to chip select disable + * + * Stw4500 Internal device structure + */ +struct ab8500_device { + void (*cs_en) (void); + void (*cs_dis) (void); + u16 ssp_controller; +}; + +/*struct t_ab8500_context;*/ + +/** + * struct client_callbacks - Client callbacks + * @callback: callback handler + * @data: private data for the handler + * + * Stw4500 maintains a internal data structure for the registered + * callback + */ +struct client_callbacks { + void (*callback)(void *data); + void *data; +}; + +/** + * struct client_signals - Client signals + * @pid: pid of process + * @signal: signal to be delivered + * + * AB8500 maintains an internal data structure for the delivery of + * required signals to registered processes + */ +struct client_signals { + struct pid *pid; + u32 signal; +}; + +/** + * struct ab8500 - AB8500 Internal data structure + * @ab8500_master: Pointer to the spi_master + * @ab8500_board_info: Pointer to the board information structure + * @ab8500_spi: Pointer to the spi_device strcture + * @spi_transfer: Pointer SPI data transfer structure spi_transfer + * @spi_message: SPI message pointer of type spi_message + * @ab8500_device: AB8500 internal data structure + * @ssp_wrbuf: SSP write data buffer of size 4 bytes + * @ssp_rdbuf: SSP read data buffer of size 4 bytes + * @work: work queue scheduled in the interrupt handler + * @c_callback: Array of client's callback handler + * @ab8500_cfg_lock: synchronization primitive to protect the data + * @ab8500_sem: synchronization primitive used in the non-interrupt context + * @irq: interrupt number of ab8500 + * @revision: revision number of ab8500 silicon + * + * Supports only SPI interface. The device can also be accessed + * through I2C in the successive version of U8500. + */ +struct ab8500 { + struct spi_master *ab8500_master; + struct spi_board_info *ab8500_board_info; + struct spi_device *ab8500_spi; + struct spi_transfer *ab8500_xfer; + struct spi_message *ab8500_msg; + struct ab8500_device *board; + u32 ssp_wrbuf[4]; + u32 ssp_rdbuf[4]; + struct client_callbacks c_callback[184]; + struct client_signals c_signals[184]; + struct work_struct work; + spinlock_t ab8500_cfg_lock; + spinlock_t ab8500_cfgsig_lock; + struct semaphore ab8500_sem; + unsigned char irq; + unsigned char revision; +}; + +int ab8500_get_version(void); +int ab8500_write(u8 block, u32 adr, u8 data); +int ab8500_read(u8 block, u32 adr); +int ab8500_set_callback_handler(int int_no, void *callback_handler, void *data); +int ab8500_remove_callback_handler(int int_no); +void ab8500_int_mask(int int_no); +void ab8500_int_unmask(int int_no); +int ab8500_set_signal_handler(int int_no, int sig_no); +int ab8500_remove_signal_handler(int int_no); +#endif /* AB8500_H_ */ diff --git a/arch/arm/mach-ux500/include/mach/ab8500_codec.h b/arch/arm/mach-ux500/include/mach/ab8500_codec.h new file mode 100755 index 00000000000..b10f28b1a1d --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/ab8500_codec.h @@ -0,0 +1,435 @@ +/*****************************************************************************/ +/** +* © ST-Ericsson, 2009 - All rights reserved +* Reproduction and Communication of this document is strictly prohibited +* unless specifically authorized in writing by ST-Ericsson +* +* \brief Public header file for AB8500 Codec +* \author ST-Ericsson +*/ +/*****************************************************************************/ + +#ifndef _AB8500_CODEC_H_ +#define _AB8500_CODEC_H_ + +/*--------------------------------------------------------------------- + * Includes + *--------------------------------------------------------------------*/ +#include "hcl_defs.h" +#include "debug.h" + +/*--------------------------------------------------------------------- + * Define + *--------------------------------------------------------------------*/ +#ifdef __cplusplus +extern "C" +{ +#endif +typedef enum +{ + AB8500_CODEC_OK, + AB8500_CODEC_ERROR, + AB8500_CODEC_UNSUPPORTED_FEATURE, + AB8500_CODEC_INVALID_PARAMETER, + AB8500_CODEC_CONFIG_NOT_COHERENT, + AB8500_CODEC_TRANSACTION_FAILED +} t_ab8500_codec_error; + + +typedef enum +{ + AB8500_CODEC_DIRECTION_IN, + AB8500_CODEC_DIRECTION_OUT, + AB8500_CODEC_DIRECTION_INOUT +} t_ab8500_codec_direction; + +typedef enum +{ + AB8500_CODEC_MASTER_MODE_DISABLE, + AB8500_CODEC_MASTER_MODE_ENABLE +}t_ab8500_codec_master_mode; + +typedef enum +{ + AB8500_CODEC_AUDIO_INTERFACE_0, + AB8500_CODEC_AUDIO_INTERFACE_1 +}t_ab8500_codec_audio_interface; + + +typedef enum +{ + AB8500_CODEC_MODE_HIFI, + AB8500_CODEC_MODE_VOICE, + AB8500_CODEC_MODE_MANUAL_SETTING +} t_ab8500_codec_mode; + +typedef enum +{ + AB8500_CODEC_DEST_HEADSET, + AB8500_CODEC_DEST_EARPIECE, + AB8500_CODEC_DEST_HANDSFREE, + AB8500_CODEC_DEST_VIBRATOR_L, + AB8500_CODEC_DEST_VIBRATOR_R, + AB8500_CODEC_DEST_ALL +} t_ab8500_codec_dest; + +typedef enum +{ + AB8500_CODEC_SRC_LINEIN, + AB8500_CODEC_SRC_MICROPHONE_1A, + AB8500_CODEC_SRC_MICROPHONE_1B, + AB8500_CODEC_SRC_MICROPHONE_2, + AB8500_CODEC_SRC_D_MICROPHONE_1, + AB8500_CODEC_SRC_D_MICROPHONE_2, + AB8500_CODEC_SRC_D_MICROPHONE_3, + AB8500_CODEC_SRC_D_MICROPHONE_4, + AB8500_CODEC_SRC_D_MICROPHONE_5, + AB8500_CODEC_SRC_D_MICROPHONE_6, + AB8500_CODEC_SRC_ALL +} t_ab8500_codec_src; + +typedef enum +{ + AB8500_CODEC_SLOT0, + AB8500_CODEC_SLOT1, + AB8500_CODEC_SLOT2, + AB8500_CODEC_SLOT3, + AB8500_CODEC_SLOT4, + AB8500_CODEC_SLOT5, + AB8500_CODEC_SLOT6, + AB8500_CODEC_SLOT7, + AB8500_CODEC_SLOT8, + AB8500_CODEC_SLOT9, + AB8500_CODEC_SLOT10, + AB8500_CODEC_SLOT11, + AB8500_CODEC_SLOT12, + AB8500_CODEC_SLOT13, + AB8500_CODEC_SLOT14, + AB8500_CODEC_SLOT15, + AB8500_CODEC_SLOT16, + AB8500_CODEC_SLOT17, + AB8500_CODEC_SLOT18, + AB8500_CODEC_SLOT19, + AB8500_CODEC_SLOT20, + AB8500_CODEC_SLOT21, + AB8500_CODEC_SLOT22, + AB8500_CODEC_SLOT23, + AB8500_CODEC_SLOT24, + AB8500_CODEC_SLOT25, + AB8500_CODEC_SLOT26, + AB8500_CODEC_SLOT27, + AB8500_CODEC_SLOT28, + AB8500_CODEC_SLOT29, + AB8500_CODEC_SLOT30, + AB8500_CODEC_SLOT31, + AB8500_CODEC_SLOT_UNDEFINED +} t_ab8500_codec_slot; + + + +typedef enum +{ + AB8500_CODEC_DA_CHANNEL_NUMBER_1, + AB8500_CODEC_DA_CHANNEL_NUMBER_2, + AB8500_CODEC_DA_CHANNEL_NUMBER_3, + AB8500_CODEC_DA_CHANNEL_NUMBER_4, + AB8500_CODEC_DA_CHANNEL_NUMBER_5, + AB8500_CODEC_DA_CHANNEL_NUMBER_6, + AB8500_CODEC_DA_CHANNEL_NUMBER_UNDEFINED +}t_ab8500_codec_da_channel_number; + + +typedef enum +{ + AB8500_CODEC_CR31_TO_CR46_SLOT_OUTPUTS_DATA_FROM_AD_OUT1, + AB8500_CODEC_CR31_TO_CR46_SLOT_OUTPUTS_DATA_FROM_AD_OUT2, + AB8500_CODEC_CR31_TO_CR46_SLOT_OUTPUTS_DATA_FROM_AD_OUT3, + AB8500_CODEC_CR31_TO_CR46_SLOT_OUTPUTS_DATA_FROM_AD_OUT4, + AB8500_CODEC_CR31_TO_CR46_SLOT_OUTPUTS_DATA_FROM_AD_OUT5, + AB8500_CODEC_CR31_TO_CR46_SLOT_OUTPUTS_DATA_FROM_AD_OUT6, + AB8500_CODEC_CR31_TO_CR46_SLOT_OUTPUTS_DATA_FROM_AD_OUT7, + AB8500_CODEC_CR31_TO_CR46_SLOT_OUTPUTS_DATA_FROM_AD_OUT8, + AB8500_CODEC_CR31_TO_CR46_SLOT_OUTPUTS_ZEROS, + AB8500_CODEC_CR31_TO_CR46_SLOT_IS_TRISTATE = 15, + AB8500_CODEC_CR31_TO_CR46_SLOT_OUTPUTS_DATA_FROM_AD_UNDEFINED +} t_ab8500_codec_cr31_to_cr46_ad_data_allocation; + + +typedef enum +{ + AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT00, + AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT01, + AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT02, + AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT03, + AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT04, + AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT05, + AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT06, + AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT07, + AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT08, + AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT09, + AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT10, + AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT11, + AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT12, + AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT13, + AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT14, + AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT15, + AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT16, + AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT17, + AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT18, + AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT19, + AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT20, + AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT21, + AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT22, + AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT23, + AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT24, + AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT25, + AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT26, + AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT27, + AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT28, + AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT29, + AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT30, + AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT31, + AB8500_CODEC_CR51_TO_CR56_SLTODA_SLOT_UNDEFINED +} t_ab8500_codec_cr51_to_cr56_sltoda; + +typedef enum +{ + AB8500_CODEC_SRC_STATE_DISABLE, + AB8500_CODEC_SRC_STATE_ENABLE +}t_ab8500_codec_src_state; + +typedef enum +{ + AB8500_CODEC_DEST_STATE_DISABLE, + AB8500_CODEC_DEST_STATE_ENABLE +}t_ab8500_codec_dest_state; + +/* CR104 - 5:0 */ +typedef t_uint8 t_ab8500_codec_cr104_bfifoint; + + +/* CR105 - 7:0 */ +typedef t_uint8 t_ab8500_codec_cr105_bfifotx; + +/* CR106 - 6:4 */ +typedef enum +{ + AB8500_CODEC_CR106_BFIFOFSEXT_NO_EXTRA_CLK, + AB8500_CODEC_CR106_BFIFOFSEXT_1SLOT_EXTRA_CLK, + AB8500_CODEC_CR106_BFIFOFSEXT_2SLOT_EXTRA_CLK, + AB8500_CODEC_CR106_BFIFOFSEXT_3SLOT_EXTRA_CLK, + AB8500_CODEC_CR106_BFIFOFSEXT_4SLOT_EXTRA_CLK, + AB8500_CODEC_CR106_BFIFOFSEXT_5SLOT_EXTRA_CLK, + AB8500_CODEC_CR106_BFIFOFSEXT_6SLOT_EXTRA_CLK +} t_ab8500_codec_cr106_bfifofsext; + +/* CR106 - 2 */ +typedef enum +{ + AB8500_CODEC_CR106_BFIFOMSK_AD_DATA0_UNMASKED, + AB8500_CODEC_CR106_BFIFOMSK_AD_DATA0_MASKED +} t_ab8500_codec_cr106_bfifomsk; + +/* CR106 - 1 */ +typedef enum +{ + AB8500_CODEC_CR106_BFIFOMSTR_SLAVE_MODE, + AB8500_CODEC_CR106_BFIFOMSTR_MASTER_MODE +} t_ab8500_codec_cr106_bfifomstr; + +/* CR106 - 0 */ +typedef enum +{ + AB8500_CODEC_CR106_BFIFOSTRT_STOPPED, + AB8500_CODEC_CR106_BFIFOSTRT_RUNNING +} t_ab8500_codec_cr106_bfifostrt; + + +/* CR107 - 7:0 */ +typedef t_uint8 t_ab8500_codec_cr107_bfifosampnr; + + +/* CR108 - 7:0 */ +typedef t_uint8 t_ab8500_codec_cr108_bfifowakeup; + + +typedef struct +{ + t_ab8500_codec_cr104_bfifoint cr104_bfifoint; + t_ab8500_codec_cr105_bfifotx cr105_bfifotx; + t_ab8500_codec_cr106_bfifofsext cr106_bfifofsext; + t_ab8500_codec_cr106_bfifomsk cr106_bfifomsk; + t_ab8500_codec_cr106_bfifomstr cr106_bfifomstr; + t_ab8500_codec_cr106_bfifostrt cr106_bfifostrt; + t_ab8500_codec_cr107_bfifosampnr cr107_bfifosampnr; + t_ab8500_codec_cr108_bfifowakeup cr108_bfifowakeup; +} t_ab8500_codec_burst_fifo_config; + +/************************************************************/ +/*--------------------------------------------------------------------- + * Exported APIs + *--------------------------------------------------------------------*/ +/* Initialization */ +t_ab8500_codec_error AB8500_CODEC_Init(IN t_uint8 slave_address_of_codec); +t_ab8500_codec_error AB8500_CODEC_Reset(void); + +/* Audio Codec basic configuration */ +t_ab8500_codec_error AB8500_CODEC_SetModeAndDirection(IN t_ab8500_codec_direction ab8500_codec_direction, IN t_ab8500_codec_mode ab8500_codec_mode_in, IN t_ab8500_codec_mode ab8500_codec_mode_out); +t_ab8500_codec_error AB8500_CODEC_SelectInput(IN t_ab8500_codec_src ab8500_codec_src); +t_ab8500_codec_error AB8500_CODEC_SelectOutput(IN t_ab8500_codec_dest ab8500_codec_dest); + +/* Burst FIFO configuration */ +t_ab8500_codec_error AB8500_CODEC_ConfigureBurstFifo(IN t_ab8500_codec_burst_fifo_config const *const p_burst_fifo_config); +t_ab8500_codec_error AB8500_CODEC_EnableBurstFifo(void); +t_ab8500_codec_error AB8500_CODEC_DisableBurstFifo(void); + +/* Audio Codec Master mode configuration */ +t_ab8500_codec_error AB8500_CODEC_SetMasterMode(IN t_ab8500_codec_master_mode mode); + +/* APIs to be implemented by user */ +t_ab8500_codec_error AB8500_CODEC_Write(IN t_uint8 register_offset, IN t_uint8 count, IN t_uint8 *p_data); +t_ab8500_codec_error AB8500_CODEC_Read(IN t_uint8 register_offset, IN t_uint8 count, IN t_uint8 *p_dummy_data, IN t_uint8 *p_data); + +/* Volume Management */ +t_ab8500_codec_error AB8500_CODEC_SetSrcVolume(IN t_ab8500_codec_src src_device, IN t_uint8 in_left_volume, IN t_uint8 in_right_volume); +t_ab8500_codec_error AB8500_CODEC_SetDestVolume(IN t_ab8500_codec_dest dest_device, IN t_uint8 out_left_volume, IN t_uint8 out_right_volume); + +/* Power management */ +t_ab8500_codec_error AB8500_CODEC_PowerDown(void); +t_ab8500_codec_error AB8500_CODEC_PowerUp(void); + +/* Interface Management */ +t_ab8500_codec_error AB8500_CODEC_SelectInterface(IN t_ab8500_codec_audio_interface audio_interface); +t_ab8500_codec_error AB8500_CODEC_GetInterface(OUT t_ab8500_codec_audio_interface *p_audio_interface); + +/* Slot Allocation */ +t_ab8500_codec_error AB8500_CODEC_ADSlotAllocation(IN t_ab8500_codec_slot ad_slot, IN t_ab8500_codec_cr31_to_cr46_ad_data_allocation value); +t_ab8500_codec_error AB8500_CODEC_DASlotAllocation(IN t_ab8500_codec_da_channel_number channel_number, IN t_ab8500_codec_cr51_to_cr56_sltoda slot); + +/* Loopback Management */ +t_ab8500_codec_error AB8500_CODEC_SetAnalogLoopback(IN t_uint8 out_left_volume, IN t_uint8 out_right_volume); +t_ab8500_codec_error AB8500_CODEC_RemoveAnalogLoopback(void); + +/* Bypass Management */ +t_ab8500_codec_error AB8500_CODEC_EnableBypassMode(void); +t_ab8500_codec_error AB8500_CODEC_DisableBypassMode(void); + +/* Power Control Management */ +t_ab8500_codec_error AB8500_CODEC_SrcPowerControl(IN t_ab8500_codec_src src_device, t_ab8500_codec_src_state state); +t_ab8500_codec_error AB8500_CODEC_DestPowerControl(IN t_ab8500_codec_dest dest_device, t_ab8500_codec_dest_state state); + +/* Version Management */ +t_ab8500_codec_error AB8500_CODEC_GetVersion(OUT t_version *p_version); + +#if 0 +/* Debug management */ +t_ab8500_codec_error AB8500_CODEC_SetDbgLevel(IN t_dbg_level dbg_level); +t_ab8500_codec_error AB8500_CODEC_GetDbgLevel(OUT t_dbg_level *p_dbg_level); +#endif + +/* +** following is added by $kardad$ +*/ + +/* duplicate copy of enum from msp.h */ +/* for MSPConfiguration.in_clock_freq parameter to select msp clock freq */ +typedef enum { + CODEC_MSP_INPUT_FREQ_1MHZ = 1024, + CODEC_MSP_INPUT_FREQ_2MHZ = 2048, + CODEC_MSP_INPUT_FREQ_3MHZ = 3072, + CODEC_MSP_INPUT_FREQ_4MHZ = 4096, + CODEC_MSP_INPUT_FREQ_5MHZ = 5760, + CODEC_MSP_INPUT_FREQ_6MHZ = 6144, + CODEC_MSP_INPUT_FREQ_8MHZ = 8192, + CODEC_MSP_INPUT_FREQ_11MHZ = 11264, + CODEC_MSP_INPUT_FREQ_12MHZ = 12288, + CODEC_MSP_INPUT_FREQ_16MHZ = 16384, + CODEC_MSP_INPUT_FREQ_22MHZ = 22579, + CODEC_MSP_INPUT_FREQ_24MHZ = 24576, + CODEC_MSP_INPUT_FREQ_48MHZ = 49152 +} codec_msp_in_clock_freq_type; + +/* msp clock source internal/external for srg_clock_sel */ +typedef enum { + CODEC_MSP_APB_CLOCK = 0, + CODEC_MSP_SCK_CLOCK = 2, + CODEC_MSP_SCK_SYNC_CLOCK = 3 +} codec_msp_srg_clock_sel_type; + +/* Sample rate supported by Codec */ + +typedef enum { + CODEC_FREQUENCY_DONT_CHANGE = -100, + CODEC_SAMPLING_FREQ_RESET = -1, + CODEC_SAMPLING_FREQ_MINLIMIT = 7, + CODEC_SAMPLING_FREQ_8KHZ = 8, /*default */ + CODEC_SAMPLING_FREQ_11KHZ = 11, + CODEC_SAMPLING_FREQ_12KHZ = 12, + CODEC_SAMPLING_FREQ_16KHZ = 16, + CODEC_SAMPLING_FREQ_22KHZ = 22, + CODEC_SAMPLING_FREQ_24KHZ = 24, + CODEC_SAMPLING_FREQ_32KHZ = 32, + CODEC_SAMPLING_FREQ_44KHZ = 44, + CODEC_SAMPLING_FREQ_48KHZ = 48, + CODEC_SAMPLING_FREQ_64KHZ = 64, /*the frequencies below this line are not supported in stw5094A */ + CODEC_SAMPLING_FREQ_88KHZ = 88, + CODEC_SAMPLING_FREQ_96KHZ = 96, + CODEC_SAMPLING_FREQ_128KHZ = 128, + CODEC_SAMPLING_FREQ_176KHZ = 176, + CODEC_SAMPLING_FREQ_192KHZ = 192, + CODEC_SAMPLING_FREQ_MAXLIMIT = 193 +} t_codec_sample_frequency; + +#define RESET -1 +#define DEFAULT -100 +/***********************************************************/ +/* +** following stuff is added to compile code without debug print support $kardad$ +*/ + +#define DBGEXIT(cr) +#define DBGEXIT0(cr) +#define DBGEXIT1(cr,ch,p1) +#define DBGEXIT2(cr,ch,p1,p2) +#define DBGEXIT3(cr,ch,p1,p2,p3) +#define DBGEXIT4(cr,ch,p1,p2,p3,p4) +#define DBGEXIT5(cr,ch,p1,p2,p3,p4,p5) +#define DBGEXIT6(cr,ch,p1,p2,p3,p4,p5,p6) + +#define DBGENTER() +#define DBGENTER0() +#define DBGENTER1(ch,p1) +#define DBGENTER2(ch,p1,p2) +#define DBGENTER3(ch,p1,p2,p3) +#define DBGENTER4(ch,p1,p2,p3,p4) +#define DBGENTER5(ch,p1,p2,p3,p4,p5) +#define DBGENTER6(ch,p1,p2,p3,p4,p5,p6) + +#define DBGPRINT(dbg_level,dbg_string) +#define DBGPRINTHEX(dbg_level,dbg_string,uint32) +#define DBGPRINTDEC(dbg_level,dbg_string,uint32) +/***********************************************************/ + +/*--------------------------------------------------------------------- + * PRIVATE APIs + *--------------------------------------------------------------------*/ +PRIVATE t_ab8500_codec_error ab8500_codec_ADSlotAllocationSwitch1(IN t_ab8500_codec_slot ad_slot, IN t_ab8500_codec_cr31_to_cr46_ad_data_allocation value); +PRIVATE t_ab8500_codec_error ab8500_codec_ADSlotAllocationSwitch2(IN t_ab8500_codec_slot ad_slot, IN t_ab8500_codec_cr31_to_cr46_ad_data_allocation value); +PRIVATE t_ab8500_codec_error ab8500_codec_ADSlotAllocationSwitch3(IN t_ab8500_codec_slot ad_slot, IN t_ab8500_codec_cr31_to_cr46_ad_data_allocation value); +PRIVATE t_ab8500_codec_error ab8500_codec_ADSlotAllocationSwitch4(IN t_ab8500_codec_slot ad_slot, IN t_ab8500_codec_cr31_to_cr46_ad_data_allocation value); +PRIVATE t_ab8500_codec_error ab8500_codec_SrcPowerControlSwitch1(IN t_ab8500_codec_src src_device, t_ab8500_codec_src_state state); +PRIVATE t_ab8500_codec_error ab8500_codec_SrcPowerControlSwitch2(IN t_ab8500_codec_src src_device, t_ab8500_codec_src_state state); +PRIVATE t_ab8500_codec_error ab8500_codec_SetModeAndDirectionUpdateCR(void); +PRIVATE t_ab8500_codec_error ab8500_codec_SetSrcVolumeUpdateCR(void); +PRIVATE t_ab8500_codec_error ab8500_codec_SetDestVolumeUpdateCR(void); +PRIVATE t_ab8500_codec_error ab8500_codec_ProgramDirectionIN(void); +PRIVATE t_ab8500_codec_error ab8500_codec_ProgramDirectionOUT(void); +PRIVATE t_ab8500_codec_error ab8500_codec_DestPowerControlUpdateCR(void); + +#ifdef __cplusplus +} /* allow C++ to use these headers*/ +#endif /* __cplusplus*/ +#endif /* _AB8500_CODEC_H_*/ + +/* End of file ab8500_codec.h*/ + diff --git a/arch/arm/mach-ux500/include/mach/ab8500_codec_p.h b/arch/arm/mach-ux500/include/mach/ab8500_codec_p.h new file mode 100755 index 00000000000..415d5f73dc0 --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/ab8500_codec_p.h @@ -0,0 +1,3371 @@ +/*****************************************************************************/ +/** +* © ST-Ericsson, 2009 - All rights reserved +* Reproduction and Communication of this document is strictly prohibited +* unless specifically authorized in writing by ST-Ericsson + * +* \brief Private Header file for AB8500 CODEC +* \author ST-Ericsson + */ +/*****************************************************************************/ + +#ifndef _AB8500_CODECP_H_ +#define _AB8500_CODECP_H_ + +/*---------------------------------------------------------------------------- + * Includes + *---------------------------------------------------------------------------*/ +#include "hcl_defs.h" + +#define AB8500_CODEC_HCL_VERSION_ID 2 +#define AB8500_CODEC_HCL_MAJOR_ID 0 +#define AB8500_CODEC_HCL_MINOR_ID 0 + +#define AB8500_CODEC_MASK_ONE_BIT 0x1UL +#define AB8500_CODEC_MASK_TWO_BITS 0x3UL +#define AB8500_CODEC_MASK_THREE_BITS 0x7UL +#define AB8500_CODEC_MASK_FOUR_BITS 0xFUL +#define AB8500_CODEC_MASK_FIVE_BITS 0x1FUL +#define AB8500_CODEC_MASK_SIX_BITS 0x3FUL +#define AB8500_CODEC_MASK_SEVEN_BITS 0x7FUL +#define AB8500_CODEC_MASK_EIGHT_BITS 0xFFUL + +#define AB8500_CODEC_WRITE_BITS(reg, val, bit_nb, pos) (reg) = ((t_uint8) ((((reg) & (~(bit_nb << pos))) | (((val) & bit_nb) << pos)))) + + +#define AB8500_CODEC_BLOCK 0x0D + +#define AB8500_CODEC_MASK_TWO_MS_BITS 0xC0UL +#define AB8500_CODEC_MASK_SIX_LS_BITS 0x3FUL + +/* Genepi AudioCodec Control Registers */ + +#define AB8500_CODEC_CR0 0x00 +#define AB8500_CODEC_CR1 0x01 +#define AB8500_CODEC_CR2 0x02 +#define AB8500_CODEC_CR3 0x03 +#define AB8500_CODEC_CR4 0x04 +#define AB8500_CODEC_CR5 0x05 +#define AB8500_CODEC_CR6 0x06 +#define AB8500_CODEC_CR7 0x07 +#define AB8500_CODEC_CR8 0x08 +#define AB8500_CODEC_CR9 0x09 +#define AB8500_CODEC_CR10 0x0A +#define AB8500_CODEC_CR11 0x0B +#define AB8500_CODEC_CR12 0x0C +#define AB8500_CODEC_CR13 0x0D +#define AB8500_CODEC_CR14 0x0E +#define AB8500_CODEC_CR15 0x0F +#define AB8500_CODEC_CR16 0x10 +#define AB8500_CODEC_CR17 0x11 +#define AB8500_CODEC_CR18 0x12 +#define AB8500_CODEC_CR19 0x13 +#define AB8500_CODEC_CR20 0x14 +#define AB8500_CODEC_CR21 0x15 +#define AB8500_CODEC_CR22 0x16 +#define AB8500_CODEC_CR23 0x17 +#define AB8500_CODEC_CR24 0x18 +#define AB8500_CODEC_CR25 0x19 +#define AB8500_CODEC_CR26 0x1A +#define AB8500_CODEC_CR27 0x1B +#define AB8500_CODEC_CR28 0x1C +#define AB8500_CODEC_CR29 0x1D +#define AB8500_CODEC_CR30 0x1E +#define AB8500_CODEC_CR31 0x1F +#define AB8500_CODEC_CR32 0x20 +#define AB8500_CODEC_CR33 0x21 +#define AB8500_CODEC_CR34 0x22 +#define AB8500_CODEC_CR35 0x23 +#define AB8500_CODEC_CR36 0x24 +#define AB8500_CODEC_CR37 0x25 +#define AB8500_CODEC_CR38 0x26 +#define AB8500_CODEC_CR39 0x27 +#define AB8500_CODEC_CR40 0x28 +#define AB8500_CODEC_CR41 0x29 +#define AB8500_CODEC_CR42 0x2A +#define AB8500_CODEC_CR43 0x2B +#define AB8500_CODEC_CR44 0x2C +#define AB8500_CODEC_CR45 0x2D +#define AB8500_CODEC_CR46 0x2E +#define AB8500_CODEC_CR47 0x2F +#define AB8500_CODEC_CR48 0x30 +#define AB8500_CODEC_CR49 0x31 +#define AB8500_CODEC_CR50 0x32 +#define AB8500_CODEC_CR51 0x33 +#define AB8500_CODEC_CR52 0x34 +#define AB8500_CODEC_CR53 0x35 +#define AB8500_CODEC_CR54 0x36 +#define AB8500_CODEC_CR55 0x37 +#define AB8500_CODEC_CR56 0x38 +#define AB8500_CODEC_CR57 0x39 +#define AB8500_CODEC_CR58 0x3A +#define AB8500_CODEC_CR59 0x3B +#define AB8500_CODEC_CR60 0x3C +#define AB8500_CODEC_CR61 0x3D +#define AB8500_CODEC_CR62 0x3E +#define AB8500_CODEC_CR63 0x3F +#define AB8500_CODEC_CR64 0x40 +#define AB8500_CODEC_CR65 0x41 +#define AB8500_CODEC_CR66 0x42 +#define AB8500_CODEC_CR67 0x43 +#define AB8500_CODEC_CR68 0x44 +#define AB8500_CODEC_CR69 0x45 +#define AB8500_CODEC_CR70 0x46 +#define AB8500_CODEC_CR71 0x47 +#define AB8500_CODEC_CR72 0x48 +#define AB8500_CODEC_CR73 0x49 +#define AB8500_CODEC_CR74 0x4A +#define AB8500_CODEC_CR75 0x4B +#define AB8500_CODEC_CR76 0x4C +#define AB8500_CODEC_CR77 0x4D +#define AB8500_CODEC_CR78 0x4E +#define AB8500_CODEC_CR79 0x4F +#define AB8500_CODEC_CR80 0x50 +#define AB8500_CODEC_CR81 0x51 +#define AB8500_CODEC_CR82 0x52 +#define AB8500_CODEC_CR83 0x53 +#define AB8500_CODEC_CR84 0x54 +#define AB8500_CODEC_CR85 0x55 +#define AB8500_CODEC_CR86 0x56 +#define AB8500_CODEC_CR87 0x57 +#define AB8500_CODEC_CR88 0x58 +#define AB8500_CODEC_CR89 0x59 +#define AB8500_CODEC_CR90 0x5A +#define AB8500_CODEC_CR91 0x5B +#define AB8500_CODEC_CR92 0x5C +#define AB8500_CODEC_CR93 0x5D +#define AB8500_CODEC_CR94 0x5E +#define AB8500_CODEC_CR95 0x5F +#define AB8500_CODEC_CR96 0x60 +#define AB8500_CODEC_CR97 0x61 +#define AB8500_CODEC_CR98 0x62 +#define AB8500_CODEC_CR99 0x63 +#define AB8500_CODEC_CR100 0x64 +#define AB8500_CODEC_CR101 0x65 +#define AB8500_CODEC_CR102 0x66 +#define AB8500_CODEC_CR103 0x67 +#define AB8500_CODEC_CR104 0x68 +#define AB8500_CODEC_CR105 0x69 +#define AB8500_CODEC_CR106 0x6A +#define AB8500_CODEC_CR107 0x6B +#define AB8500_CODEC_CR108 0x6C +#define AB8500_CODEC_CR109 0x6D + + +/* CR0-CR0x0000 */ +#define AB8500_CODEC_CR0_POWERUP 7 +#define AB8500_CODEC_CR0_ENAANA 3 + +/* CR1-CR0x0001 */ +#define AB8500_CODEC_CR1_SWRESET 7 + +/* CR2-CR0x0002 */ +#define AB8500_CODEC_CR2_ENAD1 7 +#define AB8500_CODEC_CR2_ENAD2 6 +#define AB8500_CODEC_CR2_ENAD3 5 +#define AB8500_CODEC_CR2_ENAD4 4 +#define AB8500_CODEC_CR2_ENAD5 3 +#define AB8500_CODEC_CR2_ENAD6 2 + +/* CR3-CR0x0003 */ +#define AB8500_CODEC_CR3_ENDA1 7 +#define AB8500_CODEC_CR3_ENDA2 6 +#define AB8500_CODEC_CR3_ENDA3 5 +#define AB8500_CODEC_CR3_ENDA4 4 +#define AB8500_CODEC_CR3_ENDA5 3 +#define AB8500_CODEC_CR3_ENDA6 2 + +/* CR4-CR0x0004 */ +#define AB8500_CODEC_CR4_LOWPOWHS 7 +#define AB8500_CODEC_CR4_LOWPOWDACHS 5 +#define AB8500_CODEC_CR4_LOWPOWEAR 4 +#define AB8500_CODEC_CR4_EAR_SEL_CM 2 +#define AB8500_CODEC_CR4_HS_HP_DIS 1 +#define AB8500_CODEC_CR4_EAR_HP_DIS 0 + +/* CR5-CR0x0005 */ +#define AB8500_CODEC_CR5_ENMIC1 7 +#define AB8500_CODEC_CR5_ENMIC2 6 +#define AB8500_CODEC_CR5_ENLINL 5 +#define AB8500_CODEC_CR5_ENLINR 4 +#define AB8500_CODEC_CR5_MUTMIC1 3 +#define AB8500_CODEC_CR5_MUTMIC2 2 +#define AB8500_CODEC_CR5_MUTELINL 1 +#define AB8500_CODEC_CR5_MUTELINR 0 + +/* CR6-CR0x0006 */ +#define AB8500_CODEC_CR6_ENDMIC1 7 +#define AB8500_CODEC_CR6_ENDMIC2 6 +#define AB8500_CODEC_CR6_ENDMIC3 5 +#define AB8500_CODEC_CR6_ENDMIC4 4 +#define AB8500_CODEC_CR6_ENDMIC5 3 +#define AB8500_CODEC_CR6_ENDMIC6 2 + +/* CR7-CR0x0007 */ +#define AB8500_CODEC_CR7_MIC1SEL 7 +#define AB8500_CODEC_CR7_LINRSEL 6 +#define AB8500_CODEC_CR7_ENDRVHSL 5 +#define AB8500_CODEC_CR7_ENDRVHSR 4 +#define AB8500_CODEC_CR7_ENADCMIC 2 +#define AB8500_CODEC_CR7_ENADCLINL 1 +#define AB8500_CODEC_CR7_ENADCLINR 0 + +/* CR8-CR0x0008 */ +#define AB8500_CODEC_CR8_CP_DIS_PLDWN 7 +#define AB8500_CODEC_CR8_ENEAR 6 +#define AB8500_CODEC_CR8_ENHSL 5 +#define AB8500_CODEC_CR8_ENHSR 4 +#define AB8500_CODEC_CR8_ENHFL 3 +#define AB8500_CODEC_CR8_ENHFR 2 +#define AB8500_CODEC_CR8_ENVIBL 1 +#define AB8500_CODEC_CR8_ENVIBR 0 + +/* CR9-CR0x0009 */ +#define AB8500_CODEC_CR9_ENADACEAR 6 +#define AB8500_CODEC_CR9_ENADACHSL 5 +#define AB8500_CODEC_CR9_ENADACHSR 4 +#define AB8500_CODEC_CR9_ENADACHFL 3 +#define AB8500_CODEC_CR9_ENADACHFR 2 +#define AB8500_CODEC_CR9_ENADACVIBL 1 +#define AB8500_CODEC_CR9_ENADACVIBR 0 + +/* CR10-CR0x000A */ +#define AB8500_CODEC_CR10_MUTEEAR 6 +#define AB8500_CODEC_CR10_MUTEHSL 5 +#define AB8500_CODEC_CR10_MUTEHSR 4 +#define AB8500_CODEC_CR10_MUTEHFL 3 +#define AB8500_CODEC_CR10_MUTEHFR 2 +#define AB8500_CODEC_CR10_MUTEVIBL 1 +#define AB8500_CODEC_CR10_MUTEVIBR 0 + +/* CR11-CR0x000B */ +#define AB8500_CODEC_CR11_ENSHORTPWD 7 +#define AB8500_CODEC_CR11_EARSHORTDIS 6 +#define AB8500_CODEC_CR11_HSLSHORTDIS 5 +#define AB8500_CODEC_CR11_HSRSHORTDIS 4 +#define AB8500_CODEC_CR11_HFLSHORTDIS 3 +#define AB8500_CODEC_CR11_HFRSHORTDIS 2 +#define AB8500_CODEC_CR11_VIBLSHORTDIS 1 +#define AB8500_CODEC_CR11_VIBRSHORTDIS 0 + +/* CR12-CR0x000C */ +#define AB8500_CODEC_CR12_ENCPHS 7 +#define AB8500_CODEC_CR12_HSAUTOTIME 4 +#define AB8500_CODEC_CR12_HSAUTOENSEL 1 +#define AB8500_CODEC_CR12_HSAUTOEN 0 + +/* CR13-CR0x000D */ +#define AB8500_CODEC_CR13_ENVDET_HTHRESH 4 +#define AB8500_CODEC_CR13_ENVDET_LTHRESH 0 + +/* CR14-CR0x000E */ +#define AB8500_CODEC_CR14_SMPSLVEN 7 +#define AB8500_CODEC_CR14_ENVDETSMPSEN 6 +#define AB8500_CODEC_CR14_CPLVEN 5 +#define AB8500_CODEC_CR14_ENVDETCPEN 4 +#define AB8500_CODEC_CR14_ENVDET_TIME 0 + +/* CR15-CR0x000F */ +#define AB8500_CODEC_CR15_PWMTOVIBL 7 +#define AB8500_CODEC_CR15_PWMTOVIBR 6 +#define AB8500_CODEC_CR15_PWMLCTRL 5 +#define AB8500_CODEC_CR15_PWMRCTRL 4 +#define AB8500_CODEC_CR15_PWMNLCTRL 3 +#define AB8500_CODEC_CR15_PWMPLCTRL 2 +#define AB8500_CODEC_CR15_PWMNRCTRL 1 +#define AB8500_CODEC_CR15_PWMPRCTRL 0 + +/* CR16-CR0x0010 */ +#define AB8500_CODEC_CR16_PWMNLPOL 7 +#define AB8500_CODEC_CR16_PWMNLDUTYCYCLE 0 + +/* CR17-CR0x0011 */ +#define AB8500_CODEC_CR17_PWMPLPOL 7 +#define AB8500_CODEC_CR17_PWMLPDUTYCYCLE 0 + +/* CR18-CR0x0012 */ +#define AB8500_CODEC_CR18_PWMNRPOL 7 +#define AB8500_CODEC_CR18_PWMNRDUTYCYCLE 0 + +/* CR19-CR0x0013 */ +#define AB8500_CODEC_CR19_PWMPRPOL 7 +#define AB8500_CODEC_CR19_PWMRPDUTYCYCLE 0 + +/* CR20-CR0x0014 */ +#define AB8500_CODEC_CR20_EN_SE_MIC1 7 +#define AB8500_CODEC_CR20_MIC1_GAIN 0 + +/* CR21-CR0x0015 */ +#define AB8500_CODEC_CR21_EN_SE_MIC2 7 +#define AB8500_CODEC_CR21_MIC2_GAIN 0 + +/* CR22-CR0x0016 */ +#define AB8500_CODEC_CR22_HSL_GAIN 5 +#define AB8500_CODEC_CR22_LINL_GAIN 0 + +/* CR23-CR0x0017 */ +#define AB8500_CODEC_CR23_HSR_GAIN 5 +#define AB8500_CODEC_CR23_LINR_GAIN 0 + +/* CR24-CR0x0018 */ +#define AB8500_CODEC_CR24_LINTOHSL_GAIN 0 + +/* CR25-CR0x0019 */ +#define AB8500_CODEC_CR25_LINTOHSR_GAIN 0 + +/* CR26-CR0x001A */ +#define AB8500_CODEC_CR26_AD1NH 7 +#define AB8500_CODEC_CR26_AD2NH 6 +#define AB8500_CODEC_CR26_AD3NH 5 +#define AB8500_CODEC_CR26_AD4NH 4 +#define AB8500_CODEC_CR26_AD1_VOICE 3 +#define AB8500_CODEC_CR26_AD2_VOICE 2 +#define AB8500_CODEC_CR26_AD3_VOICE 1 +#define AB8500_CODEC_CR26_AD4_VOICE 0 + +/* CR27-CR0x001B */ +#define AB8500_CODEC_CR27_EN_MASTGEN 7 +#define AB8500_CODEC_CR27_IF1_BITCLK_OSR 5 +#define AB8500_CODEC_CR27_ENFS_BITCLK1 4 +#define AB8500_CODEC_CR27_IF0_BITCLK_OSR 1 +#define AB8500_CODEC_CR27_ENFS_BITCLK0 0 + +/* CR28-CR0x001C */ +#define AB8500_CODEC_CR28_FSYNC0P 6 +#define AB8500_CODEC_CR28_BITCLK0P 5 +#define AB8500_CODEC_CR28_IF0DEL 4 +#define AB8500_CODEC_CR28_IF0FORMAT 2 +#define AB8500_CODEC_CR28_IF0WL 0 + +/* CR29-CR0x001D */ +#define AB8500_CODEC_CR29_IF0DATOIF1AD 7 +#define AB8500_CODEC_CR29_IF0CKTOIF1CK 6 +#define AB8500_CODEC_CR29_IF1MASTER 5 +#define AB8500_CODEC_CR29_IF1DATOIF0AD 3 +#define AB8500_CODEC_CR29_IF1CKTOIF0CK 2 +#define AB8500_CODEC_CR29_IF0MASTER 1 +#define AB8500_CODEC_CR29_IF0BFIFOEN 0 + +/* CR30-CR0x001E */ +#define AB8500_CODEC_CR30_FSYNC1P 6 +#define AB8500_CODEC_CR30_BITCLK1P 5 +#define AB8500_CODEC_CR30_IF1DEL 4 +#define AB8500_CODEC_CR30_IF1FORMAT 2 +#define AB8500_CODEC_CR30_IF1WL 0 + +/* CR31-CR0x001F */ +#define AB8500_CODEC_CR31_ADOTOSLOT1 4 +#define AB8500_CODEC_CR31_ADOTOSLOT0 0 + +/* CR32-CR0x0020 */ +#define AB8500_CODEC_CR32_ADOTOSLOT3 4 +#define AB8500_CODEC_CR32_ADOTOSLOT2 0 + +/* CR33-CR0x0021 */ +#define AB8500_CODEC_CR33_ADOTOSLOT5 4 +#define AB8500_CODEC_CR33_ADOTOSLOT4 0 + +/* CR34-CR0x0022 */ +#define AB8500_CODEC_CR34_ADOTOSLOT7 4 +#define AB8500_CODEC_CR34_ADOTOSLOT6 0 + +/* CR35-CR0x0023 */ +#define AB8500_CODEC_CR35_ADOTOSLOT9 4 +#define AB8500_CODEC_CR35_ADOTOSLOT8 0 + +/* CR36-CR0x0024 */ +#define AB8500_CODEC_CR36_ADOTOSLOT11 4 +#define AB8500_CODEC_CR36_ADOTOSLOT10 0 + +/* CR37-CR0x0025 */ +#define AB8500_CODEC_CR37_ADOTOSLOT13 4 +#define AB8500_CODEC_CR37_ADOTOSLOT12 0 + +/* CR38-CR0x0026 */ +#define AB8500_CODEC_CR38_ADOTOSLOT15 4 +#define AB8500_CODEC_CR38_ADOTOSLOT14 0 + +/* CR39-CR0x0027 */ +#define AB8500_CODEC_CR39_ADOTOSLOT17 4 +#define AB8500_CODEC_CR39_ADOTOSLOT16 0 + +/* CR40-CR0x0028 */ +#define AB8500_CODEC_CR40_ADOTOSLOT19 4 +#define AB8500_CODEC_CR40_ADOTOSLOT18 0 + +/* CR41-CR0x0029 */ +#define AB8500_CODEC_CR41_ADOTOSLOT21 4 +#define AB8500_CODEC_CR41_ADOTOSLOT20 0 + +/* CR42-CR0x002A */ +#define AB8500_CODEC_CR42_ADOTOSLOT23 4 +#define AB8500_CODEC_CR42_ADOTOSLOT22 0 + +/* CR43-CR0x002B */ +#define AB8500_CODEC_CR43_ADOTOSLOT25 4 +#define AB8500_CODEC_CR43_ADOTOSLOT24 0 + +/* CR44-CR0x002C */ +#define AB8500_CODEC_CR44_ADOTOSLOT27 4 +#define AB8500_CODEC_CR44_ADOTOSLOT26 0 + +/* CR45-CR0x002D */ +#define AB8500_CODEC_CR45_ADOTOSLOT29 4 +#define AB8500_CODEC_CR45_ADOTOSLOT28 0 + +/* CR46-CR0x002E */ +#define AB8500_CODEC_CR46_ADOTOSLOT31 4 +#define AB8500_CODEC_CR46_ADOTOSLOT30 0 + +/* CR47-CR0x002F */ +#define AB8500_CODEC_CR47_HIZ_SL7 7 +#define AB8500_CODEC_CR47_HIZ_SL6 6 +#define AB8500_CODEC_CR47_HIZ_SL5 5 +#define AB8500_CODEC_CR47_HIZ_SL4 4 +#define AB8500_CODEC_CR47_HIZ_SL3 3 +#define AB8500_CODEC_CR47_HIZ_SL2 2 +#define AB8500_CODEC_CR47_HIZ_SL1 1 +#define AB8500_CODEC_CR47_HIZ_SL0 0 + +/* CR48-CR0x0030 */ +#define AB8500_CODEC_CR48_HIZ_SL15 7 +#define AB8500_CODEC_CR48_HIZ_SL14 6 +#define AB8500_CODEC_CR48_HIZ_SL13 5 +#define AB8500_CODEC_CR48_HIZ_SL12 4 +#define AB8500_CODEC_CR48_HIZ_SL11 3 +#define AB8500_CODEC_CR48_HIZ_SL10 2 +#define AB8500_CODEC_CR48_HIZ_SL9 1 +#define AB8500_CODEC_CR48_HIZ_SL8 0 + +/* CR49-CR0x0031 */ +#define AB8500_CODEC_CR49_HIZ_SL23 7 +#define AB8500_CODEC_CR49_HIZ_SL22 6 +#define AB8500_CODEC_CR49_HIZ_SL21 5 +#define AB8500_CODEC_CR49_HIZ_SL20 4 +#define AB8500_CODEC_CR49_HIZ_SL19 3 +#define AB8500_CODEC_CR49_HIZ_SL18 2 +#define AB8500_CODEC_CR49_HIZ_SL17 1 +#define AB8500_CODEC_CR49_HIZ_SL16 0 + +/* CR50-CR0x0032 */ +#define AB8500_CODEC_CR50_HIZ_SL31 7 +#define AB8500_CODEC_CR50_HIZ_SL30 6 +#define AB8500_CODEC_CR50_HIZ_SL29 5 +#define AB8500_CODEC_CR50_HIZ_SL28 4 +#define AB8500_CODEC_CR50_HIZ_SL27 3 +#define AB8500_CODEC_CR50_HIZ_SL26 2 +#define AB8500_CODEC_CR50_HIZ_SL25 1 +#define AB8500_CODEC_CR50_HIZ_SL24 0 + +/* CR51-CR0x0033 */ +#define AB8500_CODEC_CR51_DA12_VOICE 7 +#define AB8500_CODEC_CR51_SLDAI1TOSLADO1 5 +#define AB8500_CODEC_CR51_SLTODA1 0 + +/* CR52-CR0x0034 */ +#define AB8500_CODEC_CR52_SLDAI1TOSLADO2 5 +#define AB8500_CODEC_CR52_SLTODA2 0 + +/* CR53-CR0x0035 */ +#define AB8500_CODEC_CR53_DA34_VOICE 7 +#define AB8500_CODEC_CR53_SLDAI1TOSLADO3 5 +#define AB8500_CODEC_CR53_SLTODA3 0 + +/* CR54-CR0x0036 */ +#define AB8500_CODEC_CR54_SLDAI1TOSLADO4 5 +#define AB8500_CODEC_CR54_SLTODA4 0 + +/* CR55-CR0x0037 */ +#define AB8500_CODEC_CR55_DA56_VOICE 7 +#define AB8500_CODEC_CR55_SLDAI1TOSLADO5 5 +#define AB8500_CODEC_CR55_SLTODA5 0 + +/* CR56-CR0x0038 */ +#define AB8500_CODEC_CR56_SLDAI1TOSLADO6 5 +#define AB8500_CODEC_CR56_SLTODA6 0 + +/* CR57-CR0x0039 */ +#define AB8500_CODEC_CR57_BFIFULL_MSK 6 +#define AB8500_CODEC_CR57_BFIEMPT_MSK 5 +#define AB8500_CODEC_CR57_DACHAN_MSK 4 +#define AB8500_CODEC_CR57_GAIN_MSK 3 +#define AB8500_CODEC_CR57_DSPAD_MSK 2 +#define AB8500_CODEC_CR57_DSPDA_MSK 1 +#define AB8500_CODEC_CR57_STFIR_MSK 0 + +/* CR58-CR0x003A */ +#define AB8500_CODEC_CR58_BFIFULL_EV 6 +#define AB8500_CODEC_CR58_BFIEMPT_EV 5 +#define AB8500_CODEC_CR58_DACHAN_EV 4 +#define AB8500_CODEC_CR58_GAIN_EV 3 +#define AB8500_CODEC_CR58_DSPAD_EV 2 +#define AB8500_CODEC_CR58_DSPDA_EV 1 +#define AB8500_CODEC_CR58_STFIR_EV 0 + +/* CR59-CR0x003B */ +#define AB8500_CODEC_CR59_VSSREADY_MSK 7 +#define AB8500_CODEC_CR59_SHRTVIBL_MSK 6 +#define AB8500_CODEC_CR59_SHRTVIBR_MSK 5 +#define AB8500_CODEC_CR59_SHRTHFL_MSK 4 +#define AB8500_CODEC_CR59_SHRTHFR_MSK 3 +#define AB8500_CODEC_CR59_SHRTHSL_MSK 2 +#define AB8500_CODEC_CR59_SHRTHSR_MSK 1 +#define AB8500_CODEC_CR59_SHRTEAR_MSK 0 + +/* CR60-CR0x003C */ +#define AB8500_CODEC_CR60_VSSREADY_EV 7 +#define AB8500_CODEC_CR60_SHRTVIBL_EV 6 +#define AB8500_CODEC_CR60_SHRTVIBR_EV 5 +#define AB8500_CODEC_CR60_SHRTHFL_EV 4 +#define AB8500_CODEC_CR60_SHRTHFR_EV 3 +#define AB8500_CODEC_CR60_SHRTHSL_EV 2 +#define AB8500_CODEC_CR60_SHRTHSR_EV 1 +#define AB8500_CODEC_CR60_SHRTEAR_EV 0 + +/* CR61-CR0x003D */ +#define AB8500_CODEC_CR61_REVISION 2 +#define AB8500_CODEC_CR61_FADE_SPEED 0 + +/* CR62-CR0x003E */ +#define AB8500_CODEC_CR62_DMIC1SINC3 5 +#define AB8500_CODEC_CR62_DMIC2SINC3 4 +#define AB8500_CODEC_CR62_DMIC3SINC3 3 +#define AB8500_CODEC_CR62_DMIC4SINC3 2 +#define AB8500_CODEC_CR62_DMIC5SINC3 1 +#define AB8500_CODEC_CR62_DMIC6SINC3 0 + +/* CR63-CR0x003F */ +#define AB8500_CODEC_CR63_DATOHSLEN 7 +#define AB8500_CODEC_CR63_DATOHSREN 6 +#define AB8500_CODEC_CR63_AD1SEL 5 +#define AB8500_CODEC_CR63_AD2SEL 4 +#define AB8500_CODEC_CR63_AD3SEL 3 +#define AB8500_CODEC_CR63_AD5SEL 2 +#define AB8500_CODEC_CR63_AD6SEL 1 +#define AB8500_CODEC_CR63_ANCSEL 0 + +/* CR64-CR0x0040 */ +#define AB8500_CODEC_CR64_DATOHFREN 7 +#define AB8500_CODEC_CR64_DATOHFLEN 6 +#define AB8500_CODEC_CR64_HFRSEL 5 +#define AB8500_CODEC_CR64_HFLSEL 4 +#define AB8500_CODEC_CR64_STFIR1SEL 2 +#define AB8500_CODEC_CR64_STFIR2SEL 0 + +/* CR65-CR0x0041 */ +#define AB8500_CODEC_CR65_FADEDIS_AD1 6 +#define AB8500_CODEC_CR65_AD1GAIN 0 + +/* CR66-CR0x0042 */ +#define AB8500_CODEC_CR66_FADEDIS_AD2 6 +#define AB8500_CODEC_CR66_AD2GAIN 0 + +/* CR67-CR0x0043 */ +#define AB8500_CODEC_CR67_FADEDIS_AD3 6 +#define AB8500_CODEC_CR67_AD3GAIN 0 + +/* CR68-CR0x0044 */ +#define AB8500_CODEC_CR68_FADEDIS_AD4 6 +#define AB8500_CODEC_CR68_AD4GAIN 0 + +/* CR69-CR0x0045 */ +#define AB8500_CODEC_CR69_FADEDIS_AD5 6 +#define AB8500_CODEC_CR69_AD5GAIN 0 + +/* CR70-CR0x0046 */ +#define AB8500_CODEC_CR70_FADEDIS_AD6 6 +#define AB8500_CODEC_CR70_AD6GAIN 0 + +/* CR71-CR0x0047 */ +#define AB8500_CODEC_CR71_FADEDIS_DA1 6 +#define AB8500_CODEC_CR71_DA1GAIN 0 + +/* CR72-CR0x0048 */ +#define AB8500_CODEC_CR72_FADEDIS_DA2 6 +#define AB8500_CODEC_CR72_DA2GAIN 0 + +/* CR73-CR0x0049 */ +#define AB8500_CODEC_CR73_FADEDIS_DA3 6 +#define AB8500_CODEC_CR73_DA3GAIN 0 + +/* CR74-CR0x004A */ +#define AB8500_CODEC_CR74_FADEDIS_DA4 6 +#define AB8500_CODEC_CR74_DA4GAIN 0 + +/* CR75-CR0x004B */ +#define AB8500_CODEC_CR75_FADEDIS_DA5 6 +#define AB8500_CODEC_CR75_DA5GAIN 0 + +/* CR76-CR0x004C */ +#define AB8500_CODEC_CR76_FADEDIS_DA6 6 +#define AB8500_CODEC_CR76_DA6GAIN 0 + +/* CR77-CR0x004D */ +#define AB8500_CODEC_CR77_FADEDIS_AD1L 6 +#define AB8500_CODEC_CR77_AD1LBGAIN 0 + +/* CR78-CR0x004E */ +#define AB8500_CODEC_CR78_FADEDIS_AD2L 6 +#define AB8500_CODEC_CR78_AD2LBGAIN 0 + +/* CR79-CR0x004F */ +#define AB8500_CODEC_CR79_HSSINC1 7 +#define AB8500_CODEC_CR79_FADEDIS_HSL 4 +#define AB8500_CODEC_CR79_HSLDGAIN 0 + +/* CR80-CR0x0050 */ +#define AB8500_CODEC_CR80_FADEDIS_HSR 4 +#define AB8500_CODEC_CR80_HSRDGAIN 0 + +/* CR81-CR0x0051 */ +#define AB8500_CODEC_CR81_STFIR1GAIN 0 + +/* CR82-CR0x0052 */ +#define AB8500_CODEC_CR82_STFIR2GAIN 0 + +/* CR83-CR0x0053 */ +#define AB8500_CODEC_CR83_ENANC 2 +#define AB8500_CODEC_CR83_ANCIIRINIT 1 +#define AB8500_CODEC_CR83_ANCFIRUPDATE 0 + +/* CR84-CR0x0054 */ +#define AB8500_CODEC_CR84_ANCINSHIFT 0 + +/* CR85-CR0x0055 */ +#define AB8500_CODEC_CR85_ANCFIROUTSHIFT 0 + +/* CR86-CR0x0056 */ +#define AB8500_CODEC_CR86_ANCSHIFTOUT 0 + +/* CR87-CR0x0057 */ +#define AB8500_CODEC_CR87_ANCFIRCOEFF_MSB 0 + +/* CR88-CR0x0058 */ +#define AB8500_CODEC_CR88_ANCFIRCOEFF_LSB 0 + +/* CR89-CR0x0059 */ +#define AB8500_CODEC_CR89_ANCIIRCOEFF_MSB 0 + +/* CR90-CR0x005A */ +#define AB8500_CODEC_CR90_ANCIIRCOEFF_LSB 0 + +/* CR91-CR0x005B */ +#define AB8500_CODEC_CR91_ANCWARPDEL_MSB 0 + +/* CR92-CR0x005C */ +#define AB8500_CODEC_CR92_ANCWARPDEL_LSB 0 + +/* CR93-CR0x005D */ +#define AB8500_CODEC_CR93_ANCFIRPEAK_MSB 0 + +/* CR94-CR0x005E */ +#define AB8500_CODEC_CR94_ANCFIRPEAK_LSB 0 + +/* CR95-CR0x005F */ +#define AB8500_CODEC_CR95_ANCIIRPEAK_MSB 0 + +/* CR96-CR0x0060 */ +#define AB8500_CODEC_CR96_ANCIIRPEAK_LSB 0 + +/* CR97-CR0x0061 */ +#define AB8500_CODEC_CR97_STFIR_SET 7 +#define AB8500_CODEC_CR97_STFIR_ADDR 0 + +/* CR98-CR0x0062 */ +#define AB8500_CODEC_CR98_STFIR_COEFF_MSB 0 + +/* CR99-CR0x0063 */ +#define AB8500_CODEC_CR99_STFIR_COEFF_LSB 0 + +/* CR100-CR0x0064 */ +#define AB8500_CODEC_CR100_ENSTFIRS 2 +#define AB8500_CODEC_CR100_STFIRSTOIF1 1 +#define AB8500_CODEC_CR100_STFIR_BUSY 0 + +/* CR101-CR0x0065 */ +#define AB8500_CODEC_CR101_PARLHF 7 +#define AB8500_CODEC_CR101_PARLVIB 6 +#define AB8500_CODEC_CR101_CLASSDVIBLSWAPEN 3 +#define AB8500_CODEC_CR101_CLASSDVIBRSWAPEN 2 +#define AB8500_CODEC_CR101_CLASSDHFLSWAPEN 1 +#define AB8500_CODEC_CR101_CLASSDHFRSWAPEN 0 + +/* CR102-CR0x0066 */ +#define AB8500_CODEC_CR102_CLASSD_FIRBYP 4 +#define AB8500_CODEC_CR102_CLASSD_HIGHVOLEN 0 + +/* CR103-CR0x0067 */ +#define AB8500_CODEC_CR103_CLASSD_DITHERHPGAIN 4 +#define AB8500_CODEC_CR103_CLASSD_DITHERWGAIN 0 + +/* CR104-CR0x0068 */ +#define AB8500_CODEC_CR104_BFIFOINT 0 + +/* CR105-CR0x0069 */ +#define AB8500_CODEC_CR105_BFIFOTX 0 + +/* CR106-CR0x006A */ +#define AB8500_CODEC_CR106_BFIFOFSEXT 4 +#define AB8500_CODEC_CR106_BFIFOMSK 2 +#define AB8500_CODEC_CR106_BFIFOMSTR 1 +#define AB8500_CODEC_CR106_BFIFOSTRT 0 + +/* CR107-CR0x006B */ +#define AB8500_CODEC_CR107_BFIFOSAMPNR 0 + +/* CR108-CR0x006C */ +#define AB8500_CODEC_CR108_BFIFOWAKEUP 0 + +/* CR109-CR0x006D */ +#define AB8500_CODEC_CR109_BFIFOSAMPLES 0 + + + +/* For SetVolume API*/ +#define AB8500_CODEC_MAX_VOLUME 100 + +/* Analog MIC1 & MIC2 */ +#define AB8500_CODEC_MIC_VOLUME_MAX 31 +#define AB8500_CODEC_MIC_VOLUME_MEDIUM 15 +#define AB8500_CODEC_MIC_VOLUME_MIN 0 + +/* Line-in */ +#define AB8500_CODEC_LINEIN_VOLUME_MAX 31 +#define AB8500_CODEC_LINEIN_VOLUME_MEDIUM 15 +#define AB8500_CODEC_LINEIN_VOLUME_MIN 0 + +/* HeadSet */ +#define AB8500_CODEC_HEADSET_VOLUME_MAX 0 +#define AB8500_CODEC_HEADSET_VOLUME_MEDIUM 3 +#define AB8500_CODEC_HEADSET_VOLUME_MIN 7 + +/* HeadSet Digital */ +#define AB8500_CODEC_HEADSET_D_VOLUME_MAX 0 +#define AB8500_CODEC_HEADSET_D_VOLUME_MEDIUM 7 +#define AB8500_CODEC_HEADSET_D_VOLUME_MIN 15 + +/* Digital AD Path */ +#define AB8500_CODEC_AD_D_VOLUME_MAX 0 +#define AB8500_CODEC_AD_D_VOLUME_MEDIUM 31 +#define AB8500_CODEC_AD_D_VOLUME_MIN 63 + +/* Digital DA Path */ +#define AB8500_CODEC_DA_D_VOLUME_MAX 0 +#define AB8500_CODEC_DA_D_VOLUME_MEDIUM 31 +#define AB8500_CODEC_DA_D_VOLUME_MIN 63 + +/* EarPiece Digital */ +#define AB8500_CODEC_EARPIECE_D_VOLUME_MAX 0 +#define AB8500_CODEC_EARPIECE_D_VOLUME_MEDIUM 7 +#define AB8500_CODEC_EARPIECE_D_VOLUME_MIN 15 + +/* AD1 loopback to HFL & HFR Digital */ +#define AB8500_CODEC_AD_LB_TO_HF_L_R_VOLUME_MAX 0 +#define AB8500_CODEC_AD_LB_TO_HF_L_R_VOLUME_MEDIUM 31 +#define AB8500_CODEC_AD_LB_TO_HF_L_R_VOLUME_MIN 63 + +/* Line-in to HSL & HSR */ +#define AB8500_CODEC_LINEIN_TO_HS_L_R_VOLUME_MAX 0 +#define AB8500_CODEC_LINEIN_TO_HS_L_R_VOLUME_MEDIUM 9 +#define AB8500_CODEC_LINEIN_TO_HS_L_R_VOLUME_MIN 18 +#define AB8500_CODEC_LINEIN_TO_HS_L_R_LOOP_OPEN 19 + +/* Vibrator */ +#define AB8500_CODEC_VIBRATOR_VOLUME_MAX 100 +#define AB8500_CODEC_VIBRATOR_VOLUME_MEDIUM 50 +#define AB8500_CODEC_VIBRATOR_VOLUME_MIN 0 + + +/* CR0 - 7 */ +typedef enum +{ + AB8500_CODEC_CR0_POWERUP_OFF, + AB8500_CODEC_CR0_POWERUP_ON +} t_ab8500_codec_cr0_powerup; + +/* CR0 - 3 */ +typedef enum +{ + AB8500_CODEC_CR0_ENAANA_OFF, + AB8500_CODEC_CR0_ENAANA_ON +} t_ab8500_codec_cr0_enaana; + + +/* CR1 - 7 */ +typedef enum +{ + AB8500_CODEC_CR1_SWRESET_DISABLED, + AB8500_CODEC_CR1_SWRESET_ENABLED +} t_ab8500_codec_cr1_swreset; + + +/* CR2 - 7 */ +typedef enum +{ + AB8500_CODEC_CR2_ENAD1_DISABLED, + AB8500_CODEC_CR2_ENAD1_ENABLED +} t_ab8500_codec_cr2_enad1; + +/* CR2 - 6 */ +typedef enum +{ + AB8500_CODEC_CR2_ENAD2_DISABLED, + AB8500_CODEC_CR2_ENAD2_ENABLED +} t_ab8500_codec_cr2_enad2; + +/* CR2 - 5 */ +typedef enum +{ + AB8500_CODEC_CR2_ENAD3_DISABLED, + AB8500_CODEC_CR2_ENAD3_ENABLED +} t_ab8500_codec_cr2_enad3; + +/* CR2 - 4 */ +typedef enum +{ + AB8500_CODEC_CR2_ENAD4_DISABLED, + AB8500_CODEC_CR2_ENAD4_ENABLED +} t_ab8500_codec_cr2_enad4; + +/* CR2 - 3 */ +typedef enum +{ + AB8500_CODEC_CR2_ENAD5_DISABLED, + AB8500_CODEC_CR2_ENAD5_ENABLED +} t_ab8500_codec_cr2_enad5; + +/* CR2 - 2 */ +typedef enum +{ + AB8500_CODEC_CR2_ENAD6_DISABLED, + AB8500_CODEC_CR2_ENAD6_ENABLED +} t_ab8500_codec_cr2_enad6; + + +/* CR3 - 7 */ +typedef enum +{ + AB8500_CODEC_CR3_ENDA1_DISABLED, + AB8500_CODEC_CR3_ENDA1_ENABLED +} t_ab8500_codec_cr3_enda1; + +/* CR3 - 6 */ +typedef enum +{ + AB8500_CODEC_CR3_ENDA2_DISABLED, + AB8500_CODEC_CR3_ENDA2_ENABLED +} t_ab8500_codec_cr3_enda2; + +/* CR3 - 5 */ +typedef enum +{ + AB8500_CODEC_CR3_ENDA3_DISABLED, + AB8500_CODEC_CR3_ENDA3_ENABLED +} t_ab8500_codec_cr3_enda3; + +/* CR3 - 4 */ +typedef enum +{ + AB8500_CODEC_CR3_ENDA4_DISABLED, + AB8500_CODEC_CR3_ENDA4_ENABLED +} t_ab8500_codec_cr3_enda4; + +/* CR3 - 3 */ +typedef enum +{ + AB8500_CODEC_CR3_ENDA5_DISABLED, + AB8500_CODEC_CR3_ENDA5_ENABLED +} t_ab8500_codec_cr3_enda5; + +/* CR3 - 2 */ +typedef enum +{ + AB8500_CODEC_CR3_ENDA6_DISABLED, + AB8500_CODEC_CR3_ENDA6_ENABLED +} t_ab8500_codec_cr3_enda6; + + +/* CR4 - 7 */ +typedef enum +{ + AB8500_CODEC_CR4_LOWPOWHS_NORMAL, + AB8500_CODEC_CR4_LOWPOWHS_LP +} t_ab8500_codec_cr4_lowpowhs; + +/* CR4 - 6:5 */ +typedef enum +{ + AB8500_CODEC_CR4_LOWPOWDACHS_NORMAL, + AB8500_CODEC_CR4_LOWPOWDACHS_DRIVERS_LP, + AB8500_CODEC_CR4_LOWPOWDACHS_LP, + AB8500_CODEC_CR4_LOWPOWDACHS_BOTH_LP +} t_ab8500_codec_cr4_lowpowdachs; + +/* CR4 - 4 */ +typedef enum +{ + AB8500_CODEC_CR4_LOWPOWEAR_NORMAL, + AB8500_CODEC_CR4_LOWPOWEAR_LP +} t_ab8500_codec_cr4_lowpowear; + +/* CR4 - 3:2 */ +typedef enum +{ + AB8500_CODEC_CR4_EAR_SEL_CM_0_95V, + AB8500_CODEC_CR4_EAR_SEL_CM_1_1V, + AB8500_CODEC_CR4_EAR_SEL_CM_1_27V, + AB8500_CODEC_CR4_EAR_SEL_CM_1_58V +} t_ab8500_codec_cr4_ear_sel_cm; + +/* CR4 - 1 */ +typedef enum +{ + AB8500_CODEC_CR4_HS_HP_DIS_FILTER_ENABLED, + AB8500_CODEC_CR4_HS_HP_DIS_FILTER_DISABLED +} t_ab8500_codec_cr4_hs_hp_dis; + +/* CR4 - 0 */ +typedef enum +{ + AB8500_CODEC_CR4_EAR_HP_DIS_FILTER_ENABLED, + AB8500_CODEC_CR4_EAR_HP_DIS_FILTER_DISABLED +} t_ab8500_codec_cr4_ear_hp_dis; + + +/* CR5 - 7 */ +typedef enum +{ + AB8500_CODEC_CR5_ENMIC1_DISABLED, + AB8500_CODEC_CR5_ENMIC1_ENABLED +} t_ab8500_codec_cr5_enmic1; + +/* CR5 - 6 */ +typedef enum +{ + AB8500_CODEC_CR5_ENMIC2_DISABLED, + AB8500_CODEC_CR5_ENMIC2_ENABLED +} t_ab8500_codec_cr5_enmic2; + +/* CR5 - 5 */ +typedef enum +{ + AB8500_CODEC_CR5_ENLINL_DISABLED, + AB8500_CODEC_CR5_ENLINL_ENABLED +} t_ab8500_codec_cr5_enlinl; + +/* CR5 - 4 */ +typedef enum +{ + AB8500_CODEC_CR5_ENLINR_DISABLED, + AB8500_CODEC_CR5_ENLINR_ENABLED +} t_ab8500_codec_cr5_enlinr; + +/* CR5 - 3 */ +typedef enum +{ + AB8500_CODEC_CR5_MUTMIC1_DISABLED, + AB8500_CODEC_CR5_MUTMIC1_ENABLED +} t_ab8500_codec_cr5_mutmic1; + +/* CR5 - 2 */ +typedef enum +{ + AB8500_CODEC_CR5_MUTMIC2_DISABLED, + AB8500_CODEC_CR5_MUTMIC2_ENABLED +} t_ab8500_codec_cr5_mutmic2; + +/* CR5 - 1 */ +typedef enum +{ + AB8500_CODEC_CR5_MUTLINL_DISABLED, + AB8500_CODEC_CR5_MUTLINL_ENABLED +} t_ab8500_codec_cr5_mutlinl; + +/* CR5 - 0 */ +typedef enum +{ + AB8500_CODEC_CR5_MUTLINR_DISABLED, + AB8500_CODEC_CR5_MUTLINR_ENABLED +} t_ab8500_codec_cr5_mutlinr; + + +/* CR6 - 7 */ +typedef enum +{ + AB8500_CODEC_CR6_ENDMIC1_DISABLED, + AB8500_CODEC_CR6_ENDMIC1_ENABLED +} t_ab8500_codec_cr6_endmic1; + +/* CR6 - 6 */ +typedef enum +{ + AB8500_CODEC_CR6_ENDMIC2_DISABLED, + AB8500_CODEC_CR6_ENDMIC2_ENABLED +} t_ab8500_codec_cr6_endmic2; + +/* CR6 - 5 */ +typedef enum +{ + AB8500_CODEC_CR6_ENDMIC3_DISABLED, + AB8500_CODEC_CR6_ENDMIC3_ENABLED +} t_ab8500_codec_cr6_endmic3; + +/* CR6 - 4 */ +typedef enum +{ + AB8500_CODEC_CR6_ENDMIC4_DISABLED, + AB8500_CODEC_CR6_ENDMIC4_ENABLED +} t_ab8500_codec_cr6_endmic4; + +/* CR6 - 3 */ +typedef enum +{ + AB8500_CODEC_CR6_ENDMIC5_DISABLED, + AB8500_CODEC_CR6_ENDMIC5_ENABLED +} t_ab8500_codec_cr6_endmic5; + +/* CR6 - 2 */ +typedef enum +{ + AB8500_CODEC_CR6_ENDMIC6_DISABLED, + AB8500_CODEC_CR6_ENDMIC6_ENABLED +} t_ab8500_codec_cr6_endmic6; + + +/* CR7 - 7 */ +typedef enum +{ + AB8500_CODEC_CR7_MIC1SEL_MIC1A, + AB8500_CODEC_CR7_MIC1SEL_MIC1B +} t_ab8500_codec_cr7_mic1sel; + +/* CR7 - 6 */ +typedef enum +{ + AB8500_CODEC_CR7_LINRSEL_MIC2, + AB8500_CODEC_CR7_LINRSEL_LINR +} t_ab8500_codec_cr7_linrsel; + +/* CR7 - 5 */ +typedef enum +{ + AB8500_CODEC_CR7_ENDRVHSL_DISABLED, + AB8500_CODEC_CR7_ENDRVHSL_ENABLED +} t_ab8500_codec_cr7_endrvhsl; + +/* CR7 - 4 */ +typedef enum +{ + AB8500_CODEC_CR7_ENDRVHSR_DISABLED, + AB8500_CODEC_CR7_ENDRVHSR_ENABLED +} t_ab8500_codec_cr7_endrvhsr; + +/* CR7 - 2 */ +typedef enum +{ + AB8500_CODEC_CR7_ENADCMIC_DISABLED, + AB8500_CODEC_CR7_ENADCMIC_ENABLED +} t_ab8500_codec_cr7_enadcmic; + +/* CR7 - 1 */ +typedef enum +{ + AB8500_CODEC_CR7_ENADCLINL_DISABLED, + AB8500_CODEC_CR7_ENADCLINL_ENABLED +} t_ab8500_codec_cr7_enadclinl; + +/* CR7 - 0 */ +typedef enum +{ + AB8500_CODEC_CR7_ENADCLINR_DISABLED, + AB8500_CODEC_CR7_ENADCLINR_ENABLED +} t_ab8500_codec_cr7_enadclinr; + + +/* CR8 - 7 */ +typedef enum +{ + AB8500_CODEC_CR8_CP_DIS_PLDWN_ENABLED, + AB8500_CODEC_CR8_CP_DIS_PLDWN_DISABLED +} t_ab8500_codec_cr8_cp_dis_pldwn; + +/* CR8 - 6 */ +typedef enum +{ + AB8500_CODEC_CR8_ENEAR_DISABLED, + AB8500_CODEC_CR8_ENEAR_ENABLED +} t_ab8500_codec_cr8_enear; + +/* CR8 - 5 */ +typedef enum +{ + AB8500_CODEC_CR8_ENHSL_DISABLED, + AB8500_CODEC_CR8_ENHSL_ENABLED +} t_ab8500_codec_cr8_enhsl; + +/* CR8 - 4 */ +typedef enum +{ + AB8500_CODEC_CR8_ENHSR_DISABLED, + AB8500_CODEC_CR8_ENHSR_ENABLED +} t_ab8500_codec_cr8_enhsr; + +/* CR8 - 3 */ +typedef enum +{ + AB8500_CODEC_CR8_ENHFL_DISABLED, + AB8500_CODEC_CR8_ENHFL_ENABLED +} t_ab8500_codec_cr8_enhfl; + +/* CR8 - 2 */ +typedef enum +{ + AB8500_CODEC_CR8_ENHFR_DISABLED, + AB8500_CODEC_CR8_ENHFR_ENABLED +} t_ab8500_codec_cr8_enhfr; + +/* CR8 - 1 */ +typedef enum +{ + AB8500_CODEC_CR8_ENVIBL_DISABLED, + AB8500_CODEC_CR8_ENVIBL_ENABLED +} t_ab8500_codec_cr8_envibl; + +/* CR8 - 0 */ +typedef enum +{ + AB8500_CODEC_CR8_ENVIBR_DISABLED, + AB8500_CODEC_CR8_ENVIBR_ENABLED +} t_ab8500_codec_cr8_envibr; + + +/* CR9 - 6 */ +typedef enum +{ + AB8500_CODEC_CR9_ENDACEAR_DISABLED, + AB8500_CODEC_CR9_ENDACEAR_ENABLED +} t_ab8500_codec_cr9_endacear; + +/* CR9 - 5 */ +typedef enum +{ + AB8500_CODEC_CR9_ENDACHSL_DISABLED, + AB8500_CODEC_CR9_ENDACHSL_ENABLED +} t_ab8500_codec_cr9_endachsl; + +/* CR9 - 4 */ +typedef enum +{ + AB8500_CODEC_CR9_ENDACHSR_DISABLED, + AB8500_CODEC_CR9_ENDACHSR_ENABLED +} t_ab8500_codec_cr9_endachsr; + +/* CR9 - 3 */ +typedef enum +{ + AB8500_CODEC_CR9_ENDACHFL_DISABLED, + AB8500_CODEC_CR9_ENDACHFL_ENABLED +} t_ab8500_codec_cr9_endachfl; + +/* CR9 - 2 */ +typedef enum +{ + AB8500_CODEC_CR9_ENDACHFR_DISABLED, + AB8500_CODEC_CR9_ENDACHFR_ENABLED +} t_ab8500_codec_cr9_endachfr; + +/* CR9 - 1 */ +typedef enum +{ + AB8500_CODEC_CR9_ENDACVIBL_DISABLED, + AB8500_CODEC_CR9_ENDACVIBL_ENABLED +} t_ab8500_codec_cr9_endacvibl; + +/* CR9 - 0 */ +typedef enum +{ + AB8500_CODEC_CR9_ENDACVIBR_DISABLED, + AB8500_CODEC_CR9_ENDACVIBR_ENABLED +} t_ab8500_codec_cr9_endacvibr; + + +/* CR10 - 6 */ +typedef enum +{ + AB8500_CODEC_CR10_MUTEEAR_DISABLED, + AB8500_CODEC_CR10_MUTEEAR_ENABLED +} t_ab8500_codec_cr10_muteear; + +/* CR10 - 5 */ +typedef enum +{ + AB8500_CODEC_CR10_MUTEHSL_DISABLED, + AB8500_CODEC_CR10_MUTEHSL_ENABLED +} t_ab8500_codec_cr10_mutehsl; + +/* CR10 - 4 */ +typedef enum +{ + AB8500_CODEC_CR10_MUTEHSR_DISABLED, + AB8500_CODEC_CR10_MUTEHSR_ENABLED +} t_ab8500_codec_cr10_mutehsr; + +/* CR10 - 3 */ +typedef enum +{ + AB8500_CODEC_CR10_MUTEHFL_DISABLED, + AB8500_CODEC_CR10_MUTEHFL_ENABLED +} t_ab8500_codec_cr10_mutehfl; + +/* CR10 - 2 */ +typedef enum +{ + AB8500_CODEC_CR10_MUTEHFR_DISABLED, + AB8500_CODEC_CR10_MUTEHFR_ENABLED +} t_ab8500_codec_cr10_mutehfr; + +/* CR10 - 1 */ +typedef enum +{ + AB8500_CODEC_CR10_MUTEVIBL_DISABLED, + AB8500_CODEC_CR10_MUTEVIBL_ENABLED +} t_ab8500_codec_cr10_mutevibl; + +/* CR10 - 0 */ +typedef enum +{ + AB8500_CODEC_CR10_MUTEVIBR_DISABLED, + AB8500_CODEC_CR10_MUTEVIBR_ENABLED +} t_ab8500_codec_cr10_mutevibr; + + +/* CR11 - 7 */ +typedef enum +{ + AB8500_CODEC_CR11_EARSHORTPWD_DISABLED, + AB8500_CODEC_CR11_EARSHORTPWD_ENABLED +} t_ab8500_codec_cr11_earshortpwd; + +/* CR11 - 6 */ +typedef enum +{ + AB8500_CODEC_CR11_EARSHORTDIS_ENABLED, + AB8500_CODEC_CR11_EARSHORTDIS_DISABLED +} t_ab8500_codec_cr11_earshortdis; + +/* CR11 - 5 */ +typedef enum +{ + AB8500_CODEC_CR11_HSLSHORTDIS_ENABLED, + AB8500_CODEC_CR11_HSLSHORTDIS_DISABLED +} t_ab8500_codec_cr11_hslshortdis; + +/* CR11 - 4 */ +typedef enum +{ + AB8500_CODEC_CR11_HSRSHORTDIS_ENABLED, + AB8500_CODEC_CR11_HSRSHORTDIS_DISABLED +} t_ab8500_codec_cr11_hsrshortdis; + +/* CR11 - 3 */ +typedef enum +{ + AB8500_CODEC_CR11_HFLSHORTDIS_ENABLED, + AB8500_CODEC_CR11_HFLSHORTDIS_DISABLED +} t_ab8500_codec_cr11_hflshortdis; + +/* CR11 - 2 */ +typedef enum +{ + AB8500_CODEC_CR11_HFRSHORTDIS_ENABLED, + AB8500_CODEC_CR11_HFRSHORTDIS_DISABLED +} t_ab8500_codec_cr11_hfrshortdis; + +/* CR11 - 1 */ +typedef enum +{ + AB8500_CODEC_CR11_VIBLSHORTDIS_ENABLED, + AB8500_CODEC_CR11_VIBLSHORTDIS_DISABLED +} t_ab8500_codec_cr11_viblshortdis; + +/* CR11 - 0 */ +typedef enum +{ + AB8500_CODEC_CR11_VIBRSHORTDIS_ENABLED, + AB8500_CODEC_CR11_VIBRSHORTDIS_DISABLED +} t_ab8500_codec_cr11_vibrshortdis; + + +/* CR12 - 7 */ +typedef enum +{ + AB8500_CODEC_CR12_ENCPHS_DISABLED, + AB8500_CODEC_CR12_ENCPHS_ENABLED +} t_ab8500_codec_cr12_encphs; + +/* CR12 - 6:4 */ +typedef enum +{ + AB8500_CODEC_CR12_HSAUTOTIME_6_6USEC, + AB8500_CODEC_CR12_HSAUTOTIME_13_3USEC, + AB8500_CODEC_CR12_HSAUTOTIME_26_6USEC, + AB8500_CODEC_CR12_HSAUTOTIME_53_2USEC, + AB8500_CODEC_CR12_HSAUTOTIME_106_4USEC, + AB8500_CODEC_CR12_HSAUTOTIME_212_8USEC, + AB8500_CODEC_CR12_HSAUTOTIME_425_6USEC, + AB8500_CODEC_CR12_HSAUTOTIME_851_2USEC, +} t_ab8500_codec_cr12_hsautotime; + +/* CR12 - 1 */ +typedef enum +{ + AB8500_CODEC_CR12_HSAUTOENSEL_DISABLED, + AB8500_CODEC_CR12_HSAUTOENSEL_ENABLED +} t_ab8500_codec_cr12_hsautoensel; + +/* CR12 - 0 */ +typedef enum +{ + AB8500_CODEC_CR12_HSAUTOEN_DISABLED, + AB8500_CODEC_CR12_HSAUTOEN_ENABLED +} t_ab8500_codec_cr12_hsautoen; + + +/* CR13 - 7:4 */ +typedef enum +{ + AB8500_CODEC_CR13_ENVDET_HTHRESH_25, + AB8500_CODEC_CR13_ENVDET_HTHRESH_50, + AB8500_CODEC_CR13_ENVDET_HTHRESH_100, + AB8500_CODEC_CR13_ENVDET_HTHRESH_150, + AB8500_CODEC_CR13_ENVDET_HTHRESH_200, + AB8500_CODEC_CR13_ENVDET_HTHRESH_250, + AB8500_CODEC_CR13_ENVDET_HTHRESH_300, + AB8500_CODEC_CR13_ENVDET_HTHRESH_350, + AB8500_CODEC_CR13_ENVDET_HTHRESH_400, + AB8500_CODEC_CR13_ENVDET_HTHRESH_450, + AB8500_CODEC_CR13_ENVDET_HTHRESH_500, + AB8500_CODEC_CR13_ENVDET_HTHRESH_550, + AB8500_CODEC_CR13_ENVDET_HTHRESH_600, + AB8500_CODEC_CR13_ENVDET_HTHRESH_650, + AB8500_CODEC_CR13_ENVDET_HTHRESH_700, + AB8500_CODEC_CR13_ENVDET_HTHRESH_750 +} t_ab8500_codec_cr13_envdet_hthresh; + +/* CR13 - 3:0 */ +typedef enum +{ + AB8500_CODEC_CR13_ENVDET_LTHRESH_25, + AB8500_CODEC_CR13_ENVDET_LTHRESH_50, + AB8500_CODEC_CR13_ENVDET_LTHRESH_100, + AB8500_CODEC_CR13_ENVDET_LTHRESH_150, + AB8500_CODEC_CR13_ENVDET_LTHRESH_200, + AB8500_CODEC_CR13_ENVDET_LTHRESH_250, + AB8500_CODEC_CR13_ENVDET_LTHRESH_300, + AB8500_CODEC_CR13_ENVDET_LTHRESH_350, + AB8500_CODEC_CR13_ENVDET_LTHRESH_400, + AB8500_CODEC_CR13_ENVDET_LTHRESH_450, + AB8500_CODEC_CR13_ENVDET_LTHRESH_500, + AB8500_CODEC_CR13_ENVDET_LTHRESH_550, + AB8500_CODEC_CR13_ENVDET_LTHRESH_600, + AB8500_CODEC_CR13_ENVDET_LTHRESH_650, + AB8500_CODEC_CR13_ENVDET_LTHRESH_700, + AB8500_CODEC_CR13_ENVDET_LTHRESH_750 +} t_ab8500_codec_cr13_envdet_lthresh; + + +/* CR14 - 7 */ +typedef enum +{ + AB8500_CODEC_CR14_SMPSLVEN_HIGHVOLTAGE, + AB8500_CODEC_CR14_SMPSLVEN_LOWVOLTAGE +} t_ab8500_codec_cr14_smpslven; + +/* CR14 - 6 */ +typedef enum +{ + AB8500_CODEC_CR14_ENVDETSMPSEN_DISABLED, + AB8500_CODEC_CR14_ENVDETSMPSEN_ENABLED +} t_ab8500_codec_cr14_envdetsmpsen; + +/* CR14 - 5 */ +typedef enum +{ + AB8500_CODEC_CR14_CPLVEN_HIGHVOLTAGE, + AB8500_CODEC_CR14_CPLVEN_LOWVOLTAGE +} t_ab8500_codec_cr14_cplven; + +/* CR14 - 4 */ +typedef enum +{ + AB8500_CODEC_CR14_ENVDETCPEN_DISABLED, + AB8500_CODEC_CR14_ENVDETCPEN_ENABLED +} t_ab8500_codec_cr14_envdetcpen; + +/* CR14 - 3:0 */ +typedef enum +{ + AB8500_CODEC_CR14_ENVET_TIME_27USEC, + AB8500_CODEC_CR14_ENVET_TIME_53USEC, + AB8500_CODEC_CR14_ENVET_TIME_106USEC, + AB8500_CODEC_CR14_ENVET_TIME_212USEC, + AB8500_CODEC_CR14_ENVET_TIME_424USEC, + AB8500_CODEC_CR14_ENVET_TIME_848USEC, + AB8500_CODEC_CR14_ENVET_TIME_1MSEC, + AB8500_CODEC_CR14_ENVET_TIME_3MSEC, + AB8500_CODEC_CR14_ENVET_TIME_6MSEC, + AB8500_CODEC_CR14_ENVET_TIME_13MSEC, + AB8500_CODEC_CR14_ENVET_TIME_27MSEC, + AB8500_CODEC_CR14_ENVET_TIME_54MSEC, + AB8500_CODEC_CR14_ENVET_TIME_109MSEC, + AB8500_CODEC_CR14_ENVET_TIME_218MSEC, + AB8500_CODEC_CR14_ENVET_TIME_436MSEC, + AB8500_CODEC_CR14_ENVET_TIME_872MSEC, +} t_ab8500_codec_cr14_envet_time; + + +/* CR15 - 7 */ +typedef enum +{ + AB8500_CODEC_CR15_PWMTOVIBL_DA_PATH, + AB8500_CODEC_CR15_PWMTOVIBL_PWM +} t_ab8500_codec_cr15_pwmtovibl; + +/* CR15 - 6 */ +typedef enum +{ + AB8500_CODEC_CR15_PWMTOVIBR_DA_PATH, + AB8500_CODEC_CR15_PWMTOVIBR_PWM +} t_ab8500_codec_cr15_pwmtovibr; + +/* CR15 - 5 */ +typedef enum +{ + AB8500_CODEC_CR15_PWMLCTRL_PWMNPLGPOL, + AB8500_CODEC_CR15_PWMLCTRL_PWMNPLDUTYCYCLE +} t_ab8500_codec_cr15_pwmlctrl; + +/* CR15 - 4 */ +typedef enum +{ + AB8500_CODEC_CR15_PWMRCTRL_PWMNPRGPOL, + AB8500_CODEC_CR15_PWMRCTRL_PWMNPRDUTYCYCLE +} t_ab8500_codec_cr15_pwmrctrl; + +/* CR15 - 3 */ +typedef enum +{ + AB8500_CODEC_CR15_PWMNLCTRL_PWMNLGPOL, + AB8500_CODEC_CR15_PWMNLCTRL_PWMNLDUTYCYCLE +} t_ab8500_codec_cr15_pwmnlctrl; + +/* CR15 - 2 */ +typedef enum +{ + AB8500_CODEC_CR15_PWMPLCTRL_PWMPLGPOL, + AB8500_CODEC_CR15_PWMPLCTRL_PWMPLDUTYCYCLE +} t_ab8500_codec_cr15_pwmplctrl; + +/* CR15 - 1 */ +typedef enum +{ + AB8500_CODEC_CR15_PWMNRCTRL_PWMNRGPOL, + AB8500_CODEC_CR15_PWMNRCTRL_PWMNRDUTYCYCLE +} t_ab8500_codec_cr15_pwmnrctrl; + +/* CR15 - 0 */ +typedef enum +{ + AB8500_CODEC_CR15_PWMPRCTRL_PWMPRGPOL, + AB8500_CODEC_CR15_PWMPRCTRL_PWMPRDUTYCYCLE +} t_ab8500_codec_cr15_pwmprctrl; + + +/* CR16 - 7 */ +typedef enum +{ + AB8500_CODEC_CR16_PWMNLPOL_GNDVIB, + AB8500_CODEC_CR16_PWMNLPOL_VINVIB +} t_ab8500_codec_cr16_pwmnlpol; + +/* CR16 - 6:0 */ +typedef t_uint8 t_ab8500_codec_cr16_pwmnldutycycle; + + +/* CR17 - 7 */ +typedef enum +{ + AB8500_CODEC_CR17_PWMPLPOL_GNDVIB, + AB8500_CODEC_CR17_PWMPLPOL_VINVIB +} t_ab8500_codec_cr17_pwmplpol; + +/* CR17 - 6:0 */ +typedef t_uint8 t_ab8500_codec_cr17_pwmpldutycycle; + + +/* CR18 - 7 */ +typedef enum +{ + AB8500_CODEC_CR18_PWMNRPOL_GNDVIB, + AB8500_CODEC_CR18_PWMNRPOL_VINVIB +} t_ab8500_codec_cr18_pwmnrpol; + +/* CR18 - 6:0 */ +typedef t_uint8 t_ab8500_codec_cr18_pwmnrdutycycle; + + +/* CR19 - 7 */ +typedef enum +{ + AB8500_CODEC_CR19_PWMPRPOL_GNDVIB, + AB8500_CODEC_CR19_PWMPRPOL_VINVIB +} t_ab8500_codec_cr19_pwmprpol; + +/* CR19 - 6:0 */ +typedef t_uint8 t_ab8500_codec_cr19_pwmprdutycycle; + + +/* CR20 - 7 */ +typedef enum +{ + AB8500_CODEC_CR20_EN_SE_MIC1_DIFFERENTIAL, + AB8500_CODEC_CR20_EN_SE_MIC1_SINGLE +} t_ab8500_codec_cr20_en_se_mic1; + +/* CR20 - 4:0 */ +typedef t_uint8 t_ab8500_codec_cr20_mic1_gain; + + +/* CR21 - 7 */ +typedef enum +{ + AB8500_CODEC_CR21_EN_SE_MIC2_DIFFERENTIAL, + AB8500_CODEC_CR21_EN_SE_MIC2_SINGLE +} t_ab8500_codec_cr21_en_se_mic2; + +/* CR21 - 4:0 */ +typedef t_uint8 t_ab8500_codec_cr21_mic2_gain; + + +/* CR22 - 7:5 */ +typedef t_uint8 t_ab8500_codec_cr22_hsl_gain; + +/* CR22 - 4:0 */ +typedef t_uint8 t_ab8500_codec_cr22_linl_gain; + + +/* CR23 - 7:5 */ +typedef t_uint8 t_ab8500_codec_cr23_hsr_gain; + +/* CR23 - 4:0 */ +typedef t_uint8 t_ab8500_codec_cr23_linr_gain; + + +/* CR24 - 4:0 */ +typedef t_uint8 t_ab8500_codec_cr24_lintohsl_gain; + + +/* CR25 - 4:0 */ +typedef t_uint8 t_ab8500_codec_cr25_lintohsr_gain; + + +/* CR26 - 7 */ +typedef enum +{ + AB8500_CODEC_CR26_AD1NH_FILTER_ENABLED, + AB8500_CODEC_CR26_AD1NH_FILTER_DISABLED +} t_ab8500_codec_cr26_ad1nh; + +/* CR26 - 6 */ +typedef enum +{ + AB8500_CODEC_CR26_AD2NH_FILTER_ENABLED, + AB8500_CODEC_CR26_AD2NH_FILTER_DISABLED +} t_ab8500_codec_cr26_ad2nh; + +/* CR26 - 5 */ +typedef enum +{ + AB8500_CODEC_CR26_AD3NH_FILTER_ENABLED, + AB8500_CODEC_CR26_AD3NH_FILTER_DISABLED +} t_ab8500_codec_cr26_ad3nh; + +/* CR26 - 4 */ +typedef enum +{ + AB8500_CODEC_CR26_AD4NH_FILTER_ENABLED, + AB8500_CODEC_CR26_AD4NH_FILTER_DISABLED +} t_ab8500_codec_cr26_ad4nh; + +/* CR26 - 3 */ +typedef enum +{ + AB8500_CODEC_CR26_AD1_VOICE_AUDIOFILTER, + AB8500_CODEC_CR26_AD1_VOICE_LOWLATENCYFILTER +} t_ab8500_codec_cr26_ad1_voice; + +/* CR26 - 2 */ +typedef enum +{ + AB8500_CODEC_CR26_AD2_VOICE_AUDIOFILTER, + AB8500_CODEC_CR26_AD2_VOICE_LOWLATENCYFILTER +} t_ab8500_codec_cr26_ad2_voice; + +/* CR26 - 1 */ +typedef enum +{ + AB8500_CODEC_CR26_AD3_VOICE_AUDIOFILTER, + AB8500_CODEC_CR26_AD3_VOICE_LOWLATENCYFILTER +} t_ab8500_codec_cr26_ad3_voice; + +/* CR26 - 0 */ +typedef enum +{ + AB8500_CODEC_CR26_AD4_VOICE_AUDIOFILTER, + AB8500_CODEC_CR26_AD4_VOICE_LOWLATENCYFILTER +} t_ab8500_codec_cr26_ad4_voice; + + +/* CR27 - 7 */ +typedef enum +{ + AB8500_CODEC_CR27_EN_MASTGEN_DISABLED, + AB8500_CODEC_CR27_EN_MASTGEN_ENABLED +} t_ab8500_codec_cr27_en_mastgen; + +/* CR27 - 6:5 */ +typedef enum +{ + AB8500_CODEC_CR27_IF1_BITCLK_OSR_32, + AB8500_CODEC_CR27_IF1_BITCLK_OSR_64, + AB8500_CODEC_CR27_IF1_BITCLK_OSR_128, + AB8500_CODEC_CR27_IF1_BITCLK_OSR_256 +} t_ab8500_codec_cr27_if1_bitclk_osr; + +/* CR27 - 4 */ +typedef enum +{ + AB8500_CODEC_CR27_ENFS_BITCLK1_DISABLED, + AB8500_CODEC_CR27_ENFS_BITCLK1_ENABLED +} t_ab8500_codec_cr27_enfs_bitclk1; + +/* CR27 - 2:1 */ +typedef enum +{ + AB8500_CODEC_CR27_IF0_BITCLK_OSR_32, + AB8500_CODEC_CR27_IF0_BITCLK_OSR_64, + AB8500_CODEC_CR27_IF0_BITCLK_OSR_128, + AB8500_CODEC_CR27_IF0_BITCLK_OSR_256 +} t_ab8500_codec_cr27_if0_bitclk_osr; + +/* CR27 - 0 */ +typedef enum +{ + AB8500_CODEC_CR27_ENFS_BITCLK0_DISABLED, + AB8500_CODEC_CR27_ENFS_BITCLK0_ENABLED +} t_ab8500_codec_cr27_enfs_bitclk0; + + +/* CR28 - 6 */ +typedef enum +{ + AB8500_CODEC_CR28_FSYNC0P_RISING_EDGE, + AB8500_CODEC_CR28_FSYNC0P_FALLING_EDGE +} t_ab8500_codec_cr28_fsync0p; + +/* CR28 - 5 */ +typedef enum +{ + AB8500_CODEC_CR28_BITCLK0P_RISING_EDGE, + AB8500_CODEC_CR28_BITCLK0P_FALLING_EDGE +} t_ab8500_codec_cr28_bitclk0p; + +/* CR28 - 4 */ +typedef enum +{ + AB8500_CODEC_CR28_IF0DEL_NOT_DELAYED, + AB8500_CODEC_CR28_IF0DEL_DELAYED +} t_ab8500_codec_cr28_if0del; + +/* CR28 - 3:2 */ +typedef enum +{ + AB8500_CODEC_CR28_IF0FORMAT_DISABLED, + AB8500_CODEC_CR28_IF0FORMAT_TDM, + AB8500_CODEC_CR28_IF0FORMAT_I2S_LEFTALIGNED +} t_ab8500_codec_cr28_if0format; + +/* CR28 - 1:0 */ +typedef enum +{ + AB8500_CODEC_CR28_IF0WL_16BITS, + AB8500_CODEC_CR28_IF0WL_20BITS, + AB8500_CODEC_CR28_IF0WL_24BITS, + AB8500_CODEC_CR28_IF0WL_32BITS +} t_ab8500_codec_cr28_if0wl; + + +/* CR29 - 7 */ +typedef enum +{ + AB8500_CODEC_CR29_IF0DATOIF1AD_NOTSENT, + AB8500_CODEC_CR29_IF0DATOIF1AD_SENT +} t_ab8500_codec_cr29_if0datoif1ad; + +/* CR29 - 6 */ +typedef enum +{ + AB8500_CODEC_CR29_IF0CKTOIF1CK_NOTSENT, + AB8500_CODEC_CR29_IF0CKTOIF1CK_SENT +} t_ab8500_codec_cr29_if0cktoif1ck; + +/* CR29 - 5 */ +typedef enum +{ + AB8500_CODEC_CR29_IF1MASTER_FS1CK1_INPUT, + AB8500_CODEC_CR29_IF1MASTER_FS1CK1_OUTPUT +} t_ab8500_codec_cr29_if1master; + +/* CR29 - 3 */ +typedef enum +{ + AB8500_CODEC_CR29_IF1DATOIF0AD_NOTSENT, + AB8500_CODEC_CR29_IF1DATOIF0AD_SENT +} t_ab8500_codec_cr29_if1datoif0ad; + +/* CR29 - 2 */ +typedef enum +{ + AB8500_CODEC_CR29_IF1CKTOIF0CK_NOTSENT, + AB8500_CODEC_CR29_IF1CKTOIF0CK_SENT +} t_ab8500_codec_cr29_if1cktoif0ck; + +/* CR29 - 1 */ +typedef enum +{ + AB8500_CODEC_CR29_IF0MASTER_FS0CK0_INPUT, + AB8500_CODEC_CR29_IF0MASTER_FS0CK0_OUTPUT +} t_ab8500_codec_cr29_if0master; + +/* CR29 - 0 */ +typedef enum +{ + AB8500_CODEC_CR29_IF0BFIFOEN_NORMAL_MODE, + AB8500_CODEC_CR29_IF0BFIFOEN_BURST_MODE +} t_ab8500_codec_cr29_if0bfifoen; + + +/* CR30 - 6 */ +typedef enum +{ + AB8500_CODEC_CR30_FSYNC1P_RISING_EDGE, + AB8500_CODEC_CR30_FSYNC1P_FALLING_EDGE +} t_ab8500_codec_cr30_fsync1p; + +/* CR30 - 5 */ +typedef enum +{ + AB8500_CODEC_CR30_BITCLK1P_RISING_EDGE, + AB8500_CODEC_CR30_BITCLK1P_FALLING_EDGE +} t_ab8500_codec_cr30_bitclk1p; + +/* CR30 - 4 */ +typedef enum +{ + AB8500_CODEC_CR30_IF1DEL_NOT_DELAYED, + AB8500_CODEC_CR30_IF1DEL_DELAYED +} t_ab8500_codec_cr30_if1del; + +/* CR30 - 3:2 */ +typedef enum +{ + AB8500_CODEC_CR30_IF1FORMAT_DISABLED, + AB8500_CODEC_CR30_IF1FORMAT_TDM, + AB8500_CODEC_CR30_IF1FORMAT_I2S_LEFTALIGNED +} t_ab8500_codec_cr30_if1format; + +/* CR30 - 1:0 */ +typedef enum +{ + AB8500_CODEC_CR30_IF1WL_16BITS, + AB8500_CODEC_CR30_IF1WL_20BITS, + AB8500_CODEC_CR30_IF1WL_24BITS, + AB8500_CODEC_CR30_IF1WL_32BITS +} t_ab8500_codec_cr30_if1wl; + + +/* CR31:46 - 7:4 or 3:0 */ +/* In ab8500_codec.h */ + + +/* CR47:50 - 7/6/5/4/3/2/1/0 */ +typedef enum +{ + AB8500_CODEC_CR47_TO_CR50_HIZ_SL_LOW_IMPEDANCE, + AB8500_CODEC_CR47_TO_CR50_HIZ_SL_HIGH_IMPEDANCE, +} t_ab8500_codec_cr47_to_cr50_hiz_sl; + + +/* CR51 - 7 */ +typedef enum +{ + AB8500_CODEC_CR51_DA12_VOICE_AUDIOFILTER, + AB8500_CODEC_CR51_DA12_VOICE_LOWLATENCYFILTER +} t_ab8500_codec_cr51_da12_voice; + +/* CR51 - 5 */ +typedef enum +{ + AB8500_CODEC_CR51_SLDAI1TOSLADO1_NOT_LOOPEDBACK, + AB8500_CODEC_CR51_SLDAI1TOSLADO1_LOOPEDBACK +} t_ab8500_codec_cr51_sldai1toslado1; + + +/* CR51:56 - 4:0 */ +/* In ab8500_codec.h */ + + +/* CR52 - 5 */ +typedef enum +{ + AB8500_CODEC_CR52_SLDAI2TOSLADO2_NOT_LOOPEDBACK, + AB8500_CODEC_CR52_SLDAI2TOSLADO2_LOOPEDBACK +} t_ab8500_codec_cr52_sldai2toslado2; + + +/* CR53 - 7 */ +typedef enum +{ + AB8500_CODEC_CR53_DA34_VOICE_AUDIOFILTER, + AB8500_CODEC_CR53_DA34_VOICE_LOWLATENCYFILTER +} t_ab8500_codec_cr53_da34_voice; + +/* CR53 - 5 */ +typedef enum +{ + AB8500_CODEC_CR53_SLDAI3TOSLADO3_NOT_LOOPEDBACK, + AB8500_CODEC_CR53_SLDAI3TOSLADO3_LOOPEDBACK +} t_ab8500_codec_cr53_sldai3toslado3; + + +/* CR54 - 5 */ +typedef enum +{ + AB8500_CODEC_CR54_SLDAI4TOSLADO4_NOT_LOOPEDBACK, + AB8500_CODEC_CR54_SLDAI4TOSLADO4_LOOPEDBACK +} t_ab8500_codec_cr54_sldai4toslado4; + + +/* CR55 - 7 */ +typedef enum +{ + AB8500_CODEC_CR55_DA56_VOICE_AUDIOFILTER, + AB8500_CODEC_CR55_DA56_VOICE_LOWLATENCYFILTER +} t_ab8500_codec_cr55_da56_voice; + +/* CR55 - 6:5 */ +typedef enum +{ + AB8500_CODEC_CR55_SLDAI5TOSLADO5_NOT_LOOPEDBACK, + AB8500_CODEC_CR55_SLDAI5TOSLADO5_DA_IN1_LOOPEDBACK, + AB8500_CODEC_CR55_SLDAI5TOSLADO5_DA_IN3_LOOPEDBACK, + AB8500_CODEC_CR55_SLDAI5TOSLADO5_DA_IN5_LOOPEDBACK +} t_ab8500_codec_cr55_sldai5toslado5; + + +/* CR56 - 6:5 */ +typedef enum +{ + AB8500_CODEC_CR56_SLDAI6TOSLADO7_NOT_LOOPEDBACK, + AB8500_CODEC_CR56_SLDAI6TOSLADO7_DA_IN2_LOOPEDBACK, + AB8500_CODEC_CR56_SLDAI6TOSLADO7_DA_IN4_LOOPEDBACK, + AB8500_CODEC_CR56_SLDAI6TOSLADO7_DA_IN6_LOOPEDBACK +} t_ab8500_codec_cr56_sldai6toslado7; + + +/* CR57 - 6 */ +typedef enum +{ + AB8500_CODEC_CR57_BFIFULL_MSK_MASKED, + AB8500_CODEC_CR57_BFIFULL_MSK_ENABLED +} t_ab8500_codec_cr57_bfifull_msk; + +/* CR57 - 5 */ +typedef enum +{ + AB8500_CODEC_CR57_BFIEMPT_MSK_MASKED, + AB8500_CODEC_CR57_BFIEMPT_MSK_ENABLED +} t_ab8500_codec_cr57_bfiempt_msk; + +/* CR57 - 4 */ +typedef enum +{ + AB8500_CODEC_CR57_DACHAN_MSK_MASKED, + AB8500_CODEC_CR57_DACHAN_MSK_ENABLED +} t_ab8500_codec_cr57_dachan_msk; + +/* CR57 - 3 */ +typedef enum +{ + AB8500_CODEC_CR57_GAIN_MSK_MASKED, + AB8500_CODEC_CR57_GAIN_MSK_ENABLED +} t_ab8500_codec_cr57_gain_msk; + +/* CR57 - 2 */ +typedef enum +{ + AB8500_CODEC_CR57_DSPAD_MSK_MASKED, + AB8500_CODEC_CR57_DSPAD_MSK_ENABLED +} t_ab8500_codec_cr57_dspad_msk; + +/* CR57 - 1 */ +typedef enum +{ + AB8500_CODEC_CR57_DSPDA_MSK_MASKED, + AB8500_CODEC_CR57_DSPDA_MSK_ENABLED +} t_ab8500_codec_cr57_dspda_msk; + +/* CR57 - 0 */ +typedef enum +{ + AB8500_CODEC_CR57_STFIR_MSK_MASKED, + AB8500_CODEC_CR57_STFIR_MSK_ENABLED +} t_ab8500_codec_cr57_stfir_msk; + + +/* CR58 - Read Only */ +/* CR58 - 6 */ +typedef enum +{ + AB8500_CODEC_CR58_BFIFULL_EV_NOT_FULL, + AB8500_CODEC_CR58_BFIFULL_EV_FULL +} t_ab8500_codec_cr58_bfifull_ev; + +/* CR58 - 5 */ +typedef enum +{ + AB8500_CODEC_CR58_BFIEMPT_EV_NOT_EMPTY, + AB8500_CODEC_CR58_BFIEMPT_EV_EMPTY +} t_ab8500_codec_cr58_bfiempt_ev; + +/* CR58 - 4 */ +typedef enum +{ + AB8500_CODEC_CR58_DACHAN_EV_NO_SATURATION, + AB8500_CODEC_CR58_DACHAN_EV_SATURATION +} t_ab8500_codec_cr58_dachan_ev; + +/* CR58 - 3 */ +typedef enum +{ + AB8500_CODEC_CR58_GAIN_EV_NO_SATURATION, + AB8500_CODEC_CR58_GAIN_EV_SATURATION +} t_ab8500_codec_cr58_gain_ev; + +/* CR58 - 2 */ +typedef enum +{ + AB8500_CODEC_CR58_DSPAD_EV_NO_SATURATION, + AB8500_CODEC_CR58_DSPAD_EV_SATURATION +} t_ab8500_codec_cr58_dspad_ev; + +/* CR58 - 1 */ +typedef enum +{ + AB8500_CODEC_CR58_DSPDA_EV_NO_SATURATION, + AB8500_CODEC_CR58_DSPDA_EV_SATURATION +} t_ab8500_codec_cr58_dspda_ev; + +/* CR58 - 0 */ +typedef enum +{ + AB8500_CODEC_CR58_STFIR_EV_NO_SATURATION, + AB8500_CODEC_CR58_STFIR_EV_SATURATION +} t_ab8500_codec_cr58_stfir_ev; + + +/* CR59 - 7 */ +typedef enum +{ + AB8500_CODEC_CR59_VSSREADY_MSK_MASKED, + AB8500_CODEC_CR59_VSSREADY_MSK_ENABLED +} t_ab8500_codec_cr59_vssready_msk; + +/* CR59 - 6 */ +typedef enum +{ + AB8500_CODEC_CR59_SHRTVIBL_MSK_MASKED, + AB8500_CODEC_CR59_SHRTVIBL_MSK_ENABLED +} t_ab8500_codec_cr59_shrtvibl_msk; + +/* CR59 - 5 */ +typedef enum +{ + AB8500_CODEC_CR59_SHRTVIBR_MSK_MASKED, + AB8500_CODEC_CR59_SHRTVIBR_MSK_ENABLED +} t_ab8500_codec_cr59_shrtvibr_msk; + +/* CR59 - 4 */ +typedef enum +{ + AB8500_CODEC_CR59_SHRTHFL_MSK_MASKED, + AB8500_CODEC_CR59_SHRTHFL_MSK_ENABLED +} t_ab8500_codec_cr59_shrthfl_msk; + +/* CR59 - 3 */ +typedef enum +{ + AB8500_CODEC_CR59_SHRTHFR_MSK_MASKED, + AB8500_CODEC_CR59_SHRTHFR_MSK_ENABLED +} t_ab8500_codec_cr59_shrthfr_msk; + +/* CR59 - 2 */ +typedef enum +{ + AB8500_CODEC_CR59_SHRTHSL_MSK_MASKED, + AB8500_CODEC_CR59_SHRTHSL_MSK_ENABLED +} t_ab8500_codec_cr59_shrthsl_msk; + +/* CR59 - 1 */ +typedef enum +{ + AB8500_CODEC_CR59_SHRTHSR_MSK_MASKED, + AB8500_CODEC_CR59_SHRTHSR_MSK_ENABLED +} t_ab8500_codec_cr59_shrthsr_msk; + +/* CR59 - 0 */ +typedef enum +{ + AB8500_CODEC_CR59_SHRTEAR_MSK_MASKED, + AB8500_CODEC_CR59_SHRTEAR_MSK_ENABLED +} t_ab8500_codec_cr59_shrtear_msk; + + +/* CR60 - Read Only */ +/* CR60 - 7 */ +typedef enum +{ + AB8500_CODEC_CR60_VSSREADY_EV_NOT_READY, + AB8500_CODEC_CR60_VSSREADY_EV_READY +} t_ab8500_codec_cr60_vssready_ev; + +/* CR60 - 6 */ +typedef enum +{ + AB8500_CODEC_CR60_SHRTVIBL_EV_NO_SHORTCIRCUIT, + AB8500_CODEC_CR60_SHRTVIBL_EV_SHORTCIRCUIT +} t_ab8500_codec_cr60_shrtvibl_ev; + +/* CR60 - 5 */ +typedef enum +{ + AB8500_CODEC_CR60_SHRTVIBR_EV_NO_SHORTCIRCUIT, + AB8500_CODEC_CR60_SHRTVIBR_EV_SHORTCIRCUIT +} t_ab8500_codec_cr60_shrtvibr_ev; + +/* CR60 - 4 */ +typedef enum +{ + AB8500_CODEC_CR60_SHRTHFL_EV_NO_SHORTCIRCUIT, + AB8500_CODEC_CR60_SHRTHFL_EV_SHORTCIRCUIT +} t_ab8500_codec_cr60_shrthfl_ev; + +/* CR60 - 3 */ +typedef enum +{ + AB8500_CODEC_CR60_SHRTHFR_EV_NO_SHORTCIRCUIT, + AB8500_CODEC_CR60_SHRTHFR_EV_SHORTCIRCUIT +} t_ab8500_codec_cr60_shrthfr_ev; + +/* CR60 - 2 */ +typedef enum +{ + AB8500_CODEC_CR60_SHRTHSL_EV_NO_SHORTCIRCUIT, + AB8500_CODEC_CR60_SHRTHSL_EV_SHORTCIRCUIT +} t_ab8500_codec_cr60_shrthsl_ev; + +/* CR60 - 1 */ +typedef enum +{ + AB8500_CODEC_CR60_SHRTHSR_EV_NO_SHORTCIRCUIT, + AB8500_CODEC_CR60_SHRTHSR_EV_SHORTCIRCUIT +} t_ab8500_codec_cr60_shrthsr_ev; + +/* CR60 - 0 */ +typedef enum +{ + AB8500_CODEC_CR60_SHRTEAR_EV_NO_SHORTCIRCUIT, + AB8500_CODEC_CR60_SHRTEAR_EV_SHORTCIRCUIT +} t_ab8500_codec_cr60_shrtear_ev; + + +/* CR61 - 6:2 - Read Only */ +typedef enum +{ + AB8500_CODEC_CR61_REVISION_1_0, + AB8500_CODEC_CR61_REVISION_TBD +} t_ab8500_codec_cr61_revision; + +/* CR61 - 1:0 */ +typedef enum +{ + AB8500_CODEC_CR61_FADE_SPEED_1MS, + AB8500_CODEC_CR61_FADE_SPEED_4MS, + AB8500_CODEC_CR61_FADE_SPEED_8MS, + AB8500_CODEC_CR61_FADE_SPEED_16MS +} t_ab8500_codec_cr61_fade_speed; + + +/* CR62 - Read Only */ +/* CR62 - 5 */ +typedef enum +{ + AB8500_CODEC_CR62_DMIC1SINC3_SINC5_SELECTED, + AB8500_CODEC_CR62_DMIC1SINC3_SINC3_SELECTED +} t_ab8500_codec_cr62_dmic1sinc3; + +/* CR62 - 4 */ +typedef enum +{ + AB8500_CODEC_CR62_DMIC2SINC3_SINC5_SELECTED, + AB8500_CODEC_CR62_DMIC2SINC3_SINC3_SELECTED +} t_ab8500_codec_cr62_dmic2sinc3; + +/* CR62 - 3 */ +typedef enum +{ + AB8500_CODEC_CR62_DMIC3SINC3_SINC5_SELECTED, + AB8500_CODEC_CR62_DMIC3SINC3_SINC3_SELECTED +} t_ab8500_codec_cr62_dmic3sinc3; + +/* CR62 - 2 */ +typedef enum +{ + AB8500_CODEC_CR62_DMIC4SINC3_SINC5_SELECTED, + AB8500_CODEC_CR62_DMIC4SINC3_SINC3_SELECTED +} t_ab8500_codec_cr62_dmic4sinc3; + +/* CR62 - 1 */ +typedef enum +{ + AB8500_CODEC_CR62_DMIC5SINC3_SINC5_SELECTED, + AB8500_CODEC_CR62_DMIC5SINC3_SINC3_SELECTED +} t_ab8500_codec_cr62_dmic5sinc3; + +/* CR62 - 0 */ +typedef enum +{ + AB8500_CODEC_CR62_DMIC6SINC3_SINC5_SELECTED, + AB8500_CODEC_CR62_DMIC6SINC3_SINC3_SELECTED +} t_ab8500_codec_cr62_dmic6sinc3; + + +/* CR63 - 7 */ +typedef enum +{ + AB8500_CODEC_CR63_DATOHSLEN_DISABLED, + AB8500_CODEC_CR63_DATOHSLEN_ENABLED +} t_ab8500_codec_cr63_datohslen; + +/* CR63 - 6 */ +typedef enum +{ + AB8500_CODEC_CR63_DATOHSREN_DISABLED, + AB8500_CODEC_CR63_DATOHSREN_ENABLED +} t_ab8500_codec_cr63_datohsren; + +/* CR63 - 5 */ +typedef enum +{ + AB8500_CODEC_CR63_AD1SEL_LINLADL_SELECTED, + AB8500_CODEC_CR63_AD1SEL_DMIC1_SELECTED +} t_ab8500_codec_cr63_ad1sel; + +/* CR63 - 4 */ +typedef enum +{ + AB8500_CODEC_CR63_AD2SEL_LINRADR_SELECTED, + AB8500_CODEC_CR63_AD2SEL_DMIC2_SELECTED +} t_ab8500_codec_cr63_ad2sel; + +/* CR63 - 3 */ +typedef enum +{ + AB8500_CODEC_CR63_AD3SEL_ADMO_SELECTED, + AB8500_CODEC_CR63_AD3SEL_DMIC3_SELECTED +} t_ab8500_codec_cr63_ad3sel; + +/* CR63 - 2 */ +typedef enum +{ + AB8500_CODEC_CR63_AD5SEL_AMADR_SELECTED, + AB8500_CODEC_CR63_AD5SEL_DMIC5_SELECTED +} t_ab8500_codec_cr63_ad5sel; + +/* CR63 - 1 */ +typedef enum +{ + AB8500_CODEC_CR63_AD6SEL_ADMO_SELECTED, + AB8500_CODEC_CR63_AD6SEL_DMIC6_SELECTED +} t_ab8500_codec_cr63_ad6sel; + +/* CR63 - 0 */ +typedef enum +{ + AB8500_CODEC_CR63_ANCSEL_NOT_MIXED_IN_EAR, + AB8500_CODEC_CR63_ANCSEL_MIXED_IN_EAR +} t_ab8500_codec_cr63_ancsel; + + +/* CR64 - 7 */ +typedef enum +{ + AB8500_CODEC_CR64_DATOHFREN_NOT_MIXED_TO_HFR, + AB8500_CODEC_CR64_DATOHFREN_MIXED_TO_HFR +} t_ab8500_codec_cr64_datohfren; + +/* CR64 - 6 */ +typedef enum +{ + AB8500_CODEC_CR64_DATOHFLEN_NOT_MIXED_TO_HFL, + AB8500_CODEC_CR64_DATOHFLEN_MIXED_TO_HFL +} t_ab8500_codec_cr64_datohflen; + +/* CR64 - 5 */ +typedef enum +{ + AB8500_CODEC_CR64_HFRSEL_DA4_MIXED_TO_HFR, + AB8500_CODEC_CR64_HFRSEL_ANC_MIXED_TO_HFR +} t_ab8500_codec_cr64_hfrsel; + +/* CR64 - 4 */ +typedef enum +{ + AB8500_CODEC_CR64_HFLSEL_DA3_MIXED_TO_HFL, + AB8500_CODEC_CR64_HFLSEL_ANC_MIXED_TO_HFL +} t_ab8500_codec_cr64_hflsel; + +/* CR64 - 3:2 */ +typedef enum +{ + AB8500_CODEC_CR64_STFIR1SEL_AD_OUT1_SELECTED, + AB8500_CODEC_CR64_STFIR1SEL_AD_OUT3_SELECTED, + AB8500_CODEC_CR64_STFIR1SEL_DA_IN1_SELECTED +} t_ab8500_codec_cr64_stfir1sel; + +/* CR64 - 1:0 */ +typedef enum +{ + AB8500_CODEC_CR64_STFIR2SEL_AD_OUT2_SELECTED, + AB8500_CODEC_CR64_STFIR2SEL_AD_OUT4_SELECTED, + AB8500_CODEC_CR64_STFIR2SEL_DA_IN2_SELECTED +} t_ab8500_codec_cr64_stfir2sel; + + +/* CR65 - 6 */ +typedef enum +{ + AB8500_CODEC_CR65_FADEDIS_AD1_ENABLED, + AB8500_CODEC_CR65_FADEDIS_AD1_DISABLED +} t_ab8500_codec_cr65_fadedis_ad1; + +/* CR65 - 5:0 */ +typedef t_uint8 t_ab8500_codec_cr65_ad1gain; + + +/* CR66 - 6 */ +typedef enum +{ + AB8500_CODEC_CR66_FADEDIS_AD2_ENABLED, + AB8500_CODEC_CR66_FADEDIS_AD2_DISABLED +} t_ab8500_codec_cr66_fadedis_ad2; + +/* CR66 - 5:0 */ +typedef t_uint8 t_ab8500_codec_cr66_ad2gain; + + +/* CR67 - 6 */ +typedef enum +{ + AB8500_CODEC_CR67_FADEDIS_AD3_ENABLED, + AB8500_CODEC_CR67_FADEDIS_AD3_DISABLED +} t_ab8500_codec_cr67_fadedis_ad3; + +/* CR67 - 5:0 */ +typedef t_uint8 t_ab8500_codec_cr67_ad3gain; + + +/* CR68 - 6 */ +typedef enum +{ + AB8500_CODEC_CR68_FADEDIS_AD4_ENABLED, + AB8500_CODEC_CR68_FADEDIS_AD4_DISABLED +} t_ab8500_codec_cr68_fadedis_ad4; + +/* CR68 - 5:0 */ +typedef t_uint8 t_ab8500_codec_cr68_ad4gain; + + +/* CR69 - 6 */ +typedef enum +{ + AB8500_CODEC_CR69_FADEDIS_AD5_ENABLED, + AB8500_CODEC_CR69_FADEDIS_AD5_DISABLED +} t_ab8500_codec_cr69_fadedis_ad5; + +/* CR69 - 5:0 */ +typedef t_uint8 t_ab8500_codec_cr69_ad5gain; + + +/* CR70 - 6 */ +typedef enum +{ + AB8500_CODEC_CR70_FADEDIS_AD6_ENABLED, + AB8500_CODEC_CR70_FADEDIS_AD6_DISABLED +} t_ab8500_codec_cr70_fadedis_ad6; + +/* CR70 - 5:0 */ +typedef t_uint8 t_ab8500_codec_cr70_ad6gain; + + +/* CR71 - 6 */ +typedef enum +{ + AB8500_CODEC_CR71_FADEDIS_DA1_ENABLED, + AB8500_CODEC_CR71_FADEDIS_DA1_DISABLED +} t_ab8500_codec_cr71_fadedis_da1; + +/* CR71 - 5:0 */ +typedef t_uint8 t_ab8500_codec_cr71_da1gain; + + +/* CR72 - 6 */ +typedef enum +{ + AB8500_CODEC_CR72_FADEDIS_DA2_ENABLED, + AB8500_CODEC_CR72_FADEDIS_DA2_DISABLED +} t_ab8500_codec_cr72_fadedis_da2; + +/* CR72 - 5:0 */ +typedef t_uint8 t_ab8500_codec_cr72_da2gain; + + +/* CR73 - 6 */ +typedef enum +{ + AB8500_CODEC_CR73_FADEDIS_DA3_ENABLED, + AB8500_CODEC_CR73_FADEDIS_DA3_DISABLED +} t_ab8500_codec_cr73_fadedis_da3; + +/* CR73 - 5:0 */ +typedef t_uint8 t_ab8500_codec_cr73_da3gain; + + +/* CR74 - 6 */ +typedef enum +{ + AB8500_CODEC_CR74_FADEDIS_DA4_ENABLED, + AB8500_CODEC_CR74_FADEDIS_DA4_DISABLED +} t_ab8500_codec_cr74_fadedis_da4; + +/* CR74 - 5:0 */ +typedef t_uint8 t_ab8500_codec_cr74_da4gain; + + +/* CR75 - 6 */ +typedef enum +{ + AB8500_CODEC_CR75_FADEDIS_DA5_ENABLED, + AB8500_CODEC_CR75_FADEDIS_DA5_DISABLED +} t_ab8500_codec_cr75_fadedis_da5; + +/* CR75 - 5:0 */ +typedef t_uint8 t_ab8500_codec_cr75_da5gain; + + +/* CR76 - 6 */ +typedef enum +{ + AB8500_CODEC_CR76_FADEDIS_DA6_ENABLED, + AB8500_CODEC_CR76_FADEDIS_DA6_DISABLED +} t_ab8500_codec_cr76_fadedis_da6; + +/* CR76 - 5:0 */ +typedef t_uint8 t_ab8500_codec_cr76_da6gain; + + +/* CR77 - 6 */ +typedef enum +{ + AB8500_CODEC_CR77_FADEDIS_AD1L_TO_HFL_ENABLED, + AB8500_CODEC_CR77_FADEDIS_AD1L_TO_HFL_DISABLED +} t_ab8500_codec_cr77_fadedis_ad1l; + +/* CR77 - 5:0 */ +typedef t_uint8 t_ab8500_codec_cr77_ad1lbgain_to_hfl; + + +/* CR78 - 6 */ +typedef enum +{ + AB8500_CODEC_CR78_FADEDIS_AD2L_TO_HFR_ENABLED, + AB8500_CODEC_CR78_FADEDIS_AD2L_TO_HFR_DISABLED +} t_ab8500_codec_cr78_fadedis_ad2l; + +/* CR78 - 5:0 */ +typedef t_uint8 t_ab8500_codec_cr78_ad2lbgain_to_hfr; + + +/* CR79 - 7 */ +typedef enum +{ + AB8500_CODEC_CR79_HSSINC1_SINC3_CHOOSEN, + AB8500_CODEC_CR79_HSSINC1_SINC1_CHOOSEN +} t_ab8500_codec_cr79_hssinc1; + +/* CR79 - 4 */ +typedef enum +{ + AB8500_CODEC_CR79_FADEDIS_HSL_ENABLED, + AB8500_CODEC_CR79_FADEDIS_HSL_DISABLED +} t_ab8500_codec_cr79_fadedis_hsl; + +/* CR79 - 3:0 */ +typedef t_uint8 t_ab8500_codec_cr79_hsldgain; + + +/* CR80 - 4 */ +typedef enum +{ + AB8500_CODEC_CR80_FADEDIS_HSR_ENABLED, + AB8500_CODEC_CR80_FADEDIS_HSR_DISABLED +} t_ab8500_codec_cr80_fadedis_hsr; + +/* CR80 - 3:0 */ +typedef t_uint8 t_ab8500_codec_cr80_hsrdgain; + + +/* CR81 - 4:0 */ +typedef t_uint8 t_ab8500_codec_cr81_stfir1gain; + + +/* CR82 - 4:0 */ +typedef t_uint8 t_ab8500_codec_cr82_stfir2gain; + + +/* CR83 - 2 */ +typedef enum +{ + AB8500_CODEC_CR83_ENANC_DISABLED, + AB8500_CODEC_CR83_ENANC_ENABLED +} t_ab8500_codec_cr83_enanc; + +/* CR83 - 1 */ +typedef enum +{ + AB8500_CODEC_CR83_ANCIIRINIT_NOT_STARTED, + AB8500_CODEC_CR83_ANCIIRINIT_STARTED +} t_ab8500_codec_cr83_anciirinit; + +/* CR83 - 0 */ +typedef enum +{ + AB8500_CODEC_CR83_ANCFIRUPDATE_RESETTED, + AB8500_CODEC_CR83_ANCFIRUPDATE_NOT_RESETTED +} t_ab8500_codec_cr83_ancfirupdate; + + +/* CR84 - 4:0 */ +typedef t_uint8 t_ab8500_codec_cr84_ancinshift; + + +/* CR85 - 4:0 */ +typedef t_uint8 t_ab8500_codec_cr85_ancfiroutshift; + + +/* CR86 - 4:0 */ +typedef t_uint8 t_ab8500_codec_cr86_ancshiftout; + + +/* CR87 - 7:0 */ +typedef t_uint8 t_ab8500_codec_cr87_ancfircoeff_msb; + + +/* CR88 - 7:0 */ +typedef t_uint8 t_ab8500_codec_cr88_ancfircoeff_lsb; + + +/* CR89 - 7:0 */ +typedef t_uint8 t_ab8500_codec_cr89_anciircoeff_msb; + + +/* CR90 - 7:0 */ +typedef t_uint8 t_ab8500_codec_cr90_anciircoeff_lsb; + + +/* CR91 - 7:0 */ +typedef t_uint8 t_ab8500_codec_cr91_ancwarpdel_msb; + + +/* CR92 - 7:0 */ +typedef t_uint8 t_ab8500_codec_cr92_ancwarpdel_lsb; + + +/* CR93 - Read Only */ +/* CR93 - 7:0 */ +typedef t_uint8 t_ab8500_codec_cr93_ancfirpeak_msb; + + +/* CR94 - Read Only */ +/* CR94 - 7:0 */ +typedef t_uint8 t_ab8500_codec_cr94_ancfirpeak_lsb; + + +/* CR95 - Read Only */ +/* CR95 - 7:0 */ +typedef t_uint8 t_ab8500_codec_cr95_anciirpeak_msb; + + +/* CR96 - Read Only */ +/* CR96 - 7:0 */ +typedef t_uint8 t_ab8500_codec_cr96_anciirpeak_lsb; + + +/* CR97 - 7 */ +typedef enum +{ + AB8500_CODEC_CR97_STFIR_SET_LAST_NOT_APPLIED, + AB8500_CODEC_CR97_STFIR_SET_LAST_APPLIED +} t_ab8500_codec_cr97_stfir_set; + +/* CR97 - 6:0 */ +typedef t_uint8 t_ab8500_codec_cr97_stfir_addr; + + +/* CR98 - 7:0 */ +typedef t_uint8 t_ab8500_codec_cr98_stfir_coeff_msb; + + +/* CR99 - 7:0 */ +typedef t_uint8 t_ab8500_codec_cr99_stfir_coeff_lsb; + + +/* CR100 - 2 */ +typedef enum +{ + AB8500_CODEC_CR100_ENSTFIRS_DISABLED, + AB8500_CODEC_CR100_ENSTFIRS_ENABLED +} t_ab8500_codec_cr100_enstfirs; + +/* CR100 - 1 */ +typedef enum +{ + AB8500_CODEC_CR100_STFIRSTOIF1_AUD_IF0_DATA_RATE, + AB8500_CODEC_CR100_STFIRSTOIF1_AUD_IF1_DATA_RATE +} t_ab8500_codec_cr100_stfirstoif1; + +/* CR100 - 0 */ +typedef enum +{ + AB8500_CODEC_CR100_STFIR_BUSY_READY, + AB8500_CODEC_CR100_STFIR_BUSY_NOT_READY +} t_ab8500_codec_cr100_stfir_busy; + + +/* CR101 - 7 */ +typedef enum +{ + AB8500_CODEC_CR101_PARLHF_INDEPENDENT, + AB8500_CODEC_CR101_PARLHF_BRIDGED +} t_ab8500_codec_cr101_parlhf; + +/* CR101 - 6 */ +typedef enum +{ + AB8500_CODEC_CR101_PARLVIB_INDEPENDENT, + AB8500_CODEC_CR101_PARLVIB_BRIDGED +} t_ab8500_codec_cr101_parlvib; + +/* CR101 - 3 */ +typedef enum +{ + AB8500_CODEC_CR101_CLASSD_VIBLSWAPEN_DISABLED, + AB8500_CODEC_CR101_CLASSD_VIBLSWAPEN_ENABLED +} t_ab8500_codec_cr101_classd_viblswapen; + +/* CR101 - 2 */ +typedef enum +{ + AB8500_CODEC_CR101_CLASSD_VIBRSWAPEN_DISABLED, + AB8500_CODEC_CR101_CLASSD_VIBRSWAPEN_ENABLED +} t_ab8500_codec_cr101_classd_vibrswapen; + +/* CR101 - 1 */ +typedef enum +{ + AB8500_CODEC_CR101_CLASSD_HFLSWAPEN_DISABLED, + AB8500_CODEC_CR101_CLASSD_HFLSWAPEN_ENABLED +} t_ab8500_codec_cr101_classd_hflswapen; + +/* CR101 - 0 */ +typedef enum +{ + AB8500_CODEC_CR101_CLASSD_HFRSWAPEN_DISABLED, + AB8500_CODEC_CR101_CLASSD_HFRSWAPEN_ENABLED +} t_ab8500_codec_cr101_classd_hfrswapen; + + +/* CR102 - 7:4 */ +typedef enum +{ + AB8500_CODEC_CR102_CLASSD_FIRBYP_ALL_ENABLED = 0, + AB8500_CODEC_CR102_CLASSD_FIRBYP_HFL_BYPASSED = 1, + AB8500_CODEC_CR102_CLASSD_FIRBYP_HFR_BYPASSED = 2, + AB8500_CODEC_CR102_CLASSD_FIRBYP_VIBL_BYPASSED = 4, + AB8500_CODEC_CR102_CLASSD_FIRBYP_VIBR_BYPASSED = 8 +} t_ab8500_codec_cr102_classd_firbyp; + +/* CR102 - 3:0 */ +typedef enum +{ + AB8500_CODEC_CR102_CLASSD_HIGHVOLEN_DISABLED = 0, + AB8500_CODEC_CR102_CLASSD_HIGHVOLEN_HFL_HIGHVOL = 1, + AB8500_CODEC_CR102_CLASSD_HIGHVOLEN_HFR_HIGHVOL = 2, + AB8500_CODEC_CR102_CLASSD_HIGHVOLEN_VIBL_HIGHVOL = 4, + AB8500_CODEC_CR102_CLASSD_HIGHVOLEN_VIBR_HIGHVOL = 8 +} t_ab8500_codec_cr102_classd_highvolen; + + +/* CR103 - 7:4 */ +typedef t_uint8 t_ab8500_codec_cr103_classd_ditherhpgain; + +/* CR103 - 3:0 */ +typedef t_uint8 t_ab8500_codec_cr103_classd_ditherwgain; + + +/* CR104 - 5:0 */ +/* In ab8500_codec.h */ + + +/* CR105 - 7:0 */ +/* In ab8500_codec.h */ + + +/* CR106 - 6:4 */ +/* In ab8500_codec.h */ + + +/* CR106 - 2 */ +/* In ab8500_codec.h */ + + +/* CR106 - 1 */ +/* In ab8500_codec.h */ + + +/* CR106 - 0 */ +/* In ab8500_codec.h */ + + +/* CR107 - 7:0 */ +/* In ab8500_codec.h */ + + +/* CR108 - 7:0 */ +/* In ab8500_codec.h */ + + +/* CR109 - Read Only */ +/* CR109 - 7:0 */ +typedef t_uint8 t_ab8500_codec_cr109_bfifosamples; + + + +/*configuration structure for AB8500 Codec*/ +typedef struct +{ + /* CR0 */ + t_ab8500_codec_cr0_powerup cr0_powerup; + t_ab8500_codec_cr0_enaana cr0_enaana; + + /* CR1 */ + t_ab8500_codec_cr1_swreset cr1_swreset; + + /* CR2 */ + t_ab8500_codec_cr2_enad1 cr2_enad1; + t_ab8500_codec_cr2_enad2 cr2_enad2; + t_ab8500_codec_cr2_enad3 cr2_enad3; + t_ab8500_codec_cr2_enad4 cr2_enad4; + t_ab8500_codec_cr2_enad5 cr2_enad5; + t_ab8500_codec_cr2_enad6 cr2_enad6; + + /* CR3 */ + t_ab8500_codec_cr3_enda1 cr3_enda1; + t_ab8500_codec_cr3_enda2 cr3_enda2; + t_ab8500_codec_cr3_enda3 cr3_enda3; + t_ab8500_codec_cr3_enda4 cr3_enda4; + t_ab8500_codec_cr3_enda5 cr3_enda5; + t_ab8500_codec_cr3_enda6 cr3_enda6; + + /* CR4 */ + t_ab8500_codec_cr4_lowpowhs cr4_lowpowhs; + t_ab8500_codec_cr4_lowpowdachs cr4_lowpowdachs; + t_ab8500_codec_cr4_lowpowear cr4_lowpowear; + t_ab8500_codec_cr4_ear_sel_cm cr4_ear_sel_cm; + t_ab8500_codec_cr4_hs_hp_dis cr4_hs_hp_dis; + t_ab8500_codec_cr4_ear_hp_dis cr4_ear_hp_dis; + + /* CR5 */ + t_ab8500_codec_cr5_enmic1 cr5_enmic1; + t_ab8500_codec_cr5_enmic2 cr5_enmic2; + t_ab8500_codec_cr5_enlinl cr5_enlinl; + t_ab8500_codec_cr5_enlinr cr5_enlinr; + t_ab8500_codec_cr5_mutmic1 cr5_mutmic1; + t_ab8500_codec_cr5_mutmic2 cr5_mutmic2; + t_ab8500_codec_cr5_mutlinl cr5_mutlinl; + t_ab8500_codec_cr5_mutlinr cr5_mutlinr; + + /* CR6 */ + t_ab8500_codec_cr6_endmic1 cr6_endmic1; + t_ab8500_codec_cr6_endmic2 cr6_endmic2; + t_ab8500_codec_cr6_endmic3 cr6_endmic3; + t_ab8500_codec_cr6_endmic4 cr6_endmic4; + t_ab8500_codec_cr6_endmic5 cr6_endmic5; + t_ab8500_codec_cr6_endmic6 cr6_endmic6; + + /* CR7 */ + t_ab8500_codec_cr7_mic1sel cr7_mic1sel; + t_ab8500_codec_cr7_linrsel cr7_linrsel; + t_ab8500_codec_cr7_endrvhsl cr7_endrvhsl; + t_ab8500_codec_cr7_endrvhsr cr7_endrvhsr; + t_ab8500_codec_cr7_enadcmic cr7_enadcmic; + t_ab8500_codec_cr7_enadclinl cr7_enadclinl; + t_ab8500_codec_cr7_enadclinr cr7_enadclinr; + + /* CR8 */ + t_ab8500_codec_cr8_cp_dis_pldwn cr8_cp_dis_pldwn; + t_ab8500_codec_cr8_enear cr8_enear; + t_ab8500_codec_cr8_enhsl cr8_enhsl; + t_ab8500_codec_cr8_enhsr cr8_enhsr; + t_ab8500_codec_cr8_enhfl cr8_enhfl; + t_ab8500_codec_cr8_enhfr cr8_enhfr; + t_ab8500_codec_cr8_envibl cr8_envibl; + t_ab8500_codec_cr8_envibr cr8_envibr; + + /* CR9 */ + t_ab8500_codec_cr9_endacear cr9_endacear; + t_ab8500_codec_cr9_endachsl cr9_endachsl; + t_ab8500_codec_cr9_endachsr cr9_endachsr; + t_ab8500_codec_cr9_endachfl cr9_endachfl; + t_ab8500_codec_cr9_endachfr cr9_endachfr; + t_ab8500_codec_cr9_endacvibl cr9_endacvibl; + t_ab8500_codec_cr9_endacvibr cr9_endacvibr; + + /* CR10 */ + t_ab8500_codec_cr10_muteear cr10_muteear; + t_ab8500_codec_cr10_mutehsl cr10_mutehsl; + t_ab8500_codec_cr10_mutehsr cr10_mutehsr; + t_ab8500_codec_cr10_mutehfl cr10_mutehfl; + t_ab8500_codec_cr10_mutehfr cr10_mutehfr; + t_ab8500_codec_cr10_mutevibl cr10_mutevibl; + t_ab8500_codec_cr10_mutevibr cr10_mutevibr; + + /* CR11 */ + t_ab8500_codec_cr11_earshortpwd cr11_earshortpwd; + t_ab8500_codec_cr11_earshortdis cr11_earshortdis; + t_ab8500_codec_cr11_hslshortdis cr11_hslshortdis; + t_ab8500_codec_cr11_hsrshortdis cr11_hsrshortdis; + t_ab8500_codec_cr11_hflshortdis cr11_hflshortdis; + t_ab8500_codec_cr11_hfrshortdis cr11_hfrshortdis; + t_ab8500_codec_cr11_viblshortdis cr11_viblshortdis; + t_ab8500_codec_cr11_vibrshortdis cr11_vibrshortdis; + + /* CR12 */ + t_ab8500_codec_cr12_encphs cr12_encphs; + t_ab8500_codec_cr12_hsautotime cr12_hsautotime; + t_ab8500_codec_cr12_hsautoensel cr12_hsautoensel; + t_ab8500_codec_cr12_hsautoen cr12_hsautoen; + + /* CR13 */ + t_ab8500_codec_cr13_envdet_hthresh cr13_envdet_hthresh; + t_ab8500_codec_cr13_envdet_lthresh cr13_envdet_lthresh; + + /* CR14 */ + t_ab8500_codec_cr14_smpslven cr14_smpslven; + t_ab8500_codec_cr14_envdetsmpsen cr14_envdetsmpsen; + t_ab8500_codec_cr14_cplven cr14_cplven; + t_ab8500_codec_cr14_envdetcpen cr14_envdetcpen; + t_ab8500_codec_cr14_envet_time cr14_envet_time; + + + /* CR15 */ + t_ab8500_codec_cr15_pwmtovibl cr15_pwmtovibl; + t_ab8500_codec_cr15_pwmtovibr cr15_pwmtovibr; + t_ab8500_codec_cr15_pwmlctrl cr15_pwmlctrl; + t_ab8500_codec_cr15_pwmrctrl cr15_pwmrctrl; + t_ab8500_codec_cr15_pwmnlctrl cr15_pwmnlctrl; + t_ab8500_codec_cr15_pwmplctrl cr15_pwmplctrl; + t_ab8500_codec_cr15_pwmnrctrl cr15_pwmnrctrl; + t_ab8500_codec_cr15_pwmprctrl cr15_pwmprctrl; + + + /* CR16 */ + t_ab8500_codec_cr16_pwmnlpol cr16_pwmnlpol; + t_ab8500_codec_cr16_pwmnldutycycle cr16_pwmnldutycycle; + + + /* CR17 */ + t_ab8500_codec_cr17_pwmplpol cr17_pwmplpol; + t_ab8500_codec_cr17_pwmpldutycycle cr17_pwmpldutycycle; + + + /* CR18 */ + t_ab8500_codec_cr18_pwmnrpol cr18_pwmnrpol; + t_ab8500_codec_cr18_pwmnrdutycycle cr18_pwmnrdutycycle; + + + /* CR19 */ + t_ab8500_codec_cr19_pwmprpol cr19_pwmprpol; + t_ab8500_codec_cr19_pwmprdutycycle cr19_pwmprdutycycle; + + + /* CR20 */ + t_ab8500_codec_cr20_en_se_mic1 cr20_en_se_mic1; + t_ab8500_codec_cr20_mic1_gain cr20_mic1_gain; + + + /* CR21 */ + t_ab8500_codec_cr21_en_se_mic2 cr21_en_se_mic2; + t_ab8500_codec_cr21_mic2_gain cr21_mic2_gain; + + + /* CR22 */ + t_ab8500_codec_cr22_hsl_gain cr22_hsl_gain; + t_ab8500_codec_cr22_linl_gain cr22_linl_gain; + + + /* CR23 */ + t_ab8500_codec_cr23_hsr_gain cr23_hsr_gain; + t_ab8500_codec_cr23_linr_gain cr23_linr_gain; + + + /* CR24 */ + t_ab8500_codec_cr24_lintohsl_gain cr24_lintohsl_gain; + + + /* CR25 */ + t_ab8500_codec_cr25_lintohsr_gain cr25_lintohsr_gain; + + + /* CR26 */ + t_ab8500_codec_cr26_ad1nh cr26_ad1nh; + t_ab8500_codec_cr26_ad2nh cr26_ad2nh; + t_ab8500_codec_cr26_ad3nh cr26_ad3nh; + t_ab8500_codec_cr26_ad4nh cr26_ad4nh; + t_ab8500_codec_cr26_ad1_voice cr26_ad1_voice; + t_ab8500_codec_cr26_ad2_voice cr26_ad2_voice; + t_ab8500_codec_cr26_ad3_voice cr26_ad3_voice; + t_ab8500_codec_cr26_ad4_voice cr26_ad4_voice; + + + /* CR27 */ + t_ab8500_codec_cr27_en_mastgen cr27_en_mastgen; + t_ab8500_codec_cr27_if1_bitclk_osr cr27_if1_bitclk_osr; + t_ab8500_codec_cr27_enfs_bitclk1 cr27_enfs_bitclk1; + t_ab8500_codec_cr27_if0_bitclk_osr cr27_if0_bitclk_osr; + t_ab8500_codec_cr27_enfs_bitclk0 cr27_enfs_bitclk0; + + /* CR28 */ + t_ab8500_codec_cr28_fsync0p cr28_fsync0p; + t_ab8500_codec_cr28_bitclk0p cr28_bitclk0p; + t_ab8500_codec_cr28_if0del cr28_if0del; + t_ab8500_codec_cr28_if0format cr28_if0format; + t_ab8500_codec_cr28_if0wl cr28_if0wl; + + + /* CR29 */ + t_ab8500_codec_cr29_if0datoif1ad cr29_if0datoif1ad; + t_ab8500_codec_cr29_if0cktoif1ck cr29_if0cktoif1ck; + t_ab8500_codec_cr29_if1master cr29_if1master; + t_ab8500_codec_cr29_if1datoif0ad cr29_if1datoif0ad; + t_ab8500_codec_cr29_if1cktoif0ck cr29_if1cktoif0ck; + t_ab8500_codec_cr29_if0master cr29_if0master; + t_ab8500_codec_cr29_if0bfifoen cr29_if0bfifoen; + + + /* CR30 */ + t_ab8500_codec_cr30_fsync1p cr30_fsync1p; + t_ab8500_codec_cr30_bitclk1p cr30_bitclk1p; + t_ab8500_codec_cr30_if1del cr30_if1del; + t_ab8500_codec_cr30_if1format cr30_if1format; + t_ab8500_codec_cr30_if1wl cr30_if1wl; + + + /* CR31 */ + t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr31_adotoslot1; + t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr31_adotoslot0; + + + /* CR32 */ + t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr32_adotoslot3; + t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr32_adotoslot2; + + + /* CR33 */ + t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr33_adotoslot5; + t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr33_adotoslot4; + + + /* CR34 */ + t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr34_adotoslot7; + t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr34_adotoslot6; + + + /* CR35 */ + t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr35_adotoslot9; + t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr35_adotoslot8; + + + /* CR36 */ + t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr36_adotoslot11; + t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr36_adotoslot10; + + + /* CR37 */ + t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr37_adotoslot13; + t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr37_adotoslot12; + + + /* CR38 */ + t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr38_adotoslot15; + t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr38_adotoslot14; + + + /* CR39 */ + t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr39_adotoslot17; + t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr39_adotoslot16; + + + /* CR40 */ + t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr40_adotoslot19; + t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr40_adotoslot18; + + + /* CR41 */ + t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr41_adotoslot21; + t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr41_adotoslot20; + + + /* CR42 */ + t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr42_adotoslot23; + t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr42_adotoslot22; + + + /* CR43 */ + t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr43_adotoslot25; + t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr43_adotoslot24; + + + /* CR44 */ + t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr44_adotoslot27; + t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr44_adotoslot26; + + + /* CR45 */ + t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr45_adotoslot29; + t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr45_adotoslot28; + + + /* CR46 */ + t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr46_adotoslot31; + t_ab8500_codec_cr31_to_cr46_ad_data_allocation cr46_adotoslot30; + + + /* CR47 */ + t_ab8500_codec_cr47_to_cr50_hiz_sl cr47_hiz_sl7; + t_ab8500_codec_cr47_to_cr50_hiz_sl cr47_hiz_sl6; + t_ab8500_codec_cr47_to_cr50_hiz_sl cr47_hiz_sl5; + t_ab8500_codec_cr47_to_cr50_hiz_sl cr47_hiz_sl4; + t_ab8500_codec_cr47_to_cr50_hiz_sl cr47_hiz_sl3; + t_ab8500_codec_cr47_to_cr50_hiz_sl cr47_hiz_sl2; + t_ab8500_codec_cr47_to_cr50_hiz_sl cr47_hiz_sl1; + t_ab8500_codec_cr47_to_cr50_hiz_sl cr47_hiz_sl0; + + + /* CR48 */ + t_ab8500_codec_cr47_to_cr50_hiz_sl cr48_hiz_sl15; + t_ab8500_codec_cr47_to_cr50_hiz_sl cr48_hiz_sl14; + t_ab8500_codec_cr47_to_cr50_hiz_sl cr48_hiz_sl13; + t_ab8500_codec_cr47_to_cr50_hiz_sl cr48_hiz_sl12; + t_ab8500_codec_cr47_to_cr50_hiz_sl cr48_hiz_sl11; + t_ab8500_codec_cr47_to_cr50_hiz_sl cr48_hiz_sl10; + t_ab8500_codec_cr47_to_cr50_hiz_sl cr48_hiz_sl9; + t_ab8500_codec_cr47_to_cr50_hiz_sl cr48_hiz_sl8; + + + /* CR49 */ + t_ab8500_codec_cr47_to_cr50_hiz_sl cr49_hiz_sl23; + t_ab8500_codec_cr47_to_cr50_hiz_sl cr49_hiz_sl22; + t_ab8500_codec_cr47_to_cr50_hiz_sl cr49_hiz_sl21; + t_ab8500_codec_cr47_to_cr50_hiz_sl cr49_hiz_sl20; + t_ab8500_codec_cr47_to_cr50_hiz_sl cr49_hiz_sl19; + t_ab8500_codec_cr47_to_cr50_hiz_sl cr49_hiz_sl18; + t_ab8500_codec_cr47_to_cr50_hiz_sl cr49_hiz_sl17; + t_ab8500_codec_cr47_to_cr50_hiz_sl cr49_hiz_sl16; + + + /* CR50 */ + t_ab8500_codec_cr47_to_cr50_hiz_sl cr50_hiz_sl31; + t_ab8500_codec_cr47_to_cr50_hiz_sl cr50_hiz_sl30; + t_ab8500_codec_cr47_to_cr50_hiz_sl cr50_hiz_sl29; + t_ab8500_codec_cr47_to_cr50_hiz_sl cr50_hiz_sl28; + t_ab8500_codec_cr47_to_cr50_hiz_sl cr50_hiz_sl27; + t_ab8500_codec_cr47_to_cr50_hiz_sl cr50_hiz_sl26; + t_ab8500_codec_cr47_to_cr50_hiz_sl cr50_hiz_sl25; + t_ab8500_codec_cr47_to_cr50_hiz_sl cr50_hiz_sl24; + + + /* CR51 */ + t_ab8500_codec_cr51_da12_voice cr51_da12_voice; + t_ab8500_codec_cr51_sldai1toslado1 cr51_sldai1toslado1; + t_ab8500_codec_cr51_to_cr56_sltoda cr51_sltoda1; + + + /* CR52 */ + t_ab8500_codec_cr52_sldai2toslado2 cr52_sldai2toslado2; + t_ab8500_codec_cr51_to_cr56_sltoda cr52_sltoda2; + + + /* CR53 */ + t_ab8500_codec_cr53_da34_voice cr53_da34_voice; + t_ab8500_codec_cr53_sldai3toslado3 cr53_sldai3toslado3; + t_ab8500_codec_cr51_to_cr56_sltoda cr53_sltoda3; + + /* CR54 */ + t_ab8500_codec_cr54_sldai4toslado4 cr54_sldai4toslado4; + t_ab8500_codec_cr51_to_cr56_sltoda cr54_sltoda4; + + + /* CR55 */ + t_ab8500_codec_cr55_da56_voice cr55_da56_voice; + t_ab8500_codec_cr55_sldai5toslado5 cr55_sldai5toslado5; + t_ab8500_codec_cr51_to_cr56_sltoda cr55_sltoda5; + + + /* CR56 */ + t_ab8500_codec_cr56_sldai6toslado7 cr56_sldai6toslado7; + t_ab8500_codec_cr51_to_cr56_sltoda cr56_sltoda6; + + + /* CR57 */ + t_ab8500_codec_cr57_bfifull_msk cr57_bfifull_msk; + t_ab8500_codec_cr57_bfiempt_msk cr57_bfiempt_msk; + t_ab8500_codec_cr57_dachan_msk cr57_dachan_msk; + t_ab8500_codec_cr57_gain_msk cr57_gain_msk; + t_ab8500_codec_cr57_dspad_msk cr57_dspad_msk; + t_ab8500_codec_cr57_dspda_msk cr57_dspda_msk; + t_ab8500_codec_cr57_stfir_msk cr57_stfir_msk; + + + /* CR58 */ + t_ab8500_codec_cr58_bfifull_ev cr58_bfifull_ev; + t_ab8500_codec_cr58_bfiempt_ev cr58_bfiempt_ev; + t_ab8500_codec_cr58_dachan_ev cr58_dachan_ev; + t_ab8500_codec_cr58_gain_ev cr58_gain_ev; + t_ab8500_codec_cr58_dspad_ev cr58_dspad_ev; + t_ab8500_codec_cr58_dspda_ev cr58_dspda_ev; + t_ab8500_codec_cr58_stfir_ev cr58_stfir_ev; + + + /* CR59 */ + t_ab8500_codec_cr59_vssready_msk cr59_vssready_msk; + t_ab8500_codec_cr59_shrtvibl_msk cr59_shrtvibl_msk; + t_ab8500_codec_cr59_shrtvibr_msk cr59_shrtvibr_msk; + t_ab8500_codec_cr59_shrthfl_msk cr59_shrthfl_msk; + t_ab8500_codec_cr59_shrthfr_msk cr59_shrthfr_msk; + t_ab8500_codec_cr59_shrthsl_msk cr59_shrthsl_msk; + t_ab8500_codec_cr59_shrthsr_msk cr59_shrthsr_msk; + t_ab8500_codec_cr59_shrtear_msk cr59_shrtear_msk; + + + /* CR60 */ + t_ab8500_codec_cr60_vssready_ev cr60_vssready_ev; + t_ab8500_codec_cr60_shrtvibl_ev cr60_shrtvibl_ev; + t_ab8500_codec_cr60_shrtvibr_ev cr60_shrtvibr_ev; + t_ab8500_codec_cr60_shrthfl_ev cr60_shrthfl_ev; + t_ab8500_codec_cr60_shrthfr_ev cr60_shrthfr_ev; + t_ab8500_codec_cr60_shrthsl_ev cr60_shrthsl_ev; + t_ab8500_codec_cr60_shrthsr_ev cr60_shrthsr_ev; + t_ab8500_codec_cr60_shrtear_ev cr60_shrtear_ev; + + + /* CR61 */ + t_ab8500_codec_cr61_revision cr61_revision; + t_ab8500_codec_cr61_fade_speed cr61_fade_speed; + + + /* CR62 */ + t_ab8500_codec_cr62_dmic1sinc3 cr62_dmic1sinc3; + t_ab8500_codec_cr62_dmic2sinc3 cr62_dmic2sinc3; + t_ab8500_codec_cr62_dmic3sinc3 cr62_dmic3sinc3; + t_ab8500_codec_cr62_dmic4sinc3 cr62_dmic4sinc3; + t_ab8500_codec_cr62_dmic5sinc3 cr62_dmic5sinc3; + t_ab8500_codec_cr62_dmic6sinc3 cr62_dmic6sinc3; + + + /* CR63 */ + t_ab8500_codec_cr63_datohslen cr63_datohslen; + t_ab8500_codec_cr63_datohsren cr63_datohsren; + t_ab8500_codec_cr63_ad1sel cr63_ad1sel; + t_ab8500_codec_cr63_ad2sel cr63_ad2sel; + t_ab8500_codec_cr63_ad3sel cr63_ad3sel; + t_ab8500_codec_cr63_ad5sel cr63_ad5sel; + t_ab8500_codec_cr63_ad6sel cr63_ad6sel; + t_ab8500_codec_cr63_ancsel cr63_ancsel; + + + /* CR64 */ + t_ab8500_codec_cr64_datohfren cr64_datohfren; + t_ab8500_codec_cr64_datohflen cr64_datohflen; + t_ab8500_codec_cr64_hfrsel cr64_hfrsel; + t_ab8500_codec_cr64_hflsel cr64_hflsel; + t_ab8500_codec_cr64_stfir1sel cr64_stfir1sel; + t_ab8500_codec_cr64_stfir2sel cr64_stfir2sel; + + + /* CR65 */ + t_ab8500_codec_cr65_fadedis_ad1 cr65_fadedis_ad1; + t_ab8500_codec_cr65_ad1gain cr65_ad1gain; + + + /* CR66 */ + t_ab8500_codec_cr66_fadedis_ad2 cr66_fadedis_ad2; + t_ab8500_codec_cr66_ad2gain cr66_ad2gain; + + + /* CR67 */ + t_ab8500_codec_cr67_fadedis_ad3 cr67_fadedis_ad3; + t_ab8500_codec_cr67_ad3gain cr67_ad3gain; + + + /* CR68 */ + t_ab8500_codec_cr68_fadedis_ad4 cr68_fadedis_ad4; + t_ab8500_codec_cr68_ad4gain cr68_ad4gain; + + + /* CR69 */ + t_ab8500_codec_cr69_fadedis_ad5 cr69_fadedis_ad5; + t_ab8500_codec_cr69_ad5gain cr69_ad5gain; + + + /* CR70 */ + t_ab8500_codec_cr70_fadedis_ad6 cr70_fadedis_ad6; + t_ab8500_codec_cr70_ad6gain cr70_ad6gain; + + + /* CR71 */ + t_ab8500_codec_cr71_fadedis_da1 cr71_fadedis_da1; + t_ab8500_codec_cr71_da1gain cr71_da1gain; + + + /* CR72 */ + t_ab8500_codec_cr72_fadedis_da2 cr72_fadedis_da2; + t_ab8500_codec_cr72_da2gain cr72_da2gain; + + + /* CR73 */ + t_ab8500_codec_cr73_fadedis_da3 cr73_fadedis_da3; + t_ab8500_codec_cr73_da3gain cr73_da3gain; + + + /* CR74 */ + t_ab8500_codec_cr74_fadedis_da4 cr74_fadedis_da4; + t_ab8500_codec_cr74_da4gain cr74_da4gain; + + + /* CR75 */ + t_ab8500_codec_cr75_fadedis_da5 cr75_fadedis_da5; + t_ab8500_codec_cr75_da5gain cr75_da5gain; + + + /* CR76 */ + t_ab8500_codec_cr76_fadedis_da6 cr76_fadedis_da6; + t_ab8500_codec_cr76_da6gain cr76_da6gain; + + + /* CR77 */ + t_ab8500_codec_cr77_fadedis_ad1l cr77_fadedis_ad1l; + t_ab8500_codec_cr77_ad1lbgain_to_hfl cr77_ad1lbgain_to_hfl; + + + /* CR78 */ + t_ab8500_codec_cr78_fadedis_ad2l cr78_fadedis_ad2l; + t_ab8500_codec_cr78_ad2lbgain_to_hfr cr78_ad2lbgain_to_hfr; + + + /* CR79 */ + t_ab8500_codec_cr79_hssinc1 cr79_hssinc1; + t_ab8500_codec_cr79_fadedis_hsl cr79_fadedis_hsl; + t_ab8500_codec_cr79_hsldgain cr79_hsldgain; + + + /* CR80 */ + t_ab8500_codec_cr80_fadedis_hsr cr80_fadedis_hsr; + t_ab8500_codec_cr80_hsrdgain cr80_hsrdgain; + + + /* CR81 */ + t_ab8500_codec_cr81_stfir1gain cr81_stfir1gain; + + + /* CR82 */ + t_ab8500_codec_cr82_stfir2gain cr82_stfir2gain; + + + /* CR83 */ + t_ab8500_codec_cr83_enanc cr83_enanc; + t_ab8500_codec_cr83_anciirinit cr83_anciirinit; + t_ab8500_codec_cr83_ancfirupdate cr83_ancfirupdate; + + + /* CR84 */ + t_ab8500_codec_cr84_ancinshift cr84_ancinshift; + + + /* CR85 */ + t_ab8500_codec_cr85_ancfiroutshift cr85_ancfiroutshift; + + + /* CR86 */ + t_ab8500_codec_cr86_ancshiftout cr86_ancshiftout; + + + /* CR87 */ + t_ab8500_codec_cr87_ancfircoeff_msb cr87_ancfircoeff_msb; + + + /* CR88 */ + t_ab8500_codec_cr88_ancfircoeff_lsb cr88_ancfircoeff_lsb; + + + /* CR89 */ + t_ab8500_codec_cr89_anciircoeff_msb cr89_anciircoeff_msb; + + + /* CR90 */ + t_ab8500_codec_cr90_anciircoeff_lsb cr90_anciircoeff_lsb; + + + /* CR91 */ + t_ab8500_codec_cr91_ancwarpdel_msb cr91_ancwarpdel_msb; + + + /* CR92 */ + t_ab8500_codec_cr92_ancwarpdel_lsb cr92_ancwarpdel_lsb; + + + /* CR93 */ + t_ab8500_codec_cr93_ancfirpeak_msb cr93_ancfirpeak_msb; + + + /* CR94 */ + t_ab8500_codec_cr94_ancfirpeak_lsb cr94_ancfirpeak_lsb; + + + /* CR95 */ + t_ab8500_codec_cr95_anciirpeak_msb cr95_anciirpeak_msb; + + + /* CR96 */ + t_ab8500_codec_cr96_anciirpeak_lsb cr96_anciirpeak_lsb; + + + /* CR97 */ + t_ab8500_codec_cr97_stfir_set cr97_stfir_set; + t_ab8500_codec_cr97_stfir_addr cr97_stfir_addr; + + + /* CR98 */ + t_ab8500_codec_cr98_stfir_coeff_msb cr98_stfir_coeff_msb; + + + /* CR99 */ + t_ab8500_codec_cr99_stfir_coeff_lsb cr99_stfir_coeff_lsb; + + + /* CR100 */ + t_ab8500_codec_cr100_enstfirs cr100_enstfirs; + t_ab8500_codec_cr100_stfirstoif1 cr100_stfirstoif1; + t_ab8500_codec_cr100_stfir_busy cr100_stfir_busy; + + + /* CR101 */ + t_ab8500_codec_cr101_parlhf cr101_parlhf; + t_ab8500_codec_cr101_parlvib cr101_parlvib; + t_ab8500_codec_cr101_classd_viblswapen cr101_classd_viblswapen; + t_ab8500_codec_cr101_classd_vibrswapen cr101_classd_vibrswapen; + t_ab8500_codec_cr101_classd_hflswapen cr101_classd_hflswapen; + t_ab8500_codec_cr101_classd_hfrswapen cr101_classd_hfrswapen; + + + /* CR102 */ + t_ab8500_codec_cr102_classd_firbyp cr102_classd_firbyp; + t_ab8500_codec_cr102_classd_highvolen cr102_classd_highvolen; + + + /* CR103 */ + t_ab8500_codec_cr103_classd_ditherhpgain cr103_classd_ditherhpgain; + t_ab8500_codec_cr103_classd_ditherwgain cr103_classd_ditherwgain; + + + /* CR104 */ + t_ab8500_codec_cr104_bfifoint cr104_bfifoint; + + + /* CR105 */ + t_ab8500_codec_cr105_bfifotx cr105_bfifotx; + + + /* CR106 */ + t_ab8500_codec_cr106_bfifofsext cr106_bfifofsext; + t_ab8500_codec_cr106_bfifomsk cr106_bfifomsk; + t_ab8500_codec_cr106_bfifomstr cr106_bfifomstr; + t_ab8500_codec_cr106_bfifostrt cr106_bfifostrt; + + + /* CR107 */ + t_ab8500_codec_cr107_bfifosampnr cr107_bfifosampnr; + + + /* CR108 */ + t_ab8500_codec_cr108_bfifowakeup cr108_bfifowakeup; + + + /* CR109 */ + t_ab8500_codec_cr109_bfifosamples cr109_bfifosamples; + + +} t_ab8500_codec_configuration; + + +typedef struct +{ + t_uint8 slave_address_of_ab8500_codec; + t_ab8500_codec_direction ab8500_codec_direction; + t_ab8500_codec_mode ab8500_codec_mode_in; + t_ab8500_codec_mode ab8500_codec_mode_out; + t_ab8500_codec_audio_interface audio_interface; + t_ab8500_codec_src ab8500_codec_src; + t_ab8500_codec_dest ab8500_codec_dest; + t_uint8 in_left_volume; + t_uint8 in_right_volume; + t_uint8 out_left_volume; + t_uint8 out_right_volume; + + t_ab8500_codec_configuration ab8500_codec_configuration; +} t_ab8500_codec_system_context; +#endif /* _AB8500_CODECP_H_ */ + +/* End of file AB8500_CODECP.h */ + + diff --git a/arch/arm/mach-ux500/include/mach/ab8500_gpadc.h b/arch/arm/mach-ux500/include/mach/ab8500_gpadc.h new file mode 100644 index 00000000000..150ff10173e --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/ab8500_gpadc.h @@ -0,0 +1,28 @@ +/* + * ab8500_gpadc.c - AB8500 GPADC Driver + * + * Copyright (C) 2010 ST-Ericsson + * Licensed under GPLv2. + * + * Author: Arun R Murthy <arun.murthy@stericsson.com> + */ + +#ifndef _AB8500_GPADC_H +#define _Ab8500_GPADC_H + +/* GPADC source: From datasheer(ADCSwSel[4:0] in GPADCCtrl2) */ +#define BAT_CTRL 0x01 +#define ACC_DETECT1 0x04 +#define ACC_DETECT2 0x05 +#define MAIN_BAT_V 0x08 +#define BK_BAT_V 0x0C +#define VBUS_V 0x09 +#define MAIN_CHARGER_V 0x03 +#define MAIN_CHARGER_C 0x0A +#define USB_CHARGER_C 0x0B +#define DIE_TEMP 0x0D +#define BTEMP_BALL 0x02 + +int ab8500_gpadc_conversion(int input); + +#endif /* _AB8500_GPADC_H */ diff --git a/arch/arm/mach-ux500/include/mach/av8100.h b/arch/arm/mach-ux500/include/mach/av8100.h new file mode 100755 index 00000000000..a4afebf3c8c --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/av8100.h @@ -0,0 +1,531 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * License terms: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef __AV8100_H +#define __AV8100_H + +#ifdef _cplusplus +extern "C" { +#endif /* _cplusplus */ + +typedef enum av8100_error +{ + AV8100_OK = 0x0, + AV8100_INVALID_COMMAND = 0x1, + AV8100_INVALID_INTERFACE = 0x2, + AV8100_INVALID_IOCTL = 0x3, + AV8100_COMMAND_FAIL = 0x4, + AV8100_FWDOWNLOAD_FAIL = 0x5, + AV8100_FAIL = 0xFF, +}av8100_error; + +typedef enum interface +{ + I2C_INTERFACE = 0x0, + DSI_INTERFACE = 0x1, +}interface; + +/** AV8100 - DSI dcs command set */ +typedef enum +{ + DCS_VSYNC_START = 0x1, + DCS_VSYNC_END = 0x11, + DCS_HSYNC_START = 0x21, + DCS_HSYNC_END = 0x31, + DCS_SHORT_WRITE = 0x15, + DCS_LONG_WRITE = 0x39, + DCS_RGB565_PACKED = 0xE, + DCS_RGB666_PACKED = 0x1E, + DCS_RGB666_UNPACKED = 0x2E, + DCS_RGB888_PACKED = 0x3E, + DCS_RAM_WRITE = 0x3C, + DCS_RAM_WRITE_CONTINUE = 0x2C, + DCS_FW_DOWNLOAD = 0xDB, + DCS_WRITE_UC = 0xDC, + DCS_READ_UC = 0xDB, + DCS_NEXT_FILED_TYPE = 0xDA, + DCS_EXEC_UC = 0xDD, +}dsi_dcs_command_type; + +/** AV8100 Operating modes */ +typedef enum +{ + AV8100_OPMODE_SHUTDOWN = 0x1, + AV8100_OPMODE_STANDBY, + AV8100_OPMODE_SCAN, + AV8100_OPMODE_INIT, + AV8100_OPMODE_IDLE, + AV8100_OPMODE_VIDEO +}av8100_operating_mode; + +/** AV8100 status */ +#define AV8100_PLUGIN_NONE 0x00 +#define AV8100_HDMI_PLUGIN 0x01 +#define AV8100_CVBS_PLUGIN 0x02 + +/** AV8100 Command Type */ +typedef enum +{ + AV8100_COMMAND_VIDEO_INPUT_FORMAT = 0x1, + AV8100_COMMAND_AUDIO_INPUT_FORMAT = 0x2, + AV8100_COMMAND_VIDEO_OUTPUT_FORMAT = 0x3, + AV8100_COMMAND_VIDEO_SCALING_FORMAT, + AV8100_COMMAND_COLORSPACECONVERSION, + AV8100_COMMAND_CEC_MESSAGEWRITE, + AV8100_COMMAND_CEC_MESSAGEREAD_BACK, + AV8100_COMMAND_DENC, + AV8100_COMMAND_HDMI, + AV8100_COMMAND_HDCP_SENDKEY, + AV8100_COMMAND_HDCP_MANAGEMENT, + AV8100_COMMAND_INFOFRAMES, + AV8100_COMMAND_EDID_SECTIONREADBACK, + AV8100_COMMAND_PATTERNGENERATOR, + +}av8100_command_type; + +/** AV8100 Command Type */ +typedef enum +{ + AV8100_COMMAND_VIDEO_INPUT_FORMAT_SIZE = 0x17, + AV8100_COMMAND_AUDIO_INPUT_FORMAT_SIZE = 0x8, + AV8100_COMMAND_VIDEO_OUTPUT_FORMAT_SIZE = 0x18, + AV8100_COMMAND_VIDEO_SCALING_FORMAT_SIZE = 0x9, + AV8100_COMMAND_COLORSPACECONVERSION_SIZE = 0x21, + AV8100_COMMAND_CEC_MESSAGEWRITE_SIZE = 0x14, + AV8100_COMMAND_CEC_MESSAGEREAD_BACK_SIZE = 0x14, + AV8100_COMMAND_DENC_SIZE = 0x5, + AV8100_COMMAND_HDMI_SIZE = 0x4, + AV8100_COMMAND_HDCP_SENDKEY_SIZE = 0x9, + AV8100_COMMAND_HDCP_MANAGEMENT_SIZE = 0x4, + AV8100_COMMAND_INFOFRAMES_SIZE = 0x22, + AV8100_COMMAND_EDID_SECTIONREADBACK_SIZE = 0x81, + AV8100_COMMAND_PATTERNGENERATOR_SIZE = 0x4, +}av8100_command_size; + +/** AV8100 structures register & command definitions */ + +/** AV8100 Internal registers ~ Register 0x0 to 0xF */ +/** Internal registers for I2C operations */ + +typedef enum +{ + STANDBY_REG = 0x0, + AV8100_5_VOLT_TIME_REG = 0x1, + STANDBY_INTERRUPT_MASK_REG = 0x2, + STANDBY_PENDING_INTERRUPT_REG = 0x3, + GENERAL_INTERRUPT_MASK_REG = 0x4, + GENERAL_INTERRUPT_REG = 0x5, + GENERAL_STATUS_REG = 0x6, + GPIO_CONFIGURATION_REG = 0x7, + GENERAL_CONTROL_REG = 0x8, + FIRMWARE_DOWNLOAD_ENTRY_REG = 0xF +}internal_reg; + +struct av8100_registers_internal +{ + volatile char standby; + volatile char av8100_5_volt_time; + volatile char standby_interrupt_mask; + volatile char standby_pending_interrupt; + volatile char general_interrupt_mask; + volatile char general_interrupt; + volatile char general_status; + volatile char gpio_configuration; + volatile char general_control; + volatile char firmware_download_entry; +}; + +/** AV8100 Video Input Format Command */ +struct av8100_video_input_format_command +{ + + volatile char Identifier; + volatile char Mode; + volatile char Pixel_format; + volatile char Htotal[2]; + volatile char Hactive[2]; + volatile char Vtotal[2]; + volatile char Vactive[2]; + volatile char Videomode; + volatile char Number_DSI; + volatile char Virtualchannelcommandmode; + volatile char Virtualchannelvideomode; + volatile char Linenumber[2]; + volatile char Tearingeffect; + volatile char Master_Clock_frequency[4]; +}; + +/** AV8100 Audio Input Format Command */ +struct av8100_audio_input_format_command +{ + + volatile char Identifier; + volatile char I2SOrTDM; + volatile char NumberofI2SentriesFreq; + volatile char BitFormat; + volatile char LPCMOrCompress; + volatile char SlaveOrMaster; + volatile char Mute; + +}; + +/** AV8100 Video Output Format Command */ +struct av8100_video_output_format_command +{ + + volatile char Identifier; + volatile char Formatter; + volatile char VSYNCpolarity; + volatile char HSYNCpolarity; + volatile char Htotal[2]; + volatile char Hactive[2]; + volatile char Vtotal[2]; + volatile char Vactive[2]; + volatile char HSYNCstart[2]; + volatile char HSYNClength[2]; + volatile char VSYNCstart[2]; + volatile char VSYNClength[2]; + volatile char Pixelfrequency[4]; +}; + +/** AV8100 Video Video Scaling Format Command */ +struct av8100_video_scaling_format_command +{ + volatile char Identifier; + volatile char Hstart[2]; + volatile char Hstop[2]; + volatile char Vstart[2]; + volatile char Vstop[2]; +}; + +/** AV8100 Video Colorspace Conversion Command */ +struct av8100_colorspace_conversion_command +{ + volatile char Identifier; + volatile char C0[2]; + volatile char C1[2]; + volatile char C2[2]; + volatile char C3[2]; + volatile char C4[2]; + volatile char C5[2]; + volatile char C6[2]; + volatile char C7[2]; + volatile char C8[21]; + volatile char AOFFSET[2]; + volatile char BOFFSET[2]; + volatile char COFFSET[2]; + volatile char AMINIMUM; + volatile char AMAXIMUM; + volatile char BMINIMUM; + volatile char BMAXIMUM; + volatile char CMINIMUM; + volatile char CMAXIMUM; +}; + +/** AV8100 Video CEC message */ +struct av8100_CEC_message +{ + volatile char Identifier; + volatile char PhysicaladdressAB; + volatile char PhysicaladdressCD; + volatile char Bufferlength; + volatile char BufferData[16]; +}; + +/** AV8100 Video CEC message Readback Command */ +struct av8100_CEC_message_readback_command +{ + volatile char Identifier; +}; + +/** AV8100 Video DENC Command */ +struct av8100_DENC_command +{ + volatile char Identifier; + volatile char CVBSvideoformatoutputchoice ; + volatile char Standardselection; + volatile char ON_OFF; + volatile char Macrovision_ON_OFF; +}; + +/** AV8100 Video HDMI Command */ +struct av8100_HDMI_command +{ + volatile char Identifier; + volatile char OFF_ON_AVMUTE; + volatile char HDMI_DVI; + volatile char DVIcontrolbit; +}; + +/** AV8100 Video HDCP sendkey Command */ +struct av8100_HDCP_sendkey_command +{ + volatile char Identifier; + volatile char Keynumber; + volatile char Key[7]; +}; + +/** AV8100 Video HDCP management Command */ +struct av8100_HDCP_management_command +{ + volatile char Identifier; + volatile char RequestHDCPauthentication; + volatile char Requestencryptedtransmission; + volatile char OESS_EESS; +}; + +/** AV8100 Video Infoframe Command */ +struct av8100_Infoframe_command +{ + volatile char Identifier; + volatile char Infoframetype; + volatile char Infoframedata[30]; + volatile char InfoframeCRC; +}; + +/** AV8100 Video EDID section readback Command */ +struct av8100_EDIDsectionreadback_command +{ + volatile char Identifier; + volatile char EDIDaddress; + volatile char EDIDblocknumber; +}; + +/** AV8100 Video Pattern Generator Command */ +struct av8100_PatternGenerator_command +{ + volatile char Identifier; + volatile char Testtypeselection; + volatile char VideoPatterngeneratorselection; + volatile char AudioSound; +}; + +/** AV8100 Video Command return */ +struct av8100_command_return +{ + volatile char Identifier; + volatile char OK_FAIL; +}; + +/** AV8100 Video CEC messgae readback command */ +struct av8100_EDID_section_readback +{ + volatile char Identifier; + volatile char OK_FAIL; + volatile char EDID[128]; +}; + +typedef enum{ + AV8100_AUDIO_I2S_MODE, + AV8100_AUDIO_I2SDELAYED_MODE, /* I2S Mode by default*/ + AV8100_AUDIO_TDM_MODE /* 8 Channels by default*/ +} av8100_audio_if_format; + +typedef enum{ + AV8100_AUDIO_MUTE_DISABLE, + AV8100_AUDIO_MUTE_ENABLE +} av8100_audio_mute; + +typedef enum{ + AV8100_AUDIO_SLAVE, + AV8100_AUDIO_MASTER +} av8100_audio_if_mode; + +typedef enum{ + AV8100_AUDIO_LPCM_MODE, + AV8100_AUDIO_COMPRESS_MODE +} av8100_audio_format; + +typedef enum{ + AV8100_AUDIO_16BITS, + AV8100_AUDIO_20BITS, + AV8100_AUDIO_24BITS +} av8100_audio_word_length; + +typedef enum{ + AV8100_AUDIO_FREQ_32KHZ, + AV8100_AUDIO_FREQ_44_1KHZ, + AV8100_AUDIO_FREQ_48KHZ, + AV8100_AUDIO_FREQ_64KHZ, + AV8100_AUDIO_FREQ_88_2KHZ, + AV8100_AUDIO_FREQ_96KHZ, + AV8100_AUDIO_FREQ_128KHZ, + AV8100_AUDIO_FREQ_176_1KHZ, + AV8100_AUDIO_FREQ_192KHZ +} av8100_sample_freq; + + +typedef enum{ + AV8100_PATTERN_AUDIO_OFF, + AV8100_PATTERN_AUDIO_ON, + AV8100_PATTERN_AUDIO_I2S_MEM +} av8100_pattern_audio; + +typedef enum{ + AV8100_PATTERN_OFF, + AV8100_PATTERN_GENERATOR, + AV8100_PRODUCTION_TESTING +} av8100_pattern_type; + +typedef enum{ + AV8100_NO_PATTERN, + AV8100_PATTERN_VGA, + AV8100_PATTERN_720P, + AV8100_PATTERN_1080P +} av8100_pattern_format; + +typedef enum{ + AV8100_HDMI_OFF, + AV8100_HDMI_ON, + AV8100_HDMI_AVMUTE +} av8100_hdmi_mode; + +typedef enum{ + AV8100_HDMI, + AV8100_DVI +} av8100_hdmi_format; + +typedef enum{ + AV8100_DVI_CTRL_CTL0, + AV8100_DVI_CTRL_CTL1, + AV8100_DVI_CTRL_CTL2 +} av8100_DVI_format; + +typedef enum{ + AV8100_SYNC_POSITIVE, + AV8100_SYNC_NEGATIVE +} av8100_video_sync_pol; + +typedef enum{ + + AV8100_INPUT_PIX_RGB565, + AV8100_INPUT_PIX_RGB666, + AV8100_INPUT_PIX_RGB666P, + AV8100_INPUT_PIX_RGB888, + AV8100_INPUT_PIX_YCBCR422 +} av8100_pixel_format; + +typedef enum{ + AV8100_TE_OFF, /* NO TE*/ + AV8100_TE_DSI_LANE, /* TE generated on DSI lane */ + AV8100_TE_IT_LINE, /* TE generated on IT line (GPIO) */ + AV8100_TE_DSI_IT /* TE generatedon both DSI lane & IT line*/ +} av8100_te_config; + +typedef enum{ + + AV8100_DATA_LANES_USED_0, /* 0 DSI data lane connected*/ + AV8100_DATA_LANES_USED_1, /* 1 DSI data lane connected */ + AV8100_DATA_LANES_USED_2, /* 2 DSI data lane connected */ + AV8100_DATA_LANES_USED_3, /* 3 DSI data lane connected */ + AV8100_DATA_LANES_USED_4 /* 4 DSI data lane connected */ +} av8100_dsi_nb_data_lane; + +typedef enum{ + + AV8100_VIDEO_INTERLACE, + AV8100_VIDEO_PROGRESSIVE +} av8100_video_mode; + +typedef enum{ + + AV8100_HDMI_DSI_OFF, + AV8100_HDMI_DSI_COMMAND_MODE, + AV8100_HDMI_DSI_VIDEO_MODE +} av8100_dsi_mode; + +/* AV8100 video modes */ +typedef enum{ + AV8100_CUSTOM, + AV8100_CEA1_640X480P_59_94HZ, + AV8100_CEA2_3_720X480P_59_94HZ, // new + AV8100_CEA4_1280X720P_60HZ, + AV8100_CEA5_1920X1080I_60HZ, + AV8100_CEA6_7_NTSC_60HZ, //new + AV8100_CEA14_15_480p_60HZ, //new + AV8100_CEA16_1920X1080P_60HZ, //new + AV8100_CEA17_18_720X576P_50HZ, //new + AV8100_CEA19_1280X720P_50HZ, + AV8100_CEA20_1920X1080I_50HZ, + AV8100_CEA21_22_576I_PAL_50HZ, //new + AV8100_CEA29_30_576P_50HZ, //new + AV8100_CEA31_1920x1080P_50Hz, //new + AV8100_CEA32_1920X1080P_24HZ, + AV8100_CEA33_1920X1080P_25HZ, + AV8100_CEA34_1920X1080P_30HZ, + AV8100_CEA60_1280X720P_24HZ, + AV8100_CEA61_1280X720P_25HZ, + AV8100_CEA62_1280X720P_30HZ, + AV8100_VESA9_800X600P_60_32HZ, + AV8100_VESA14_848X480P_60HZ, + AV8100_VESA16_1024X768P_60HZ, + AV8100_VESA22_1280X768P_59_99HZ, + AV8100_VESA23_1280X768P_59_87HZ, + AV8100_VESA27_1280X800P_59_91HZ, + AV8100_VESA28_1280X800P_59_81HZ, + AV8100_VESA39_1360X768P_60_02HZ, + AV8100_VESA81_1366X768P_59_79HZ, + AV8100_VIDEO_OUTPUT_CEA_VESA_MAX +} av8100_output_CEA_VESA; + +/** AV8100 internal register access structure*/ +struct av8100_register +{ + char value; + char offset; +}; + +/** AV8100 command configuration registers access structure*/ +struct av8100_command_register +{ + unsigned char cmd_id; /* input */ + unsigned char buf_len; /* input, output */ + unsigned char buf[128]; /* input, output */ + unsigned char return_status; /* output */ +}; + +/* IOCTL return status */ +#define HDMI_COMMAND_RETURN_STATUS_OK 0 +#define HDMI_COMMAND_RETURN_STATUS_FAIL 1 + +#define HDMI_REQUEST_FOR_REVOCATION_LIST_INPUT 2 +#define HDMI_CEC_MESSAGE_READBACK_MAXSIZE 16 + +/** AV8100 status structure*/ +struct av8100_status +{ + char av8100_state; + char av8100_plugin_status; +}; + +/** Maximum size of the structure need to passed to AV8100 */ + +#define AV8100_IOC_MAGIC 0xcc + +/** IOCTL Operations for accessing information from AV8100 */ + +#define IOC_AV8100_READ_REGISTER _IOWR(AV8100_IOC_MAGIC,1,struct av8100_register) +#define IOC_AV8100_WRITE_REGISTER _IOWR(AV8100_IOC_MAGIC,2,struct av8100_register) +#define IOC_AV8100_SEND_CONFIGURATION_COMMAND _IOWR(AV8100_IOC_MAGIC,3,struct av8100_command_register) +//#define IOC_AV8100_READ_CONFIGURATION_COMMAND _IOWR(AV8100_IOC_MAGIC,4,struct av8100_command_register) +#define IOC_AV8100_GET_STATUS _IOWR(AV8100_IOC_MAGIC,4,struct av8100_status) +#define IOC_AV8100_ENABLE _IOWR(AV8100_IOC_MAGIC,5,struct av8100_status) +#define IOC_AV8100_DISABLE _IOWR(AV8100_IOC_MAGIC,6,struct av8100_status) +#define IOC_AV8100_SET_VIDEO_FORMAT _IOWR(AV8100_IOC_MAGIC,7,struct av8100_status) +#define IOC_AV8100_HDMI_ON _IOWR(AV8100_IOC_MAGIC,8,struct av8100_status) +#define IOC_AV8100_HDMI_OFF _IOWR(AV8100_IOC_MAGIC,9,struct av8100_status) + +#define AV8100_IOC_MAXNR (1) + +#ifdef _cplusplus +} +#endif /* _cplusplus */ + +#endif /* !defined(__AV8100_H) */ diff --git a/arch/arm/mach-ux500/include/mach/av8100_fw.h b/arch/arm/mach-ux500/include/mach/av8100_fw.h new file mode 100755 index 00000000000..94c913dddb5 --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/av8100_fw.h @@ -0,0 +1,1050 @@ +/*---------------------------------------------------------------------------*/ +/* © copyright STEricsson,2009. All rights reserved. For */ +/* information, STEricsson reserves the right to license */ +/* this software concurrently under separate license conditions. */ +/* */ +/* This program is free software; you can redistribute it and/or modify it */ +/* under the terms of the GNU Lesser General Public License as published */ +/* by the Free Software Foundation; either version 2.1 of the License, */ +/* or (at your option)any later version. */ +/* */ +/* This program is distributed in the hope that it will be useful, but */ +/* WITHOUT ANY WARRANTY; without even the implied warranty of */ +/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See */ +/* the GNU Lesser General Public License for more details. */ +/* */ +/* You should have received a copy of the GNU Lesser General Public License */ +/* along with this program. If not, see <http://www.gnu.org/licenses/>. */ +/*---------------------------------------------------------------------------*/ + +/* AV8100 Firmware version : V3.02 */ +#define fw_size 16384 +char ReceiveTab[fw_size]; +char TransmitTab[fw_size]; +char av8100_fw_buff[fw_size] = { +0x80,0xfe,0xcb,0xfe,0xbc,0xc2,0x73,0xc4,0x73,0xc4,0xc9,0xc5,0x72,0xc3,0xce,0xc5, +0x16,0xc7,0xd0,0xc8,0xe5,0xc8,0xf6,0xc8,0x08,0xc9,0x1b,0xc9,0x20,0xc9,0x25,0xc9, +0x2a,0xc9,0x2f,0xc9,0x44,0xc9,0x7e,0xc9,0xfa,0xc9,0xb6,0xc2,0xb6,0xc2,0xb7,0xc2, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x81,0xea,0xad,0xec,0xad, +0x38,0x20,0x1b,0x72,0x80,0x81,0x4d,0x51,0x4d,0x51,0x4d,0x51,0x4d,0x51,0x4d,0x51, +0x4d,0x51,0xb4,0x20,0xf4,0x2a,0x5a,0x90,0x82,0xfe,0xcd,0x80,0x00,0xaf,0x72,0x93, +0xa3,0x20,0x5f,0x90,0x80,0x80,0x97,0x90,0x8d,0x20,0x0f,0xab,0x01,0xa6,0x88,0x89, +0x90,0x96,0xad,0x97,0x90,0x9a,0xad,0x8b,0x93,0x9e,0xad,0x97,0x90,0xa2,0xad,0x80, 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STEricsson,2009. All rights reserved. For */ +/* information, STEricsson reserves the right to license */ +/* this software concurrently under separate license conditions. */ +/* */ +/* This program is free software; you can redistribute it and/or modify it */ +/* under the terms of the GNU Lesser General Public License as published */ +/* by the Free Software Foundation; either version 2.1 of the License, */ +/* or (at your option)any later version. */ +/* */ +/* This program is distributed in the hope that it will be useful, but */ +/* WITHOUT ANY WARRANTY; without even the implied warranty of */ +/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See */ +/* the GNU Lesser General Public License for more details. */ +/* */ +/* You should have received a copy of the GNU Lesser General Public License */ +/* along with this program. If not, see <http://www.gnu.org/licenses/>. */ +/*---------------------------------------------------------------------------*/ + +#include <mach/av8100.h> + +/* defines for av8100_ */ +#define av8100_command_offset 0x10 +#define AV8100_COMMAND_MAX_LENGTH 0x81 +#define GPIO_AV8100_RSTN 196 +#define GPIO_AV8100_INT 192 +#define AV8100_DRIVER_MINOR_NUMBER 240 + + +#define HDMI_HOTPLUG_INTERRUPT 0x1 +#define HDMI_HOTPLUG_INTERRUPT_MASK 0xFE +#define CVBS_PLUG_INTERRUPT 0x2 +#define CVBS_PLUG_INTERRUPT_MASK 0xFD +#define TE_INTERRUPT_MASK 0x40 +#define UNDER_OVER_FLOW_INTERRUPT_MASK 0x20 + +#define REG_16_8_LSB(p) (unsigned char)(p & 0xFF) +#define REG_16_8_MSB(p) (unsigned char)((p & 0xFF00)>>8) +#define REG_32_8_MSB(p) (unsigned char)((p & 0xFF000000)>>24) +#define REG_32_8_MMSB(p) (unsigned char)((p & 0x00FF0000)>>16) +#define REG_32_8_MLSB(p) (unsigned char)((p & 0x0000FF00)>>8) +#define REG_32_8_LSB(p) (unsigned char)(p & 0x000000FF) + +/** + * struct av8100_cea - CEA(consumer electronic access) standard structure + * @cea_id: + * @cea_nb: + * @vtotale: + **/ + + typedef struct { + char cea_id[40] ; + int cea_nb ; + int vtotale; + int vactive; + int vsbp ; + int vslen ; + int vsfp; + char vpol[5]; + int htotale; + int hactive; + int hbp ; + int hslen ; + int hfp; + int frequence; + char hpol[5]; + int reg_line_duration; + int blkoel_duration; + int uix4; + int pll_mult; + int pll_div; +}av8100_cea; + +/** + * struct av8100_data - av8100_ internal structure + * @client: pointer to i2c client + * @work: work_struct scheduled during bottom half + * @sem: semaphore used for data protection + * @device_type: hdmi or cvbs + * @edid: extended display identification data + **/ +struct av8100_data{ + struct i2c_client *client; + struct work_struct work; + struct semaphore sem; + char device_type; + char edid[127]; +}; + +/** + * struct av8100_platform_data - av8100_ platform data + * @irq: irq num + **/ +struct av8100_platform_data { + unsigned gpio_base; + int irq; +}; +/** + * struct av8100_video_input_format_cmd - video input format structure + * @dsi_input_mode: + * @input_pixel_format: + * @total_horizontal_pixel: + **/ +typedef struct { + av8100_dsi_mode dsi_input_mode; + av8100_pixel_format input_pixel_format; + unsigned short total_horizontal_pixel; /*number of total horizontal pixels in the frame*/ + unsigned short total_horizontal_active_pixel; /*number of total horizontal active pixels in the frame*/ + unsigned short total_vertical_lines; /*number of total vertical lines in the frame*/ + unsigned short total_vertical_active_lines; /*number of total vertical active lines*/ + av8100_video_mode video_mode; + av8100_dsi_nb_data_lane nb_data_lane; + unsigned char nb_virtual_ch_command_mode; + unsigned char nb_virtual_ch_video_mode; + unsigned short TE_line_nb; /* Tearing effect line number*/ + av8100_te_config TE_config; + unsigned long master_clock_freq; /* Master clock frequency in HZ */ +} av8100_video_input_format_cmd; +/** + * struct av8100_video_output_format_cmd - video output format structure + * @dsi_input_mode: + * @input_pixel_format: + * @total_horizontal_pixel: + **/ +typedef struct { + av8100_output_CEA_VESA video_output_cea_vesa; + av8100_video_sync_pol vsync_polarity; + av8100_video_sync_pol hsync_polarity; + unsigned short total_horizontal_pixel; /*number of total horizontal pixels in the frame*/ + unsigned short total_horizontal_active_pixel; /*number of total horizontal active pixels in the frame*/ + unsigned short total_vertical_in_half_lines; /*number of total vertical lines in the frame*/ + unsigned short total_vertical_active_in_half_lines; /*number of total vertical active lines*/ + unsigned short hsync_start_in_pixel; + unsigned short hsync_length_in_pixel; + unsigned short vsync_start_in_half_line; + unsigned short vsync_length_in_half_line; + unsigned long pixel_clock_freq_Hz; +} av8100_video_output_format_cmd; +/** + * struct av8100_pattern_generator_cmd - pattern generator format structure + * @pattern_type: + * @pattern_video_format: + * @pattern_audio_mode: + **/ +typedef struct { + av8100_pattern_type pattern_type; + av8100_pattern_format pattern_video_format; + av8100_pattern_audio pattern_audio_mode; +} av8100_pattern_generator_cmd; +/** + * struct av8100_audio_input_format_cmd - audio input format structure + * @audio_input_if_format: + * @i2s_input_nb: + * @sample_audio_freq: + **/ +typedef struct { + av8100_audio_if_format audio_input_if_format; /* mode of the MSP*/ + unsigned char i2s_input_nb; /* 0, 1 2 3 4*/ + av8100_sample_freq sample_audio_freq; + av8100_audio_word_length audio_word_lg; + av8100_audio_format audio_format; + av8100_audio_if_mode audio_if_mode; + av8100_audio_mute audio_mute; +} av8100_audio_input_format_cmd; +/** + * struct av8100_video_scaling_format_cmd - video scaling format structure + * @h_start_in_pixel: + * @h_stop_in_pixel: + * @v_start_in_line: + **/ +typedef struct { + unsigned short h_start_in_pixel; + unsigned short h_stop_in_pixel; + unsigned short v_start_in_line; + unsigned short v_stop_in_line; +} av8100_video_scaling_format_cmd; +/** + * struct av8100_hdmi_cmd - hdmi command structure + * @hdmi_mode: + * @hdmi_format: + * @dvi_format: + **/ +typedef struct { + av8100_hdmi_mode hdmi_mode; + av8100_hdmi_format hdmi_format; + av8100_DVI_format dvi_format; /* used only if HDMI_format = DVI*/ +} av8100_hdmi_cmd; +/* STWav8100 Private functions */ diff --git a/arch/arm/mach-ux500/include/mach/bit_mask.h b/arch/arm/mach-ux500/include/mach/bit_mask.h new file mode 100755 index 00000000000..9487dff5242 --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/bit_mask.h @@ -0,0 +1,110 @@ +/*---------------------------------------------------------------------------*/ +/* Copyright (C) STEricsson 2009. */ +/* */ +/* This program is free software; you can redistribute it and/or modify it */ +/* under the terms of the GNU Lesser General Public License as published */ +/* by the Free Software Foundation; either version 2.1 of the License, */ +/* or (at your option)any later version. */ +/* */ +/* This program is distributed in the hope that it will be useful, but */ +/* WITHOUT ANY WARRANTY; without even the implied warranty of */ +/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See */ +/* the GNU Lesser General Public License for more details. */ +/* */ +/* You should have received a copy of the GNU Lesser General Public License */ +/* along with this program. If not, see <http://www.gnu.org/licenses/>. */ +/*---------------------------------------------------------------------------*/ + +#ifndef _BITMASK_H_ +#define _BITMASK_H_ + +/*----------------------------------------------------------------------------- + * Bit mask definition + *---------------------------------------------------------------------------*/ +#define TRUE 0x1 +#define FALSE 0x0 +#define MASK_NULL8 0x00 +#define MASK_NULL16 0x0000 +#define MASK_NULL32 0x00000000 +#define MASK_ALL8 0xFF +#define MASK_ALL16 0xFFFF +#define MASK_ALL32 0xFFFFFFFF + +#define MASK_BIT0 (1UL<<0) +#define MASK_BIT1 (1UL<<1) +#define MASK_BIT2 (1UL<<2) +#define MASK_BIT3 (1UL<<3) +#define MASK_BIT4 (1UL<<4) +#define MASK_BIT5 (1UL<<5) +#define MASK_BIT6 (1UL<<6) +#define MASK_BIT7 (1UL<<7) +#define MASK_BIT8 (1UL<<8) +#define MASK_BIT9 (1UL<<9) +#define MASK_BIT10 (1UL<<10) +#define MASK_BIT11 (1UL<<11) +#define MASK_BIT12 (1UL<<12) +#define MASK_BIT13 (1UL<<13) +#define MASK_BIT14 (1UL<<14) +#define MASK_BIT15 (1UL<<15) +#define MASK_BIT16 (1UL<<16) +#define MASK_BIT17 (1UL<<17) +#define MASK_BIT18 (1UL<<18) +#define MASK_BIT19 (1UL<<19) +#define MASK_BIT20 (1UL<<20) +#define MASK_BIT21 (1UL<<21) +#define MASK_BIT22 (1UL<<22) +#define MASK_BIT23 (1UL<<23) +#define MASK_BIT24 (1UL<<24) +#define MASK_BIT25 (1UL<<25) +#define MASK_BIT26 (1UL<<26) +#define MASK_BIT27 (1UL<<27) +#define MASK_BIT28 (1UL<<28) +#define MASK_BIT29 (1UL<<29) +#define MASK_BIT30 (1UL<<30) +#define MASK_BIT31 (1UL<<31) + +/*----------------------------------------------------------------------------- + * quartet shift definition + *---------------------------------------------------------------------------*/ +#define MASK_QUARTET (0xFUL) +#define SHIFT_QUARTET0 0 +#define SHIFT_QUARTET1 4 +#define SHIFT_QUARTET2 8 +#define SHIFT_QUARTET3 12 +#define SHIFT_QUARTET4 16 +#define SHIFT_QUARTET5 20 +#define SHIFT_QUARTET6 24 +#define SHIFT_QUARTET7 28 +#define MASK_QUARTET0 (MASK_QUARTET << SHIFT_QUARTET0) +#define MASK_QUARTET1 (MASK_QUARTET << SHIFT_QUARTET1) +#define MASK_QUARTET2 (MASK_QUARTET << SHIFT_QUARTET2) +#define MASK_QUARTET3 (MASK_QUARTET << SHIFT_QUARTET3) +#define MASK_QUARTET4 (MASK_QUARTET << SHIFT_QUARTET4) +#define MASK_QUARTET5 (MASK_QUARTET << SHIFT_QUARTET5) +#define MASK_QUARTET6 (MASK_QUARTET << SHIFT_QUARTET6) +#define MASK_QUARTET7 (MASK_QUARTET << SHIFT_QUARTET7) + +/*----------------------------------------------------------------------------- + * Byte shift definition + *---------------------------------------------------------------------------*/ +#define MASK_BYTE (0xFFUL) +#define SHIFT_BYTE0 0 +#define SHIFT_BYTE1 8 +#define SHIFT_BYTE2 16 +#define SHIFT_BYTE3 24 +#define MASK_BYTE0 (MASK_BYTE << SHIFT_BYTE0) +#define MASK_BYTE1 (MASK_BYTE << SHIFT_BYTE1) +#define MASK_BYTE2 (MASK_BYTE << SHIFT_BYTE2) +#define MASK_BYTE3 (MASK_BYTE << SHIFT_BYTE3) + +/*----------------------------------------------------------------------------- + * Halfword shift definition + *---------------------------------------------------------------------------*/ +#define MASK_HALFWORD (0xFFFFUL) +#define SHIFT_HALFWORD0 0 +#define SHIFT_HALFWORD1 16 +#define MASK_HALFWORD0 (MASK_HALFWORD << SHIFT_HALFWORD0) +#define MASK_HALFWORD1 (MASK_HALFWORD << SHIFT_HALFWORD1) + +#endif + diff --git a/arch/arm/mach-ux500/include/mach/bits.h b/arch/arm/mach-ux500/include/mach/bits.h new file mode 100755 index 00000000000..0f0e4edd1cc --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/bits.h @@ -0,0 +1,64 @@ +/*----------------------------------------------------------------------------------*/ +/* copyright STMicroelectronics, 2007. */ +/* */ +/* This program is free software; you can redistribute it and/or modify it under */ +/* the terms of the GNU General Public License as published by the Free */ +/* Software Foundation; either version 2.1 of the License, or (at your option) */ +/* any later version. */ +/* */ +/* This program is distributed in the hope that it will be useful, but WITHOUT */ +/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS */ +/* FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. */ +/* */ +/* You should have received a copy of the GNU General Public License */ +/* along with this program. If not, see <http://www.gnu.org/licenses/>. */ +/*----------------------------------------------------------------------------------*/ + + + +/* DO NOT EDIT!! - this file automatically generated + * from .s file by awk -f s2h.awk + */ +/* Bit field definitions + * Copyright (C) ARM Limited 1998. All rights reserved. + */ + +#ifndef __bits_h +#define __bits_h 1 + +#define BIT0 0x00000001 +#define BIT1 0x00000002 +#define BIT2 0x00000004 +#define BIT3 0x00000008 +#define BIT4 0x00000010 +#define BIT5 0x00000020 +#define BIT6 0x00000040 +#define BIT7 0x00000080 +#define BIT8 0x00000100 +#define BIT9 0x00000200 +#define BIT10 0x00000400 +#define BIT11 0x00000800 +#define BIT12 0x00001000 +#define BIT13 0x00002000 +#define BIT14 0x00004000 +#define BIT15 0x00008000 +#define BIT16 0x00010000 +#define BIT17 0x00020000 +#define BIT18 0x00040000 +#define BIT19 0x00080000 +#define BIT20 0x00100000 +#define BIT21 0x00200000 +#define BIT22 0x00400000 +#define BIT23 0x00800000 +#define BIT24 0x01000000 +#define BIT25 0x02000000 +#define BIT26 0x04000000 +#define BIT27 0x08000000 +#define BIT28 0x10000000 +#define BIT29 0x20000000 +#define BIT30 0x40000000 +#define BIT31 0x80000000 + +#endif + +/* END */ diff --git a/arch/arm/mach-ux500/include/mach/clkdev.h b/arch/arm/mach-ux500/include/mach/clkdev.h new file mode 100755 index 00000000000..04b37a89801 --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/clkdev.h @@ -0,0 +1,7 @@ +#ifndef __ASM_MACH_CLKDEV_H +#define __ASM_MACH_CLKDEV_H + +#define __clk_get(clk) ({ 1; }) +#define __clk_put(clk) do { } while (0) + +#endif diff --git a/arch/arm/mach-ux500/include/mach/db5500-regs.h b/arch/arm/mach-ux500/include/mach/db5500-regs.h new file mode 100644 index 00000000000..474f6d3d968 --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/db5500-regs.h @@ -0,0 +1,96 @@ +/* + * Copyright (C) 2010 ST-Ericsson + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __MACH_DB5500_REGS_H +#define __MACH_DB5500_REGS_H + +#define U5500_PER1_BASE 0xA0020000 +#define U5500_PER2_BASE 0xA0010000 +#define U5500_PER3_BASE 0x80140000 +#define U5500_PER4_BASE 0x80150000 +#define U5500_PER5_BASE 0x80100000 +#define U5500_PER6_BASE 0x80120000 + +#define U5500_GIC_DIST_BASE 0xA0411000 +#define U5500_GIC_CPU_BASE 0xA0410100 +#define U5500_DMA_BASE 0x90030000 +#define U5500_MCDE_BASE 0xA0400000 +#define U5500_MODEM_BASE 0xB0000000 +#define U5500_L2CC_BASE 0xA0412000 +#define U5500_SCU_BASE 0xA0410000 +#define U5500_DSI1_BASE 0xA0401000 +#define U5500_DSI2_BASE 0xA0402000 +#define U5500_SIA_BASE 0xA0100000 +#define U5500_SVA_BASE 0x80200000 +#define U5500_HSEM_BASE 0xA0000000 +#define U5500_NAND0_BASE 0x60000000 +#define U5500_NAND1_BASE 0x70000000 +#define U5500_TWD_BASE 0xa0410600 +#define U5500_B2R2_BASE 0xa0200000 + +#define U5500_FSMC_BASE (U5500_PER1_BASE + 0x0000) +#define U5500_SDI0_BASE (U5500_PER1_BASE + 0x1000) +#define U5500_SDI2_BASE (U5500_PER1_BASE + 0x2000) +#define U5500_UART0_BASE (U5500_PER1_BASE + 0x3000) +#define U5500_I2C1_BASE (U5500_PER1_BASE + 0x4000) +#define U5500_MSP0_BASE (U5500_PER1_BASE + 0x5000) +#define U5500_GPIO0_BASE (U5500_PER1_BASE + 0xE000) +#define U5500_CLKRST1_BASE (U5500_PER1_BASE + 0xF000) + +#define U5500_USBOTG_BASE (U5500_PER2_BASE + 0x0000) +#define U5500_GPIO1_BASE (U5500_PER2_BASE + 0xE000) +#define U5500_CLKRST2_BASE (U5500_PER2_BASE + 0xF000) + +#define U5500_KEYPAD_BASE (U5500_PER3_BASE + 0x0000) +#define U5500_PWM_BASE (U5500_PER3_BASE + 0x1000) +#define U5500_GPIO3_BASE (U5500_PER3_BASE + 0xE000) +#define U5500_CLKRST3_BASE (U5500_PER3_BASE + 0xF000) + +#define U5500_BACKUPRAM0_BASE (U5500_PER4_BASE + 0x0000) +#define U5500_BACKUPRAM1_BASE (U5500_PER4_BASE + 0x1000) +#define U5500_RTT0_BASE (U5500_PER4_BASE + 0x2000) +#define U5500_RTT1_BASE (U5500_PER4_BASE + 0x3000) +#define U5500_RTC_BASE (U5500_PER4_BASE + 0x4000) +#define U5500_SCR_BASE (U5500_PER4_BASE + 0x5000) +#define U5500_DMC_BASE (U5500_PER4_BASE + 0x6000) +#define U5500_PRCMU_BASE (U5500_PER4_BASE + 0x7000) +#define U5500_MSP1_BASE (U5500_PER4_BASE + 0x9000) +#define U5500_GPIO2_BASE (U5500_PER4_BASE + 0xA000) +#define U5500_CDETECT_BASE (U5500_PER4_BASE + 0xF000) + +#define U5500_SPI0_BASE (U5500_PER5_BASE + 0x0000) +#define U5500_SPI1_BASE (U5500_PER5_BASE + 0x1000) +#define U5500_SPI2_BASE (U5500_PER5_BASE + 0x2000) +#define U5500_SPI3_BASE (U5500_PER5_BASE + 0x3000) +#define U5500_UART1_BASE (U5500_PER5_BASE + 0x4000) +#define U5500_UART2_BASE (U5500_PER5_BASE + 0x5000) +#define U5500_UART3_BASE (U5500_PER5_BASE + 0x6000) +#define U5500_SDI1_BASE (U5500_PER5_BASE + 0x7000) +#define U5500_SDI3_BASE (U5500_PER5_BASE + 0x8000) +#define U5500_SDI4_BASE (U5500_PER5_BASE + 0x9000) +#define U5500_I2C2_BASE (U5500_PER5_BASE + 0xA000) +#define U5500_I2C3_BASE (U5500_PER5_BASE + 0xB000) +#define U5500_MSP2_BASE (U5500_PER5_BASE + 0xC000) +#define U5500_IRDA_BASE (U5500_PER5_BASE + 0xD000) +#define U5500_IRRC_BASE (U5500_PER5_BASE + 0x10000) +#define U5500_GPIO4_BASE (U5500_PER5_BASE + 0x1E000) +#define U5500_CLKRST5_BASE (U5500_PER5_BASE + 0x1F000) + +#define U5500_RNG_BASE (U5500_PER6_BASE + 0x0000) +#define U5500_HASH0_BASE (U5500_PER6_BASE + 0x1000) +#define U5500_HASH1_BASE (U5500_PER6_BASE + 0x2000) +#define U5500_PKA_BASE (U5500_PER6_BASE + 0x4000) +#define U5500_PKAM_BASE (U5500_PER6_BASE + 0x5000) +#define U5500_MTU0_BASE (U5500_PER6_BASE + 0x6000) +#define U5500_MTU1_BASE (U5500_PER6_BASE + 0x7000) +#define U5500_CR_BASE (U5500_PER6_BASE + 0x8000) +#define U5500_CRYP0_BASE (U5500_PER6_BASE + 0xA000) +#define U5500_CRYP1_BASE (U5500_PER6_BASE + 0xB000) +#define U5500_CLKRST6_BASE (U5500_PER6_BASE + 0xF000) + +#endif diff --git a/arch/arm/mach-ux500/include/mach/db8500-regs.h b/arch/arm/mach-ux500/include/mach/db8500-regs.h new file mode 100644 index 00000000000..e3d62b94ffc --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/db8500-regs.h @@ -0,0 +1,117 @@ +/* + * Copyright (C) 2010 ST-Ericsson + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __MACH_DB8500_REGS_H +#define __MACH_DB8500_REGS_H + +#define U8500_PER3_BASE 0x80000000 +#define U8500_STM_BASE 0x80100000 +#define U8500_STM_REG_BASE (U8500_STM_BASE+0xF000) +#define U8500_PER2_BASE 0x80110000 +#define U8500_PER1_BASE 0x80120000 +#define U8500_B2R2_BASE 0x80130000 +#define U8500_HSEM_BASE 0x80140000 +#define U8500_PER4_BASE 0x80150000 + +#define U8500_PER6_BASE 0xa03c0000 +#define U8500_PER5_BASE 0xa03e0000 +#define U8500_PER7_BASE_ED 0xa03d0000 + +#define U8500_SVA_BASE 0xa0100000 +#define U8500_SIA_BASE 0xa0200000 + +#define U8500_SGA_BASE 0xa0300000 +#define U8500_MCDE_BASE 0xa0350000 +#define U8500_DMA_BASE_ED 0xa0362000 +#define U8500_DMA_BASE 0x801C0000 /* v1 */ + +#define U8500_SCU_BASE 0xa0410000 +#define U8500_GIC_CPU_BASE 0xa0410100 +#define U8500_TWD_BASE 0xa0410600 +#define U8500_GIC_DIST_BASE 0xa0411000 +#define U8500_L2CC_BASE 0xa0412000 + +#define U8500_GPIO0_BASE (U8500_PER1_BASE + 0xE000) +#define U8500_GPIO1_BASE (U8500_PER3_BASE + 0xE000) +#define U8500_GPIO2_BASE (U8500_PER2_BASE + 0xE000) +#define U8500_GPIO3_BASE (U8500_PER5_BASE + 0x1E000) + +/* per7 base addressess */ +#define U8500_CR_BASE_ED (U8500_PER7_BASE_ED + 0x8000) +#define U8500_MTU0_BASE_ED (U8500_PER7_BASE_ED + 0xa000) +#define U8500_MTU1_BASE_ED (U8500_PER7_BASE_ED + 0xb000) +#define U8500_TZPC0_BASE_ED (U8500_PER7_BASE_ED + 0xc000) +#define U8500_CLKRST7_BASE (U8500_PER7_BASE_ED + 0xf000) + +#define U8500_UART0_BASE (U8500_PER1_BASE + 0x0000) +#define U8500_UART1_BASE (U8500_PER1_BASE + 0x1000) + +/* per6 base addressess */ +#define U8500_RNG_BASE (U8500_PER6_BASE + 0x0000) +#define U8500_PKA_BASE (U8500_PER6_BASE + 0x1000) +#define U8500_PKAM_BASE (U8500_PER6_BASE + 0x2000) +#define U8500_MTU0_BASE (U8500_PER6_BASE + 0x6000) /* v1 */ +#define U8500_MTU1_BASE (U8500_PER6_BASE + 0x7000) /* v1 */ +#define U8500_CR_BASE (U8500_PER6_BASE + 0x8000) /* v1 */ +#define U8500_CRYPTO0_BASE (U8500_PER6_BASE + 0xa000) +#define U8500_CRYPTO1_BASE (U8500_PER6_BASE + 0xb000) +#define U8500_CLKRST6_BASE (U8500_PER6_BASE + 0xf000) + +/* per5 base addressess */ +#define U8500_USBOTG_BASE (U8500_PER5_BASE + 0x00000) +#define U8500_CLKRST5_BASE (U8500_PER5_BASE + 0x1f000) + +/* per4 base addressess */ +#define U8500_BACKUPRAM0_BASE (U8500_PER4_BASE + 0x00000) +#define U8500_BACKUPRAM1_BASE (U8500_PER4_BASE + 0x01000) +#define U8500_RTT0_BASE (U8500_PER4_BASE + 0x02000) +#define U8500_RTT1_BASE (U8500_PER4_BASE + 0x03000) +#define U8500_RTC_BASE (U8500_PER4_BASE + 0x04000) +#define U8500_DMC_BASE (U8500_PER4_BASE + 0x06000) +#define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000) +#define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x0f000) + +/* per3 base addresses */ +#define U8500_FSMC_BASE (U8500_PER3_BASE + 0x0000) +#define U8500_SSP0_BASE (U8500_PER3_BASE + 0x2000) +#define U8500_SSP1_BASE (U8500_PER3_BASE + 0x3000) +#define U8500_I2C0_BASE (U8500_PER3_BASE + 0x4000) +#define U8500_SDI2_BASE (U8500_PER3_BASE + 0x5000) +#define U8500_SKE_BASE (U8500_PER3_BASE + 0x6000) +#define U8500_UART2_BASE (U8500_PER3_BASE + 0x7000) +#define U8500_SDI5_BASE (U8500_PER3_BASE + 0x8000) +#define U8500_CLKRST3_BASE (U8500_PER3_BASE + 0xf000) + +/* per2 base addressess */ +#define U8500_I2C3_BASE (U8500_PER2_BASE + 0x0000) +#define U8500_SPI2_BASE (U8500_PER2_BASE + 0x1000) +#define U8500_SPI1_BASE (U8500_PER2_BASE + 0x2000) +#define U8500_PWL_BASE (U8500_PER2_BASE + 0x3000) +#define U8500_SDI4_BASE (U8500_PER2_BASE + 0x4000) +#define U8500_MSP2_BASE (U8500_PER2_BASE + 0x7000) +#define U8500_SDI1_BASE (U8500_PER2_BASE + 0x8000) +#define U8500_SDI3_BASE (U8500_PER2_BASE + 0x9000) +#define U8500_SPI0_BASE (U8500_PER2_BASE + 0xa000) +#define U8500_HSIR_BASE (U8500_PER2_BASE + 0xb000) +#define U8500_HSIT_BASE (U8500_PER2_BASE + 0xc000) +#define U8500_CLKRST2_BASE (U8500_PER2_BASE + 0xf000) + +/* per1 base addresses */ +#define U8500_I2C1_BASE (U8500_PER1_BASE + 0x2000) +#define U8500_MSP0_BASE (U8500_PER1_BASE + 0x3000) +#define U8500_MSP1_BASE (U8500_PER1_BASE + 0x4000) +#define U8500_SDI0_BASE (U8500_PER1_BASE + 0x6000) +#define U8500_I2C2_BASE (U8500_PER1_BASE + 0x8000) +#define U8500_SPI3_BASE (U8500_PER1_BASE + 0x9000) +#define U8500_I2C4_BASE (U8500_PER1_BASE + 0xa000) +#define U8500_SLIM0_BASE (U8500_PER1_BASE + 0xb000) +#define U8500_CLKRST1_BASE (U8500_PER1_BASE + 0xf000) + +#define U8500_SHRM_GOP_INTERRUPT_BASE 0xB7C00040 + +#endif diff --git a/arch/arm/mach-ux500/include/mach/debug-macro.S b/arch/arm/mach-ux500/include/mach/debug-macro.S new file mode 100755 index 00000000000..9cec503ff01 --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/debug-macro.S @@ -0,0 +1,20 @@ +/* + * Debugging macro include header + * + * Copyright (C) 2009 ST-Ericsson + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +#include <mach/hardware.h> + + .macro addruart,rx + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 @MMU enabled? + ldreq \rx, =UX500_UART2_BASE @ no, physical address + ldrne \rx, =IO_ADDRESS(UX500_UART2_BASE) @ yes, virtual address + .endm + +#include <asm/hardware/debug-pl01x.S> diff --git a/arch/arm/mach-ux500/include/mach/debug.h b/arch/arm/mach-ux500/include/mach/debug.h new file mode 100755 index 00000000000..3567d7f5b38 --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/debug.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2009 STMicroelectronics + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + */ +#ifndef __INC_DBG_H +#define __INC_DBG_H + +/* Store a submitter ID, unique for each HCL. */ + +struct driver_debug_st { + int mtd; + int gpio; + int mmc; + int ssp; + int mtu; + int msp; + int spi; + int touch; + int dma; + int rtc; + int acodec; + int tourg; + int alsa; + int keypad; + int mcde; + int power; + int i2c; + int hsi; +}; + +#define stm_error(format, arg...) printk(KERN_ERR DRIVER_DEBUG_PFX ":ERROR " format "\n" , ## arg) +#define stm_warn(format, arg...) printk(KERN_WARNING DRIVER_DEBUG_PFX ":WARNING " format "\n" , ## arg) +#define stm_info(format, arg...) printk(KERN_INFO DRIVER_DEBUG_PFX ":INFO" format "\n" , ## arg) + + +#define stm_dbg(debug, format, arg...) (!(DRIVER_DEBUG)) ? ({do {} while(0); }) : debug == 1 ? (printk(DRIVER_DBG DRIVER_DEBUG_PFX ": " format "\n" , ## arg)) : ({do {} while (0); }) + +#define stm_dbg2(debug, format, arg...) (!(DRIVER_DEBUG)) ? ({do {} while(0); }) : debug == 2 ? (printk(DRIVER_DBG DRIVER_DEBUG_PFX ": " format "\n" , ## arg)) : ({do {} while (0); }) + +#define stm_dbg3(debug, format, arg...) (!(DRIVER_DEBUG)) ? ({do {} while(0); }) : debug == 3 ? (printk(DRIVER_DBG DRIVER_DEBUG_PFX ": " format "\n" , ## arg)) : ({do {} while (0); }) + +#define stm_dbg4(format, arg...) (DRIVER_DEBUG & 1) ? (printk(DRIVER_DBG DRIVER_DEBUG_PFX ": " format "\n" , ## arg)) : ({do {} while (0); }) + +extern struct driver_debug_st DBG_ST; +#endif + +/* __INC_DBG_H */ + +/* End of file - debug.h */ diff --git a/arch/arm/mach-ux500/include/mach/devices.h b/arch/arm/mach-ux500/include/mach/devices.h new file mode 100644 index 00000000000..0ffc1a05c3d --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/devices.h @@ -0,0 +1,72 @@ +/* + * Copyright (C) 2010 ST-Ericsson + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_DEVICES_H__ +#define __ASM_ARCH_DEVICES_H__ + +struct platform_device; +struct amba_device; + +void __init u8500_register_device(struct platform_device *dev, void *data); +void __init u8500_register_amba_device(struct amba_device *dev, void *data); + +extern struct amba_device u5500_gpio0_device; +extern struct amba_device u5500_gpio1_device; +extern struct amba_device u5500_gpio2_device; +extern struct amba_device u5500_gpio3_device; +extern struct amba_device u5500_gpio4_device; + +extern struct amba_device u8500_gpio0_device; +extern struct amba_device u8500_gpio1_device; +extern struct amba_device u8500_gpio2_device; +extern struct amba_device u8500_gpio3_device; + +extern struct platform_device u8500_msp0_device; +extern struct platform_device u8500_msp1_device; +extern struct platform_device u8500_msp2_device; +extern struct amba_device u8500_msp2_spi_device; +extern struct platform_device u8500_i2c0_device; +extern struct platform_device ux500_i2c1_device; +extern struct platform_device ux500_i2c2_device; +extern struct platform_device ux500_i2c3_device; +extern struct platform_device u8500_i2c4_device; +extern struct platform_device u8500_mcde2_device; +extern struct platform_device u8500_mcde3_device; +extern struct platform_device u8500_mcde1_device; +extern struct platform_device u8500_mcde0_device; +extern struct platform_device u8500_hsit_device; +extern struct platform_device u8500_hsir_device; +extern struct platform_device u8500_shrm_device; +extern struct platform_device ux500_b2r2_device; +extern struct platform_device u8500_pmem_device; +extern struct platform_device u8500_pmem_mio_device; +extern struct platform_device u8500_pmem_hwb_device; +extern struct amba_device ux500_rtc_device; +extern struct platform_device ux500_dma_device; +extern struct amba_device u8500_ssp0_device; +extern struct amba_device u8500_ssp1_device; +extern struct amba_device ux500_spi0_device; +extern struct amba_device ux500_sdi4_device; +extern struct amba_device ux500_sdi0_device; +extern struct amba_device ux500_sdi1_device; +extern struct amba_device ux500_sdi2_device; +extern struct platform_device u8500_ab8500_device; +extern struct platform_device ux500_musb_device; +extern struct amba_device ux500_uart0_device; +extern struct amba_device ux500_uart1_device; +extern struct amba_device ux500_uart2_device; + +/* + * Do not use inside drivers. Check it in the board file and alter platform + * data. + */ +extern int platform_id; +#define MOP500_PLATFORM_ID 0 +#define HREF_PLATFORM_ID 1 + +#endif diff --git a/arch/arm/mach-ux500/include/mach/dma.h b/arch/arm/mach-ux500/include/mach/dma.h new file mode 100755 index 00000000000..269dd4c8108 --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/dma.h @@ -0,0 +1,106 @@ +/* + * Copyright 2009 ST-Ericsson. + * Copyright 2009 STMicroelectronics. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + */ +#ifndef __INC_ASM_ARCH_DMA_H +#define __INC_ASM_ARCH_DMA_H + +#define MAX_DMA_CHANNELS 32 +#ifndef __ASSEMBLY__ +#include <asm/scatterlist.h> + +typedef unsigned int dmach_t; +typedef unsigned int dmamode_t; + +enum dma_flow_controller { + DMA_IS_FLOW_CNTLR, + PERIPH_IS_FLOW_CNTLR +}; +enum { + DMA_FALSE, + DMA_TRUE +}; + +enum dma_xfer_dir { + MEM_TO_MEM, + MEM_TO_PERIPH, + PERIPH_TO_MEM, + PERIPH_TO_PERIPH +}; + +enum dma_endianess { + DMA_LITTLE_ENDIAN, + DMA_BIG_ENDIAN +}; +enum dma_event { + XFER_COMPLETE, + XFER_ERROR +}; +typedef void (*dma_callback_t)(void *data, enum dma_event event); + +#include <mach/dma_40-8500.h> + +/** + * struct stm_dma_pipe_info - Structure to be filled by client drivers. + * + * @reserve_channel: Whether you want to reserve the channel + * @dir: MEM 2 MEM, PERIPH 2 MEM , MEM 2 PERIPH, PERIPH 2 PERIPH + * @flow_cntlr: who is flow controller (Device or DMA) + * @phys_chan_id: physical channel ID on which this channel will execute + * @data: data of callback handler + * @callback: callback handler registered by client + * @channel_type: std/ext, basic/log/operational, priority, security + * @src_dev_type: Src device type + * @dst_dev_type: Dest device type + * @src_addr: Source address + * @dst_addr: Dest address + * @src_info: Parameters for Source half channel + * @dst_info: Parameters for Dest half channel + * + * + * This structure has to be filled by the client drivers, before requesting + * a DMA pipe. This information is used by the Driver to allocate or + * reserve an appropriate DMA channel for this client. + * + */ +struct stm_dma_pipe_info { + unsigned int reserve_channel; + enum dma_xfer_dir dir; + enum dma_flow_controller flow_cntlr; + enum dma_chan_id phys_chan_id; + void *data; + dma_callback_t callback; + unsigned int channel_type; + enum dma_src_dev_type src_dev_type; + enum dma_dest_dev_type dst_dev_type; + void *src_addr; + void *dst_addr; + struct dma_half_channel_info src_info; + struct dma_half_channel_info dst_info; +}; + +extern int stm_configure_dma_channel(int channel, + struct stm_dma_pipe_info *info); +extern int stm_request_dma(int *channel, struct stm_dma_pipe_info *info); +extern void stm_free_dma(int channel); +extern int stm_set_callback_handler(int channel, void *callback_handler, + void *data); +extern int stm_enable_dma(int channel); +extern void stm_disable_dma(int channel); +extern int stm_pause_dma(int channel); +extern void stm_unpause_dma(int channel); +extern void stm_set_dma_addr(int channel, void *src_addr , void *dst_addr); +extern void stm_set_dma_count(int channel, int count); +extern void stm_set_dma_sg(int channel, struct scatterlist *sg, + int nr_sg, int type); + +extern int stm_dma_residue(int channel); + +#endif /*__ASSEMBLY__*/ +#endif /* __INC_ASM_ARCH_DMA_H */ +/* End of file - dma.h */ + diff --git a/arch/arm/mach-ux500/include/mach/dma_40-8500.h b/arch/arm/mach-ux500/include/mach/dma_40-8500.h new file mode 100755 index 00000000000..7e0c15c7752 --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/dma_40-8500.h @@ -0,0 +1,788 @@ +/*----------------------------------------------------------------------------*/ +/* copyright STMicroelectronics, 2008. */ +/* */ +/* This program is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU General Public License as published by */ +/* the Free Software Foundation; either version 2.1 of the License, or */ +/* (at your option) any later version. */ +/* */ +/* This program is distributed in the hope that it will be useful, */ +/* but WITHOUT ANY WARRANTY; without even the implied warranty of */ +/* MERCHANTABILITY or FITNESS */ +/* FOR A PARTICULAR PURPOSE. See the GNU General Public License for */ +/* more details. */ +/* */ +/* You should have received a copy of the GNU General Public License */ +/* along with this program. If not, see <http://www.gnu.org/licenses/>. */ +/*----------------------------------------------------------------------------*/ + +#ifndef __INC_ARCH_ARM_SOC_DMA_H +#define __INC_ARCH_ARM_SOC_DMA_H +#include <linux/spinlock.h> + +/******************************************************************************/ +#define MEM_WRITE_BITS(reg, val, mask, sb) \ + ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask)))) +#define MEM_READ_BITS(reg, mask, sb) \ + (((reg) & (mask)) >> (sb)) + +#define REG_WR_BITS_1(reg, val, mask, sb) \ + iowrite32(((val)<<(sb) | (~mask)), reg) +#define REG_WR_BITS(reg, val, mask, sb) \ + iowrite32(((ioread32(reg) & ~(mask)) | (((val)<<(sb)) & (mask))), reg) +#define REG_RD_BITS(reg, mask, sb) (((ioread32(reg)) & (mask)) >> (sb)) +/******************************************************************************/ +#define FULL32_MASK 0xFFFFFFFF +#define NO_SHIFT 0 +#define MAX_PHYSICAL_CHANNELS 32 +#define MAX_AVAIL_PHY_CHANNELS 8 +#define MAX_LOGICAL_CHANNELS 128 +#define NUM_CHANNELS (MAX_LOGICAL_CHANNELS + MAX_PHYSICAL_CHANNELS) +/******************************************************************************/ + +#define PHYSICAL_RESOURCE_TYPE_POS(i) (2*(i / 2)) +#define PHYSICAL_RESOURCE_TYPE_MASK(i) (0x3UL << PHYSICAL_RESOURCE_TYPE_POS(i)) + +#define PHYSICAL_RESOURCE_CHANNEL_MODE_POS(i) (2*(i / 2)) +#define PHYSICAL_RESOURCE_CHANNEL_MODE_MASK(i) \ + (0x3UL << PHYSICAL_RESOURCE_CHANNEL_MODE_POS(i)) + + +#define PHYSICAL_RESOURCE_CHANNEL_MODE_OPTION_POS(i) (2*(i / 2)) +#define PHYSICAL_RESOURCE_CHANNEL_MODE_OPTION_MASK(i) \ + (0x3UL << PHYSICAL_RESOURCE_CHANNEL_MODE_OPTION_POS(i)) + +#define PHYSICAL_RESOURCE_SECURE_MODE_POS(i) (2*(i / 2)) +#define PHYSICAL_RESOURCE_SECURE_MODE_MASK(i) \ + (0x3UL << PHYSICAL_RESOURCE_SECURE_MODE_POS(i)) + +#define ACT_PHY_RES_POS(i) (2*(i / 2)) +#define ACT_PHY_RES_MASK(i) (0x3UL << ACT_PHY_RES_POS(i)) + +#define ACTIVATE_RESOURCE_MODE_POS(i) (2*(i / 2)) +#define ACTIVATE_RESOURCE_MODE_MASK(i) (0x3UL << ACTIVATE_RESOURCE_MODE_POS(i)) + +/***************************************************************************** + Standard basic Channel configuration macros - start +******************************************************************************/ + +/* Standard channel parameters - basic mode */ +/* (Source and Destination config regs have */ +/* similar bit descriptions and hence same mask) */ +/*---------------------------------------------------------------------------*/ +#define SREG_CFG_PHY_MST_POS 15 +#define SREG_CFG_PHY_TIM_POS 14 +#define SREG_CFG_PHY_EIM_POS 13 +#define SREG_CFG_PHY_PEN_POS 12 +#define SREG_CFG_PHY_PSIZE_POS 10 +#define SREG_CFG_PHY_ESIZE_POS 8 +#define SREG_CFG_PHY_PRI_POS 7 +#define SREG_CFG_PHY_LBE_POS 6 +#define SREG_CFG_PHY_TM_POS 4 +#define SREG_CFG_PHY_EVTL_POS 0 + +#define SREG_CFG_PHY_MST_MASK (0x1UL << SREG_CFG_PHY_MST_POS) +#define SREG_CFG_PHY_TIM_MASK (0x1UL << SREG_CFG_PHY_TIM_POS) +#define SREG_CFG_PHY_EIM_MASK (0x1UL << SREG_CFG_PHY_EIM_POS) +#define SREG_CFG_PHY_PEN_MASK (0x1UL << SREG_CFG_PHY_PEN_POS) +#define SREG_CFG_PHY_PSIZE_MASK (0x3UL << SREG_CFG_PHY_PSIZE_POS) +#define SREG_CFG_PHY_ESIZE_MASK (0x3UL << SREG_CFG_PHY_ESIZE_POS) +#define SREG_CFG_PHY_PRI_MASK (0x1UL << SREG_CFG_PHY_PRI_POS) +#define SREG_CFG_PHY_LBE_MASK (0x1UL << SREG_CFG_PHY_LBE_POS) +#define SREG_CFG_PHY_TM_MASK (0x3UL << SREG_CFG_PHY_TM_POS) +#define SREG_CFG_PHY_EVTL_MASK (0xFUL << SREG_CFG_PHY_EVTL_POS) + +/* Standard channel parameters - basic mode (element register) */ +/*---------------------------------------------------------------------------*/ +#define SREG_ELEM_PHY_ECNT_POS 16 +#define SREG_ELEM_PHY_EIDX_POS 0 + +#define SREG_ELEM_PHY_ECNT_MASK (0xFFFFUL << SREG_ELEM_PHY_ECNT_POS) +#define SREG_ELEM_PHY_EIDX_MASK (0xFFFFUL << SREG_ELEM_PHY_EIDX_POS) + +/* Standard channel parameters - basic mode (Pointer register) */ +/*---------------------------------------------------------------------------*/ +#define SREG_PTR_PHYS_PTR_MASK (0xFFFFFFFFUL) + +/* Standard channel parameters - basic mode (Link register) */ +/*---------------------------------------------------------------------------*/ +#define SREG_LNK_PHY_TCP_POS 0 +#define SREG_LNK_PHY_LMP_POS 1 +#define SREG_LNK_PHY_PRE_POS 2 +/* Source destination link address. Contains the + * 29-bit byte word aligned address of the reload area. + */ +#define SREG_LNK_PHYS_LNK_MASK (0xFFFFFFF8UL) +#define SREG_LNK_PHYS_TCP_MASK (0x1UL << SREG_LNK_PHY_TCP_POS) +#define SREG_LNK_PHYS_LMP_MASK (0x1UL << SREG_LNK_PHY_LMP_POS) +#define SREG_LNK_PHYS_PRE_MASK (0x1UL << SREG_LNK_PHY_PRE_POS) +/******************************************************************************/ +/* Standard basic Channel configuration macros end */ +/******************************************************************************/ + +/****************************************************************************/ +/* Standard basic Channel LOGICAL mode - start */ +/****************************************************************************/ +/*Configuration register */ +/*--------------------------------------------------------------------------*/ + +#define SREG_CFG_LOG_MST_POS 15 +#define SREG_CFG_LOG_TIM_POS 14 +#define SREG_CFG_LOG_EIM_POS 13 +#define SREG_CFG_LOG_INCR_POS 12 +#define SREG_CFG_LOG_PSIZE_POS 10 +#define SREG_CFG_LOG_ESIZE_POS 8 +#define SREG_CFG_LOG_PRI_POS 7 +#define SREG_CFG_LOG_LBE_POS 6 +#define SREG_CFG_LOG_GIM_POS 5 +#define SREG_CFG_LOG_MFU_POS 4 + +#define SREG_CFG_LOG_MST_MASK (0x1UL << SREG_CFG_LOG_MST_POS) +#define SREG_CFG_LOG_TIM_MASK (0x1UL << SREG_CFG_LOG_TIM_POS) +#define SREG_CFG_LOG_EIM_MASK (0x1UL << SREG_CFG_LOG_EIM_POS) +#define SREG_CFG_LOG_INCR_MASK (0x1UL << SREG_CFG_LOG_INCR_POS) +#define SREG_CFG_LOG_PSIZE_MASK (0x3UL << SREG_CFG_LOG_PSIZE_POS) +#define SREG_CFG_LOG_ESIZE_MASK (0x3UL << SREG_CFG_LOG_ESIZE_POS) +#define SREG_CFG_LOG_PRI_MASK (0x1UL << SREG_CFG_LOG_PRI_POS) +#define SREG_CFG_LOG_LBE_MASK (0x1UL << SREG_CFG_LOG_LBE_POS) +#define SREG_CFG_LOG_GIM_MASK (0x1UL << SREG_CFG_LOG_GIM_POS) +#define SREG_CFG_LOG_MFU_MASK (0x1UL << SREG_CFG_LOG_MFU_POS) + +/*Element register*/ + +#define SREG_ELEM_LOG_ECNT_POS 16 +#define SREG_ELEM_LOG_LIDX_POS 8 +#define SREG_ELEM_LOG_LOS_POS 1 +#define SREG_ELEM_LOG_TCP_POS 0 + +#define SREG_ELEM_LOG_ECNT_MASK (0xFFFFUL << SREG_ELEM_LOG_ECNT_POS) +#define SREG_ELEM_LOG_LIDX_MASK (0xFFUL << SREG_ELEM_LOG_LIDX_POS) +#define SREG_ELEM_LOG_LOS_MASK (0x7FUL << SREG_ELEM_LOG_LOS_POS) +#define SREG_ELEM_LOG_TCP_MASK (0x1UL << SREG_ELEM_LOG_TCP_POS) + +/*Pointer register */ +#define SREG_PTR_LOG_PTR_MASK (0xFFFFFFFFUL) + +/*Link registeri */ +#define DEACTIVATE_EVENTLINE 0x0 +#define ACTIVATE_EVENTLINE 0x1 +#define EVENTLINE_POS(i) (2*i) +#define EVENTLINE_MASK(i) (0x3UL << EVENTLINE_POS(i)) + +/* Standard basic Channel LOGICAL params in memory*/ +#define MEM_LCSP0_ECNT_POS 16 +#define MEM_LCSP0_SPTR_POS 0 + +#define MEM_LCSP0_ECNT_MASK (0xFFFFUL << MEM_LCSP0_ECNT_POS) +#define MEM_LCSP0_SPTR_MASK (0xFFFFUL << MEM_LCSP0_SPTR_POS) + +#define MEM_LCSP1_SPTR_POS 16 + +#define MEM_LCSP1_SCFG_MST_POS 15 +#define MEM_LCSP1_SCFG_TIM_POS 14 +#define MEM_LCSP1_SCFG_EIM_POS 13 +#define MEM_LCSP1_SCFG_INCR_POS 12 +#define MEM_LCSP1_SCFG_PSIZE_POS 10 +#define MEM_LCSP1_SCFG_ESIZE_POS 8 + +#define MEM_LCSP1_SLOS_POS 1 +#define MEM_LCSP1_STCP_POS 0 + +#define MEM_LCSP1_SPTR_MASK (0xFFFFUL << MEM_LCSP1_SPTR_POS) + +#define MEM_LCSP1_SCFG_MST_MASK (0x1UL << MEM_LCSP1_SCFG_MST_POS) +#define MEM_LCSP1_SCFG_TIM_MASK (0x1UL << MEM_LCSP1_SCFG_TIM_POS) +#define MEM_LCSP1_SCFG_EIM_MASK (0x1UL << MEM_LCSP1_SCFG_EIM_POS) +#define MEM_LCSP1_SCFG_INCR_MASK (0x1UL << MEM_LCSP1_SCFG_INCR_POS) +#define MEM_LCSP1_SCFG_PSIZE_MASK (0x3UL << MEM_LCSP1_SCFG_PSIZE_POS) +#define MEM_LCSP1_SCFG_ESIZE_MASK (0x3UL << MEM_LCSP1_SCFG_ESIZE_POS) + +#define MEM_LCSP1_SLOS_MASK (0x7FUL << MEM_LCSP1_SLOS_POS) +#define MEM_LCSP1_STCP_MASK (0x1UL << MEM_LCSP1_STCP_POS) + +#define MEM_LCSP2_ECNT_POS 16 +#define MEM_LCSP2_DPTR_POS 0 + +#define MEM_LCSP2_ECNT_MASK (0xFFFFUL << MEM_LCSP2_ECNT_POS) +#define MEM_LCSP2_DPTR_MASK (0xFFFFUL << MEM_LCSP2_DPTR_POS) + +#define MEM_LCSP3_DPTR_POS 16 + +#define MEM_LCSP3_DCFG_MST_POS 15 +#define MEM_LCSP3_DCFG_TIM_POS 14 +#define MEM_LCSP3_DCFG_EIM_POS 13 +#define MEM_LCSP3_DCFG_INCR_POS 12 +#define MEM_LCSP3_DCFG_PSIZE_POS 10 +#define MEM_LCSP3_DCFG_ESIZE_POS 8 + +#define MEM_LCSP3_DLOS_POS 1 +#define MEM_LCSP3_DTCP_POS 0 + +#define MEM_LCSP3_DPTR_MASK (0xFFFFUL << MEM_LCSP3_DPTR_POS) + +#define MEM_LCSP3_DCFG_MST_MASK (0x1UL << MEM_LCSP3_DCFG_MST_POS) +#define MEM_LCSP3_DCFG_TIM_MASK (0x1UL << MEM_LCSP3_DCFG_TIM_POS) +#define MEM_LCSP3_DCFG_EIM_MASK (0x1UL << MEM_LCSP3_DCFG_EIM_POS) +#define MEM_LCSP3_DCFG_INCR_MASK (0x1UL << MEM_LCSP3_DCFG_INCR_POS) +#define MEM_LCSP3_DCFG_PSIZE_MASK (0x3UL << MEM_LCSP3_DCFG_PSIZE_POS) +#define MEM_LCSP3_DCFG_ESIZE_MASK (0x3UL << MEM_LCSP3_DCFG_ESIZE_POS) + +#define MEM_LCSP3_DLOS_MASK (0x7FUL << MEM_LCSP3_DLOS_POS) +#define MEM_LCSP3_DTCP_MASK (0x1UL << MEM_LCSP3_DTCP_POS) +#define DMA_INFINITE_XFER (0x80000000) +#define CONFIG_USB_U8500_EVENT_LINES +/******************************************************************************/ + +/* Logical Standard Channel Parameters */ + +struct std_log_memory_param { + u32 dmac_lcsp0; + u32 dmac_lcsp1; + u32 dmac_lcsp2; + u32 dmac_lcsp3; +}; + +struct std_src_log_memory_param { + u32 dmac_lcsp0; + u32 dmac_lcsp1; +}; + +struct std_dest_log_memory_param { + u32 dmac_lcsp2; + u32 dmac_lcsp3; +}; + +enum channel_command { + STOP_CHANNEL = 0x1, + RUN_CHANNEL = 0x2, + SUSPEND_REQ = 0x2, + SUSPENDED = 0x3 +}; + +/* Standard Channel parameter register offsets */ +#define CHAN_REG_SSCFG 0x00 +#define CHAN_REG_SSELT 0x04 +#define CHAN_REG_SSPTR 0x08 +#define CHAN_REG_SSLNK 0x0C +#define CHAN_REG_SDCFG 0x10 +#define CHAN_REG_SDELT 0x14 +#define CHAN_REG_SDPTR 0x18 +#define CHAN_REG_SDLNK 0x1C + +/* DMA Register Offsets */ +#define DREG_GCC 0x000 +#define DREG_PRTYP 0x004 +#define DREG_PRSME 0x008 +#define DREG_PRSMO 0x00C +#define DREG_PRMSE 0x010 +#define DREG_PRMSO 0x014 +#define DREG_PRMOE 0x018 +#define DREG_PRMOO 0x01C +#define DREG_LCPA 0x020 +#define DREG_LCLA 0x024 +#define DREG_SLCPA 0x028 +#define DREG_SLCLA 0x02C +#define DREG_SSEG(j) (0x030 + j*4) +#define DREG_SCEG(j) (0x040 + j*4) +#define DREG_ACTIVE 0x050 +#define DREG_ACTIVO 0x054 +#define DREG_FSEB1 0x058 +#define DREG_FSEB2 0x05C +#define DREG_PCMIS 0x060 +#define DREG_PCICR 0x064 +#define DREG_PCTIS 0x068 +#define DREG_PCEIS 0x06C +#define DREG_SPCMIS 0x070 +#define DREG_SPCICR 0x074 +#define DREG_SPCTIS 0x078 +#define DREG_SPCEIS 0x07C +#define DREG_LCMIS(j) (0x080 + j*4) +#define DREG_LCICR(j) (0x090 + j*4) +#define DREG_LCTIS(j) (0x0A0 + j*4) +#define DREG_LCEIS(j) (0x0B0 + j*4) +#define DREG_SLCMIS(j) (0x0C0 + j*4) +#define DREG_SLCICR(j) (0x0D0 + j*4) +#define DREG_SLCTIS(j) (0x0E0 + j*4) +#define DREG_SLCEIS(j) (0x0F0 + j*4) +#define DREG_STFU 0xFC8 +#define DREG_ICFG 0xFCC +#define DREG_MPLUG(j) (0xFD0 + j*4) +#define DREG_PERIPHID(j) (0xFE0 + j*4) +#define DREG_CELLID(j) (0xFF0 + j*4) + +/* + * LLI related structures +*/ + +struct dma_lli_info { + u32 reg_cfg; + u32 reg_elt; + u32 reg_ptr; + u32 reg_lnk; +}; + +struct dma_logical_src_lli_info { + u32 dmac_lcsp0; + u32 dmac_lcsp1; +}; + +struct dma_logical_dest_lli_info { + u32 dmac_lcsp2; + u32 dmac_lcsp3; +}; + +/*****************************************************************************/ +enum dma_toggle_endianess { + DO_NOT_CHANGE_ENDIANESS, + CHANGE_ENDIANESS +}; + +enum dma_master_id { + DMA_MASTER_0, + DMA_MASTER_1 +}; + +/******************************************************************/ +/*Description of bitfields of channel_type variable in info structure*/ + +#define INFO_CH_TYPE_POS 0 +#define STANDARD_CHANNEL (0x1 << INFO_CH_TYPE_POS) +#define EXTENDED_CHANNEL (0x2 << INFO_CH_TYPE_POS) + +#define INFO_PRIO_TYPE_POS 2 +#define HIGH_PRIORITY_CHANNEL (0x1 << INFO_PRIO_TYPE_POS) +#define LOW_PRIORITY_CHANNEL (0x2 << INFO_PRIO_TYPE_POS) + +#define INFO_SEC_TYPE_POS 4 +#define SECURE_CHANNEL (0x1 << INFO_SEC_TYPE_POS) +#define NON_SECURE_CHANNEL (0x2 << INFO_SEC_TYPE_POS) + +#define INFO_CH_MODE_TYPE_POS 6 +#define CHANNEL_IN_PHYSICAL_MODE (0x1 << INFO_CH_MODE_TYPE_POS) +#define CHANNEL_IN_LOGICAL_MODE (0x2 << INFO_CH_MODE_TYPE_POS) +#define CHANNEL_IN_OPERATION_MODE (0x3 << INFO_CH_MODE_TYPE_POS) + +#define INFO_CH_MODE_OPTION_POS 8 +#define PCHAN_BASIC_MODE (0x1 << INFO_CH_MODE_OPTION_POS) +#define PCHAN_MODULO_MODE (0x2 << INFO_CH_MODE_OPTION_POS) +#define PCHAN_DOUBLE_DEST_MODE (0x3 << INFO_CH_MODE_OPTION_POS) +#define LCHAN_SRC_PHY_DEST_LOG (0x1 << INFO_CH_MODE_OPTION_POS) +#define LCHAN_SRC_LOG_DEST_PHS (0x2 << INFO_CH_MODE_OPTION_POS) +#define LCHAN_SRC_LOG_DEST_LOG (0x3 << INFO_CH_MODE_OPTION_POS) + +#define INFO_LINK_TYPE_POS 9 +#define LINK_PRE (0x0 << INFO_LINK_TYPE_POS) +#define LINK_POST (0x1 << INFO_LINK_TYPE_POS) + +#define INFO_TIM_POS 10 +#define NO_TIM_FOR_LINK (0x0 << INFO_TIM_POS) +#define TIM_FOR_LINK (0x1 << INFO_TIM_POS) + +/******************************************************************/ + +enum dma_phys_res_type { + DMA_STANDARD = 0x1, + DMA_EXTENDED = 0x2 +}; + +enum dma_chan_priority { + DMA_LOW_PRIORITY = 0x1, + DMA_HIGH_PRIORITY = 0x2 +}; + +enum dma_chan_security { + DMA_SECURE_CHAN = 0x1, + DMA_NONSECURE_CHAN = 0x2 +}; + +enum dma_channel_mode_option { + BASIC_MODE = 0x1, + MODULO_MODE = 0x2, + DOUBLE_DESTINATION_MODE = 0x3, + + SRC_PHY_DEST_LOG = 0x1, + SRC_LOG_DEST_PHS = 0x2, + SRC_LOG_DEST_LOG = 0x3 +}; + +enum dma_channel_mode { + DMA_CHAN_IN_PHYS_MODE = 0x1, + DMA_CHAN_IN_LOG_MODE = 0x2, + DMA_CHAN_IN_OPERATION_MODE = 0x3 +}; + +enum dma_event_group { + DMA_EVENT_GROUP_0, + DMA_EVENT_GROUP_1, + DMA_EVENT_GROUP_2, + DMA_EVENT_GROUP_3, + DMA_NO_EVENT_GROUP +}; + +enum dma_half_chan { + DMA_SRC_HALF_CHANNEL, + DMA_DEST_HALF_CHANNEL +}; + +enum dma_addr_inc { + DMA_ADR_NOINC, + DMA_ADR_INC +}; + +enum dma_command { + DMA_STOP, + DMA_RUN, + DMA_SUSPEND_REQ, + DMA_SUSPENDED +}; + +enum dma_chan_status { + DMA_ONGOING_EXCHANGE, + DMA_SUSPENDED_EXCHANGE, + DMA_HALTED_EXCHANGE, + DMA_STATUS_UNKNOWN = -1 +}; + +enum dma_chan_id { + DMA_CHAN_0, + DMA_CHAN_1, + DMA_CHAN_2, + DMA_CHAN_3, + DMA_CHAN_4, + DMA_CHAN_5, + DMA_CHAN_6, + DMA_CHAN_7, + DMA_CHAN_NOT_ALLOCATED = -1 +}; + +enum dma_src_dev_type { + DMA_DEV_SPI0_RX = 0, + DMA_DEV_SD_MMC0_RX, + DMA_DEV_SD_MMC1_RX, + DMA_DEV_SD_MMC2_RX, + DMA_DEV_I2C1_RX, + DMA_DEV_I2C3_RX, + DMA_DEV_I2C2_RX, + DMA_DEV_SSP0_RX = 8, + DMA_DEV_SSP1_RX, + DMA_DEV_MCDE_RX, + DMA_DEV_UART2_RX, + DMA_DEV_UART1_RX, + DMA_DEV_UART0_RX, + DMA_DEV_MSP2_RX, + DMA_DEV_I2C0_RX, /*15*/ +#ifndef CONFIG_USB_U8500_EVENT_LINES + DMA_DEV_USB_OTG_IEP_8 , + DMA_DEV_USB_OTG_IEP_1_9 , + DMA_DEV_USB_OTG_IEP_2_10 , + DMA_DEV_USB_OTG_IEP_3_11 , +#else + DMA_DEV_USB_OTG_IEP_7_15 , + DMA_DEV_USB_OTG_IEP_6_14 , + DMA_DEV_USB_OTG_IEP_5_13 , + DMA_DEV_USB_OTG_IEP_4_12 , +#endif + DMA_DEV_SLIM0_CH0_RX_HSI_RX_CH0, + DMA_DEV_SLIM0_CH1_RX_HSI_RX_CH1, + DMA_DEV_SLIM0_CH2_RX_HSI_RX_CH2, + DMA_DEV_SLIM0_CH3_RX_HSI_RX_CH3, + DMA_DEV_SRC_SXA0_RX_TX, + DMA_DEV_SRC_SXA1_RX_TX, + DMA_DEV_SRC_SXA2_RX_TX, + DMA_DEV_SRC_SXA3_RX_TX, + DMA_DEV_SD_MM2_RX, + DMA_DEV_SD_MM0_RX, + DMA_DEV_MSP1_RX, + DMA_SLIM0_CH0_RX, + DMA_DEV_MSP0_RX = DMA_SLIM0_CH0_RX, + DMA_DEV_SD_MM1_RX, + DMA_DEV_SPI2_RX, + DMA_DEV_I2C3_RX2, + DMA_DEV_SPI1_RX, +#ifndef CONFIG_USB_U8500_EVENT_LINES + DMA_DEV_USB_OTG_IEP_4_12 , + DMA_DEV_USB_OTG_IEP_5_13 , + DMA_DEV_USB_OTG_IEP_6_14 , + DMA_DEV_USB_OTG_IEP_7_15 , +#else + DMA_DEV_USB_OTG_IEP_3_11 , + DMA_DEV_USB_OTG_IEP_2_10 , + DMA_DEV_USB_OTG_IEP_1_9 , + DMA_DEV_USB_OTG_IEP_8 , +#endif + DMA_DEV_SPI3_RX, + DMA_DEV_SD_MM3_RX, + DMA_DEV_SD_MM4_RX, + DMA_DEV_SD_MM5_RX, + DMA_DEV_SRC_SXA4_RX_TX, + DMA_DEV_SRC_SXA5_RX_TX, + DMA_DEV_SRC_SXA6_RX_TX, + DMA_DEV_SRC_SXA7_RX_TX, + DMA_DEV_CAC1_RX, + DMA_DEV_MSHC_RX = 51, + DMA_DEV_SLIM1_CH0_RX_HSI_RX_CH4, + DMA_DEV_SLIM1_CH1_RX_HSI_RX_CH5, + DMA_DEV_SLIM1_CH2_RX_HSI_RX_CH6, + DMA_DEV_SLIM1_CH3_RX_HSI_RX_CH7, + DMA_DEV_CAC0_RX = 61, + DMA_DEV_SRC_MEMORY = 64, +}; + +enum dma_dest_dev_type { + DMA_DEV_SPI0_TX = 0, + DMA_DEV_SD_MMC0_TX, + DMA_DEV_SD_MMC1_TX, + DMA_DEV_SD_MMC2_TX, + DMA_DEV_I2C1_TX, + DMA_DEV_I2C3_TX, + DMA_DEV_I2C2_TX, + DMA_DEV_SSP0_TX = 8, + DMA_DEV_SSP1_TX, + DMA_DEV_UART2_TX = 11, + DMA_DEV_UART1_TX, + DMA_DEV_UART0_TX, + DMA_DEV_MSP2_TX, + DMA_DEV_I2C0_TX, +#ifndef CONFIG_USB_U8500_EVENT_LINES + DMA_DEV_USB_OTG_OEP_8 , + DMA_DEV_USB_OTG_OEP_1_9 , + DMA_DEV_USB_OTG_OEP_2_10 , + DMA_DEV_USB_OTG_OEP_3_11 , +#else + DMA_DEV_USB_OTG_OEP_7_15 , + DMA_DEV_USB_OTG_OEP_6_14 , + DMA_DEV_USB_OTG_OEP_5_13 , + DMA_DEV_USB_OTG_OEP_4_12 , +#endif + DMA_DEV_SLIM0_CH0_TX_HSI_TX_CH0, + DMA_DEV_SLIM0_CH1_TX_HSI_TX_CH1, + DMA_DEV_SLIM0_CH2_TX_HSI_TX_CH2, + DMA_DEV_SLIM0_CH3_TX_HSI_TX_CH3, + DMA_DEV_DST_SXA0_RX_TX, + DMA_DEV_DST_SXA1_RX_TX, + DMA_DEV_DST_SXA2_RX_TX, + DMA_DEV_DST_SXA3_RX_TX, + DMA_DEV_SD_MM2_TX, + DMA_DEV_SD_MM0_TX, + DMA_DEV_MSP1_TX, + DMA_SLIM0_CH0_TX, + DMA_DEV_MSP0_TX = DMA_SLIM0_CH0_TX, + DMA_DEV_SD_MM1_TX, + DMA_DEV_SPI2_TX, + DMA_DEV_I2C3_TX2, + DMA_DEV_SPI1_TX, +#ifndef CONFIG_USB_U8500_EVENT_LINES + DMA_DEV_USB_OTG_OEP_4_12 , + DMA_DEV_USB_OTG_OEP_5_13 , + DMA_DEV_USB_OTG_OEP_6_14 , + DMA_DEV_USB_OTG_OEP_7_15 , +#else + DMA_DEV_USB_OTG_OEP_3_11 , + DMA_DEV_USB_OTG_OEP_2_10 , + DMA_DEV_USB_OTG_OEP_1_9 , + DMA_DEV_USB_OTG_OEP_8 , +#endif + DMA_DEV_SPI3_TX, + DMA_DEV_SD_MM3_TX, + DMA_DEV_SD_MM4_TX, + DMA_DEV_SD_MM5_TX, + DMA_DEV_DST_SXA4_RX_TX, + DMA_DEV_DST_SXA5_RX_TX, + DMA_DEV_DST_SXA6_RX_TX, + DMA_DEV_DST_SXA7_RX_TX, + DMA_DEV_CAC1_TX, + DMA_DEV_CAC1_TX_HAC1_TX, + DMA_DEV_HAC1_TX, + DMA_DEV_MSHC_TX, + DMA_DEV_SLIM1_CH0_TX_HSI_TX_CH4, + DMA_DEV_SLIM1_CH1_TX_HSI_TX_CH5, + DMA_DEV_SLIM1_CH2_TX_HSI_TX_CH6, + DMA_DEV_SLIM1_CH3_TX_HSI_TX_CH7, + DMA_DEV_CAC0_TX = 61, + DMA_DEV_CAC0_TX_HAC0_TX, + DMA_DEV_HAC0_TX, + DMA_DEV_DEST_MEMORY = 64, +}; + +enum dma_half_chan_sync { + DMA_NO_SYNC, + DMA_PACKET_SYNC, + DMA_FRAME_SYNC, + DMA_BLOCK_SYNC +}; + +enum half_channel_type { + PHYSICAL_HALF_CHANNEL = 0x1, + LOGICAL_HALF_CHANNEL, +}; + +enum periph_data_width { + DMA_BYTE_WIDTH, + DMA_HALFWORD_WIDTH, + DMA_WORD_WIDTH, + DMA_DOUBLEWORD_WIDTH +}; + +enum dma_burst_size { + DMA_BURST_SIZE_1, + DMA_BURST_SIZE_4, + DMA_BURST_SIZE_8, + DMA_BURST_SIZE_16, + DMA_NO_BURST +}; + +enum dma_buffer_type { + SINGLE_BUFFERED, + DOUBLE_BUFFERED +}; + +enum dma_link_type { + POSTLINK, + PRELINK +}; + +struct dma_half_channel_info { + enum half_channel_type half_chan_type; + enum dma_endianess endianess; + enum periph_data_width data_width; + enum dma_burst_size burst_size; + enum dma_buffer_type buffer_type; + enum dma_event_group event_group; + enum dma_addr_inc addr_inc; + u32 event_line; +}; + +/** + * struct dma_channel_info - Data structure to + * manage state of a DMA channel. + * + * @device_id: Name of the device + * @pipe_id: Pipe Id allocated to the client driver. + * @channel_id: Channel Id allocated for the client, + * used internally by DMA Driver(when interrupt comes) + * (there are 128 Logical + 32 Physical). Max is 160 channels + * @active: Is the channel active at this point? + * 1 - active, 0- inactive + * @invalid: Has configuration been updated since we last updated + * the registers? invalid = 1 (need to update) + * @phys_chan_id:physical channel ID on which this channel will execute + * @src_addr: Src address for single DMA + * @dst_addr: Dest address for single DMA + * @xfer_len: Length of transfer expressed in Bytes + * @current_sg: Pointer to current SG element being used for xfer(only active + * if TIM_MASK is set) + * @lli_interrupt: 1 if interrupts generated for each LLI + * @sgcount_src: Number of SG items in source sg list + * @lli_block_id_src: Block id for LLI pool used for source half channel + * @sg_src: Head Pointer to SG list for source half channel + * @sgcount_dest: Number of SG items in Dest sg list + * @lli_block_id_dest: Block id for LLI pool used for Dest half channel + * @sg_dest: Head Pointer to SG list for Destination half channel + * @sg_block_id_src: Block id for SG pool used for SRC half channel + * @sg_block_id_dest: Block id for SG pool used for DEST half channel + * @link_type: Whether prelink or postlink + * @reserve_channel: whether channel is reserved. + * @dir: MEM 2 MEM, PERIPH 2 MEM , MEM 2 PERIPH, PERIPH 2 PERIPH + * @flow_cntlr: who is the flow controller DMA or Peripheral + * @data: Pointer to data of callback function + * @callback: Pointer to callback function + * @pr_type: Physical resource type : standard or extended + * @chan_mode: Mode of Physical resource + * For std channel: Physical,Logical,Operation + * @mode_option: Further options of mode selected above + * @priority: Priority for this channel + * @security: security for this channel + * @bytes_xfred: Number of Bytes xfered till now + * @ch_status: + * @src_dev_type: Device type of Source + * @dst_dev_type: Device type of Dest + * @src_info: Parameters describing source half channel + * @dst_info: Parameters describing dest half channel + * This is a private data structure of DMA driver used to maintain + * state information of a particular channel + */ +struct dma_channel_info { + const char *device_id; + u32 src_cfg; + u32 dst_cfg; + u32 dmac_lcsp3; + u32 dmac_lcsp1; + int pipe_id; + int channel_id; + int active; + int invalid; + enum dma_chan_id phys_chan_id; + void *src_addr; + void *dst_addr; + u32 xfer_len; + u32 src_xfer_elem; + u32 dst_xfer_elem; + struct scatterlist *current_sg; + /*For Scatter Gather DMA */ + int lli_interrupt; + int sgcount_src; + int lli_block_id_src; + struct scatterlist *sg_src; + int sgcount_dest; + int lli_block_id_dest; + struct scatterlist *sg_dest; + int sg_block_id_src; + int sg_block_id_dest; + + enum dma_link_type link_type; + unsigned int reserve_channel; + enum dma_xfer_dir dir; + enum dma_flow_controller flow_cntlr; + + void *data; + dma_callback_t callback; + + enum dma_phys_res_type pr_type; + enum dma_channel_mode chan_mode; + enum dma_channel_mode_option mode_option; + enum dma_chan_priority priority; + enum dma_chan_security security; + + int bytes_xfred; + enum dma_chan_status ch_status; + enum dma_src_dev_type src_dev_type; + enum dma_dest_dev_type dst_dev_type; + struct dma_half_channel_info src_info; + struct dma_half_channel_info dst_info; + spinlock_t cfg_lock; +}; + +enum res_status { + RESOURCE_FREE, + RESOURCE_PHYSICAL, + RESOURCE_LOGICAL +}; + +struct phys_res_status { + int count; + enum res_status status; +}; + +struct phy_res_info { + enum res_status status; + u32 count; + u32 dirty; +}; + +#define NUM_LLI_PER_REQUEST 40 +#define NUM_SG_PER_REQUEST 40 +#define NUM_LOGICAL_CHANNEL_PER_PHY_RESOURCE 16 +#define NUM_LLI_PER_LOG_CHANNEL 8 +#define SIXTY_FOUR_KB (64 * 1024) + +#define MAX_NUM_OF_ELEM_IN_A_XFER (64*1024) +/*Number of Fixed size LLI Blocks available for Physical channels */ +#define NUM_PCHAN_LLI_BLOCKS 32 +/*Number of Fixed size SG blocks */ +#define NUM_SG_BLOCKS 32 +/*Maximum Iterations taken before giving up suspending a channel */ +#define MAX_ITERATIONS 500 + +extern struct driver_debug_st DBG_ST; + +#endif diff --git a/arch/arm/mach-ux500/include/mach/dsi.h b/arch/arm/mach-ux500/include/mach/dsi.h new file mode 100755 index 00000000000..553ad998bb1 --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/dsi.h @@ -0,0 +1,777 @@ +/*---------------------------------------------------------------------------*/ +/* Copyright ST Ericsson 2009. */ +/* */ +/* This program is free software; you can redistribute it and/or modify it */ +/* under the terms of the GNU Lesser General Public License as published */ +/* by the Free Software Foundation; either version 2.1 of the License, */ +/* or (at your option)any later version. */ +/* */ +/* This program is distributed in the hope that it will be useful, but */ +/* WITHOUT ANY WARRANTY; without even the implied warranty of */ +/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See */ +/* the GNU Lesser General Public License for more details. */ +/* */ +/* You should have received a copy of the GNU Lesser General Public License */ +/* along with this program. If not, see <http://www.gnu.org/licenses/>. */ +/*---------------------------------------------------------------------------*/ + +#ifndef _DSI_H_ +#define _DSI_H_ + +#ifdef _cplusplus +extern "C" { +#endif /* _cplusplus */ +#include <mach/mcde.h> +#ifdef __KERNEL__ + +#define DSI_DPHY_Z_CALIB_OUT_VALID 0x1 +/******************************************************************************* +DSI Error Enums +******************************************************************************/ + + + typedef enum + { + DSI_OK = 0x1, /** No error.*/ + DSI_NO_PENDING_EVENT_ERROR = 0x2, + DSI_NO_MORE_FILTER_PENDING_EVENT = 0x3, + DSI_NO_MORE_PENDING_EVENT = 0x4, + DSI_REMAINING_FILTER_PENDING_EVENTS = 0x5, + DSI_REMAINING_PENDING_EVENTS = 0x6, + DSI_INTERNAL_EVENT = 0x7, + DSI_INTERNAL_ERROR = 0x8, + DSI_NOT_CONFIGURED = 0x9, + DSI_REQUEST_PENDING = 0xA, + DSI_PLL_PROGRAM_ERROR = 0xB, + DSI_CLOCK_LANE_NOT_READY = 0xC, + DSI_DATA_LANE1_NOT_READY = 0xD, + DSI_DATA_LANE2_NOT_READY = 0xE, + DSI_REQUEST_NOT_APPLICABLE = 0x10, + DSI_INVALID_PARAMETER = 0x11, + DSI_UNSUPPORTED_FEATURE = 0x12, + DSI_UNSUPPORTED_HW = 0x13 + }dsi_error; + +/******************************************************************************** +DSI Interrupt Type Enums +********************************************************************************/ +#define DSI_NO_INTERRUPT 0x0 + +typedef enum +{ + DSI_IRQ_TYPE_MCTL_MAIN = 0x01, + DSI_IRQ_TYPE_CMD_MODE = 0x02, + DSI_IRQ_TYPE_DIRECT_CMD_MODE = 0x03, + DSI_IRQ_TYPE_DIRECT_CMD_RD_MODE = 0x04, + DSI_IRQ_TYPE_VID_MODE = 0x05, + DSI_IRQ_TYPE_TG = 0x06, + DSI_IRQ_TYPE_DPHY_ERROR = 0x07, + DSI_IRQ_TYPE_DPHY_CLK_TRIM_RD = 0x08 +} dsi_irq_type; + + + + +/******************************************************************************* + DSI Main Setting Registers Enums and structures +******************************************************************************/ + + typedef enum + { + DSI_INT_MODE_DISABLE = 0x00, + DSI_INT_MODE_ENABLE = 0x01 + }dsi_int_mode; + + typedef enum + { + DSI_VSG_MODE_DISABLE = 0x00, + DSI_VSG_MODE_ENABLE = 0x01 + }dsi_vsg_ctrl; + + typedef enum + { + DSI_TVG_MODE_DISABLE = 0x00, + DSI_TVG_MODE_ENABLE = 0x01 + }dsi_tvg_ctrl; + + typedef enum + { + DSI_TBG_MODE_DISABLE = 0x00, + DSI_TBG_MODE_ENABLE = 0x01 + }dsi_tbg_ctrl; + + typedef enum + { + DSI_RD_MODE_DISABLE = 0x00, + DSI_RD_MODE_ENABLE = 0x01 + }dsi_rd_ctrl; + + + typedef enum + { + DSI_SIGNAL_LOW = 0x0, + DSI_SIGNAL_HIGH = 0x1 + }dsi_signal_state; + + typedef enum + { + DSI_LINK0 = 0x00, + DSI_LINK1 = 0x01, + DSI_LINK2 = 0x02 + }dsi_link; + + typedef enum + { + DSI_COMMAND_MODE = 0x0, + DSI_VIDEO_MODE = 0x1, + DSI_INTERFACE_BOTH = 0x2, + DSI_INTERFACE_NONE = 0x3 + }dsi_interface_mode; + + typedef enum + { + DSI_INTERFACE_1 = 0x0, + DSI_INTERFACE_2 = 0x1 + }dsi_interface; + + typedef enum + { + DSI_DISABLE = 0x0, + DSI_ENABLE = 0x1 + }dsi_link_state; + + typedef enum + { + DSI_SIGNAL_RESET = 0x0, + DSI_SIGNAL_SET = 0x1 + }dsi_stall_signal_state; + + typedef enum + { + DSI_IF1_DISABLE = 0x0, + DSI_IF1_ENABLE = 0x1 + }dsi_if1_state; + + typedef enum + { + DSI_IF_DISABLE = 0x0, + DSI_IF_ENABLE = 0x1 + }dsi_if_state; + + typedef enum + { + DSI_PLL_IN_CLK_27 = 0x0,/** from TV PLL*/ + DSI_PLL_IN_CLK_26 = 0x1 /** from system PLL*/ + }dsi_pll_clk_in; + + typedef enum + { + DSI_PLL_STOP = 0x0, + DSI_PLL_START = 0x1 + }dsi_pll_mode; + + typedef enum + { + DSI_BTA_DISABLE = 0x0, + DSI_BTA_ENABLE = 0x1 + }dsi_bta_mode; + + typedef enum + { + DSI_ECC_GEN_DISABLE = 0x0, + DSI_ECC_GEN_ENABLE = 0x1 + }dsi_ecc_gen_mode; + + typedef enum + { + DSI_CHECKSUM_GEN_DISABLE = 0x0, + DSI_CHECKSUM_GEN_ENABLE = 0x1 + }dsi_checksum_gen_mode; + + typedef enum + { + DSI_EOT_GEN_DISABLE = 0x0, + DSI_EOT_GEN_ENABLE = 0x1 + }dsi_eot_gen_mode; + + typedef enum + { + DSI_HOST_EOT_GEN_DISABLE = 0x0, + DSI_HOST_EOT_GEN_ENABLE = 0x1 + }dsi_host_eot_gen_mode; + + typedef enum + { + DSI_LANE_STOP = 0x0, + DSI_LANE_START = 0x1 + }dsi_lane_state; + typedef enum + { + DSI_LANE_DISABLE = 0x0, + DSI_LANE_ENABLE = 0x1 + }dsi_lane_mode; + typedef enum + { + DSI_CLK_CONTINIOUS_HS_DISABLE = 0x0, + DSI_CLK_CONTINIOUS_HS_ENABLE = 0x1 + }dsi_clk_continious_hs_mode; + typedef enum + { + DSI_INTERNAL_PLL = 0x0, + DSI_SYSTEM_PLL = 0x1 + }pll_out_sel; /** DPHY HS bit clock select*/ + typedef enum + { + HS_INVERT_DISABLE = 0x0, + HS_INVERT_ENABLE = 0x1 + }dsi_hs_invert_mode; + typedef enum + { + HS_SWAP_PIN_DISABLE = 0x0, + HS_SWAP_PIN_ENABLE = 0x1 + }dsi_swap_pin_mode; + typedef enum + { + DSI_PLL_MASTER = 0x0, + DSI_PLL_SLAVE = 0x1 + }dsi_pll_mode_sel; + + typedef struct + { + u8 multiplier; + u8 division_ratio; + dsi_pll_clk_in pll_in_sel; + pll_out_sel pll_out_sel; + dsi_pll_mode_sel pll_master; + }dsi_pll_ctl; + + typedef enum + { + DSI_REG_TE = 0x00, + DSI_IF_TE = 0x01 + }dsi_te_sel; + + typedef struct + { + dsi_te_sel te_sel; + dsi_interface interface; + }dsi_te_en; + + typedef enum + { + DSI_TE_DISABLE = 0x0, + DSI_TE_ENABLE = 0x1 + }dsi_te_ctrl; + + typedef enum + { + DSI_CLK_LANE = 0x00, + DSI_DATA_LANE1 = 0x01, + DSI_DATA_LANE2 = 0x02 + }dsi_lane; + + typedef enum + { + DSI_DAT_LANE1 = 0x0, + DSI_DAT_LANE2 = 0x1 + }dsi_data_lane; + + typedef enum + { + DSI_CLK_LANE_START = 0x00, + DSI_CLK_LANE_IDLE = 0x01, + DSI_CLK_LANE_HS = 0x02, + DSI_CLK_LANE_ULPM = 0x03 + }dsi_clk_lane_state; + typedef enum + { + DSI_CLK_LANE_LPM = 0x0, + DSI_CLK_LANE_HSM = 0x01 + }dsi_interface_mode_type; + typedef enum + { + DSI_DATA_LANE_START = 0x000, + DSI_DATA_LANE_IDLE = 0x001, + DSI_DATA_LANE_WRITE = 0x002, + DSI_DATA_LANE_ULPM = 0x003, + DSI_DATA_LANE_READ = 0x004 + }dsi_data_lane_state; + + typedef struct + { + u8 clk_div; + u16 hs_tx_timeout; + u16 lp_rx_timeout; + }dsi_dphy_timeout; + + typedef enum + { + DSI_PLL_LOCK = 0x01, + DSI_CLKLANE_READY = 0x02, + DSI_DAT1_READY = 0x04, + DSI_DAT2_READY = 0x08, + DSI_HSTX_TO_ERROR = 0x10, + DSI_LPRX_TO_ERROR = 0x20, + DSI_CRS_UNTERM_PCK = 0x40, + DSI_VRS_UNTERM_PCK = 0x80 + }dsi_link_status; + + typedef struct + { + u16 if_data; + dsi_signal_state if_valid; + dsi_signal_state if_start; + dsi_signal_state if_frame_sync; + }dsi_int_read; + + typedef enum + { + DSI_ERR_SOT_HS_1 = 0x1, + DSI_ERR_SOT_HS_2 = 0x2, + DSI_ERR_SOTSYNC_1 = 0x4, + DSI_ERR_SOTSYNC_2 = 0x8, + DSI_ERR_EOTSYNC_1 = 0x10, + DSI_ERR_EOTSYNC_2 = 0x20, + DSI_ERR_ESC_1 = 0x40, + DSI_ERR_ESC_2 = 0x80, + DSI_ERR_SYNCESC_1 = 0x100, + DSI_ERR_SYNCESC_2 = 0x200, + DSI_ERR_CONTROL_1 = 0x400, + DSI_ERR_CONTROL_2 = 0x800, + DSI_ERR_CONT_LP0_1 = 0x1000, + DSI_ERR_CONT_LP0_2 = 0x2000, + DSI_ERR_CONT_LP1_1 = 0x4000, + DSI_ERR_CONT_LP1_2 = 0x8000, + }dsi_dphy_err; + + typedef enum + { + DSI_VIRTUAL_CHANNEL_0 = 0x0, + DSI_VIRTUAL_CHANNEL_1 = 0x1, + DSI_VIRTUAL_CHANNEL_2 = 0x2, + DSI_VIRTUAL_CHANNEL_3 = 0x3 + }dsi_virtual_ch; + + typedef enum + { + DSI_ERR_NO_TE = 0x1, + DSI_ERR_TE_MISS = 0x2, + DSI_ERR_SDI1_UNDERRUN = 0x4, + DSI_ERR_SDI2_UNDERRUN = 0x8, + DSI_ERR_UNWANTED_RD = 0x10, + DSI_CSM_RUNNING = 0x20 + }dsi_cmd_mode_sts; + + typedef enum + { + DSI_COMMAND_DIRECT = 0x0, + DSI_COMMAND_GENERIC = 0x1 + }dsi_cmd_type; + + typedef struct + { + u16 rd_size; + dsi_virtual_ch rd_id; + dsi_cmd_type cmd_type; + }dsi_cmd_rd_property; + + typedef enum + { + DSI_CMD_WRITE = 0x0, + DSI_CMD_READ = 0x1, + DSI_CMD_TE_REQUEST = 0x4, + DSI_CMD_TRIGGER_REQUEST = 0x5, + DSI_CMD_BTA_REQUEST = 0x6 + }dsi_cmd_nat; + + typedef enum + { + DSI_CMD_SHORT = 0x0, + DSI_CMD_LONG = 0x1 + }dsi_cmd_packet; + + typedef struct + { + u8 rddat0; + u8 rddat1; + u8 rddat2; + u8 rddat3; + }dsi_cmd_rddat; + + typedef struct + { + dsi_cmd_nat cmd_nature; + dsi_cmd_packet packet_type; + u8 cmd_header; + dsi_virtual_ch cmd_id; + u8 cmd_size; + dsi_link_state cmd_lp_enable; + u8 cmd_trigger_val; + }dsi_cmd_main_setting; + + typedef enum + { + DSI_CMD_TRANSMISSION = 0x1, + DSI_WRITE_COMPLETED = 0x2, + DSI_TRIGGER_COMPLETED = 0x4, + DSI_READ_COMPLETED = 0x8, + DSI_ACKNOWLEDGE_RECEIVED = 0x10, + DSI_ACK_WITH_ERR_RECEIVED = 0x20, + DSI_TRIGGER_RECEIVED = 0x40, + DSI_TE_RECEIVED = 0x80, + DSI_BTA_COMPLETED = 0x100, + DSI_BTA_FINISHED = 0x200, + DSI_READ_COMPLETED_WITH_ERR = 0x400, + DSI_TRIGGER_VAL = 0x7800, + DSI_ACK_VAL = 0xFFFF0000 + }dsi_direct_cmd_sts; + + typedef enum + { + DSI_TE_256 = 0x00, + DSI_TE_512 = 0x01, + DSI_TE_1024 = 0x02, + DSI_TE_2048 = 0x03 + }dsi_te_timeout; + + typedef enum + { + DSI_ARB_MODE_FIXED = 0x0, + DSI_ARB_MODE_ROUNDROBIN = 0x1 + }dsi_arb_mode; + + typedef struct + { + dsi_arb_mode arb_mode; + dsi_interface arb_fixed_if; + }dsi_arb_ctl; + + typedef enum + { + DSI_STARTON_VSYNC = 0x00, + DSI_STARTON_VFP = 0x01, + }dsi_start_mode; + + typedef enum + { + DSI_STOPBEFORE_VSYNV = 0x0, + DSI_STOPAT_LINEEND = 0x1, + DSI_STOPAT_ACTIVELINEEND = 0x2, + }dsi_stop_mode; + + typedef enum + { + DSI_NO_BURST_MODE = 0x0, + DSI_BURST_MODE = 0x1, + }dsi_burst_mode; + + typedef enum + { + DSI_VID_MODE_16_PACKED = 0x0, + DSI_VID_MODE_18_PACKED = 0x1, + DSI_VID_MODE_16_LOOSELY = 0x2, + DSI_VID_MODE_18_LOOSELY = 0x3 + }dsi_vid_pixel_mode; + + typedef enum + { + DSI_SYNC_PULSE_NOTACTIVE = 0x0, + DSI_SYNC_PULSE_ACTIVE = 0x1 + }dsi_sync_pulse_active; + + typedef enum + { + DSI_SYNC_PULSE_HORIZONTAL_NOTACTIVE = 0x0, + DSI_SYNC_PULSE_HORIZONTAL_ACTIVE = 0x1 + }dsi_sync_pulse_horizontal; + + typedef enum + { + DSI_NULL_PACKET = 0x0, + DSI_BLANKING_PACKET = 0x1, + DSI_LP_MODE = 0x2, + }dsi_blanking_packet; + + typedef enum + { + DSI_RECOVERY_HSYNC = 0x0, + DSI_RECOVERY_VSYNC = 0x1, + DSI_RECOVERY_STOP = 0x2, + DSI_RECOVERY_HSYNC_VSYNC = 0x3 + }dsi_recovery_mode; + + typedef struct + { + dsi_start_mode vid_start_mode; + dsi_stop_mode vid_stop_mode; + dsi_virtual_ch vid_id; + u8 header; + dsi_vid_pixel_mode vid_pixel_mode; + dsi_burst_mode vid_burst_mode; + dsi_sync_pulse_active sync_pulse_active; + dsi_sync_pulse_horizontal sync_pulse_horizontal; + dsi_blanking_packet blkline_mode; + dsi_blanking_packet blkeol_mode; + dsi_recovery_mode recovery_mode; + }dsi_vid_main_ctl; + + typedef struct + { + u16 vact_length; + u8 vfp_length; + u8 vbp_length; + u8 vsa_length; + }dsi_img_vertical_size; + + typedef struct + { + u8 hsa_length; + u8 hbp_length; + u16 hfp_length; + u16 rgb_size; + }dsi_img_horizontal_size; + + typedef struct + { + u16 line_val; + u8 line_pos; + u16 horizontal_val; + u8 horizontal_pos; + }dsi_img_position; + + typedef enum + { + DSI_VSG_RUNNING = 0x1, + DSI_ERR_MISSING_DATA = 0x2, + DSI_ERR_MISSING_HSYNC = 0x4, + DSI_ERR_MISSING_VSYNC = 0x8, + DSI_ERR_SMALL_LENGTH = 0x10, + DSI_ERR_SMALL_HEIGHT = 0x20, + DSI_ERR_BURSTWRITE = 0x40, + DSI_ERR_LINEWRITE = 0x80, + DSI_ERR_LONGWRITE = 0x100, + DSI_ERR_VRS_WRONG_LENGTH = 0x200 + }dsi_vid_mode_sts; + + typedef enum + { + DSI_NULL_PACK = 0x0, + DSI_LP = 0x1, + }dsi_burst_lp; + + typedef struct + { + dsi_burst_lp burst_lp; + u16 max_burst_limit; + u16 max_line_limit; + u16 exact_burst_limit; + }dsi_vca_setting; + + typedef struct + { + u16 blkeol_pck; + u16 blkline_event_pck; + u16 blkline_pulse_pck; + u16 vert_balnking_duration; + u16 blkeol_duration; + }dsi_vid_blanking; + + typedef struct + { + u8 col_red; + u8 col_green; + u8 col_blue; + u8 pad_val; + }dsi_vid_err_color; + + typedef enum + { + DSI_TVG_MODE_UNIQUECOLOR = 0x0, + DSI_TVG_MODE_STRIPES = 0x1, + }dsi_tvg_mode; + + typedef enum + { + DSI_TVG_STOP_FRAMEEND = 0x0, + DSI_TVG_STOP_LINEEND = 0x1, + DSI_TVG_STOP_IMMEDIATE = 0x2, + }dsi_tvg_stop_mode; + + + + typedef struct + { + u8 tvg_stripe_size; + dsi_tvg_mode tvg_mode; + dsi_tvg_stop_mode stop_mode; + }dsi_tvg_control; + + typedef struct + { + u16 tvg_nbline; + u16 tvg_line_size; + }dsi_tvg_img_size; + + typedef struct + { + u8 col_red; + u8 col_green; + u8 col_blue; + }dsi_frame_color; + + typedef enum + { + DSI_TVG_COLOR1 = 0x0, + DSI_TVG_COLOR2 = 0x1 + }dsi_color_type; + + typedef enum + { + DSI_TVG_STOPPED = 0x0, + DSI_TVG_RUNNING = 0x1 + }dsi_tvg_state; + + typedef enum + { + DSI_TVG_STOP = 0x0, + DSI_TVG_START = 0x1 + }dsi_tvg_ctrl_state; + + typedef enum + { + DSI_TBG_STOPPED = 0x0, + DSI_TBG_RUNNING = 0x1 + }dsi_tbg_state; + + typedef enum + { + DSI_SEND_1BYTE = 0x0, + DSI_SEND_2BYTE = 0x1, + DSI_SEND_BURST_STOP_COUNTER = 0x3, + DSI_SEND_BURST_STOP = 0x4 + }dsi_tbg_mode; + + typedef enum + { + DSI_ERR_FIXED = 0x1, + DSI_ERR_UNCORRECTABLE = 0x2, + DSI_ERR_CHECKSUM = 0x4, + DSI_ERR_UNDECODABLE = 0x8, + DSI_ERR_RECEIVE = 0x10, + DSI_ERR_OVERSIZE = 0x20, + DSI_ERR_WRONG_LENGTH = 0x40, + DSI_ERR_MISSING_EOT = 0x80, + DSI_ERR_EOT_WITH_ERR = 0x100 + }dsi_direct_cmd_rd_sts_ctl; + + typedef enum + { + DSI_TVG_STS = 0x1, + DSi_TBG_STS = 0x2 + }dsi_tg_sts_ctl; + +typedef struct +{ + dsi_interface_mode dsi_if_mode; + dsi_interface dsiInterface; + dsi_if1_state dsi_if1_state; + dsi_link_state dsi_link_state; + dsi_int_mode dsi_int_mode; + dsi_interface_mode_type if_mode_type; +}dsi_link_context; + +struct dsi_dphy_static_conf { + dsi_hs_invert_mode clocklanehsinvermode; + dsi_swap_pin_mode clocklaneswappinmode; + dsi_hs_invert_mode datalane1hsinvermode; + dsi_swap_pin_mode datalane1swappinmode; + dsi_hs_invert_mode datalane2hsinvermode; + dsi_swap_pin_mode datalane2swappinmode; + u8 ui_x4; /** unit interval time for clock lane*/ +}; +struct dsi_link_conf { + dsi_link_state dsiLinkState; + dsi_interface dsiInterface; + dsi_interface_mode dsiInterfaceMode; + dsi_interface_mode_type videoModeType; /** for LP/HS mode for vide mode */ + dsi_interface_mode_type commandModeType;/** for LP/HS mode for command mode */ + dsi_lane_mode clockLaneMode; + dsi_lane_mode dataLane1Mode; + dsi_lane_mode dataLane2Mode; + dsi_arb_mode arbMode; + dsi_te_ctrl if1TeCtrl; + dsi_te_ctrl if2TeCtrl; + dsi_te_ctrl regTeCtrl; + dsi_bta_mode btaMode; + dsi_rd_ctrl rdCtrl; + dsi_host_eot_gen_mode hostEotGenMode; + dsi_eot_gen_mode displayEotGenMode; + dsi_ecc_gen_mode dispEccGenMode; + dsi_checksum_gen_mode dispChecksumGenMode; + dsi_clk_continious_hs_mode clockContiniousMode; + u8 paddingValue; +}; +#endif /** __KERNEL_ */ + +u32 dsiconfdphy1(mcde_pll_ref_clk pll_sel, mcde_ch_id chid, dsi_link link); +u32 dsidisplayinitLPcmdmode(mcde_ch_id chid, dsi_link link); + +dsi_error dsisetlinkstate(dsi_link link, dsi_link_state linkState, mcde_ch_id chid); +u32 dsiLinkInit(struct dsi_link_conf *pdsiLinkConf, struct dsi_dphy_static_conf dphyStaticConf, mcde_ch_id chid, dsi_link link); +int mcde_dsi_test_LP_directcommand_mode(struct fb_info *info,u32 key); +int mcde_dsi_start(struct fb_info *info); +int mcde_dsi_test_dsi_HS_directcommand_mode(struct fb_info *info,u32 key); + +int mcde_dsi_read_reg(struct fb_info *info, u32 reg, u32 *value); +int mcde_dsi_write_reg(struct fb_info *info, u32 reg, u32 value); + +dsi_error dsisetPLLcontrol(dsi_link link, mcde_ch_id chid, dsi_pll_ctl pll_ctl); +dsi_error dsisetPLLmode(dsi_link link, mcde_ch_id chid, dsi_pll_mode mode); +dsi_error dsigetlinkstatus(dsi_link link, mcde_ch_id chid, u8 *p_status); +dsi_error dsisetInterface(dsi_link link, mcde_ch_id chid, dsi_if_state state, dsi_interface interface); +dsi_error dsisetInterface1mode(dsi_link link, dsi_interface_mode mode, mcde_ch_id chid); +dsi_error dsisetInterfaceInLpm(dsi_link link, mcde_ch_id chid, dsi_interface_mode_type modType, dsi_interface interface); +dsi_error dsisetTEtimeout(dsi_link link, mcde_ch_id chid, u32 te_timeout); +dsi_error dsireadset(dsi_link link, dsi_rd_ctrl state, mcde_ch_id chid); +dsi_error dsisetBTAmode(dsi_link link, dsi_bta_mode mode, mcde_ch_id chid); +dsi_error dsisetdispEOTGenmode(dsi_link link, dsi_eot_gen_mode mode, mcde_ch_id chid); +dsi_error dsisetdispHOSTEOTGenmode(dsi_link link, dsi_host_eot_gen_mode mode, mcde_ch_id chid); +dsi_error dsisetdispCHKSUMGenmode(dsi_link link, dsi_checksum_gen_mode mode, mcde_ch_id chid); +dsi_error dsisetdispECCGenmode(dsi_link link, dsi_ecc_gen_mode mode, mcde_ch_id chid); +dsi_error dsisetCLKHSsendingmode(dsi_link link, dsi_clk_continious_hs_mode mode, mcde_ch_id chid); +dsi_error dsisetpaddingval(dsi_link link, mcde_ch_id chid, u8 padding); +dsi_error dsisetTE(dsi_link link, dsi_te_en tearing, dsi_te_ctrl state, mcde_ch_id chid); +dsi_error dsisetlaneULPwaittime(dsi_link link, mcde_ch_id chid, dsi_lane lane, u16 timeout); + +dsi_error dsisetlanestate(dsi_link link, mcde_ch_id chid, dsi_lane_state mode, dsi_lane lane); +dsi_error dsiset_hs_clock(dsi_link link, struct dsi_dphy_static_conf dphyStaticConf, mcde_ch_id chid); +dsi_error dsisetDPHYtimeout(dsi_link link, mcde_ch_id chid, dsi_dphy_timeout timeout); +void mcde_dsi_tpodisplay_init(struct fb_info *info); +void mcde_dsi_taaldisplay_init(struct fb_info *info); + +/* following Apis are used by stw5810 driver for configuration */ +u32 dsisenddirectcommand(dsi_interface_mode_type mode_type, u32 cmd_head,u32 cmd_size,u32 cmd1,u32 cmd2,u32 cmd3,u32 cmd4, dsi_link link, mcde_ch_id chid); + +u32 dsiLPdcslongwrite(u32 VC_ID, u32 NoOfParam, u32 Param0, u32 Param1,u32 Param2, u32 Param3, + u32 Param4,u32 Param5,u32 Param6,u32 Param7,u32 Param8, u32 Param9,u32 Param10,u32 Param11, + u32 Param12,u32 Param13,u32 Param14, u32 Param15, mcde_ch_id chid, dsi_link link); + +u32 dsiLPdcsshortwrite1parm(u32 VC_ID, u32 Param0,u32 Param1, mcde_ch_id chid, dsi_link link); +u32 dsiLPdcsshortwritenoparam(u32 VC_ID, u32 Param0, mcde_ch_id chid, dsi_link link); + +u32 dsiHSdcslongwrite(u32 VC_ID, u32 NoOfParam, u32 Param0, u32 Param1,u32 Param2, u32 Param3, + u32 Param4,u32 Param5,u32 Param6,u32 Param7,u32 Param8, u32 Param9,u32 Param10,u32 Param11, + u32 Param12,u32 Param13,u32 Param14, u32 Param15, mcde_ch_id chid, dsi_link link); + +u32 dsiHSdcsshortwrite1parm(u32 VC_ID, u32 Param0,u32 Param1, mcde_ch_id chid, dsi_link link); +u32 dsiHSdcsshortwritenoparam(u32 VC_ID, u32 Param0, mcde_ch_id chid, dsi_link link); +u32 dsireaddata(u8* byte0, u8* byte1, u8* byte2, u8* byte3, mcde_ch_id chid, dsi_link link); + + +#ifdef _cplusplus +} +#endif /* _cplusplus */ + +#endif /* !defined(_DSI_H_) */ + + diff --git a/arch/arm/mach-ux500/include/mach/dsi_reg.h b/arch/arm/mach-ux500/include/mach/dsi_reg.h new file mode 100755 index 00000000000..a5fc8e39ff2 --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/dsi_reg.h @@ -0,0 +1,495 @@ +/*---------------------------------------------------------------------------*/ +/* Copyright (C) ST Ericsson 2009 */ +/* */ +/* This program is free software; you can redistribute it and/or modify it */ +/* under the terms of the GNU Lesser General Public License as published */ +/* by the Free Software Foundation; either version 2.1 of the License, */ +/* or (at your option)any later version. */ +/* */ +/* This program is distributed in the hope that it will be useful, but */ +/* WITHOUT ANY WARRANTY; without even the implied warranty of */ +/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See */ +/* the GNU Lesser General Public License for more details. */ +/* */ +/* You should have received a copy of the GNU Lesser General Public License */ +/* along with this program. If not, see <http://www.gnu.org/licenses/>. */ +/*---------------------------------------------------------------------------*/ + +#ifndef _DSIREG_H_ +#define _DSIREG_H_ + +#ifdef _cplusplus +extern "C" { +#endif /* _cplusplus */ + +#include <linux/types.h> + +#define DSI_SET_BIT 0x1 +#define DSI_CLEAR_BIT 0x0 +#define DSI_SET_ALL_BIT 0xFFFFFFFF +#define DSI_CLEAR_ALL_BIT 0x0 +#define DSI_MCTL_INTMODE_MASK MASK_BIT0 +#define DSI_MCTL_LINKEN_MASK MASK_BIT0 +#define DSI_MCTL_INTERFACE1_MODE_MASK MASK_BIT1 +#define DSI_MCTL_VID_EN_MASK MASK_BIT2 +#define DSI_MCTL_TVG_SEL_MASK MASK_BIT3 +#define DSI_MCTL_TBG_SEL_MASK MASK_BIT4 +#define DSI_MCTL_READEN_MASK MASK_BIT8 +#define DSI_MCTL_BTAEN_MASK MASK_BIT9 +#define DSI_MCTL_DISPECCGEN_MASK MASK_BIT10 +#define DSI_MCTL_DISPCHECKSUMGEN_MASK MASK_BIT11 +#define DSI_MCTL_HOSTEOTGEN_MASK MASK_BIT12 +#define DSI_MCTL_DISPEOTGEN_MASK MASK_BIT13 +#define DSI_PLL_MASTER_MASK MASK_BIT16 +#define DSI_PLL_OUT_SEL_MASK MASK_BIT11 +#define DSI_PLL_IN_SEL_MASK MASK_BIT10 +#define DSI_PLL_DIV_MASK (MASK_BIT7 | MASK_BIT8 | MASK_BIT9) +#define DSI_PLL_MULT_MASK (MASK_BYTE0 & 0x7F) +#define DSI_REG_TE_MASK MASK_BIT7 +#define DSI_IF1_TE_MASK MASK_BIT5 +#define DSI_IF2_TE_MASK MASK_BIT6 +#define DSI_LANE2_EN_MASK MASK_BIT0 +#define DSI_FORCE_STOP_MODE_MASK MASK_BIT1 +#define DSI_CLK_CONTINUOUS_MASK MASK_BIT2 +#define DSI_CLK_ULPM_EN_MASK MASK_BIT3 +#define DSI_DAT1_ULPM_EN_MASK MASK_BIT4 +#define DSI_DAT2_ULPM_EN_MASK MASK_BIT5 +#define DSI_WAIT_BURST_MASK (MASK_BIT6 | MASK_BIT7 | MASK_BIT8 | MASK_BIT9) +#define DSI_CLKLANESTS_MASK (MASK_BIT0 | MASK_BIT1) +#define DSI_DATALANE1STS_MASK (MASK_BIT2 | MASK_BIT3 | MASK_BIT4) +#define DSI_DATALANE2STS_MASK (MASK_BIT5 | MASK_BIT6) +#define DSI_CLK_DIV_MASK MASK_QUARTET0 +#define DSI_HSTX_TO_MASK (MASK_QUARTET1 | MASK_BYTE1 | MASK_BIT16 | MASK_BIT17) +#define DSI_LPRX_TO_MASK (MASK_BYTE3 | MASK_QUARTET5 | MASK_BIT18 | MASK_BIT18) +#define DSI_CLK_ULPOUT_MASK (MASK_BYTE0 | MASK_BIT8) +#define DSI_DATA_ULPOUT_MASK (MASK_QUARTET3 | MASK_BIT9 | MASK_BIT10 | MASK_BIT11 | MASK_BIT16 | MASK_BIT17) +#define DSI_PLL_START_MASK MASK_BIT0 +#define DSI_CKLANE_EN_MASK MASK_BIT3 +#define DSI_DAT1_EN_MASK MASK_BIT4 +#define DSI_DAT2_EN_MASK MASK_BIT5 +#define DSI_CLK_ULPM_MASK MASK_BIT6 +#define DSI_DAT1_ULPM_MASK MASK_BIT7 +#define DSI_DAT2_ULPM_MASK MASK_BIT8 +#define DSI_IF1_EN_MASK MASK_BIT9 +#define DSI_IF2_EN_MASK MASK_BIT10 +#define DSI_MAIN_STS_MASK MASK_BYTE0 +#define DSI_DPHY_ERROR_MASK MASK_HALFWORD0 +#define DSI_IF_DATA_MASK MASK_HALFWORD0 +#define DSI_IF_VALID_MASK MASK_BIT16 +#define DSI_IF_START_MASK MASK_BIT17 +#define DSI_IF_FRAME_SYNC_MASK MASK_BIT18 +#define DSI_IF_STALL_MASK MASK_BIT0 +#define DSI_INT_VAL_MASK MASK_BIT0 +#define DSI_DIRECT_CMD_RD_STS_MASK (MASK_BYTE0 | MASK_BIT8) +#define DSI_CMD_MODE_STS_MASK (MASK_QUARTET0 | MASK_BIT4 | MASK_BIT5) +#define DSI_RD_ID_MASK (MASK_BIT16 | MASK_BIT17 ) +#define DSI_RD_DCSNOTGENERIC_MASK MASK_BIT18 +#define DSI_CMD_NAT_MASK (MASK_BIT0 | MASK_BIT1 | MASK_BIT2) +#define DSI_CMD_LONGNOTSHORT_MASK MASK_BIT3 +#define DSI_CMD_HEAD_MASK (MASK_QUARTET2 | MASK_BIT12 | MASK_BIT13) +#define DSI_CMD_ID_MASK (MASK_BIT14 | MASK_BIT15) +#define DSI_CMD_SIZE_MASK (MASK_QUARTET4 | MASK_BIT20) +#define DSI_CMD_LP_EN_MASK (MASK_BIT21) +#define DSI_TRIGGER_VAL_MASK MASK_QUARTET6 +#define DSI_TE_LOWERBIT_MASK MASK_BYTE2 +#define DSI_TE_UPPERBIT_MASK (MASK_BIT24 | MASK_BIT25) +#define DSI_FIL_VAL_MASK MASK_BYTE1 +#define DSI_ARB_MODE_MASK MASK_BIT6 +#define DSI_ARB_PRI_MASK MASK_BIT7 +#define DSI_START_MODE_MASK (MASK_BIT0 | MASK_BIT1 ) +#define DSI_STOP_MODE_MASK (MASK_BIT2 | MASK_BIT3) +#define DSI_VID_ID_MASK (MASK_BIT4 | MASK_BIT5) +#define DSI_HEADER_MASK (MASK_BIT6 | MASK_BIT7 | MASK_BIT8 | MASK_BIT9 | MASK_BIT10 | MASK_BIT11) +#define DSI_PIXEL_MODE_MASK (MASK_BIT12 | MASK_BIT13) +#define DSI_BURST_MODE_MASK (MASK_BIT14) +#define DSI_SYNC_PULSE_ACTIVE_MASK (MASK_BIT15) +#define DSI_SYNC_PULSE_HORIZONTAL_MASK (MASK_BIT16) +#define DSI_BLKLINE_MASK (MASK_BIT17 | MASK_BIT18) +#define DSI_BLKEOL_MASK (MASK_BIT19 | MASK_BIT20) +#define DSI_RECOVERY_MODE_MASK (MASK_BIT21 | MASK_BIT22) +#define DSI_VSA_LENGTH_MASK MASK_QUARTET0 +#define DSI_VBP_LENGTH_MASK MASK_QUARTET1 +#define DSI_VFP_LENGTH_MASK MASK_BYTE1 +#define DSI_VACT_LENGTH_MASK (MASK_BYTE2 | MASK_QUARTET6) +#define DSI_HSA_LENGTH_MASK MASK_BYTE0 +#define DSI_HBP_LENGTH_MASK MASK_BYTE1 +#define DSI_HFP_LENGTH_MASK (MASK_BYTE2 | MASK_BIT24 | MASK_BIT25 | MASK_BIT26) +#define DSI_RGB_SIZE_MASK (MASK_BYTE0 | MASK_QUARTET2 | MASK_BIT12) +#define DSI_LINE_POS_MASK (MASK_BIT0 | MASK_BIT1) +#define DSI_LINE_VAL_MASK (MASK_BIT2 | MASK_BIT3 | MASK_QUARTET1 | MASK_QUARTET2 | MASK_BIT12) +#define DSI_HORI_POS_MASK (MASK_BIT0 | MASK_BIT1 |MASK_BIT2) +#define DSI_HORI_VAL_MASK (MASK_BYTE1 | MASK_QUARTET1 | MASK_BIT3) +#define DSI_VID_MODE_STS_MASK (MASK_BYTE0 | MASK_BIT8 | MASK_BIT9) +#define DSI_BURST_LP_MASK MASK_BIT16 +#define DSI_MAX_BURST_LIMIT_MASK MASK_HALFWORD0 +#define DSI_MAX_LINE_LIMIT_MASK MASK_HALFWORD1 +#define DSI_EXACT_BURST_LIMIT_MASK MASK_HALFWORD0 +#define DSI_BLKLINE_EVENT_MASK (MASK_BYTE0 | MASK_QUARTET2 | MASK_BIT12) +#define DSI_BLKEOL_PCK_MASK (MASK_BYTE2 | MASK_BIT15 | MASK_BIT14 | MASK_BIT13 | MASK_BIT24 | MASK_BIT25) +#define DSI_BLKLINE_PULSE_PCK_MASK (MASK_BYTE0 | MASK_QUARTET2 | MASK_BIT12) +#define DSI_BLKEOL_DURATION_MASK (MASK_BYTE0 | MASK_QUARTET2 | MASK_BIT12) +#define DSI_VERT_BLANK_DURATION_MASK (MASK_BYTE2 | MASK_BIT15 | MASK_BIT14 | MASK_BIT13 | MASK_BIT24 | MASK_BIT25) +#define DSI_COL_RED_MASK MASK_BYTE0 +#define DSI_COL_GREEN_MASK MASK_BYTE1 +#define DSI_COL_BLUE_MASK MASK_BYTE2 +#define DSI_PAD_VAL_MASK MASK_BYTE3 +#define DSI_TVG_STRIPE_MASK (MASK_BIT5 | MASK_BIT6 | MASK_BIT7) +#define DSI_TVG_MODE_MASK (MASK_BIT3 | MASK_BIT4 ) +#define DSI_TVG_STOPMODE_MASK (MASK_BIT1 | MASK_BIT2 ) +#define DSI_TVG_RUN_MASK MASK_BIT0 +#define DSI_TVG_NBLINE_MASK (MASK_BYTE2 | MASK_BIT24 | MASK_BIT25 | MASK_BIT26) +#define DSI_TVG_LINE_SIZE_MASK (MASK_BYTE0 | MASK_QUARTET2 | MASK_BIT12) +#define DSI_CMD_MODE_STATUS_MASK (MASK_QUARTET0 | MASK_BIT4 | MASK_BIT5 ) +#define DSI_DIRECT_CMD_STS_MASK (MASK_BYTE0 | MASK_BIT8 | MASK_BIT9 | MASK_BIT10 ) +#define DSI_DIRECT_CMD_RD_STATUS_MASK (MASK_BYTE0 | MASK_BIT8 ) +#define DSI_VID_MODE_STATUS_MASK (MASK_BYTE0 | MASK_BIT8 | MASK_BIT9 ) +#define DSI_TG_STS_MASK (MASK_BIT0 | MASK_BIT1) +#define DSI_CLK_TRIM_RD_MASK MASK_BIT0 +#define DSI_IF1_LPM_EN_MASK MASK_BIT4 +#define DSI_IF2_LPM_EN_MASK MASK_BIT5 +#define DSIMCTL_DPHY_STATIC_HS_INVERT_DAT2 MASK_BIT5 +#define DSIMCTL_DPHY_STATIC_SWAP_PINS_DAT2 MASK_BIT4 +#define DSIMCTL_DPHY_STATIC_HS_INVERT_DAT1 MASK_BIT3 +#define DSIMCTL_DPHY_STATIC_SWAP_PINS_DAT1 MASK_BIT2 +#define DSIMCTL_DPHY_STATIC_HS_INVERT_CLK MASK_BIT1 +#define DSIMCTL_DPHY_STATIC_SWAP_PINS_CLK MASK_BIT0 +#define DSIMCTL_DPHY_STATIC_UI_X4 (MASK_BIT6 | MASK_BIT7 | MASK_QUARTET2) + +#define DSI_MCTL_INTERFACE1_MODE_SHIFT 1 +#define DSI_MCTL_VID_EN_SHIF 2 +#define DSI_MCTL_TVG_SEL_SHIFT 3 +#define DSI_MCTL_TBG_SEL_SHIFT 4 +#define DSI_MCTL_READEN_SHIFT 8 +#define DSI_MCTL_BTAEN_SHIFT 9 +#define DSI_MCTL_DISPECCGEN_SHIFT 10 +#define DSI_MCTL_DISPCHECKSUMGEN_SHIFT 11 +#define DSI_MCTL_HOSTEOTGEN_SHIFT 12 +#define DSI_MCTL_DISPEOTGEN_SHIFT 13 +#define DSI_PLL_MASTER_SHIFT 16 +#define DSI_PLL_OUT_SEL_SHIFT 11 +#define DSI_PLL_IN_SEL_SHIFT 10 +#define DSI_MCTL_VID_EN_SHIFT 2 +#define DSI_PLL_DIV_SHIFT 7 +#define DSI_REG_TE_SHIFT 7 +#define DSI_IF1_TE_SHIFT 5 +#define DSI_IF2_TE_SHIFT 6 +#define DSI_FORCE_STOP_MODE_SHIFT 1 +#define DSI_CLK_CONTINUOUS_SHIFT 2 +#define DSI_CLK_ULPM_EN_SHIFT 3 +#define DSI_DAT1_ULPM_EN_SHIFT 4 +#define DSI_DAT2_ULPM_EN_SHIFT 5 +#define DSI_WAIT_BURST_SHIFT 6 +#define DSI_DATALANE1STS_SHIFT 2 +#define DSI_DATALANE2STS_SHIFT 5 +#define DSI_HSTX_TO_SHIFT 4 +#define DSI_LPRX_TO_SHIFT 18 +#define DSI_DATA_ULPOUT_SHIFT 9 +#define DSI_CKLANE_EN_SHIFT 3 +#define DSI_DAT1_EN_SHIFT 4 +#define DSI_DAT2_EN_SHIFT 5 +#define DSI_CLK_ULPM_SHIFT 6 +#define DSI_DAT1_ULPM_SHIFT 7 +#define DSI_DAT2_ULPM_SHIFT 8 +#define DSI_IF1_EN_SHIFT 9 +#define DSI_IF2_EN_SHIFT 10 +#define DSI_IF_VALID_SHIFT 16 +#define DSI_IF_START_SHIFT 17 +#define DSI_IF_FRAME_SYNC_SHIFT 18 +#define DSI_RD_ID_SHIFT 16 +#define DSI_RD_DCSNOTGENERIC_SHIFT 18 +#define DSI_CMD_LONGNOTSHORT_SHIFT 3 +#define DSI_CMD_HEAD_SHIFT 8 +#define DSI_CMD_ID_SHIFT 14 +#define DSI_CMD_SIZE_SHIFT 16 +#define DSI_CMD_LP_EN_SHIFT 21 +#define DSI_TRIGGER_VAL_SHIFT 24 +#define DSI_TE_LOWERBIT_SHIFT 16 +#define DSI_TE_UPPERBIT_SHIFT 24 +#define DSI_FIL_VAL_SHIFT 8 +#define DSI_ARB_MODE_SHIFT 6 +#define DSI_ARB_PRI_SHIFT 7 +#define DSI_STOP_MODE_SHIFT 2 +#define DSI_VID_ID_SHIFT 4 +#define DSI_HEADER_SHIFT 6 +#define DSI_PIXEL_MODE_SHIFT 12 +#define DSI_BURST_MODE_SHIFT 14 +#define DSI_SYNC_PULSE_ACTIVE_SHIFT 15 +#define DSI_SYNC_PULSE_HORIZONTAL_SHIFT 16 +#define DSI_BLKLINE_SHIFT 17 +#define DSI_BLKEOL_SHIFT 19 +#define DSI_RECOVERY_MODE_SHIFT 21 +#define DSI_VBP_LENGTH_SHIFT 4 +#define DSI_VFP_LENGTH_SHIFT 8 +#define DSI_VACT_LENGTH_SHIFT 16 +#define DSI_HBP_LENGTH_SHIFT 8 +#define DSI_HFP_LENGTH_SHIFT 16 +#define DSI_LINE_VAL_SHIFT 2 +#define DSI_HORI_VAL_SHIFT 3 +#define DSI_BURST_LP_SHIFT 16 +#define DSI_MAX_LINE_LIMIT_SHIFT 16 +#define DSI_BLKEOL_PCK_SHIFT 13 +#define DSI_VERT_BLANK_DURATION_SHIFT 13 +#define DSI_COL_GREEN_SHIFT 8 +#define DSI_COL_BLUE_SHIFT 16 +#define DSI_PAD_VAL_SHIFT 24 +#define DSI_TVG_STRIPE_SHIFT 1 +#define DSI_TVG_MODE_SHIFT 3 +#define DSI_TVG_STOPMODE_SHIFT 5 +#define DSI_TVG_NBLINE_SHIFT 16 +#define DSIMCTL_DPHY_STATIC_SWAP_PINS_CLK_SHIFT 0 +#define DSIMCTL_DPHY_STATIC_HS_INVERT_CLK_SHIFT 1 +#define DSIMCTL_DPHY_STATIC_SWAP_PINS_DAT1_SHIFT 2 +#define DSIMCTL_DPHY_STATIC_HS_INVERT_DAT1_SHIFT 3 +#define DSIMCTL_DPHY_STATIC_SWAP_PINS_DAT2_SHIFT 4 +#define DSIMCTL_DPHY_STATIC_HS_INVERT_DAT2_SHIFT 5 +#define DSIMCTL_DPHY_STATIC_UI_X4_SHIFT 6 +#define DSI_IF1_LPM_EN_MASK_SHIFT 4 +#define DSI_IF2_LPM_EN_MASK_SHIFT 5 + +#define DSI_MCTL_MAIN_STS_VRS_UNTERM_PCK 0x80 +#define DSI_MCTL_MAIN_STS_VRS_UNTERM_PCK_SHIFT 7 + +#define DSI_MCTL_MAIN_STS_CRS_UNTERM_PCK 0x40 +#define DSI_MCTL_MAIN_STS_CRS_UNTERM_PCK_SHIFT 6 + +#define DSI_MCTL_MAIN_STS_LPRX_TO_ERR 0x20 +#define DSI_MCTL_MAIN_STS_LPRX_TO_ERR_SHIFT 5 + +#define DSI_MCTL_MAIN_STS_HSTX_TO_ERR 0x10 +#define DSI_MCTL_MAIN_STS_HSTX_TO_ERR_SHIFT 4 + +#define DSI_MCTL_MAIN_STS_DAT2_READY 0x8 +#define DSI_MCTL_MAIN_STS_DAT2_READY_SHIFT 3 + +#define DSI_MCTL_MAIN_STS_DAT1_READY 0x4 +#define DSI_MCTL_MAIN_STS_DAT1_READY_SHIFT 2 + +#define DSI_MCTL_MAIN_STS_CLKLANE_READY 0x2 +#define DSI_MCTL_MAIN_STS_CLKLANE_READY_SHIFT 1 + +#define DSI_MCTL_MAIN_STS_PLL_LOCK 0x1 +#define DSI_MCTL_MAIN_STS_PLL_LOCK_SHIFT 0 +/** Test mode conf */ + +//********************************************************************************************************************** +/** - DIRECT_CMD_WRDAT0 */ +//********************************************************************************************************************** + +#define DSIDIRECT_CMD_WRDAT0_WRDAT3 (0xFF000000) +#define Shift_DSIDIRECT_CMD_WRDAT0_WRDAT3 (24) +#define DSIDIRECT_CMD_WRDAT0_WRDAT2 (0xFF0000) +#define Shift_DSIDIRECT_CMD_WRDAT0_WRDAT2 (16) +#define DSIDIRECT_CMD_WRDAT0_WRDAT1 (0xFF00) +#define Shift_DSIDIRECT_CMD_WRDAT0_WRDAT1 (8) +#define DSIDIRECT_CMD_WRDAT0_WRDAT0 (0xFF) +#define Shift_DSIDIRECT_CMD_WRDAT0_WRDAT0 (0) + +//********************************************************************************************************************** +/** - DIRECT_CMD_WRDAT1 */ +//********************************************************************************************************************** + +#define DSIDIRECT_CMD_WRDAT1_WRDAT7 (0xFF000000) +#define Shift_DSIDIRECT_CMD_WRDAT1_WRDAT7 (24) +#define DSIDIRECT_CMD_WRDAT1_WRDAT6 (0xFF0000) +#define Shift_DSIDIRECT_CMD_WRDAT1_WRDAT6 (16) +#define DSIDIRECT_CMD_WRDAT1_WRDAT5 (0xFF00) +#define Shift_DSIDIRECT_CMD_WRDAT1_WRDAT5 (8) +#define DSIDIRECT_CMD_WRDAT1_WRDAT4 (0xFF) +#define Shift_DSIDIRECT_CMD_WRDAT1_WRDAT4 (0) + + +//********************************************************************************************************************** +/** - DIRECT_CMD_WRDAT2 */ +//********************************************************************************************************************** + +#define DSIDIRECT_CMD_WRDAT2_WRDAT11 (0xFF000000) +#define Shift_DSIDIRECT_CMD_WRDAT2_WRDAT11 (24) +#define DSIDIRECT_CMD_WRDAT2_WRDAT10 (0xFF0000) +#define Shift_DSIDIRECT_CMD_WRDAT2_WRDAT10 (16) +#define DSIDIRECT_CMD_WRDAT2_WRDAT9 (0xFF00) +#define Shift_DSIDIRECT_CMD_WRDAT2_WRDAT9 (8) +#define DSIDIRECT_CMD_WRDAT2_WRDAT8 (0xFF) +#define Shift_DSIDIRECT_CMD_WRDAT2_WRDAT8 (0) + +//********************************************************************************************************************** +/** - DIRECT_CMD_WRDAT3 */ +//********************************************************************************************************************** + +#define DSIDIRECT_CMD_WRDAT3_WRDAT15 (0xFF000000) +#define Shift_DSIDIRECT_CMD_WRDAT3_WRDAT15 (24) +#define DSIDIRECT_CMD_WRDAT3_WRDAT14 (0xFF0000) +#define Shift_DSIDIRECT_CMD_WRDAT3_WRDAT14 (16) +#define DSIDIRECT_CMD_WRDAT3_WRDAT13 (0xFF00) +#define Shift_DSIDIRECT_CMD_WRDAT3_WRDAT13 (8) +#define DSIDIRECT_CMD_WRDAT3_WRDAT12 (0xFF) +#define Shift_DSIDIRECT_CMD_WRDAT3_WRDAT12 (0) +//********************************************************************************************************************** +/** - DIRECT_CMD_READ */ +//********************************************************************************************************************** + +#define DSIDIRECT_CMD_RDAT3 (0xFF000000) +#define Shift_DSIDIRECT_CMD_RDAT3 (24) +#define DSIDIRECT_CMD_RDAT2 (0xFF0000) +#define Shift_DSIDIRECT_CMD_RDAT2 (16) +#define DSIDIRECT_CMD_RDAT1 (0xFF00) +#define Shift_DSIDIRECT_CMD_RDAT1 (8) +#define DSIDIRECT_CMD_RDAT0 (0xFF) +#define Shift_DSIDIRECT_CMD_RDAT0 (0) + +/** TPO COMMAND HEADER */ +#define TPO_CMD_NONE 0x00 +#define TPO_CMD_SWRESET 0x01 /** SWRESET: Software Reset (01h) */ +#define TPO_CMD_SLPOUT 0x11 /** SLPOUT: Sleep Out (11h) */ +#define TPO_CMD_NORON 0x13 /** NORON: Normal Display Mode On (13h) */ +#define TPO_CMD_INVOFF 0x20 /** INVOFF: Display Inversion Off (20h) */ +#define TPO_CMD_INVON 0x21 /** INVOFF: Display Inversion Off (20h) */ +#define TPO_CMD_GAMMA_SET 0x26 /** Gamma set//reset GC0G2.2 */ + +#define TPO_CMD_DISPOFF 0x28 /** DISPON: Display On (29h) */ +#define TPO_CMD_DISPON 0x29 /** DISPON: Display On (29h) */ +#define TPO_CMD_CASET 0x2A /** CASET :Columen address select */ +#define TPO_CMD_RASET 0x2B /** RASET :Row address select */ +#define TPO_CMD_RAMWR 0x2C /** RAMWR ram write */ + +#define TPO_CMD_MADCTR 0x36 /** MADCTR: Memory Data Access Control (36h) */ +#define TPO_CMD_IDMOFF 0x38 /** IDMON: Idle Mode On (39h) */ +#define TPO_CMD_IDMON 0x39 /** IDMON: Idle Mode On (39h) */ +#define TPO_CMD_COLMOD 0x3A /** COLMOD: Interface Pixel Format (3Ah). */ +#define TPO_CMD_RAMWR_CONTINUE 0x3C /** Ram write continue */ +#define TPO_CMD_IFMODE 0xB0 /** IFMODE: Set Display Interface Mode (B0h) */ +#define TPO_CMD_DISSET6 0xB7 /** Display Function Setting 6 (B7h) */ +#define TPO_CMD_LPTS_FUNCTION_SET3 0xBC /** LPTS_FUNCTION_SET3 (0xBC) */ +#define TPO_CMD_DSLPOUT 0xCA /** deep sleepout 0xca */ + + +#define TPO_CMD_GAMCTRP1 0xE0 /** GAMCTRP1: Set Positive Gamma Correction Characteristics (E0h) */ +#define TPO_CMD_GAMCTRN1 0xE1 /** GAMCTRN1: Set Negative Gamma Correction Characteristics (E1h) */ +#define TPO_CMD_GAMCTRP2 0xE2 /** GAMCTRP2: Gamma (‘+’polarity) Correction Characteristics Setting (E2h) */ +#define TPO_CMD_GAMCTRN2 0xE3 /** GAMCTRN2: Gamma (‘-’polarity) Correction Characteristics Setting (E3h) */ +#define TPO_CMD_GAMCTRP3 0xE4 /** GAMCTRP3: Gamma (‘+’polarity) Correction Characteristics Setting (E4h) */ +#define TPO_CMD_GAMCTRN3 0xE5 /** GAMCTRN3: Gamma (‘-’polarity) Correction Characteristics Setting (E5h) */ +#define TPO_CMD_GAM_R_SEL 0xEA /** GAMMA SELECTION */ + + + +#define VC_ID0 0 +#define VC_ID1 1 + + + + +struct dsi_link_registers +{ + /** Main control registers */ + volatile u32 mctl_integration_mode; + volatile u32 mctl_main_data_ctl; + volatile u32 mctl_main_phy_ctl; + volatile u32 mctl_pll_ctl; + volatile u32 mctl_lane_sts; + volatile u32 mctl_dphy_timeout; + volatile u32 mctl_ulpout_time; + volatile u32 mctl_dphy_static; + volatile u32 mctl_main_en; + volatile u32 mctl_main_sts; + volatile u32 mctl_dphy_err; + + volatile u32 reserved1; + /** + integration mode registers */ + volatile u32 int_vid_rddata; + volatile u32 int_vid_gnt; + volatile u32 int_cmd_rddata; + volatile u32 int_cmd_gnt; + volatile u32 int_interrupt_ctl; + volatile u32 reserved2[3]; + /** + Command mode registers */ + volatile u32 cmd_mode_ctl; + volatile u32 cmd_mode_sts; + volatile u32 reserved3[2]; + /** + Direct Command registers */ + volatile u32 direct_cmd_send; + volatile u32 direct_cmd_main_settings; + volatile u32 direct_cmd_sts; + volatile u32 direct_cmd_rd_init; + volatile u32 direct_cmd_wrdat0; + volatile u32 direct_cmd_wrdat1; + volatile u32 direct_cmd_wrdat2; + volatile u32 direct_cmd_wrdat3; + volatile u32 direct_cmd_rddat; + volatile u32 direct_cmd_rd_property; + volatile u32 direct_cmd_rd_sts; + volatile u32 reserved4; + /** + Video mode registers */ + volatile u32 vid_main_ctl; + volatile u32 vid_vsize; + volatile u32 vid_hsize1; + volatile u32 vid_hsize2; + volatile u32 vid_blksize1; + volatile u32 vid_blksize2; + volatile u32 vid_pck_time; + volatile u32 vid_dphy_time; + volatile u32 vid_err_color; + volatile u32 vid_vpos; + volatile u32 vid_hpos; + volatile u32 vid_mode_sts; + volatile u32 vid_vca_setting1; + volatile u32 vid_vca_setting2; + /** + Test Video Mode regsiter */ + volatile u32 tvg_ctl; + volatile u32 tvg_img_size; + volatile u32 tvg_color1; + volatile u32 tvg_color2; + volatile u32 tvg_sts; + volatile u32 reserved5; + /** + Test Byte generator register */ + volatile u32 tbg_ctl; + volatile u32 tbg_setting; + volatile u32 tbg_sts; + volatile u32 reserved6; + /** + Interrupt Enable and Edge detection register */ + volatile u32 mctl_main_sts_ctl; + volatile u32 cmd_mode_sts_ctl; + volatile u32 direct_cmd_sts_ctl; + volatile u32 direct_cmd_rd_sts_ctl; + volatile u32 vid_mode_sts_ctl; + volatile u32 tg_sts_ctl; + volatile u32 mctl_dphy_err_ctl; + volatile u32 dphy_clk_trim_rd_ctl; + /** + Error/Interrupt Clear Register */ + volatile u32 mctl_main_sts_clr; + volatile u32 cmd_mode_sts_clr; + volatile u32 direct_cmd_sts_clr; + volatile u32 direct_cmd_rd_sts_clr; + volatile u32 vid_mode_sts_clr; + volatile u32 tg_sts_clr; + volatile u32 mctl_dphy_err_clr; + volatile u32 dphy_clk_trim_rd_clr; + /** + Flag registers */ + volatile u32 mctl_main_sts_flag; + volatile u32 cmd_mode_sts_flag; + volatile u32 direct_cmd_sts_flag; + volatile u32 direct_cmd_rd_sts_flag; + volatile u32 vid_mode_sts_flag; + volatile u32 tg_sts_flag; + volatile u32 mctl_dphy_err_flag; + volatile u32 dphy_clk_trim_rd_flag; + volatile u32 dhy_lanes_trim; +}; + + + +#ifdef _cplusplus +} +#endif /* _cplusplus */ + +#endif /* !defined(_DSI_H_) */ + + diff --git a/arch/arm/mach-ux500/include/mach/entry-macro.S b/arch/arm/mach-ux500/include/mach/entry-macro.S new file mode 100755 index 00000000000..af3998021e2 --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/entry-macro.S @@ -0,0 +1,84 @@ +/* + * Low-level IRQ helper macros for U8500 platforms based + * heavily on realview platform + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ +#include <mach/hardware.h> +#include <asm/hardware/gic.h> + + .macro disable_fiq + .endm + + .macro get_irqnr_preamble, base, tmp + ldr \base, =IO_ADDRESS(U8500_GIC_CPU_BASE) + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + + /* + * The interrupt numbering scheme is defined in the + * interrupt controller spec. To wit: + * + * Interrupts 0-15 are IPI + * 16-28 are reserved + * 29-31 are local. We allow 30 to be used for the watchdog. + * 32-1020 are global + * 1021-1022 are reserved + * 1023 is "spurious" (no interrupt) + * + * For now, we ignore all local interrupts so only return an + * interrupt if it's between 30 and 1020. The test_for_ipi + * routine below will pick up on IPIs. + * + * A simple read from the controller will tell us the number + * of the highest priority enabled interrupt. We then just + * need to check whether it is in the + * valid range for an IRQ (30-1020 inclusive). + */ + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + /* bits 12-10 = src CPU, 9-0 = int # */ + ldr \irqstat, [\base, #GIC_CPU_INTACK] + + ldr \tmp, =1021 + + bic \irqnr, \irqstat, #0x1c00 + + cmp \irqnr, #29 + cmpcc \irqnr, \irqnr + cmpne \irqnr, \tmp + cmpcs \irqnr, \irqnr + + .endm + + /* We assume that irqstat (the raw value of the IRQ acknowledge + * register) is preserved from the macro above. + * If there is an IPI, we immediately signal end of interrupt + * on the controller, since this requires the original + * irqstat value which we won't easily be able to recreate + * later. + */ + + .macro test_for_ipi, irqnr, irqstat, base, tmp + bic \irqnr, \irqstat, #0x1c00 + cmp \irqnr, #16 + strcc \irqstat, [\base, #GIC_CPU_EOI] + cmpcs \irqnr, \irqnr + .endm + + /* As above, this assumes that irqstat and base are + * preserved.. + */ + + .macro test_for_ltirq, irqnr, irqstat, base, tmp + bic \irqnr, \irqstat, #0x1c00 + mov \tmp, #0 + cmp \irqnr, #29 + moveq \tmp, #1 + streq \irqstat, [\base, #GIC_CPU_EOI] + cmp \tmp, #0 + .endm diff --git a/arch/arm/mach-ux500/include/mach/gpio.h b/arch/arm/mach-ux500/include/mach/gpio.h new file mode 100755 index 00000000000..b358f71b8cd --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/gpio.h @@ -0,0 +1,190 @@ +/*----------------------------------------------------------------------------------*/ +/* copyright STMicroelectronics, 2007. */ +/* */ +/* This program is free software; you can redistribute it and/or modify it under */ +/* the terms of the GNU General Public License as published by the Free */ +/* Software Foundation; either version 2.1 of the License, or (at your option) */ +/* any later version. */ +/* */ +/* This program is distributed in the hope that it will be useful, but WITHOUT */ +/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS */ +/* FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. */ +/* */ +/* You should have received a copy of the GNU General Public License */ +/* along with this program. If not, see <http://www.gnu.org/licenses/>. */ +/*----------------------------------------------------------------------------------*/ +#ifndef __MACH_GPIO_H +#define __MACH_GPIO_H + +#ifndef __LINUX_GPIO_H +#error "Do not include this file directly, include <linux/gpio.h> instead." +#endif + +#define ARCH_NR_GPIOS 309 /* 292+17 for STMPE1601*/ + +#include <mach/hardware.h> +#include <asm-generic/gpio.h> +#include <mach/irqs.h> + +/* + * Macro to decorate plain GPIO numbers + */ +#define GPIO(x) (x) +#define stm_get_gpio_base(base, offset) base +/* + * Macros to get IRQ number from GPIO pin and vice-versa + */ +#define GPIO_TO_IRQ(gpio) (gpio + MAX_CHIP_IRQ) +#define IRQ_TO_GPIO(irq) (irq - MAX_CHIP_IRQ) + +/* + * Standard GPIOLIB APIs (additional APIs in include/asm-generic/gpio.h) + */ +static inline int gpio_to_irq(unsigned int gpio) +{ + if (gpio_is_valid(gpio)) + return GPIO_TO_IRQ(gpio); + else + return -EINVAL; +} + +static inline int irq_to_gpio(unsigned int irq) +{ + if (irq < NR_IRQS) + return IRQ_TO_GPIO(irq); + else + return -EINVAL; +} + +static inline int gpio_get_value(unsigned int gpio) +{ + return __gpio_get_value(gpio); +} + +static inline void gpio_set_value(unsigned int gpio, int value) +{ + __gpio_set_value(gpio, value); +} + +/* + * Special values for gpio_set_value() to enable platform-specific + * GPIO configurations, in addition to named values for 0 and 1 + */ +#define GPIO_LOW 0 +#define GPIO_HIGH 1 +#define GPIO_PULLUP_DIS 0xA +#define GPIO_PULLUP_EN 0xB +#define GPIO_ALTF_A 0xAFA /* Alternate function A */ +#define GPIO_ALTF_B 0xAFB /* Alternate function B */ +#define GPIO_ALTF_C 0xAFC /* Alternate function C */ +#define GPIO_RESET 0xAFD /* Input with pull-up/down */ + +/* + * Alternate Function: + * refered in altfun_table to pointout particular altfun to be enabled + * when using GPIO_ALT_FUNCTION A/B/C enable/disable operation + */ +typedef enum { + GPIO_ALT_UART_0_MODEM, + GPIO_ALT_UART_0_NO_MODEM, + GPIO_ALT_UART_1, + GPIO_ALT_UART_2, + GPIO_ALT_I2C_0, + GPIO_ALT_I2C_1, + GPIO_ALT_I2C_2, + GPIO_ALT_I2C_3, + GPIO_ALT_I2C_4, + GPIO_ALT_MSP_0, + GPIO_ALT_MSP_1, + GPIO_ALT_MSP_2, + GPIO_ALT_MSP_3, + GPIO_ALT_SSP_0, + GPIO_ALT_SSP_1, + GPIO_ALT_MM_CARD, + GPIO_ALT_SD_CARD, + GPIO_ALT_DMA_0, + GPIO_ALT_DMA_1, + GPIO_ALT_HSIR, + GPIO_ALT_CCIR656_INPUT, + GPIO_ALT_CCIR656_OUTPUT, + GPIO_ALT_LCD_PANELA, + GPIO_ALT_LCD_PANELB_ED, + GPIO_ALT_LCD_PANELB, + GPIO_ALT_MDIF, + GPIO_ALT_SDRAM, + GPIO_ALT_HAMAC_AUDIO_DBG, + GPIO_ALT_HAMAC_VIDEO_DBG, + GPIO_ALT_CLOCK_RESET, + GPIO_ALT_TSP, + GPIO_ALT_IRDA, + GPIO_ALT_USB_MINIMUM, + GPIO_ALT_USB_I2C, + GPIO_ALT_OWM, + GPIO_ALT_PWL, + GPIO_ALT_FSMC, + GPIO_ALT_COMP_FLASH, + GPIO_ALT_SRAM_NOR_FLASH, + GPIO_ALT_FSMC_ADDLINE_0_TO_15, + GPIO_ALT_SCROLL_KEY, + GPIO_ALT_MSHC, + GPIO_ALT_HPI, + GPIO_ALT_USB_OTG, + GPIO_ALT_SDIO, + GPIO_ALT_HSMMC, + GPIO_ALT_FSMC_ADD_DATA_0_TO_25, + GPIO_ALT_HSIT, + GPIO_ALT_NOR, + GPIO_ALT_NAND, + GPIO_ALT_KEYPAD, + GPIO_ALT_VPIP, + GPIO_ALT_CAM, + GPIO_ALT_CCP1, + GPIO_ALT_EMMC, + GPIO_ALT_SDMMC, + GPIO_ALT_TRACE, + GPIO_ALT_MMIO_INIT_BOARD, + GPIO_ALT_MMIO_CAM_SET_I2C, + GPIO_ALT_MMIO_CAM_SET_EXT_CLK, + GPIO_ALT_SDMMC2, + GPIO_ALT_TP_SET_EXT_CLK, + GPIO_ALT_FUNMAX /* Add new alt func before this */ + + +} gpio_alt_function; + +/* GPIO pin data*/ +typedef enum { + GPIO_DATA_LOW, /* GPIO pin status is low. */ + GPIO_DATA_HIGH /* GPIO pin status is high. */ +} gpio_data; + +struct gpio_altfun_data { + gpio_alt_function altfun; + int start; + int end; + int cont; + int type; + char dev_name[20]; +}; + +struct clk; +struct gpio_platform_data { + struct gpio_block_data *gpio_data; + int gpio_block_size; + struct gpio_altfun_data *altfun_table; + int altfun_table_size; + struct clk *clk; /* FIXME put this somewhere more appropriate */ +}; + +struct gpio_block_data { + u32 block_base; + u32 block_size; + u32 base_offset; + int blocks_per_irq; + int irq; +}; + +extern int stm_gpio_altfuncenable(gpio_alt_function alt_func); +extern int stm_gpio_altfuncdisable(gpio_alt_function alt_func); + +#endif /* __INC_GPIO_H */ diff --git a/arch/arm/mach-ux500/include/mach/hardware.h b/arch/arm/mach-ux500/include/mach/hardware.h new file mode 100755 index 00000000000..cd37b6bb1ee --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/hardware.h @@ -0,0 +1,219 @@ +/* + * Copyright (C) 2009 ST-Ericsson. + * + * U8500 hardware definitions + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#define IO_BASE 0xF0000000 /* VA of IO */ +#define IO_SIZE 0x1FF00000 /* VA Size for IO */ +#define IO_START 0x10100000 /* PA of IO */ + +/* + * macro to get at IO space when running virtually + */ +#define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + IO_BASE) + +#include <mach/db8500-regs.h> +#include <mach/db5500-regs.h> + +#ifdef CONFIG_UX500_SOC_DB8500 +#define UX500(periph) U8500_##periph##_BASE +#elif defined(CONFIG_UX500_SOC_DB5500) +#define UX500(periph) U5500_##periph##_BASE +#endif + +#define UX500_BACKUPRAM0_BASE UX500(BACKUPRAM0) +#define UX500_BACKUPRAM1_BASE UX500(BACKUPRAM1) +#define UX500_B2R2_BASE UX500(B2R2) + +#define UX500_CLKRST1_BASE UX500(CLKRST1) +#define UX500_CLKRST2_BASE UX500(CLKRST2) +#define UX500_CLKRST3_BASE UX500(CLKRST3) +#define UX500_CLKRST5_BASE UX500(CLKRST5) +#define UX500_CLKRST6_BASE UX500(CLKRST6) + +#define UX500_DMA_BASE UX500(DMA) +#define UX500_FSMC_BASE UX500(FSMC) + +#define UX500_GIC_CPU_BASE UX500(GIC_CPU) +#define UX500_GIC_DIST_BASE UX500(GIC_DIST) + +#define UX500_I2C1_BASE UX500(I2C1) +#define UX500_I2C2_BASE UX500(I2C2) +#define UX500_I2C3_BASE UX500(I2C3) + +#define UX500_L2CC_BASE UX500(L2CC) +#define UX500_MCDE_BASE UX500(MCDE) +#define UX500_MTU0_BASE UX500(MTU0) +#define UX500_MTU1_BASE UX500(MTU1) +#define UX500_PRCMU_BASE UX500(PRCMU) + +#define UX500_RNG_BASE UX500(RNG) +#define UX500_RTC_BASE UX500(RTC) + +#define UX500_SCU_BASE UX500(SCU) + +#define UX500_SDI0_BASE UX500(SDI0) +#define UX500_SDI1_BASE UX500(SDI1) +#define UX500_SDI2_BASE UX500(SDI2) +#define UX500_SDI3_BASE UX500(SDI3) +#define UX500_SDI4_BASE UX500(SDI4) + +#define UX500_SPI0_BASE UX500(SPI0) +#define UX500_SPI1_BASE UX500(SPI1) +#define UX500_SPI2_BASE UX500(SPI2) +#define UX500_SPI3_BASE UX500(SPI3) + +#define UX500_SIA_BASE UX500(SIA) +#define UX500_SVA_BASE UX500(SVA) + +#define UX500_TWD_BASE UX500(TWD) + +#define UX500_UART0_BASE UX500(UART0) +#define UX500_UART1_BASE UX500(UART1) +#define UX500_UART2_BASE UX500(UART2) + +#define UX500_USBOTG_BASE UX500(USBOTG) + +#define U8500_ESRAM_BASE 0x40000000 +#define U8500_ESRAM_DMA_LCLA_OFFSET 0x80000 +#define U8500_ESRAM_DMA_LCPA_OFFSET 0x84000 + +#define U8500_DMA_LCLA_BASE (U8500_ESRAM_BASE + U8500_ESRAM_DMA_LCLA_OFFSET) +#define U8500_DMA_LCPA_BASE (U8500_ESRAM_BASE + U8500_ESRAM_DMA_LCPA_OFFSET) + +/* SSP specific declaration */ +#define SSP_PER_ID 0x01080022 +#define SSP_PER_MASK 0x0fffffff + +/* SSP specific declaration */ +#define SPI_PER_ID 0x00080023 +#define SPI_PER_MASK 0x0fffffff + +/* MSP specific declaration */ +#define MSP_PER_ID 0x00280021 +#define MSP_PER_MASK 0x00ffffff + +/* DMA specific declaration */ +#define DMA_PER_ID 0x8A280080 +#define DMA_PER_MASK 0xffffffff + +#define GPIO_TOTAL_PINS 267 +#define GPIO_PER_ID 0x1f380060 +#define GPIO_PER_MASK 0xffffffff + +/* RTC specific declaration */ +#define RTC_PER_ID 0x00280031 +#define RTC_PER_MASK 0x00ffffff + +/* + * FIFO offsets for IPs + */ +#define I2C_TX_REG_OFFSET (0x10) +#define I2C_RX_REG_OFFSET (0x18) +#define UART_TX_RX_REG_OFFSET (0) +#define MSP_TX_RX_REG_OFFSET (0) +#define SSP_TX_RX_REG_OFFSET (0x8) +#define SPI_TX_RX_REG_OFFSET (0x8) +#define SD_MMC_TX_RX_REG_OFFSET (0x80) + +#define MSP_0_CONTROLLER 1 +#define MSP_1_CONTROLLER 2 +#define MSP_2_CONTROLLER 3 + +#define SSP_0_CONTROLLER 4 +#define SSP_1_CONTROLLER 5 + +#define SPI023_0_CONTROLLER 6 +#define SPI023_1_CONTROLLER 7 +#define SPI023_2_CONTROLLER 8 +#define SPI023_3_CONTROLLER 9 + +/* MSP related board specific declaration************************/ + +#define MSP_DATA_DELAY MSP_DELAY_0 +#define MSP_TX_CLOCK_EDGE MSP_FALLING_EDGE +#define MSP_RX_CLOCK_EDGE MSP_FALLING_EDGE +#define NUM_MSP_CONTROLLER 3 + +/* I2C configuration + * * * + * * */ +#define I2C0_LP_OWNADDR 0x31 +#define I2C1_LP_OWNADDR 0x60 +#define I2C2_LP_OWNADDR 0x70 +#define I2C3_LP_OWNADDR 0x80 +#define I2C4_LP_OWNADDR 0x90 + +/* SDMMC specific declarations */ +#define SDI_PER_ID 0x00480180 +#define SDI_PER_MASK 0x00ffffff +/* B2R2 clock management register */ +#define PRCM_B2R2CLK_MGT_REG 0x80157078 /** B2R2 clock selection */ + +#include <mach/mcde-base.h> + +#ifndef __ASSEMBLY__ + +#include <asm/cputype.h> + +/* TODO: dynamic detection */ +static inline bool cpu_is_u8500(void) +{ +#ifdef CONFIG_UX500_SOC_DB8500 + return 1; +#else + return 0; +#endif +} + +static inline bool cpu_is_u8500ed(void) +{ +#ifdef CONFIG_MACH_U8500_SIMULATOR + /* + * SVP8500v1 unfortunately does not implement the changed MIDR register + * on v1, but instead maintains the old ED revision. + * + * So we hardcode this assuming that only SVP8500v1 is supported. If + * SVP8500ed is required, another Kconfig option will have to be added. + */ + return 0; +#else + return cpu_is_u8500() && ((read_cpuid_id() & 15) == 0); +#endif +} + +static inline bool cpu_is_u8500v1(void) +{ +#ifdef CONFIG_MACH_U8500_SIMULATOR + /* See comment in cpu_is_u8500ed() */ + return cpu_is_u8500(); +#else + return cpu_is_u8500() && ((read_cpuid_id() & 15) == 1); +#endif +} + +static inline bool cpu_is_u5500(void) +{ +#ifdef CONFIG_UX500_SOC_DB5500 + return 1; +#else + return 0; +#endif +} + +/* Deprecated, don't use in new code. Just call cpu_is_u8500ed() directly. */ +static inline int u8500_is_earlydrop(void) +{ + return cpu_is_u8500ed(); +} + +#endif + +#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/mach-ux500/include/mach/hcl_defs.h b/arch/arm/mach-ux500/include/mach/hcl_defs.h new file mode 100755 index 00000000000..ce8ac33618f --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/hcl_defs.h @@ -0,0 +1,252 @@ +/* + * Copyright (C) 2009 ST Ericsson. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef _HCL_DEFS_H +#define _HCL_DEFS_H +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +//#include "platform_os.h" + +/*----------------------------------------------------------------------------- + * Type definition + *---------------------------------------------------------------------------*/ +typedef unsigned char t_uint8; +typedef signed char t_sint8; +typedef unsigned short t_uint16; +typedef signed short t_sint16; +typedef unsigned long t_uint32; +typedef signed long t_sint32; + +typedef unsigned int t_bitfield; + + + +#if !defined(FALSE) && !defined(TRUE) +typedef int t_bool; +#define FALSE 0 +#define TRUE 1 +#endif + +/* + * Definition of the different kind of addresses manipulated into a system with MMU + * (handle physical AND logical addresses) + */ + + +typedef t_uint32 t_physical_address; +typedef t_uint32 t_logical_address; + + + +/* + * Global frequency enumuration + * Added to avoid frequency conversion function which is required to convert one HCL + * frequency enumuration values to another HCL frequency enumuration values. + */ + +/*typedef enum { + HCL_FREQ_NOT_SUPPORTED=-1, + HCL_FREQ_8KHZ , + HCL_FREQ_11_25KHZ, + HCL_FREQ_12KHZ, + HCL_FREQ_16KHZ, + HCL_FREQ_22_05KHZ, + HCL_FREQ_22_5KHZ, + HCL_FREQ_24KHZ, + HCL_FREQ_32KHZ, + HCL_FREQ_44KHZ, + HCL_FREQ_44_1KHZ, + HCL_FREQ_48KHZ, + HCL_FREQ_64KHZ, + HCL_FREQ_88KHZ, + HCL_FREQ_88_2KHZ, + HCL_FREQ_96KHZ, + HCL_FREQ_128KHZ, + HCL_FREQ_176_4KHZ, + HCL_FREQ_192KHZ, + + HCL_FREQ_1MHZ, + HCL_FREQ_2MHZ, + HCL_FREQ_3MHZ, + HCL_FREQ_4MHZ, + HCL_FREQ_5MHZ, + HCL_FREQ_6MHZ, + HCL_FREQ_8MHZ, + HCL_FREQ_11MHZ, + HCL_FREQ_12MHZ, + HCL_FREQ_16MHZ, + HCL_FREQ_22MHZ, + HCL_FREQ_24MHZ, + HCL_FREQ_48MHZ +} t_frequency; + +*/ + +typedef struct { + t_physical_address physical; + t_logical_address logical; +} t_system_address; + + +/* + * Define a type used to manipulate size of various buffers + */ +typedef t_uint32 t_size; + +typedef struct { + t_bitfield minor:8; + t_bitfield major:8; + t_bitfield version:16; +} t_version; + + + + +/*----------------------------------------------------------------------------- + * Keyword definition + *---------------------------------------------------------------------------*/ +#define PUBLIC /* Extern by default */ +#define PRIVATE static + +#ifndef NULL +#define NULL (0) +#endif /* ndef NULL */ + + +/*----------------------------------------------------------------------------- + * Bit setting or clearing + *---------------------------------------------------------------------------*/ +#define HCL_SET_BITS(reg,mask) ((reg) |= (mask)) +#define HCL_CLEAR_BITS(reg,mask) ((reg) &= ~(mask)) +#define HCL_READ_BITS(reg,mask) ((reg) & (mask)) +#define HCL_WRITE_BITS(reg,val,mask) ((reg) = (((reg) & ~(mask)) | ((val) & (mask)))) +#define HCL_READ_REG(reg) (reg) +#define HCL_WRITE_REG(reg,val) ((reg) = (val)) + +/*----------------------------------------------------------------------------- + * field offset extraction from a structure + *---------------------------------------------------------------------------*/ +#define HCL_BITFIELD_OFFSET(typeName, fieldName) (t_uint32)(&(((typeName *)0)->fieldName)) + +/*----------------------------------------------------------------------------- + * Bit mask definition + *---------------------------------------------------------------------------*/ +#define MASK_NULL8 0x00 +#define MASK_NULL16 0x0000 +#define MASK_NULL32 0x00000000 +#define MASK_ALL8 0xFF +#define MASK_ALL16 0xFFFF +#define MASK_ALL32 0xFFFFFFFF + +#define MASK_BIT0 (1UL<<0) +#define MASK_BIT1 (1UL<<1) +#define MASK_BIT2 (1UL<<2) +#define MASK_BIT3 (1UL<<3) +#define MASK_BIT4 (1UL<<4) +#define MASK_BIT5 (1UL<<5) +#define MASK_BIT6 (1UL<<6) +#define MASK_BIT7 (1UL<<7) +#define MASK_BIT8 (1UL<<8) +#define MASK_BIT9 (1UL<<9) +#define MASK_BIT10 (1UL<<10) +#define MASK_BIT11 (1UL<<11) +#define MASK_BIT12 (1UL<<12) +#define MASK_BIT13 (1UL<<13) +#define MASK_BIT14 (1UL<<14) +#define MASK_BIT15 (1UL<<15) +#define MASK_BIT16 (1UL<<16) +#define MASK_BIT17 (1UL<<17) +#define MASK_BIT18 (1UL<<18) +#define MASK_BIT19 (1UL<<19) +#define MASK_BIT20 (1UL<<20) +#define MASK_BIT21 (1UL<<21) +#define MASK_BIT22 (1UL<<22) +#define MASK_BIT23 (1UL<<23) +#define MASK_BIT24 (1UL<<24) +#define MASK_BIT25 (1UL<<25) +#define MASK_BIT26 (1UL<<26) +#define MASK_BIT27 (1UL<<27) +#define MASK_BIT28 (1UL<<28) +#define MASK_BIT29 (1UL<<29) +#define MASK_BIT30 (1UL<<30) +#define MASK_BIT31 (1UL<<31) + +/*----------------------------------------------------------------------------- + * quartet shift definition + *---------------------------------------------------------------------------*/ +#define MASK_QUARTET (0xFUL) +#define SHIFT_QUARTET0 0 +#define SHIFT_QUARTET1 4 +#define SHIFT_QUARTET2 8 +#define SHIFT_QUARTET3 12 +#define SHIFT_QUARTET4 16 +#define SHIFT_QUARTET5 20 +#define SHIFT_QUARTET6 24 +#define SHIFT_QUARTET7 28 +#define MASK_QUARTET0 (MASK_QUARTET << SHIFT_QUARTET0) +#define MASK_QUARTET1 (MASK_QUARTET << SHIFT_QUARTET1) +#define MASK_QUARTET2 (MASK_QUARTET << SHIFT_QUARTET2) +#define MASK_QUARTET3 (MASK_QUARTET << SHIFT_QUARTET3) +#define MASK_QUARTET4 (MASK_QUARTET << SHIFT_QUARTET4) +#define MASK_QUARTET5 (MASK_QUARTET << SHIFT_QUARTET5) +#define MASK_QUARTET6 (MASK_QUARTET << SHIFT_QUARTET6) +#define MASK_QUARTET7 (MASK_QUARTET << SHIFT_QUARTET7) + +/*----------------------------------------------------------------------------- + * Byte shift definition + *---------------------------------------------------------------------------*/ +#define MASK_BYTE (0xFFUL) +#define SHIFT_BYTE0 0 +#define SHIFT_BYTE1 8 +#define SHIFT_BYTE2 16 +#define SHIFT_BYTE3 24 +#define MASK_BYTE0 (MASK_BYTE << SHIFT_BYTE0) +#define MASK_BYTE1 (MASK_BYTE << SHIFT_BYTE1) +#define MASK_BYTE2 (MASK_BYTE << SHIFT_BYTE2) +#define MASK_BYTE3 (MASK_BYTE << SHIFT_BYTE3) + +/*----------------------------------------------------------------------------- + * Halfword shift definition + *---------------------------------------------------------------------------*/ +#define MASK_HALFWORD (0xFFFFUL) +#define SHIFT_HALFWORD0 0 +#define SHIFT_HALFWORD1 16 +#define MASK_HALFWORD0 (MASK_HALFWORD << SHIFT_HALFWORD0) +#define MASK_HALFWORD1 (MASK_HALFWORD << SHIFT_HALFWORD1) + +/*----------------------------------------------------------------------------- + * Global constants definition + *---------------------------------------------------------------------------*/ + #define ONE_KB (1024) + #define ONE_MB (ONE_KB * ONE_KB) + + +/*----------------------------------------------------------------------------- + * Address translation macros declaration + *---------------------------------------------------------------------------*/ + +#define ARM_TO_AHB_ADDR(addr) (addr) +#define AHB_TO_ARM_ADDR(addr) (addr) + +/* For input parameters - would not be changed by the API */ +#define IN +/* For output parameters - would be changes by the API */ +#define OUT +/* For input-output parameters - provides input to the API but would be changed by the API */ +#define INOUT +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* _HCL_DEFS_H */ + +/* End of file hcl_defs.h */ + + diff --git a/arch/arm/mach-ux500/include/mach/hsi-stm.h b/arch/arm/mach-ux500/include/mach/hsi-stm.h new file mode 100755 index 00000000000..3d1ac521ee1 --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/hsi-stm.h @@ -0,0 +1,186 @@ +/* + * Copyright (C) 2007 STMicroelectronics + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __HSI_STM_H__ +#define __HSI_STM_H__ + +#define HSI_DRIVER_AUTHOR "STMicroelectronics" +#define HSI_DRIVER_DESC "High-Speed Synchronous Serial Interface Driver" + +#define DRIVER_NAME "DRIVER HSI" +/* enables/disables debug msgs */ +#define DRIVER_DEBUG 0 +/* msg header represents this module */ +#define DRIVER_DEBUG_PFX DRIVER_NAME +#define DRIVER_DBG KERN_ERR + +#define HSI_DRIVER_NAME "hsi_driver" + +#define HSI_DEVICE_NAME "hsi_device" +#define HSI_TX_PREFIX "hsi_tx:" +#define HSI_RX_PREFIX "hsi_rx:" +#define HSI_PREFIX "hsi:" +/** HSIT register offsets */ +#define HSI_TX_ID 0x0 +#define HSI_TX_MODE 0x4 +#define HSI_TX_STATE 0x8 +#define HSI_TX_IOSTATE 0xC +#define HSI_TX_BUFSTATE 0x10 +#define HSI_TX_DIVISOR 0x14 +#define HSI_TX_PARITY 0x18 +#define HSI_TX_BREAK 0x1C +#define HSI_TX_CHANNELS 0x20 +#define HSI_TX_FLUSHBITS 0x24 +#define HSI_TX_PRIORITY 0x28 +#define HSI_TX_BURSTLEN 0x2C +#define HSI_TX_PREAMBLE 0x30 +#define HSI_TX_DATASWAP 0x34 +#define HSI_TX_FRAMELENX 0x80 +#define HSI_TX_BUFFERX 0xC0 +#define HSI_TX_BASEX 0x100 +#define HSI_TX_SPANX 0x140 +#define HSI_TX_GAUGEX 0x180 +#define HSI_TX_WATERMARKX 0x1C0 +#define HSI_TX_DMAEN 0x200 +#define HSI_TX_WATERMARKIS 0x204 +#define HSI_TX_WATERMARKIM 0x208 +#define HSI_TX_WATERMARKIC 0x20C +#define HSI_TX_WATERMARKID 0x210 +#define HSI_TX_PERIPHID0 0xFE0 +#define HSI_TX_PERIPHID1 0xFE4 +#define HSI_TX_PERIPHID2 0xFE8 +#define HSI_TX_PERIPHID3 0xFEC + + +/** HSIT register offsets */ +#define HSI_RX_ID 0x0 +#define HSI_RX_MODE 0x4 +#define HSI_RX_STATE 0x8 +#define HSI_RX_BUFSTATE 0xC +#define HSI_RX_THRESHOLD 0x10 +#define HSI_RX_PARITY 0x14 +#define HSI_RX_DETECTOR 0x18 +#define HSI_RX_EXCEP 0x1C +#define HSI_RX_ACK 0x20 +#define HSI_RX_CHANNELS 0x24 +#define HSI_RX_REALTIME 0x28 +#define HSI_RX_OVERRUN 0x2C +#define HSI_RX_OVERRUNACK 0x30 +#define HSI_RX_PREAMBLE 0x34 +#define HSI_RX_PIPEGAUGE 0x38 +#define HSI_RX_TIMEOUT 0x3C +#define HSI_RX_BUFFERX 0x80 +#define HSI_RX_FRAMELENX 0xC0 +#define HSI_RX_BASEX 0x100 +#define HSI_RX_SPANX 0x140 +#define HSI_RX_GAUGEX 0x180 +#define HSI_RX_WATERMARKX 0x1C0 +#define HSI_RX_DMAEN 0x200 +#define HSI_RX_WATERMARKIS 0x204 +#define HSI_RX_WATERMARKIM 0x208 +#define HSI_RX_WATERMARKIC 0x20C +#define HSI_RX_WATERMARKID 0x210 +#define HSI_RX_OVERRUNMIS 0x214 +#define HSI_RX_OVERRUNIM 0x218 +#define HSI_RX_EXCEPMIS 0x21C +#define HSI_RX_EXCEPIM 0x220 +#define HSI_RX_PERIPHID0 0xFE0 +#define HSI_RX_PERIPHID1 0xFE4 +#define HSI_RX_PERIPHID2 0xFE8 +#define HSI_RX_PERIPHID3 0xFEC + +/* + * Masks used to enable or disable the reception of certain hardware events + * for the hsi_device_drivers + */ +#define HSI_EVENT_CLEAR 0x00 +#define HSI_EVENT_MASK 0xFF +#define HSI_EVENT_BREAK_DETECTED_MASK 0x01 +#define HSI_EVENT_ERROR_MASK 0x02 + +#define HSI_CH_OPEN 0x1 + +#define ANY_HSI_CONTROLLER -1 +#define ANY_CHANNEL -1 +#define CHANNEL(channel) (1<<channel) + + +#define HSI_MAX_FRAMELEN 32 +#define PLAT_HSI_MAX_CHANNELS 8 + +struct base_span { + u8 base; + u8 span; +}; + +struct hsi_plat_data { + u8 dev_type; + u8 mode; + u8 parity; + u8 priority; + u8 channels; + u8 threshold; + u8 flushbits; + u8 dataswap; + u8 realtime; + u8 detector; + u8 framelen; + u8 watermark; + u8 currmode; + gpio_alt_function gpio_alt_func; + u32 divisor; + u32 burstlen; + u32 preamble; + u32 timeout; + struct base_span ch_base_span[PLAT_HSI_MAX_CHANNELS]; + struct stm_dma_pipe_info hsi_dma_info[PLAT_HSI_MAX_CHANNELS]; + struct hsi_controller *controller; +}; + +struct hsi_algorithm; +extern struct hsi_algorithm hsi_algo; +int hsi_read_interrupt_mode(struct hsi_channel *chnl); +int hsi_write_interrupt_mode(struct hsi_channel *chnl); +void hsi_cancel_write_interrupt_mode(struct hsi_channel *chnl); +void hsi_cancel_read_interrupt_mode(struct hsi_channel *chnl); + +irqreturn_t hsi_tx_irq_handler(int irq, void *ctrlr); +irqreturn_t hsi_rx_irq_handler(int irq, void *ctrlr); +irqreturn_t hsi_rxexcep_irq_handler(int irq, void *ctrlr); + +void do_hsi_tx_tasklet(unsigned long ctrlr); +void do_hsi_rx_tasklet(unsigned long ctrlr); +void do_hsi_tx_dma_tasklet(unsigned long ctrlr); +void do_hsi_rx_dma_tasklet(unsigned long ctrlr); +void do_hsi_rxexcep_tasklet(unsigned long ctrlr); +void hsi_u8_writer(struct hsi_channel *ch); +void hsi_u8_reader(struct hsi_channel *ch); +void hsi_u16_writer(struct hsi_channel *ch); +void hsi_u16_reader(struct hsi_channel *ch); +void hsi_u32_writer(struct hsi_channel *ch); +void hsi_u32_reader(struct hsi_channel *ch); +void hsi_dma_read_eot_handler(void *data); +void hsi_dma_write_eot_handler(void *data); + +void hsi_cancel_write_dma_mode(struct hsi_channel *chnl); +void hsi_cancel_read_dma_mode(struct hsi_channel *chnl); +/*DMA Functions*/ +int hsi_read_dma_mode(struct hsi_channel *chnl); +int hsi_write_dma_mode(struct hsi_channel *chnl); + +#endif /* __HSI_STM_H__ */ diff --git a/arch/arm/mach-ux500/include/mach/i2c-stm.h b/arch/arm/mach-ux500/include/mach/i2c-stm.h new file mode 100755 index 00000000000..f211cfe9118 --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/i2c-stm.h @@ -0,0 +1,404 @@ +/* + * arch/arm/mach-stn8500/include/mach/i2c-stm.h + * + * Copyright (C) 2009 STMicroelectronics Pvt. Ltd. + * + * Author: Sachin Verma <sachin.verma@st.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef STM_I2C_HEADER +#define STM_I2C_HEADER +#include <linux/i2c.h> + +/* + * I2C Controller register offsets + */ +#define I2C_CR(r) (r + 0x000) +#define I2C_SCR(r) (r + 0x004) +#define I2C_HSMCR(r) (r + 0x008) +#define I2C_MCR(r) (r + 0x00C) +#define I2C_TFR(r) (r + 0x010) +#define I2C_SR(r) (r + 0x014) +#define I2C_RFR(r) (r + 0x018) +#define I2C_TFTR(r) (r + 0x01C) +#define I2C_RFTR(r) (r + 0x020) +#define I2C_DMAR(r) (r + 0x024) +#define I2C_BRCR(r) (r + 0x028) +#define I2C_IMSCR(r) (r + 0x02C) +#define I2C_RISR(r) (r + 0x030) +#define I2C_MISR(r) (r + 0x034) +#define I2C_ICR(r) (r + 0x038) +#define I2C_THD_FST_STD(r) (r + 0x050) +#define I2C_THU_FST_STD(r) (r + 0x058) + + +/* + * I2C :: Controller Register + */ +#define I2C_CR_PE_POS 0 +#define I2C_CR_OM_POS 1 +#define I2C_CR_SAM_POS 3 +#define I2C_CR_SM_POS 4 +#define I2C_CR_SGCM_POS 6 +#define I2C_CR_FTX_POS 7 +#define I2C_CR_FRX_POS 8 +#define I2C_CR_DMA_TX_EN_POS 9 +#define I2C_CR_DMA_RX_EN_POS 10 +#define I2C_CR_DMA_SLE_POS 11 +#define I2C_CR_LM_POS 12 +#define I2C_CR_FON_POS 13 +#define I2C_CR_FS_POS 15 + +#define I2C_CR_PE ((u32)(0x1UL << I2C_CR_PE_POS)) +#define I2C_CR_OM ((u32)(0x3UL << I2C_CR_OM_POS)) +#define I2C_CR_SAM ((u32)(0x1UL << I2C_CR_SAM_POS)) +#define I2C_CR_SM ((u32)(0x3UL << I2C_CR_SM_POS)) +#define I2C_CR_SGCM ((u32)(0x1UL << I2C_CR_SGCM_POS)) +#define I2C_CR_FTX ((u32)(0x1UL << I2C_CR_FTX_POS)) +#define I2C_CR_FRX ((u32)(0x1UL << I2C_CR_FRX_POS)) +#define I2C_CR_DMA_TX_EN ((u32)(0x1UL << I2C_CR_DMA_TX_EN_POS)) +#define I2C_CR_DMA_RX_EN ((u32)(0x1UL << I2C_CR_DMA_RX_EN_POS)) +#define I2C_CR_DMA_SLE ((u32)(0x1UL << I2C_CR_DMA_SLE_POS)) +#define I2C_CR_LM ((u32)(0x1UL << I2C_CR_LM_POS)) +#define I2C_CR_FON ((u32)(0x3UL << I2C_CR_FON_POS)) +#define I2C_CR_FS ((u32)(0x3UL << I2C_CR_FS_POS)) + +/* + * I2C :: Slave Controller Register + */ +#define I2C_SCR_SLAVE_ADDR7BIT ((u32)(0x7FUL << 0)) +#define I2C_SCR_ESA10 ((u32)(0x7UL << 7)) +#define I2C_SCR_DATA_SETUP_TIME ((u32)(0xFFFFUL << 16)) + +/* + * I2C :: Master Controller Register + */ +#define I2C_MCR_OP_POS 0 +#define I2C_MCR_A7_POS 1 +#define I2C_MCR_EA10_POS 8 +#define I2C_MCR_SB_POS 11 +#define I2C_MCR_AM_POS 12 +#define I2C_MCR_STOP_POS 14 +#define I2C_MCR_LENGTH_POS 15 + +#define I2C_MCR_OP ((u32)(0x1UL << I2C_MCR_OP_POS)) +#define I2C_MCR_A7 ((u32)(0x7FUL << I2C_MCR_A7_POS)) +#define I2C_MCR_EA10 ((u32)(0x7UL << I2C_MCR_EA10_POS)) +#define I2C_MCR_SB ((u32)(0x1UL << I2C_MCR_SB_POS)) +#define I2C_MCR_AM ((u32)(0x3UL << I2C_MCR_AM_POS)) +#define I2C_MCR_STOP ((u32)(0x1UL << I2C_MCR_STOP_POS)) +#define I2C_MCR_LENGTH ((u32)(0x7FFUL << I2C_MCR_LENGTH_POS)) + +/* + *Transmit FIFO Register + */ +#define I2C_TFR_TDATA ((u32)(0xFFUL << 0)) + +/* + *Status Register + */ +#define I2C_SR_OP ((u32)(0x3UL << 0)) +#define I2C_SR_STATUS ((u32)(0x3UL << 2)) +#define I2C_SR_CAUSE ((u32)(0x7UL << 4)) +#define I2C_SR_TYPE ((u32)(0x3UL << 7)) +#define I2C_SR_LENGTH ((u32)(0x7FFUL << 9)) + +/* + *Receive FIFO Register + */ +#define I2C_RFR_RDATA ((u32)(0xFFUL << 0)) + +/* + *Transmit FIFO Threshhold register + */ +#define I2C_TFTR_THRESHOLD_TX ((u32)(0x3FFUL << 0)) + +/* + *Receive FIFO Threshhold register + */ +#define I2C_RFTR_THRESHOLD_RX ((u32)(0x3FFUL << 0)) + +/* + *BaudRate Control Register + */ +#define I2C_BRCR_BRCNT2 0x0000FFFF +#define I2C_BRCR_BRCNT1 0xFFFF0000 + +/* + *Interrupt bits in I2C_IMSCR, I2C_ICR, I2C_RIS + */ +#define I2C_IT_TXFE ((u32)(0x1UL << 0)) +#define I2C_IT_TXFNE ((u32)(0x1UL << 1)) +#define I2C_IT_TXFF ((u32)(0x1UL << 2)) +#define I2C_IT_TXFOVR ((u32)(0x1UL << 3)) +#define I2C_IT_RXFE ((u32)(0x1UL << 4)) +#define I2C_IT_RXFNF ((u32)(0x1UL << 5)) +#define I2C_IT_RXFF ((u32)(0x1UL << 6)) +#define I2C_IT_RFSR ((u32)(0x1UL << 16)) +#define I2C_IT_RFSE ((u32)(0x1UL << 17)) +#define I2C_IT_WTSR ((u32)(0x1UL << 18)) +#define I2C_IT_MTD ((u32)(0x1UL << 19)) +#define I2C_IT_STD ((u32)(0x1UL << 20)) +#define I2C_IT_MAL ((u32)(0x1UL << 24)) +#define I2C_IT_BERR ((u32)(0x1UL << 25)) +#define I2C_IT_MTDWS ((u32)(0x1UL << 28)) + + +#define I2C_IRQ_SRC_ALL 0x131F007F + +/**************************************************************/ +#define I2C_TEST_BIT(reg_name, val) (readl(reg_name) & (val)) +#define NUM_I2C_ADAPTERS 4 + + +#define MAX_I2C_FIFO_THRESHOLD 15 + + +typedef enum { + I2C_NO_OPERATION = 0xFF, + I2C_WRITE = 0x00, + I2C_READ = 0x01 +} i2c_operation_t; + + +typedef enum { + I2C_DIGITAL_FILTERS_OFF, + I2C_DIGITAL_FILTERS_1_CLK_SPIKES, + I2C_DIGITAL_FILTERS_2_CLK_SPIKES, + I2C_DIGITAL_FILTERS_4_CLK_SPIKES +} i2c_digital_filter_t; + +typedef enum { + I2C_DISABLED, + I2C_ENABLED +} i2c_control_t; + +typedef enum { + I2C_FREQ_MODE_STANDARD, /* Standard mode. */ + I2C_FREQ_MODE_FAST, /* Fast mode. */ + I2C_FREQ_MODE_HIGH_SPEED +} i2c_freq_mode_t; + +typedef enum { + I2C_BUS_SLAVE_MODE = 0, /* Slave Mode */ + I2C_BUS_MASTER_MODE, /* Master Mode */ + I2C_BUS_MASTER_SLAVE_MODE /* Dual Configuration Mode */ +} i2c_bus_control_mode_t; + +typedef enum { + I2C_NO_GENERAL_CALL_HANDLING, + I2C_SOFTWARE_GENERAL_CALL_HANDLING, + I2C_HARDWARE_GENERAL_CALL_HANDLING +} i2c_general_call_handling_t; + +typedef enum { + I2C_TRANSFER_MODE_POLLING, + I2C_TRANSFER_MODE_INTERRUPT, + I2C_TRANSFER_MODE_DMA +} i2c_transfer_mode_t; + +typedef enum { + I2C_7_BIT_ADDRESS = 0x1, + I2C_10_BIT_ADDRESS = 0x2 +} i2c_addr_t; + +typedef enum { + I2C_NO_INDEX, /* Current transfer is non-indexed */ + I2C_BYTE_INDEX, /* Current transfer uses 8-bit index */ + I2C_HALF_WORD_LITTLE_ENDIAN, /* Current transfer uses 16-bit index + in little endian mode */ + I2C_HALF_WORD_BIG_ENDIAN, /* Current transfer uses 16-bit index + in big endian mode */ + I2C_INVALID_INDEX = -1 +} i2c_index_format_t; + +typedef enum{ + I2C_NOP, + I2C_ON_GOING, + I2C_OK, + I2C_ABORT +} i2c_status_t; + +typedef enum { + I2C_NACK_ADDR, + I2C_NACK_DATA, + I2C_ACK_MCODE, + I2C_ARB_LOST, + I2C_BERR_START, + I2C_BERR_STOP, + I2C_OVFL +} i2c_error_t; + +/** + * struct i2c_platform_data - Platform Data structure for I2C controller + * @gpio_alt_func: Gpio Alternate function used by this controller + * @name: Name of this I2C controller + * @own_addr: Own address of this I2C controller on the i2c bus + * @mode: Freq mode in which this controller will operate(std, fast, highspeed) + * @clk_freq: Frequenct at which SCL line is driven (e.g. 100 KHz) + * @slave_addressing_mode: seven or 10 bit addressing + * @digital_filter_control: Digital Filters to be applied + * @dma_sync_logic_control: Enabled/Disaled + * @start_byte_procedure: Enabled/Disabled + * @slave_data_setup_time: Data setup time for slave + * @bus_control_mode: Whether slave or master + * @i2c_loopback_mode: If true controller works in Loopback mode + * @xfer_mode: Polling/Interrupt/DMA mode + * @high_speed_master_code: Code for high speed master mode + * @i2c_tx_int_threshold: Interrupt Tx threshold + * @i2c_rx_int_threshold: Interrupt Rx Threshold + * + **/ +struct i2c_platform_data { + gpio_alt_function gpio_alt_func; + char name[48]; + u32 own_addr; + i2c_freq_mode_t mode; + u32 clk_freq; + i2c_addr_t slave_addressing_mode; + i2c_digital_filter_t digital_filter_control; + i2c_control_t dma_sync_logic_control; + i2c_control_t start_byte_procedure; + u16 slave_data_setup_time; + i2c_bus_control_mode_t bus_control_mode; + i2c_control_t i2c_loopback_mode; + i2c_transfer_mode_t xfer_mode; + u8 high_speed_master_code; + u8 i2c_tx_int_threshold; + u8 i2c_rx_int_threshold; +}; + + +/** + * struct i2c_controller_config - Configuration stored by controller + * @own_addr: Controllers own address on the I2C bus + * @clk_freq: Frequency at which SCL line is Driven + * @digital_filter_control: Digital filter control to be applied + * @dma_sync_logic_control: Enabled/Disabled + * @start_byte_procedure: Enabled/Disabled + * @slave_data_setup_time: Slave set up time + * @slave_addressing_mode: seven or 10 bit addressing + * @high_speed_master_code: Code for high speed master mode + * @mode: Standard/fast/Highspeed mode + * @bus_control_mode: Master/Slave/Dual + * @i2c_loopback_mode: Loopback mode + * @general_call_mode_handling: + * @xfer_mode: Polling/Interrupt/DMA mode + * @i2c_transmit_interrupt_threshold: Tx interrupt threshold + * @i2c_receive_interrupt_threshold: Rx interrupt threshold + * @transmit_burst_length: + * @receive_burst_length: + * @burst_length: + * + **/ +struct i2c_controller_config { + u16 own_addr; + u32 clk_freq; + i2c_digital_filter_t digital_filter_control; + i2c_control_t dma_sync_logic_control; + i2c_control_t start_byte_procedure; + u16 slave_data_setup_time; + i2c_addr_t slave_addressing_mode; + u8 high_speed_master_code; + i2c_freq_mode_t mode; + i2c_bus_control_mode_t bus_control_mode; + i2c_control_t i2c_loopback_mode; + i2c_general_call_handling_t general_call_mode_handling; + i2c_transfer_mode_t xfer_mode; + u8 i2c_transmit_interrupt_threshold; + u8 i2c_receive_interrupt_threshold; + u8 transmit_burst_length; + u8 receive_burst_length; + u16 burst_length; +}; + + +/** + * struct client_data - Holds Data specific to a client we are dealing with + * @slave_address: Address of the Slave I2C Chip + * @register_index: Index at which we wish to read data on this I2C slave chip + * @index_format: 8bit/16bit(big/Little endian) index + * @count_data: The number of bytes to be transferred. + * @databuffer: Pointer to the data buffer. Used in Multi operation. + * @transfer_data: Number of bytes transferred till now + * @operation: Read/Write + * + * + **/ +struct client_data { + u16 slave_address; + u16 register_index; + i2c_index_format_t index_format; + u32 count_data; + u8 *databuffer; + u32 transfer_data; + i2c_operation_t operation; +}; + +/** + * struct i2c_driver_data - Private data structure for the I2C Controller driver + * @id: Bus Id of this I2C controller + * @adap: reference to the I2C adapter structure + * @irq: IRQ line for this Controller + * @regs: I/O regs Memory Area of this controller + * @event_wq: + * @config: Controller configuration + * @cli_data: Data of the client transfer we are about to perform + * @stop: Whether we need a stop condition or not + * @xfer_complete: used for timeout in interrupt xfer. + * + * + **/ +struct i2c_driver_data { + struct i2c_adapter adap; + int irq; + void __iomem *regs; + struct clk *clk; + struct i2c_controller_config cfg; + struct client_data cli_data; + int stop; + int result; + struct completion xfer_complete; +}; + +#define I2C_FIFO_FLUSH_COUNTER 5000000 +#define I2C_STATUS_UPDATE_COUNTER 5000000 + +#define I2C_SET_BIT(reg_name, mask) (writel(readl(reg_name) | mask, (reg_name))) +#define I2C_CLR_BIT(reg_name, mask) (writel(readl(reg_name) & ~(mask), \ + (reg_name))) + +#define I2C_ALGO_STM 0x15000000 +#define I2C_HW_STM 0x01 +#define I2C_DRIVERID_STM 0xF000 +#define WRITE_FIELD(reg_name, mask, shift, value) \ + (reg_name = ((reg_name & ~mask) | (value << shift))) + +#define GEN_MASK(val, mask, sb) ((u32)((((u32)val)<<(sb)) & (mask))) + +#define STM_SET_BITS(reg, mask) ((reg) |= (mask)) +#define STM_CLEAR_BITS(reg, mask) ((reg) &= ~(mask)) + +#define I2C_WRITE 0 +#define I2C_READ 1 + +#define I2C_MCR_LENGTH_STOP_OP 0x3FFC001 +#define I2C_WRITE_FIELD(reg_name, mask, shift, value) \ + (writel((readl(reg_name) & ~mask) | (value << shift), \ + reg_name)) + +#define DEFAULT_BRCNT_REG (GEN_MASK((__u32)(STD_F_IN_HZ/(STD_SPEED_IN_HZ*2)), \ + I2C_BRCR_BRCNT2, 0)| \ + GEN_MASK(0, I2C_BRCR_BRCNT1, 16)) + +#endif diff --git a/arch/arm/mach-ux500/include/mach/io.h b/arch/arm/mach-ux500/include/mach/io.h new file mode 100755 index 00000000000..50553776b39 --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/io.h @@ -0,0 +1,22 @@ +/* + * arch/arm/mach-sa1100/include/mach/io.h + * + * Copyright (C) 1997-1999 Russell King + * + * Modifications: + * 06-12-1997 RMK Created. + * 07-04-1999 RMK Major cleanup + */ +#ifndef __ASM_ARM_ARCH_IO_H +#define __ASM_ARM_ARCH_IO_H + +#define IO_SPACE_LIMIT 0xffffffff + +/* + * We don't actually have real ISA nor PCI buses, but there is so many + * drivers out there that might just work if we fake them... + */ +#define __io(a) __typesafe_io(a) +#define __mem_pci(a) (a) + +#endif diff --git a/arch/arm/mach-ux500/include/mach/irqs.h b/arch/arm/mach-ux500/include/mach/irqs.h new file mode 100755 index 00000000000..363cd443c18 --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/irqs.h @@ -0,0 +1,109 @@ +/* + * Copyright (C) 2008 ST Microelectronics + * Copyright (C) 2009 ST-Ericsson. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#ifndef ASM_ARCH_IRQS_H +#define ASM_ARCH_IRQS_H + +#include <mach/hardware.h> + +#define IRQ_LOCALTIMER 29 +#define IRQ_LOCALWDOG 30 + + +#define IRQ_SPI_START 32 + +/* Interrupt numbers generic for shared peripheral */ +#define IRQ_MTU0 (IRQ_SPI_START + 4) +#define IRQ_SPI2 (IRQ_SPI_START + 6) +#define IRQ_SPI0 (IRQ_SPI_START + 8) +#define IRQ_UART0 (IRQ_SPI_START + 11) +#define IRQ_I2C3 (IRQ_SPI_START + 12) +#define IRQ_SSP0 (IRQ_SPI_START + 14) +#define IRQ_MTU1 (IRQ_SPI_START + 17) +#define IRQ_RTC_RTT (IRQ_SPI_START + 18) +#define IRQ_UART1 (IRQ_SPI_START + 19) +#define IRQ_I2C0 (IRQ_SPI_START + 21) +#define IRQ_I2C1 (IRQ_SPI_START + 22) +#define IRQ_USBOTG (IRQ_SPI_START + 23) +#define IRQ_DMA (IRQ_SPI_START + 25) +#define IRQ_UART2 (IRQ_SPI_START + 26) +#define IRQ_HSIR_EXCEP (IRQ_SPI_START + 29) +#define IRQ_MSP0 (IRQ_SPI_START + 31) +#define IRQ_HSIR_CH0_OVRRUN (IRQ_SPI_START + 32) +#define IRQ_HSIR_CH1_OVRRUN (IRQ_SPI_START + 33) +#define IRQ_HSIR_CH2_OVRRUN (IRQ_SPI_START + 34) +#define IRQ_HSIR_CH3_OVRRUN (IRQ_SPI_START + 35) +#define STW4500_IRQ (IRQ_SPI_START + 40) +#define IRQ_SDMMC2 (IRQ_SPI_START + 41) +#define IRQ_SIA_IT0 (IRQ_SPI_START + 42) +#define IRQ_SIA_IT1 (IRQ_SPI_START + 43) +#define IRQ_SVA_IT0 (IRQ_SPI_START + 44) +#define IRQ_SVA_IT1 (IRQ_SPI_START + 45) +#define IRQ_PRCM_ACK_MBOX (IRQ_SPI_START + 47) +#define IRQ_DISP (IRQ_SPI_START + 48) +#define IRQ_SPI3 (IRQ_SPI_START + 49) +#define IRQ_SDMMC1 (IRQ_SPI_START + 50) +#define IRQ_I2C4 (IRQ_SPI_START + 51) +#define IRQ_SSP1 (IRQ_SPI_START + 52) +#define IRQ_I2C2 (IRQ_SPI_START + 55) +#define IRQ_SDMMC3 (IRQ_SPI_START + 59) +#define IRQ_SDMMC0 (IRQ_SPI_START + 60) +#define IRQ_HWSEM (IRQ_SPI_START + 61) +#define IRQ_MSP1 (IRQ_SPI_START + 62) +#define IRQ_SPI1 (IRQ_SPI_START + 96) +#define IRQ_MSP2 (IRQ_SPI_START + 98) +#define IRQ_SDMMC4 (IRQ_SPI_START + 99) +#define IRQ_SDMMC5 (IRQ_SPI_START + 100) +#define IRQ_HSIRD0 (IRQ_SPI_START + 104) +#define IRQ_HSIRD1 (IRQ_SPI_START + 105) +#define IRQ_HSITD0 (IRQ_SPI_START + 106) +#define IRQ_HSITD1 (IRQ_SPI_START + 107) +#define IRQ_GPIO0 (IRQ_SPI_START + 119) +#define IRQ_GPIO1 (IRQ_SPI_START + 120) +#define IRQ_GPIO2 (IRQ_SPI_START + 121) +#define IRQ_GPIO3 (IRQ_SPI_START + 122) +#define IRQ_GPIO4 (IRQ_SPI_START + 123) +#define IRQ_GPIO5 (IRQ_SPI_START + 124) +#define IRQ_GPIO6 (IRQ_SPI_START + 125) +#define IRQ_GPIO7 (IRQ_SPI_START + 126) +#define IRQ_GPIO8 (IRQ_SPI_START + 127) +#define IRQ_B2R2 (IRQ_SPI_START + 56) + +#define IRQ_CA_WAKE_REQ_ED (IRQ_SPI_START + 71) +#define IRQ_AC_READ_NOTIFICATION_0_ED (IRQ_SPI_START + 66) +#define IRQ_AC_READ_NOTIFICATION_1_ED (IRQ_SPI_START + 64) +#define IRQ_CA_MSG_PEND_NOTIFICATION_0_ED (IRQ_SPI_START + 67) +#define IRQ_CA_MSG_PEND_NOTIFICATION_1_ED (IRQ_SPI_START + 65) + +#define IRQ_CA_WAKE_REQ_V1 (IRQ_SPI_START + 83) +#define IRQ_AC_READ_NOTIFICATION_0_V1 (IRQ_SPI_START + 78) +#define IRQ_AC_READ_NOTIFICATION_1_V1 (IRQ_SPI_START + 76) +#define IRQ_CA_MSG_PEND_NOTIFICATION_0_V1 (IRQ_SPI_START + 79) +#define IRQ_CA_MSG_PEND_NOTIFICATION_1_V1 (IRQ_SPI_START + 77) + +#define GPIO_TOTAL_PINS 267 + +#define MAX_CHIP_IRQ 161 +#define MAX_GPIO_IRQ (MAX_CHIP_IRQ + GPIO_TOTAL_PINS) + +#ifndef NR_IRQS +#define NR_IRQS (MAX_GPIO_IRQ + 1) +#endif + +/* Macros to get irqno for GPIO pin and vice-versa*/ +#define IRQNO_GPIO(x) (MAX_CHIP_IRQ + x) +#define GPIO_PIN_FOR_IRQ(x) (x - MAX_CHIP_IRQ) + +/* Macros to get irqno for DMA channels and vice-versa*/ +#define IRQNO_FOR_DMACH(x) (MAX_GPIO_IRQ + x) +#define DMACH_FOR_IRQNO(x) (x - MAX_GPIO_IRQ) + + +#endif /*ASM_ARCH_IRQS_H*/ + diff --git a/arch/arm/mach-ux500/include/mach/isa_ioctl.h b/arch/arm/mach-ux500/include/mach/isa_ioctl.h new file mode 100755 index 00000000000..b05726f8c3c --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/isa_ioctl.h @@ -0,0 +1,51 @@ +/*---------------------------------------------------------------------------*/ +/* Copyright ST Ericsson, 2009. */ +/* This program is free software; you can redistribute it and/or modify it */ +/* under the terms of the GNU General Public License as published by the */ +/* Free Software Foundation; either version 2.1 of the License, or */ +/* (at your option) any later version. */ +/* */ +/* This program is distributed in the hope that it will be useful, but */ +/* WITHOUT ANY WARRANTY; without even the implied warranty of */ +/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. */ +/* See the GNU General Public License for more details. */ +/* */ +/* You should have received a copy of the GNU General Public License */ +/* along with this program. If not, see <http://www.gnu.org/licenses/>. */ +/*---------------------------------------------------------------------------*/ +#ifndef __MODEM_IPC_INCLUDED +#define __MODEM_IPC_INCLUDED + +#define DLP_IOCTL_MAGIC_NUMBER 'M' +#define COMMON_BUFFER_SIZE (1024*1024) + +/** +DLP Message Structure for Userland +*/ +struct t_dlp_message{ + unsigned int offset; + unsigned int size; +}; + +/** +mmap constants. +*/ +enum t_dlp_mmap_params { + MMAP_DLQUEUE, + MMAP_ULQUEUE +}; + +/** +DLP IOCTLs for Userland +*/ +#define DLP_IOC_ALLOCATE_BUFFER \ + _IOWR(DLP_IOCTL_MAGIC_NUMBER, 0, struct t_dlp_message *) +#define DLP_IOC_DEALLOCATE_BUFFER \ + _IOWR(DLP_IOCTL_MAGIC_NUMBER, 1, struct t_dlp_message *) +#define DLP_IOC_GET_MESSAGE \ + _IOWR(DLP_IOCTL_MAGIC_NUMBER, 2, struct t_dlp_message *) +#define DLP_IOC_PUT_MESSAGE \ + _IOWR(DLP_IOCTL_MAGIC_NUMBER, 3, struct t_dlp_message *) + +#endif /*__MODEM_IPC_INCLUDED*/ + diff --git a/arch/arm/mach-ux500/include/mach/kpd.h b/arch/arm/mach-ux500/include/mach/kpd.h new file mode 100755 index 00000000000..eae65ea7f94 --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/kpd.h @@ -0,0 +1,117 @@ +/* + * Copyright STMicroelectronics, 2009. + * Copyright (C) 2009 ST-Ericsson. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License + */ + +#ifndef __U8500_KPD_H +#define __U8500_KPD_H + +#ifndef CONFIG_AUTOSCAN_ENABLED +#define CONFIG_AUTOSCAN_ENABLED 1 +#endif +#include <mach/hardware.h> + +#define MAX_KPROW 8 +#define MAX_KPCOL 8 +/*keypad related Constants*/ +#define KEYPAD_RELEASE_PERIOD 11 /*110 Msec, repeate key scan time */ +#define KEYPAD_SCAN_PERIOD 4 /*40Msec for new keypress */ +#define KEYPAD_STATE_DEFAULT 0 +#define KEYPAD_STATE_PRESSED 1 +#define KEYPAD_STATE_PRESSACK 2 +#define KEYPAD_STATE_RELEASED 3 +#define KEYPAD_STATE_RELEASEACK 2 + +#define KPINTR_LKBIT 0 /*bit used for interrupt locking */ + +struct keypad_t; +/** + * struct keypad_device - + * platform data for keypad driver + * @init: pointer to keypad init function + * @exit: pointer to keypad deinitialisation function + * @autoscan_check: pointer to read autoscan status function, not used + * currently + * @autoscan_disable: pointer to autoscan feature disable function, + * not used currently + * @autoscan_results: pointer to read autoscan results function + * @autoscan_en: pointer to enable autoscan feature function, not used + * currently + * @irqen: pointer to enable irq function + * @irqdis: pointer to disable irq function + * @kcode_tbl: lookup table for keycodes + * @krow: mask for available rows, value is 0xFF + * @kcol: mask for available columns, value is 0xFF + * @irqdis_int: pointer to disable irq function, to be called from ISR + * @debounce_period: platform specific debounce time, can be fine tuned later + * @irqtype: type of interrupt + * @irq: irq no, + * @int_status: interrupt status + * @int_line_behaviour: dynamis interrupt line behaviour + */ +struct keypad_device { + int (*init)(struct keypad_t *kp); + int (*exit)(struct keypad_t *kp); + int (*autoscan_check)(void); + void (*autoscan_disable)(void); + int (*autoscan_results)(struct keypad_t *kp); + void (*autoscan_en)(void); + int (*irqen)(struct keypad_t *kp); + int (*irqdis)(struct keypad_t *kp); /* normal disable */ + u8 *kcode_tbl; + u8 krow; + u8 kcol; + int (*irqdis_int)(struct keypad_t *kp); + /* func used wen disable in interrupt handler */ + u8 debounce_period; + unsigned long irqtype; + u8 irq; /*IRQ no*/ + u8 int_status; + u8 int_line_behaviour; + bool enable_wakeup; +}; + +/** + * struct keypad_t - keypad data structure used internally by keypad driver + * @irq: irq no + * @mode: 0 for interrupt mode, 1 for polling mode + * @key_state: array for saving keystates + * @lockbits: used for synchronisation in ISR + * @inp_dev: pointer to input device object + * @address_for_data: not used + * @kscan_work: work queue + * @board: keypad platform device + */ +struct keypad_t { + int irq; + int mode; + int key_state[MAX_KPROW][MAX_KPCOL]; + unsigned long lockbits; + struct input_dev *inp_dev; + void *address_for_data; + struct delayed_work kscan_work; + struct keypad_device *board; +}; +/** + * enum kp_int_status - enum for INTR status + * @KP_INT_DISABLED: interrupt disabled + * @KP_INT_ENABLED: interrupt enabled + */ +enum kp_int_status { + KP_INT_DISABLED = 0, + KP_INT_ENABLED, +}; +/** + *enum kp_int_line_behaviour - enum for kp_int_line dynamic status + * @INT_LINE_NOTSET: IRQ not asserted + * @INT_LINE_SET: IRQ asserted + */ +enum kp_int_line_behaviour { + INT_LINE_NOTSET = 0, + INT_LINE_SET, +}; +#endif /*__U8500_KPD_H*/ diff --git a/arch/arm/mach-ux500/include/mach/mcde-base.h b/arch/arm/mach-ux500/include/mach/mcde-base.h new file mode 100644 index 00000000000..c785fcac2de --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/mcde-base.h @@ -0,0 +1,83 @@ +/* + * Copyright (C) 2010 ST-Ericsson + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/* MCDE specific declaration */ +#ifdef CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT + +#define U8500_MCDE_REGISTER_BANK_SIZE 0x20 +#define U8500_MCDE_BASE_SIZE 0x200 + +#define U8500_MCDE_EXTSRC_BASE (U8500_MCDE_BASE + U8500_MCDE_BASE_SIZE) +#define U8500_MCDE_EXTSRC_SIZE (U8500_MCDE_REGISTER_BANK_SIZE * 0x10) + +#define U8500_MCDE_OVERLAY_BASE (U8500_MCDE_BASE + 0x400) +#define U8500_MCDE_OVERLAY_SIZE (0x20 * 0x10) + +#define U8500_MCDE_CHANNELA_CONFIG_BASE (U8500_MCDE_BASE + 0x600) /* MCDE channel config registers */ +#define U8500_MCDE_CHANNELB_CONFIG_BASE (U8500_MCDE_BASE + 0x600) /* MCDE channel config registers */ +#define U8500_MCDE_CHANNELC0_CONFIG_BASE (U8500_MCDE_BASE + 0x600) /* MCDE channel config registers */ +#define U8500_MCDE_CHANNELC1_CONFIG_BASE (U8500_MCDE_BASE + 0x600) /* MCDE channel config registers */ +#define U8500_MCDE_CHANNEL_CONFIG_SIZE (0x20 * 0x10) + +#define U8500_MCDE_CHANNELA_SPECIFIC_REGISTER_BASE (U8500_MCDE_BASE + 0x800) /* MCDE channel A specific registers */ +#define U8500_MCDE_CHANNELA_SPECIFIC_REGISTER_SIZE 0x200 + +#define U8500_MCDE_CHANNELB_SPECIFIC_REGISTER_BASE (U8500_MCDE_BASE + 0xA00) /* MCDE channel B specific registers */ +#define U8500_MCDE_CHANNELB_SPECIFIC_REGISTER_SIZE 0x200 + +#define U8500_MCDE_CHANNELC0C1_SPECIFIC_REGISTER_BASE (U8500_MCDE_BASE + 0xC00) /* MCDE channel C0/C1 speicific registers */ +#define U8500_MCDE_CHANNELC0C1_SPECIFIC_REGISTER_SIZE 0xCB + +#define U8500_MCDE_DSI_CHANNEL_BASE (U8500_MCDE_BASE + 0xE00) /* MCDE channelC0 config registers */ +#define U8500_MCDE_DSI_CHANNEL_SIZE 0x20 +#define U8500_MCDE_DSI_SIZE 0xF4 +#define U8500_MCDE_DSI_CLOCK_OFFSET 0xF0 /* MCDE DSI clock */ +#define U8500_DSI_LINK1_BASE 0xA0351000 +#define U8500_DSI_LINK_SIZE 0x1000 +#define U8500_DSI_LINK_COUNT 0x3 +#define U8500_DSI_LINK2_BASE (U8500_DSI_LINK1_BASE + U8500_DSI_LINK_SIZE) +#define U8500_DSI_LINK3_BASE (U8500_DSI_LINK2_BASE + U8500_DSI_LINK_SIZE) + +#define PRCM_HDMICLK_MGT_REG 0x80157058 /** HDMI clock selection */ +#define PRCM_MCDECLK_MGT_REG 0x80157064 /** MCDE clock selection */ +#define PRCM_TVCLK_MGT_REG 0x8015707c /** MCDE clock selection */ + +#else /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */ + +#define U8500_MCDE_REGISTER_SIZE 0x20 +#define U8500_MCDE_EXTSRC_BASE 0xA0350200 +#define U8500_MCDE_EXTSRC_SIZE (0x20 * 0x10) +#define U8500_MCDE_OVL_BASE 0xA0350400 +#define U8500_MCDE_OVL_SIZE (0x20 * 0x10) +#define U8500_MCDE_CHANNELA_CONFIG_BASE 0xA0350600 /* MCDE channelA config registers */ +#define U8500_MCDE_CHANNEL_CONFIG_SIZE (0x20 * 0x10) +#define U8500_MCDE_CHANNELA_SPECIFIC_REGISTER_BASE 0xA0350800 /* MCDE channelA specific registers */ +#define U8500_MCDE_CHANNEL_SPECIFIC_REGISTER_SIZE 0x80 +#define U8500_MCDE_CHANNELB_CONFIG_BASE 0xA0350600 /* MCDE channelA config registers */ +#define U8500_MCDE_CHANNELB_SPECIFIC_REGISTER_BASE 0xA0350A00 /* MCDE channelA specific registers */ +#define U8500_MCDE_CHANNELC0_CONFIG_BASE 0xA0350600 /* MCDE channelC0 config registers */ +#define U8500_MCDE_CHANNELC_SPECIFIC_REGISTER_BASE 0xA0350C00 /* MCDE channelC specific registers */ +#define U8500_MCDE_CHANNELC1_CONFIG_BASE 0xA0350600 /* MCDE channelC1 config registers */ +#define U8500_MCDE_CHANNELC_SPECIFIC_REGISTER_BASE 0xA0350C00 /* MCDE channelC specific registers */ +#define U8500_MCDE_CHANNELC_SPECIFIC_REGISTER_SIZE 0xA8 +#define U8500_MCDE_DSI_CHANNEL_BASE 0xA0350E00 /* MCDE channelC0 config registers */ +#define U8500_MCDE_DSI_CHANNEL_SIZE 0x20 +#define U8500_MCDE_DSI_SIZE 0xF4 +#define U8500_MCDE_DSI_CLOCK_OFFSET 0xF0 /* MCDE DSI clock */ +#define U8500_DSI_LINK1_BASE 0xA0351000 +#define U8500_DSI_LINK_SIZE 0x1000 +#define U8500_DSI_LINK_COUNT 0x3 +#define U8500_DSI_LINK2_BASE (U8500_DSI_LINK1_BASE + U8500_DSI_LINK_SIZE) +#define U8500_DSI_LINK3_BASE (U8500_DSI_LINK2_BASE + U8500_DSI_LINK_SIZE) + +#define PRCM_HDMICLK_MGT_REG 0x80157058 /** HDMI clock selection */ +#define PRCM_MCDECLK_MGT_REG 0x80157064 /** MCDE clock selection */ +#define PRCM_TVCLK_MGT_REG 0x8015707c /** MCDE clock selection */ + +#endif /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */ + diff --git a/arch/arm/mach-ux500/include/mach/mcde.h b/arch/arm/mach-ux500/include/mach/mcde.h new file mode 100755 index 00000000000..9da3eab3018 --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/mcde.h @@ -0,0 +1,1381 @@ +/*---------------------------------------------------------------------------*/ +/* Copyright (C) STEricssoni 2009. */ +/* */ +/* This program is free software; you can redistribute it and/or modify it */ +/* under the terms of the GNU Lesser General Public License as published */ +/* by the Free Software Foundation; either version 2.1 of the License, */ +/* or (at your option)any later version. */ +/* */ +/* This program is distributed in the hope that it will be useful, but */ +/* WITHOUT ANY WARRANTY; without even the implied warranty of */ +/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See */ +/* the GNU Lesser General Public License for more details. */ +/* */ +/* You should have received a copy of the GNU Lesser General Public License */ +/* along with this program. If not, see <http://www.gnu.org/licenses/>. */ +/*---------------------------------------------------------------------------*/ + +#ifndef _MCDE_H_ +#define _MCDE_H_ +#include <linux/gpio.h> +#include <linux/fb.h> +#include <mach/mcde_ioctls.h> + +#ifdef __KERNEL__ + +/******************************************************************************* + MCDE Control Enums and structures + ******************************************************************************/ +/* typedef enum +{ + MCDE_CH_A_LSB = 0x00, + MCDE_CH_A_MID = 0x01, + MCDE_CH_A_MSB = 0x02, + MCDE_CH_B_LSB = 0x03, + MCDE_CH_B_MID = 0x04, + MCDE_CH_B_MSB = 0x05, + MCDE_CH_C_LSB = 0x06 +}mcde_out_mux_cfg; + +typedef enum +{ + MCDE_CH_NORMAL_MODE = 0x0, + MCDE_CH_MUX_MODE = 0x1 +}mcde_ch_ctrl; +*/ + typedef enum + { + MCDE_CH_FIFO_A_ENABLE = 0x0, + MCDE_CH_FIFO_B_ENABLE = 0x1 + }mcde_ch_fifo_ab_mux_ctrl; + + typedef enum + { + MCDE_CH_FIFO_0_ENABLE = 0x0, + MCDE_CH_FIFO_1_ENABLE = 0x1 + }mcde_ch_fifo_01_mux_ctrl; + + typedef enum + { + MCDE_INPUT_FIFO_DISABLE = 0x0, + MCDE_INPUT_FIFO_ENABLE = 0x1 + }mcde_input_fifo_ctrl; + + typedef enum + { + MCDE_DPI_DISABLE = 0x0, + MCDE_DPI_ENABLE = 0x1 + }mcde_dpi_ctrl; + + typedef enum + { + MCDE_DBI_DISABLE = 0x0, + MCDE_DBI_ENABLE = 0x1 + }mcde_dbi_ctrl; + + typedef enum + { + MCDE_DSIVID_DISABLE = 0x0, + MCDE_DSIVID_ENABLE = 0x1 + }mcde_dsivid_ctrl; + + typedef enum + { + MCDE_DSICMD_DISABLE = 0x0, + MCDE_DSICMD_ENABLE = 0x1 + }mcde_dsicmd_ctrl; + + typedef enum + { + MCDE_WTRMRK_LEVEL_0, + MCDE_WTRMRK_LEVEL_1, + MCDE_WTRMRK_LEVEL_2, + MCDE_WTRMRK_LEVEL_3, + MCDE_WTRMRK_LEVEL_4, + MCDE_WTRMRK_LEVEL_5, + MCDE_WTRMRK_LEVEL_6, + MCDE_WTRMRK_LEVEL_7 + }mcde_fifo_wrtmrk_level; + typedef enum + { + MCDE_CH_AB_FRAMESYNC_DPI = 0x0, + MCDE_CH_AB_FRAMESYNC_DBI = 0x1 + }mcde_ch_ab_framesync_cfg; + +typedef enum +{ + MCDE_DISABLE = 0x0, + MCDE_ENABLE = 0x1 +}mcde_state; + +typedef enum +{ + MCDE_CH_A_OUTPUT_FIFO_B = 0x0, + MCDE_CH_A_OUTPUT_FIFO_C1 = 0x1 + }mcde_fifo_sel_bc1_cfg; + + typedef enum + { + MCDE_CH_A_OUTPUT_FIFO_A = 0x0, + MCDE_CH_A_OUTPUT_FIFO_C0 = 0x1 + }mcde_fifo_sel_ac0_cfg; + + typedef enum + { + MCDE_CH_B_PULSE_PANEL7 = 0x0, + MCDE_CH_C0C1_PULSE_PANEL = 0x1 + }mcde_sync_mux7_cfg; + + typedef enum + { + MCDE_CH_A_PULSE_PANEL = 0x0, + MCDE_CH_B_PULSE_PANEL6 = 0x1 + }mcde_sync_mux6_cfg; + + typedef enum + { + MCDE_CH_B_CLK_PANEL5 = 0x0, + MCDE_CH_C_CHIP_SELECT5 = 0x1 + }mcde_sync_mux5_cfg; + + typedef enum + { + MCDE_CH_A_CLK_PANEL4 = 0x0, + MCDE_CH_B_CLK_PANEL4 = 0x1 + }mcde_sync_mux4_cfg; +/* +typedef enum +{ + MCDE_CHIPSELECT_C0 = 0x0, + MCDE_CHIPSELECT_C1 = 0x1 +}mcde_sync_mux23_cfg; + +typedef enum +{ + MCDE_CH_A_OUT_ENABLE = 0x0, + MCDE_CH_C_OUT_ENABLE = 0x1 +}mcde_sync_mux1_cfg; +*/ + typedef enum + { + MCDE_CH_A_CLK_PANEL0 = 0x0, + MCDE_CH_C_CHIP_SELECT0 = 0x1 + }mcde_sync_mux0_cfg; +/* +struct mcde_config +{ + mcde_out_mux_cfg data_msb1; + mcde_out_mux_cfg data_msb0; + mcde_out_mux_cfg data_mid; + mcde_out_mux_cfg data_lsb1; + mcde_out_mux_cfg data_lsb0; + mcde_fifo_wrtmrk_level fifo_wtrmrk_level; + mcde_ch_ab_framesync_cfg ch_b_frame_sync_ctrl; + mcde_ch_ab_framesync_cfg ch_a_frame_sync_ctrl; + mcde_fifo_sel_bc1_cfg ch_b_fifo_sel; + mcde_fifo_sel_ac0_cfg ch_a_fifo_sel; + mcde_sync_mux7_cfg panel_mcdeblp; + mcde_sync_mux6_cfg panel_mcdeealp; + mcde_sync_mux4_cfg panel_mcdebcp; + mcde_sync_mux4_cfg panel_mcdeacp4; + mcde_sync_mux23_cfg panel_mcdeaspl; + mcde_sync_mux23_cfg panel_mcdeaps; + mcde_sync_mux1_cfg panel_mcdealp; + mcde_sync_mux0_cfg panel_mcdeacp; +};*/ + struct mcde_control + { + mcde_ch_fifo_ab_mux_ctrl ch_fifo_ab_mux; + mcde_ch_fifo_01_mux_ctrl ch_fifo_01_mux; + mcde_input_fifo_ctrl input_fifo_enable; + mcde_dpi_ctrl dpi_a_enable; + mcde_dpi_ctrl dpi_b_enable; + mcde_dbi_ctrl dbi_c0_enable; + mcde_dbi_ctrl dbi_c1_enable; + mcde_dsivid_ctrl dsi_vid0_enable; + mcde_dsivid_ctrl dsi_vid1_enable; + mcde_dsivid_ctrl dsi_vid2_enable; + mcde_dsicmd_ctrl dsi_cmd0_enable; + mcde_dsicmd_ctrl dsi_cmd1_enable; + mcde_dsicmd_ctrl dsi_cmd2_enable; + }; +/* +struct mcde_ch_mode_ctrl +{ + mcde_ch_ctrl sync_ctrl_chA; + mcde_ch_ctrl sync_ctrl_chB; + mcde_ch_ctrl flow_ctrl_chA; + mcde_ch_ctrl flow_ctrl_chB; +}; +*/ + struct mcde_irq_status + { + u32 irq_status; + u32 event_status; + u8 is_new; + } ; +/* +typedef enum +{ + MCDE_EVENT_MASTER_BUS_ERROR = 0x01, + MCDE_EVENT_END_OF_FRAME_TRANSFER = 0x02, + MCDE_EVENT_SYNCHRO_CAPTURE_TRIGGER = 0x04, + MCDE_EVENT_HORIZONTAL_SYNCHRO_CAPTURE = 0x08, + MCDE_EVENT_VERTICAL_SYNCHRO_CAPTURE = 0x10 +} mcde_event_id; +*/ +/* Check *********************************/ + +typedef enum +{ + MCDE_CH_A_LSB = 0x00, + MCDE_CH_A_MID = 0x01, + MCDE_CH_A_MSB = 0x02, + MCDE_CH_B_LSB = 0x03, + MCDE_CH_B_MID = 0x04, + MCDE_CH_B_MSB = 0x05, + MCDE_CH_C_LSB = 0x06 +}mcde_out_mux_ctrl; + +typedef enum +{ + MCDE_FIFO_FA = 0x0, + MCDE_FIFO_FB = 0x1, + MCDE_FIFO_F0 = 0x2, + MCDE_FIFO_F1 = 0x3 +}mcde_fifo; + +typedef enum +{ + MCDE_DPI_A = 0x0, + MCDE_DPI_B = 0x1, + MCDE_DBI_C0 = 0x2, + MCDE_DBI_C1 = 0x3, + MCDE_DSI_VID0 = 0x4, + MCDE_DSI_VID1 = 0x5, + MCDE_DSI_VID2 = 0x6, + MCDE_DSI_CMD0 = 0x7, + MCDE_DSI_CMD1 = 0x8, + MCDE_DSI_CMD2 = 0x9 +}mcde_fifo_output; + +struct mcde_fifo_ctrl +{ + mcde_fifo_output out_fifoa; + mcde_fifo_output out_fifob; + mcde_fifo_output out_fifo0; + mcde_fifo_output out_fifo1; +}; + +typedef enum +{ + MCDE_CH_NORMAL_MODE = 0x0, + MCDE_CH_MUX_MODE = 0x1 +}mcde_ch_ctrl; + +typedef enum +{ + MCDE_CHIPSELECT_C0 = 0x0, + MCDE_CHIPSELECT_C1 = 0x1 +}mcde_sync_mux_ctrl; + +typedef enum +{ + MCDE_CH_A_OUT_ENABLE = 0x0, + MCDE_CH_C_OUT_ENABLE = 0x1 +}mcde_sync_mux1_ctrl; + +typedef enum +{ + MCDE_CH_A_CLK_PANEL = 0x0, + MCDE_CH_C_CHIP_SELECT = 0x1 +}mcde_sync_mux0_ctrl; + +typedef enum +{ + MCDE_CDI_CH_A = 0x0, + MCDE_CDI_CH_B = 0x1 +}mcde_cdi_ctrl; + +typedef enum +{ + MCDE_CDI_DISABLE = 0x0, + MCDE_CDI_ENABLE = 0x1 +}mcde_cdi; +/* +typedef enum +{ + MCDE_DISABLE = 0x0, + MCDE_ENABLE = 0x1 +}mcde_state; + +typedef struct +{ + t_mcde_out_mux_ctrl data_msb1; + t_mcde_out_mux_ctrl data_msb0; + t_mcde_out_mux_ctrl data_mid; + t_mcde_out_mux_ctrl data_lsb1; + t_mcde_out_mux_ctrl data_lsb0; + u8 ififo_watermark; +}mcde_control; +*/ +typedef enum +{ + MCDE_OUTPUT_FIFO_B = 0x0, + MCDE_OUTPUT_FIFO_C1 = 0x1 +}mcde_swap_b_c1_ctrl; + +typedef enum +{ + MCDE_CONF_TVA_DPIC0_LCDB = 0x0, + MCDE_CONF_TVB_DPIC1_LCDA = 0x1, + MCDE_CONF_DPIC1_LCDA = 0x2, + MCDE_CONF_DPIC0_LCDB = 0x3, + MCDE_CONF_LCDA_LCDB = 0x4, + MCDE_CONF_DSI = 0x5 +}mcde_output_conf; + +typedef enum +{ + MCDE_OUTPUT_FIFO_A = 0x0, + MCDE_OUTPUT_FIFO_C0 = 0x1 +}mcde_swap_a_c0_ctrl; + +/* +typedef struct +{ + u32 irq_status; + u32 event_status; + t_bool is_new; +}mcde_irq_status; +*/ + typedef enum + { + MCDE_EVENT_MASTER_BUS_ERROR = 0x01, + MCDE_EVENT_END_OF_FRAME_TRANSFER = 0x02, + MCDE_EVENT_SYNCHRO_CAPTURE_TRIGGER = 0x04, + MCDE_EVENT_HORIZONTAL_SYNCHRO_CAPTURE = 0x08, + MCDE_EVENT_VERTICAL_SYNCHRO_CAPTURE = 0x10 + } mcde_event_id; + +typedef struct +{ + u8 pllfreq_div; + u8 datachannels_num; + u8 delay_clk; + u8 delay_d2; + u8 delay_d1; + u8 delay_d0; +}mcde_cdi_delay; +/******************************************************************************* + External Source Enums and Structures + ******************************************************************************/ + + typedef enum + { + MCDE_EXT_SRC_0 = 0x0, + MCDE_EXT_SRC_1 = 0x1, + MCDE_EXT_SRC_2 = 0x2, + MCDE_EXT_SRC_3 = 0x3, + MCDE_EXT_SRC_4 = 0x4, + MCDE_EXT_SRC_5 = 0x5, + MCDE_EXT_SRC_6 = 0x6, + MCDE_EXT_SRC_7 = 0x7, + MCDE_EXT_SRC_8 = 0x8, + MCDE_EXT_SRC_9 = 0x9, + MCDE_EXT_SRC_10 = 0xA, + MCDE_EXT_SRC_11 = 0xB, + MCDE_EXT_SRC_12 = 0xC, + MCDE_EXT_SRC_13 = 0xD, + MCDE_EXT_SRC_14 = 0xE, + MCDE_EXT_SRC_15 = 0xF + }mcde_ext_src; + + + typedef enum + { + MCDE_U8500_PANEL_1BPP=1, + MCDE_U8500_PANEL_2BPP=2, + MCDE_U8500_PANEL_4BPP=4, + MCDE_U8500_PANEL_8BPP=8, + MCDE_U8500_PANEL_16BPP=16, + MCDE_U8500_PANEL_24BPP_PACKED=24, + MCDE_U8500_PANEL_24BPP=25, + MCDE_U8500_PANEL_32BPP=32, + MCDE_U8500_PANEL_YCBCR=11, + }mcde_fb_bpp; + + typedef enum + { + MCDE_U8500_PANEL_16BPP_RGB=35, + MCDE_U8500_PANEL_16BPP_IRGB=36, + MCDE_U8500_PANEL_16BPP_ARGB=37, + MCDE_U8500_PANEL_12BPP=38, + }mcde_fb_16bpp_type; + + + typedef enum + { + MCDE_FS_FREQ_UNCHANGED = 0x0, + MCDE_FS_FREQ_DIV_2 = 0x1 + }mcde_fs_div; + + typedef enum + { + MCDE_FS_FREQ_DIV_ENABLE = 0x0, + MCDE_FS_FREQ_DIV_DISABLE = 0x1 + }mcde_fs_ctrl; + + typedef enum + { + MCDE_MULTI_CH_CTRL_ALL_OVR = 0x0, + MCDE_MULTI_CH_CTRL_PRIMARY_OVR = 0x1 + }mcde_multi_ovr_ctrl; + + typedef enum + { + MCDE_BUFFER_SEL_EXT = 0x0, + MCDE_BUFFER_AUTO_TOGGLE = 0x1, + MCDE_BUFFER_SOFTWARE_SELECT = 0x2, + MCDE_BUFFER_RESERVED + }mcde_buffer_sel_mode; + + struct mcde_ext_src_ctrl + { + mcde_fs_div fs_div; + mcde_fs_ctrl fs_ctrl; + mcde_multi_ovr_ctrl ovr_ctrl; + mcde_buffer_sel_mode sel_mode; + }; + + +/******************************************************************************* + Overlay Enums and Structures + ******************************************************************************/ + + +/* typedef enum + { + MCDE_OVERLAY_0, + MCDE_OVERLAY_1, + MCDE_OVERLAY_2, + MCDE_OVERLAY_3, + MCDE_OVERLAY_4, + MCDE_OVERLAY_5, + MCDE_OVERLAY_6, + MCDE_OVERLAY_7 + }mcde_overlay_id; */ + + + + + + + + /* typedef enum + { + MCDE_OVR_INTERLACE_DISABLE = 0x0, + MCDE_OVR_INTERLACE_ENABLE = 0x1 + }mcde_ovr_interlace_ctrl; + + typedef enum + { + MCDE_OVR_INTERLACE_TOPFIELD = 0x0, + MCDE_OVR_INTERLACE_BOTTOMFIELD = 0x1 + }mcde_ovr_interlace_mode;*/ + + typedef enum + { + MCDE_CH_A = 0x0, + MCDE_CH_B = 0x1, + MCDE_CH_C0 = 0x2, + MCDE_CH_C1 = 0x3 + }mcde_ch_id; + + typedef enum + { + MCDE_FETCH_INPROGRESS = 0x0, + MCDE_FETCH_COMPLETE = 0x1 + }mcde_ovr_fetch_status; + + typedef enum + { + MCDE_OVR_READ_COMPLETE = 0x0, + MCDE_OVR_READ_INPROGRESS = 0x1 + }mcde_ovr_read_status; + + struct mcde_ovr_control + { + mcde_rotate_req rot_burst_req; + mcde_outsnd_req outstnd_req; + mcde_burst_req burst_req; + u8 priority; + mcde_color_key_ctrl color_key; + mcde_pal_ctrl pal_control; + mcde_col_conv_ctrl col_ctrl; + mcde_overlay_ctrl ovr_state; + mcde_ovr_alpha_enable alpha; + mcde_ovr_clip_enable clip; + }; + + struct mcde_ovr_config + { + u32 line_per_frame; + /* mcde_ovr_interlace_mode ovr_interlace; + mcde_ovr_interlace_ctrl ovr_intlace_ctrl;*/ + mcde_ext_src src_id; + u16 ovr_ppl; + }; + + struct mcde_ovr_conf2 + { + u8 alpha_value; + u8 pixoff; + mcde_ovr_opq_ctrl ovr_opaq; + mcde_blend_ctrl ovr_blend; + u32 watermark_level; + }; + /* + struct mcde_ovr_blend_ctrl + { + u8 alpha_value; + mcde_ovr_opq_ctrl ovr_opaq; + mcde_blend_ctrl ovr_blend; + u8 ovr_zlevel; + u16 ovr_xpos; + u16 ovr_ypos; + };*/ + + struct mcde_ovr_comp + { + u8 ovr_zlevel; + u16 ovr_ypos; + mcde_ch_id ch_id; + u16 ovr_xpos; + }; + + struct mcde_ovr_clipincr + { + u32 lineincr; + u32 yclip; + u32 xclip; + }; + +struct mcde_ovr_clip +{ + u32 ytlcoor; + u32 xtlcoor; + u32 ybrcoor; + u32 xbrcoor; +}; + +typedef struct +{ + u16 ovr_ypos; + u16 ovr_xpos; +}mcde_ovr_xy; + + +typedef enum +{ + MCDE_OVERLAY_NOT_BLOCKED = 0x0, + MCDE_OVERLAY_BLOCKED = 0x1 +}mcde_ovr_blocked_status; + struct mcde_ovr_status + { + mcde_ovr_blocked_status ovrb_status; + mcde_ovr_fetch_status ovr_status; + mcde_ovr_read_status ovr_read; + }; + + /******************************************************************************* + Channel Configuration Enums and Structures + ******************************************************************************/ + + + + /* struct + { + u16 InitDelay; + u16 PPDelay; + }mcde_ch_delay;*/ + + struct mcde_chsyncconf + { + u16 swint_vcnt; + mcde_frame_events swint_vevent; + u16 hwreq_vcnt; + mcde_frame_events hwreq_vevent; + }; + + struct mcde_chsyncmod + { + mcde_synchro_out_interface out_synch_interface; + mcde_synchro_source ch_synch_src; + mcde_sw_trigger sw_trig; + + }; + + + + struct mcde_ch_priority + { + u8 ch_priority; + }; + +typedef enum +{ + MCDE_CHNL_RUNNING_NORMALLY = 0x0, + MCDE_CHNL_ABORT_OCCURRED = 0x1 +}mcde_chnl_abort_state; + +typedef enum +{ + MCDE_CHNL_READ_ONGOING = 0x0, + MCDE_CHNL_READ_DONE = 0x1 +}mcde_chnl_read_status; + +typedef struct +{ + mcde_chnl_abort_state abort_state; + mcde_chnl_read_status read_state; +}mcde_chnl_state; + /******************************************************************************* + Channel A/B Enums and Structures + ******************************************************************************/ + + typedef enum + { + MCDE_CLOCKWISE = 0x0, + MCDE_ANTICLOCKWISE = 0x1 + }mcde_rot_dir; + + typedef enum + { + MCDE_GAMMA_ENABLE = 0x0, + MCDE_GAMMA_DISABLE = 0x1 + }mcde_gamma_ctrl; + + typedef enum + { + MCDE_INPUT_YCrCb = 0x0, + MCDE_INPUT_RGB = 0x1 + }mcde_flicker_format; + + typedef enum + { + MCDE_ALPHA_INPUTSRC = 0x0, + MCDE_ALPHA_REGISTER = 0x1 + }mcde_blend_control; + + typedef enum + { + MCDE_FORCE_FILTER0 = 0x0, + MCDE_ADAPTIVE_FILTER = 0x1, + MCDE_TEST_MODE = 0x2 + }mcde_flicker_filter_mode; + + + typedef enum + { + MCDE_ROTATION_DISABLE = 0x0, + MCDE_ROTATION_ENABLE = 0x1 + }mcde_roten; + + typedef enum + { + MCDE_CLR_ENHANCE_DISABLE = 0x0, + MCDE_CLR_ENHANCE_ENABLE = 0x1 + }mcde_clr_enhance_ctrl; + + typedef enum + { + MCDE_BLEND_DISABLE = 0x0, + MCDE_BLEND_ENABLE = 0x1 + }mcde_blend_status; + + + typedef enum + { + MCDE_VERTICAL_ACTIVE_FRAME_DISABLE = 0x0, + MCDE_ALL_FRAME_ENABLE = 0x1 + }mcde_va_enable; + + typedef enum + { + MCDE_OUTPUT_NORMAL = 0x0, + MCDE_OUTPUT_TOGGLE = 0x1 + }mcde_toggle_enable; + + typedef enum + { + MCDE_SYNCHRO_HBP = 0x0, + MCDE_SYNCHRO_CLP = 0x1, + MCDE_SYNCHRO_HFP = 0x2, + MCDE_SYNCHRO_HSW = 0x3 + }mcde_loadsel; + + typedef enum + { + MCDE_DATA_RISING_EDGE = 0x0, + MCDE_DATA_FALLING_EDGE = 0x1 + }mcde_data_lines; + + struct mcde_chx_control0 + { + mcde_rotate_req chx_read_request; + u8 alpha_blend; + mcde_rot_dir rot_dir; + mcde_gamma_ctrl gamma_ctrl; + mcde_flicker_format flicker_format; + mcde_flicker_filter_mode filter_mode; + mcde_blend_control blend_ctrl; + mcde_key_ctrl key_ctrl; + mcde_roten rot_enable; + mcde_dithering_control dither_ctrl; + mcde_clr_enhance_ctrl color_enhance; + mcde_antiflicker_ctrl anti_flicker; + mcde_blend_status blend; + }; + struct mcde_chx_rgb_conv_coef + { + u16 Yr_red; + u16 Yr_green; + u16 Yr_blue; + u16 Cr_red; + u16 Cr_green; + u16 Cr_blue; + u16 Cb_red; + u16 Cb_green; + u16 Cb_blue; + u16 Off_red; + u16 Off_green; + u16 Off_blue; + }; + + struct mcde_chx_flickfilter_coef + { + u8 threshold_ctrl0; + u8 threshold_ctrl1; + u8 threshold_ctrl2; + u8 Coeff0_N3; + u8 Coeff0_N2; + u8 Coeff0_N1; + u8 Coeff1_N3; + u8 Coeff1_N2; + u8 Coeff1_N1; + u8 Coeff2_N3; + u8 Coeff2_N2; + u8 Coeff2_N1; + }; + + struct mcde_chx_tv_control + { + u16 num_lines; + mcde_tvmode tv_mode; + mcde_signal_level ifield; + mcde_display_mode sel_mode; + }; + + struct mcde_chx_tv_blanking_field + { + u16 blanking_start; + u16 blanking_end; + }; + +struct mcde_chx_tv_blanking2_field + { + u16 blanking_start; + u16 blanking_end; + }; + + + struct mcde_chx_tv_start_line + { + u16 field2_start_line; + u16 field1_start_line; + }; + + struct mcde_chx_tv_dvo_offset + { + u16 field2_window_offset; + u16 field1_window_offset; + }; + + struct mcde_chx_tv_swh_time + { + u16 tv_swh2; + u16 tv_swh1; + }; + + struct mcde_chx_tv_timing1 + { + u16 src_window_width; + u16 destination_hor_offset; + }; + + struct mcde_chx_tv_lbalw_timing + { + u16 active_line_width; + u16 line_blanking_width; + }; + + struct mcde_chx_tv_background_time + { + u8 background_cr; + u8 background_cb; + u8 background_lu; + }; + +struct mcde_chx_lcd_timing0 + { + mcde_va_enable rev_va_enable; + mcde_toggle_enable rev_toggle_enable; + mcde_loadsel rev_sync_sel; + u8 rev_delay1; + u8 rev_delay0; + mcde_va_enable ps_va_enable; + mcde_toggle_enable ps_toggle_enable; + mcde_loadsel ps_sync_sel; + u8 ps_delay1; + u8 ps_delay0; + }; + + struct mcde_chx_lcd_timing1 + { + mcde_signal_level io_enable; + mcde_data_lines ipc; + mcde_signal_level ihs; + mcde_signal_level ivs; + mcde_signal_level ivp; + mcde_signal_level iclspl; + mcde_signal_level iclrev; + mcde_signal_level iclsp; + mcde_va_enable mcde_spl; + mcde_toggle_enable spltgen; + mcde_loadsel spl_sync_sel; + u8 spl_delay1; + u8 spl_delay0; + }; + + + struct mcde_chx_palette + { + u16 alphared; + u8 green; + u8 blue; + }; + + struct mcde_chx_gamma + { + u8 red; + u8 green; + u8 blue; + }; + typedef enum + { + MCDE_ROTATE0 = 0x0, + MCDE_ROTATE1 = 0x1 +}mcde_rotate_num; + + + /******************************************************************************* + Channel C Enums + ******************************************************************************/ + + typedef enum + { + MCDE_SYNCHRO_NONE = 0x0, + MCDE_SYNCHRO_C0 = 0x1, + MCDE_SYNCHRO_C1 = 0x2, + MCDE_SYNCHRO_PINGPONG = 0x3 + }mcde_sync_ctrl; + + typedef enum + { + MCDE_SIG_INACTIVE_POL_LOW = 0x0, + MCDE_SIG_INACTIVE_POL_HIGH = 0x1 + }mcde_sig_pol; + + typedef enum + { + MCDE_CD_LOW = 0x0, /* CD low for data and high for command */ + MCDE_CD_HIGH = 0x1 /* CD high for data and low for command */ + }mcde_cd_polarity; + + typedef enum + { + MCDE_RES_INACTIVE = 0x0, + MCDE_RES_ACTIVE = 0x1 + }mcde_resen; + + typedef enum + { + MCDE_CSEN_DEACTIVATED = 0x0, + MCDE_CSEN_ACTIVATED = 0x1 + }mcde_cs_enable_rw; + + typedef enum + { + MCDE_PCLK_TVCLK1 = 0x0, + MCDE_PCLK_72 = 0x1, + MCDE_PCLK_TVCLK2 = 0x2 + }mcde_clk_sel; + + typedef enum + { + MCDE_SELECT_OUTBAND = 0x0, + MCDE_SELECT_INBAND = 0x1, + }mcde_inband_select; + + typedef enum + { + MCDE_BUS_SIZE_8 = 0x0, + MCDE_BUS_SIZE_16 = 0x1 + }mcde_bus_size; + + typedef enum + { + MCDE_SYNCHRO_CAPTURE_DISABLE = 0x0, + MCDE_SYNCHRO_CAPTURE_ENABLE = 0x1 + }mcde_synchro_capture; + + typedef enum + { + MCDE_VERTICAL_SYNCHRO_CAPTURE1 = 0x0, + MCDE_VERTICAL_SYNCHRO_CHANELA = 0x1, + }mcde_synchro_select; + + typedef enum + { + MCDE_FIFO_WMLVL_4 = 0x0, + MCDE_FIFO_WMLVL_8 = 0x1 + }mcde_fifo_wmlvl_sel; + + typedef enum + { + MCDE_CHANEL_C_DISABLE = 0x0, + MCDE_CHANEL_C_ENABLE = 0x1 + }mcde_chc_enable; + + typedef enum + { + MCDE_POWER_DISABLE = 0x0, + MCDE_POWER_ENABLE = 0x1 + }mcde_powen_select; + + typedef enum + { + MCDE_FLOW_DISABLE = 0x0, + MCDE_FLOW_ENABLE = 0x1 + }mcde_flow_select; + + typedef enum + { + MCDE_DUPLX_DISABLE = 0x0, + MCDE_DUPLX_ENABLE = 0x1 + }mcde_duplx_ctrl; + + typedef enum + { + MCDE_DUPLX_MODE_NONE = 0x0, + MCDE_DUPLX_MODE_16_TO_32 = 0x1, + MCDE_DUPLX_MODE_24_TO_32_RS = 0x2, + MCDE_DUPLX_MODE_24_TO_32_LS = 0x3 + }mcde_duplx_mode_select; + + typedef enum + { + MCDE_TRANSFER_8_1 = 0x0, + MCDE_TRANSFER_8_2 = 0x1, + MCDE_TRANSFER_8_3 = 0x2, + MCDE_TRANSFER_16_1 = 0x4, + MCDE_TRANSFER_16_2 = 0x5 + }mcde_bit_segmentation_select; + + typedef enum + { + MCDE_TRANSACTION_COMMAND = 0x0, + MCDE_TRANSACTION_DATA = 0x1 + }mcde_transaction_type; + + typedef enum + { + MCDE_VSYNC_SELECT = 0x0, + MCDE_HSYNC_SELECT = 0x1 + }mcde_vertical_sync_sel; + + typedef enum + { + MCDE_VSYNC_ACTIVE_HIGH = 0x0, + MCDE_VSYNC_ACTIVE_LOW = 0x1, + }mcde_vertical_sync_polarity; + + typedef enum + { + MCDE_STBCLK_DIV_1 = 0x0, + MCDE_STBCLK_DIV_2 = 0x1, + MCDE_STBCLK_DIV_4 = 0x2, + MCDE_STBCLK_DIV_8 = 0x3, + MCDE_STBCLK_DIV_16 = 0x4, + MCDE_STBCLK_DIV_32 = 0x5, + MCDE_STBCLK_DIV_64 = 0x6, + MCDE_STBCLK_DIV_128 = 0x7 + }mcde_synchro_clk_div_factor; + + typedef enum + { + MCDE_PANEL_INTEL_SERIES = 0x0, + MCDE_PANEL_MOTOROLA_SERIES = 0x1 + }mcde_panel_protocol; + + typedef enum + { + MCDE_PANEL_C0 = 0x0, + MCDE_PANEL_C1 = 0x1 + }mcde_chc_panel; + + typedef enum + { + MCDE_TXFIFO_WRITE_DATA = 0, + MCDE_TXFIFO_READ_DATA, + MCDE_TXFIFO_WRITE_COMMAND + } mcde_txfifo_request_type; + + + struct mcde_chc_ctrl + { + mcde_sync_ctrl sync; + mcde_resen resen; + mcde_synchro_select synsel; + mcde_clk_sel clksel; + }; + + struct mcde_chc_config + { + mcde_sig_pol res_pol; + mcde_sig_pol rd_pol; + mcde_sig_pol wr_pol; + mcde_cd_polarity cd_pol; + mcde_sig_pol cs_pol; + mcde_cs_enable_rw csen; + mcde_inband_select inband_mode; + mcde_bus_size bus_size; + mcde_synchro_capture syncen; + mcde_fifo_wmlvl_sel fifo_watermark; + mcde_chc_enable chcen; + }; + + struct mcde_pbc_config + { + mcde_duplx_ctrl duplex_ctrl; + mcde_duplx_mode_select duplex_mode; + mcde_bit_segmentation_select data_segment; + mcde_bit_segmentation_select cmd_segment; + }; + + struct mcde_pbc_mux + { + u32 imux0; + u32 imux1; + u32 imux2; + u32 imux3; + u32 imux4; + }; + + struct mcde_pbc_bitctrl + { + u32 bit_ctrl0; + u32 bit_ctrl1; + }; + + struct mcde_sync_conf + { + u8 debounce_length; + mcde_vertical_sync_sel sync_sel; + mcde_vertical_sync_polarity sync_pol; + mcde_synchro_clk_div_factor clk_div; + u16 vsp_max; + u16 vsp_min; + }; + + struct mcde_sync_trigger + { + u16 trigger_delay_cx; + u8 sync_delay_c1; + u8 sync_delay_c2; + }; + + struct mcde_cd_timing_activate + { + u8 cs_cd_deactivate; + u8 cs_cd_activate; + }; + + struct mcde_rw_timing + { + mcde_panel_protocol panel_type; + u8 readwrite_activate; + u8 readwrite_deactivate; + }; + + struct mcde_data_out_timing + { + u8 data_out_deactivate; + u8 data_out_activate; + }; + + /********************************************************************* + DSIX typedefs + *********************************************************************/ + typedef enum + { + MCDE_DSI_CH_VID0 = 0x0, + MCDE_DSI_CH_CMD0 = 0x1, + MCDE_DSI_CH_VID1 = 0x2, + MCDE_DSI_CH_CMD1 = 0x3, + MCDE_DSI_CH_VID2 = 0x4, + MCDE_DSI_CH_CMD2 = 0x5 + }mcde_dsi_channel; + + typedef enum + { + MCDE_PLL_OUT_OFF = 0x0, + MCDE_PLL_OUT_1 = 0x1, + MCDE_PLL_OUT_2 = 0x2, + MCDE_PLL_OUT_4 = 0x3 + }mcde_pll_div_sel; + + typedef enum + { + MCDE_CLK27 = 0x0, + MCDE_TV1CLK = 0x1, + MCDE_HDMICLK = 0x2, + MCDE_TV2CLK = 0x3, + MCDE_MXTALI = 0x4 + }mcde_pll_ref_clk; + + typedef enum + { + MCDE_DSI_CLK27 = 0x0, + MCDE_DSI_MCDECLK = 0x1 + }mcde_clk_divider; + + typedef struct + { + mcde_pll_div_sel pllout_divsel2; + mcde_pll_div_sel pllout_divsel1; + mcde_pll_div_sel pllout_divsel0; + mcde_pll_ref_clk pll4in_sel; + mcde_clk_divider txescdiv_sel; + u32 txescdiv; + }mcde_dsi_clk_config; + + typedef enum + { + MCDE_PACKING_RGB565 = 0x0, + MCDE_PACKING_RGB666 = 0x1, + MCDE_PACKING_RGB888_R = 0x2, + MCDE_PACKING_RGB888_B = 0x3, + MCDE_PACKING_HDTV = 0x4 + }mcde_dsi_packing; + + typedef enum + { + MCDE_DSI_OUT_GENERIC_CMD = 0x0, + MCDE_DSI_OUT_VIDEO_DCS = 0x1 + }mcde_dsi_synchro; + + typedef enum + { + MCDE_DSI_NO_SWAP = 0x0, + MCDE_DSI_SWAP = 0x1, + }mcde_dsi_swap; + + typedef enum + { + MCDE_DSI_CMD_16 = 0x0, + MCDE_DSI_CMD_8 = 0x1 + }mcde_dsi_cmd; + + typedef enum + { + MCDE_DSI_CMD_MODE = 0x0, + MCDE_DSI_VID_MODE = 0x1, + }mcde_vid_mode; + + typedef struct + { + mcde_dsi_packing packing; + mcde_dsi_synchro synchro; + mcde_dsi_swap byte_swap; + mcde_dsi_swap bit_swap; + mcde_dsi_cmd cmd8; + mcde_vid_mode vid_mode; + u8 blanking; + u32 words_per_frame; + u32 words_per_packet; + }mcde_dsi_conf; + + + +/******************************************************************************* +MCDE Error Enums +******************************************************************************/ +typedef enum +{ + MCDE_OK = 0x00, /* No error.*/ + MCDE_NO_PENDING_EVENT_ERROR = 0x01, + MCDE_NO_MORE_FILTER_PENDING_EVENT = 0x02, + MCDE_NO_MORE_PENDING_EVENT = 0x03, + MCDE_REMAINING_FILTER_PENDING_EVENTS = 0x04, + MCDE_REMAINING_PENDING_EVENTS = 0x05, + MCDE_INTERNAL_EVENT = 0x06, + MCDE_INTERNAL_ERROR = 0x07, + MCDE_NOT_CONFIGURED = 0x08, + MCDE_REQUEST_PENDING = 0x09, + MCDE_REQUEST_NOT_APPLICABLE = 0x0A, + MCDE_INVALID_PARAMETER = 0x0B, + MCDE_UNSUPPORTED_FEATURE = 0x0C, + MCDE_UNSUPPORTED_HW = 0x0D +}mcde_error; + +/******************************************************************************* +MCDE driver specific structures +******************************************************************************/ + +typedef enum { + CHANNEL_A = 0x0, + CHANNEL_B = 0x1, + CHANNEL_C0 = 0x2, + CHANNEL_C1 = 0x3, +}channel ; + +typedef enum { + RES_QVGA = 0x0, + RES_VGA = 0x1, + RES_WVGA = 0x2, +}screenres; + + typedef struct + { + u16 alphared; + u8 green; + u8 blue; + }mcde_palette; + +typedef struct +{ + u8 red; + u8 green; + u8 blue; +}t_mcde_gamma; + +struct mcde_channel_data{ + channel channelid; + u8 nopan; + u8 nowrap; + const char *restype; + mcde_bpp_ctrl inbpp; + mcde_out_bpp outbpp; + u8 bpp16_type; + u8 bgrinput; + gpio_alt_function gpio_alt_func; +}; +// per channel structure +struct mcde_ovlextsrc_conf{ + u16 ovl_id; //bitmap of overlays used + u8 num_ovl; +}; + +struct clut_addrmap { + u32 clutaddr; + u32 clutdmaaddr; +}; + + +#endif //__KERNEL__ + +/* FUNCTION PROTOTYPE */ +void mcdefb_enable(struct fb_info *info); +void mcdefb_disable(struct fb_info *info); +int mcde_enable(struct fb_info *info); +int mcde_disable(struct fb_info *info); +int convertbpp(u8 bpp); +int mcde_conf_channel_color_key(struct fb_info *info, struct mcde_channel_color_key chnannel_color_key); +/*inline */unsigned long get_line_length(int x, int bpp); +/* inline */unsigned long claim_mcde_lock(mcde_ch_id chid); +/*inline*/ void release_mcde_lock(mcde_ch_id chid, unsigned long flags); +int mcde_set_buffer(struct fb_info *info, u32 buffer_address, mcde_buffer_id buff_id); +int mcde_conf_dithering_ctrl(struct mcde_dithering_ctrl_conf dithering_ctrl_conf, struct fb_info *info); +bool mcde_get_hdmi_flag(void); +void mcde_configure_hdmi_channel(void); +void mcde_hdmi_display_init_command_mode(void); +void mcde_hdmi_display_init_video_mode(void); +void mcde_hdmi_test_directcommand_mode_highspeed(void); +void mcde_send_hdmi_cmd_data(char* buf,int length, int dsicommand); +void mcde_send_hdmi_cmd(char* buf,int length, int dsicommand); + +int mcde_extsrc_ovl_create(struct mcde_overlay_create *extsrc_ovl ,struct fb_info *info,u32 *pkey); +int mcde_extsrc_ovl_remove(struct fb_info *info,u32 key); +int mcde_alloc_source_buffer(struct mcde_sourcebuffer_alloc source_buff ,struct fb_info *info, u32 *pkey, u8 isUserRequest); +int mcde_dealloc_source_buffer(struct fb_info *info, u32 srcbufferindex, u8 isUserRequest); +int mcde_conf_extsource(struct mcde_ext_conf ext_src_config ,struct fb_info *info); +int mcde_conf_overlay(struct mcde_conf_overlay ovrlayConfig ,struct fb_info *info); +int mcde_conf_channel(struct mcde_ch_conf ch_config ,struct fb_info *info); +int mcde_conf_lcd_timing(struct mcde_chnl_lcd_ctrl chnl_lcd_ctrl, struct fb_info *info); +int mcde_conf_color_conversion_coeff(struct fb_info *info, mcde_colorconv_type color_conv_type); +int mcde_conf_color_conversion(struct fb_info *info, struct mcde_conf_color_conv color_conv_ctrl); +int mcde_conf_blend_ctrl(struct fb_info *info, struct mcde_blend_control blend_ctrl); +int mcde_conf_rotation(struct fb_info *info, mcde_rot_dir rot_dir, mcde_roten rot_ctrl, u32 rot_addr0, u32 rot_addr1); +int mcde_conf_chnlc(struct mcde_chc_config chnlc_config, struct mcde_chc_ctrl chnlc_control, struct fb_info *info); +int mcde_conf_dsi_chnl(mcde_dsi_conf dsi_conf, mcde_dsi_clk_config clk_config, struct fb_info *info); +int mcde_conf_scan_mode(mcde_scan_mode scan_mode, struct fb_info *info); + +mcde_error mcdesetextsrcconf(mcde_ch_id chid, mcde_ext_src src_id, struct mcde_ext_conf config); +mcde_error mcdesetextsrcctrl(mcde_ch_id chid, mcde_ext_src src_id, struct mcde_ext_src_ctrl control); +mcde_error mcdesetbufferaddr(mcde_ch_id chid, mcde_ext_src src_id, mcde_buffer_id buffer_id, u32 address); +mcde_error mcdesetovrctrl(mcde_ch_id chid, mcde_overlay_id overlay, struct mcde_ovr_control ovr_cr); +mcde_error mcdesetovrlayconf(mcde_ch_id chid, mcde_overlay_id overlay, struct mcde_ovr_config ovr_conf); +mcde_error mcdesetovrconf2(mcde_ch_id chid, mcde_overlay_id overlay, struct mcde_ovr_conf2 ovr_conf2); +mcde_error mcdesetovrljinc(mcde_ch_id chid, mcde_overlay_id overlay, u32 ovr_ljinc); +mcde_error mcdesettopleftmargincrop(mcde_ch_id chid, mcde_overlay_id overlay, u32 ovr_topmargin, u16 ovr_leftmargin); +mcde_error mcdesetovrcomp(mcde_ch_id chid, mcde_overlay_id overlay, struct mcde_ovr_comp ovr_comp); +mcde_error mcdesetovrclip(mcde_ch_id chid, mcde_overlay_id overlay, struct mcde_ovr_clip ovr_clip); +mcde_error mcdesetovrstate(mcde_ch_id chid, mcde_overlay_id overlay, mcde_overlay_ctrl state); +mcde_error mcdesetovrpplandlpf(mcde_ch_id chid, mcde_overlay_id overlay, u16 ppl, u16 lpf); +mcde_error mcdesetstate(mcde_ch_id chid, mcde_state state); +mcde_error mcdesetchnlXconf(mcde_ch_id chid, u16 channelnum, struct mcde_chconfig config); +mcde_error mcdesetswsync(mcde_ch_id chid, u16 channelnum, mcde_sw_trigger sw_trig); +mcde_error mcdesetchnlbckgndcol(mcde_ch_id chid, u16 channelnum, struct mcde_ch_bckgrnd_col color); +mcde_error mcdesetchnlsyncprio(mcde_ch_id chid, u16 channelnum, u32 priority); +mcde_error mcdesetchnlXpowermode(mcde_ch_id chid, mcde_powen_select power); +mcde_error mcdesetflowXctrl(mcde_ch_id chid, struct mcde_chx_control0 control); +mcde_error mcdesetpanelctrl(mcde_ch_id chid, struct mcde_chx_control1 control); +mcde_error mcdesetcolorkey(mcde_ch_id chid, struct mcde_chx_color_key key, mcde_colorkey_type type); +mcde_error mcdesetcolorconvmatrix(mcde_ch_id chid, struct mcde_chx_rgb_conv_coef coef); +mcde_error mcdesetflickerfiltercoef(mcde_ch_id chid, struct mcde_chx_flickfilter_coef coef); +mcde_error mcdesetLCDtiming0ctrl(mcde_ch_id chid, struct mcde_chx_lcd_timing0 control); +mcde_error mcdesetLCDtiming1ctrl(mcde_ch_id channel, struct mcde_chx_lcd_timing1 control); +mcde_error mcdesetrotaddr(mcde_ch_id chid, u32 address, mcde_rotate_num rotnum); +mcde_error mcdesetpalette(mcde_ch_id chid, mcde_palette palette); +mcde_error mcdesetditherctrl(mcde_ch_id chid, struct mcde_chx_dither_ctrl control); +mcde_error mcdesetditheroffset(mcde_ch_id chid, struct mcde_chx_dithering_offset offset); +mcde_error mcdesetgammacoeff(mcde_ch_id chid, struct mcde_chx_gamma gamma); +mcde_error mcdesetoutmuxconf(mcde_ch_id chid, mcde_out_bpp outbpp); +mcde_error mcdesetchnlXpowermode(mcde_ch_id chid, mcde_powen_select power); +mcde_error mcdesetchnlXflowmode(mcde_ch_id chid, mcde_flow_select flow); +mcde_error mcdesetcflowXcolorkeyctrl(mcde_ch_id chid, mcde_key_ctrl key_ctrl); +mcde_error mcdesetblendctrl(mcde_ch_id chid, struct mcde_blend_control blend_ctrl); +mcde_error mcdesetrotation(mcde_ch_id chid, mcde_rot_dir rot_dir, mcde_roten rot_ctrl); +mcde_error mcdesetcolorconvctrl(mcde_ch_id chid, mcde_overlay_id overlay, mcde_col_conv_ctrl col_ctrl); +mcde_error mcderesetextsrcovrlay(mcde_ch_id chid); +mcde_error mcdesetchnlsyncsrc(mcde_ch_id chid, u16 channelnum, struct mcde_chsyncmod sync_mod); +mcde_error mcdesetchnlsyncevent(mcde_ch_id chid, struct mcde_ch_conf ch_config); +mcde_error mcdesetchnlLCDctrlreg(mcde_ch_id chid, struct mcde_chnl_lcd_ctrl_reg lcd_ctrl_reg); +mcde_error mcdesetchnlLCDhorizontaltiming(mcde_ch_id chid, struct mcde_chnl_lcd_horizontal_timing lcd_horizontal_timing); +mcde_error mcdesetchnlLCDverticaltiming(mcde_ch_id chid, struct mcde_chnl_lcd_vertical_timing lcd_vertical_timing); +mcde_error mcdesetditheringctrl(mcde_ch_id chid, mcde_dithering_ctrl dithering_control); +mcde_error mcdesetscanmode(mcde_ch_id chid, mcde_scan_mode scan_mode); +#endif + diff --git a/arch/arm/mach-ux500/include/mach/mcde_a0.h b/arch/arm/mach-ux500/include/mach/mcde_a0.h new file mode 100755 index 00000000000..f848b6eaa90 --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/mcde_a0.h @@ -0,0 +1,866 @@ +#define WRITE_FIELD(reg, field, value) \ + (reg = (reg & (~((field##_MASK) << (field##_SHIFT)))) | ((value & (field##_MASK)) << (field##_SHIFT)) ) + + +#define MCDE_CR (MCDE_BASE + 0x0) +#define MCDE_CR_MCDEEN 0x80000000 +#define MCDE_CR_AUTOCLKG_EN 0x40000000 +#define MCDE_CR_FABMUX 0x00020000 +#define MCDE_CR_F01MUX 0x00010000 +#define MCDE_CR_IFIFOCTRLEN 0x00008000 +#define MCDE_CR_DPIA_EN 0x00000200 +#define MCDE_CR_DPIB_EN 0x00000100 +#define MCDE_CR_DPIC0_EN 0x00000080 +#define MCDE_CR_DPIC1_EN 0x00000040 +#define MCDE_CR_DSIVID0_EN 0x00000020 +#define MCDE_CR_DSIVID1_EN 0x00000010 +#define MCDE_CR_DSIVID2_EN 0x00000008 +#define MCDE_CR_DSICMD0_EN 0x00000004 +#define MCDE_CR_DSICMD1_EN 0x00000002 +#define MCDE_CR_DSICMD2_EN 0x00000001 + + +#define MCDE_CONF0 (MCDE_BASE + 0x4) +#define MCDE_CONF0_OUTMUX4_SHIFT 28 +#define MCDE_CONF0_OUTMUX4_MASK 0x7 +#define MCDE_CONF0_OUTMUX3_SHIFT 25 +#define MCDE_CONF0_OUTMUX3_MASK 0x7 +#define MCDE_CONF0_OUTMUX2_SHIFT 22 +#define MCDE_CONF0_OUTMUX2_MASK 0x7 +#define MCDE_CONF0_OUTMUX1_SHIFT 19 +#define MCDE_CONF0_OUTMUX1_MASK 0x7 +#define MCDE_CONF0_OUTMUX0_SHIFT 16 +#define MCDE_CONF0_OUTMUX0_MASK 0x7 +#define MCDE_CONF0_IFIFOCTRLWTRMRKLVL_SHIFT 12 +#define MCDE_CONF0_IFIFOCTRLWTRMRKLVL_MASK 0x7 +#define MCDE_CONF0_FSYNCTRLB 0x00000800 +#define MCDE_CONF0_FSYNCTRLA 0x00000400 +#define MCDE_CONF0_SWAP_B_C1 0x00000200 +#define MCDE_CONF0_SWAP_A_C0 0x00000100 +#define MCDE_CONF0_SYNCMUX7 0x00000080 +#define MCDE_CONF0_SYNCMUX6 0x00000040 +#define MCDE_CONF0_SYNCMUX5 0x00000020 +#define MCDE_CONF0_SYNCMUX4 0x00000010 +#define MCDE_CONF0_SYNCMUX3 0x00000008 +#define MCDE_CONF0_SYNCMUX2 0x00000004 +#define MCDE_CONF0_SYNCMUX1 0x00000002 +#define MCDE_CONF0_SYNCMUX0 0x00000001 + + +#define MCDE_SSP (MCDE_BASE + 0x8) +#define MCDE_SSP_SSPEN 0x00010000 +#define MCDE_SSP_SSPCMD 0x00000100 +#define MCDE_SSP_SSPDATA_SHIFT 0 +#define MCDE_SSP_SSPDATA_MASK 0xFF + + +#define MCDE_AIS (MCDE_BASE + 0x100) +#define MCDE_AIS_DSI2AI 0x00000040 +#define MCDE_AIS_DSI1AI 0x00000020 +#define MCDE_AIS_DSI0AI 0x00000010 +#define MCDE_AIS_MCDEERRI 0x00000008 +#define MCDE_AIS_MCDECHNLI 0x00000004 +#define MCDE_AIS_MCDEOVLI 0x00000002 +#define MCDE_AIS_MCDEPPI 0x00000001 + + +#define MCDE_IMSCPP (MCDE_BASE + 0x104) +#define MCDE_IMSCPP_ROTFDIM_SHIFT 6 +#define MCDE_IMSCPP_ROTFDIM_MASK 0x3 +#define MCDE_IMSCPP_VCMPC1IM 0x00000020 +#define MCDE_IMSCPP_VCMPC0IM 0x00000010 +#define MCDE_IMSCPP_VSCC1IM 0x00000008 +#define MCDE_IMSCPP_VSCC0IM 0x00000004 +#define MCDE_IMSCPP_VCMPBIM 0x00000002 +#define MCDE_IMSCPP_VCMPAIM 0x00000001 + + +#define MCDE_IMSCOVL (MCDE_BASE + 0x108) +#define MCDE_IMSCOVL_OVLFDIM_SHIFT 16 +#define MCDE_IMSCOVL_OVLFDIM_MASK 0xFFFF +#define MCDE_IMSCOVL_OVLRDIM_SHIFT 0 +#define MCDE_IMSCOVL_OVLRDIM_MASK 0xFFFF + + +#define MCDE_IMSCCHNL (MCDE_BASE + 0x10C) +#define MCDE_IMSCCHNL_CHNLAIM_SHIFT 16 +#define MCDE_IMSCCHNL_CHNLAIM_MASK 0xFFFF +#define MCDE_IMSCCHNL_CHNLRDIM_SHIFT 0 +#define MCDE_IMSCCHNL_CHNLRDIM_MASK 0xFFFF + + +#define MCDE_IMSCERR (MCDE_BASE + 0x110) +#define MCDE_IMSCERR_OVLFERRIM_SHIFT 16 +#define MCDE_IMSCERR_OVLFERRIM_MASK 0xFFFF +#define MCDE_IMSCERR_FUC1IM 0x00000100 +#define MCDE_IMSCERR_FUC0IM 0x00000080 +#define MCDE_IMSCERR_ROTBFEIM_SHIFT 5 +#define MCDE_IMSCERR_ROTBFEIM_MASK 0x3 +#define MCDE_IMSCERR_ROTAFEIM_SHIFT 3 +#define MCDE_IMSCERR_ROTAFEIM_MASK 0x3 +#define MCDE_IMSCERR_SCHBLCKDIM 0x00000004 +#define MCDE_IMSCERR_FUBIM 0x00000002 +#define MCDE_IMSCERR_FUAIM 0x00000001 + + +#define MCDE_RISPP (MCDE_BASE + 0x114) +#define MCDE_RISPP_ROTFDRIS_SHIFT 6 +#define MCDE_RISPP_ROTFDRIS_MASK 0x3 +#define MCDE_RISPP_VCMPC1RIS 0x00000020 +#define MCDE_RISPP_VCMPC0RIS 0x00000010 +#define MCDE_RISPP_VSCC1RIS 0x00000008 +#define MCDE_RISPP_VSCC0RIS 0x00000004 +#define MCDE_RISPP_VCMPBRIS 0x00000002 +#define MCDE_RISPP_VCMPARIS 0x00000001 + + +#define MCDE_RISOVL (MCDE_BASE + 0x118) +#define MCDE_RISOVL_OVLFDRIS_SHIFT 16 +#define MCDE_RISOVL_OVLFDRIS_MASK 0xFFFF +#define MCDE_RISOVL_OVLRDRIS_SHIFT 0 +#define MCDE_RISOVL_OVLRDRIS_MASK 0xFFFF + + +#define MCDE_RISCHNL (MCDE_BASE + 0x11C) +#define MCDE_RISCHNL_CHNLARIS_SHIFT 16 +#define MCDE_RISCHNL_CHNLARIS_MASK 0xFFFF +#define MCDE_RISCHNL_CHNLRDRIS_SHIFT 0 +#define MCDE_RISCHNL_CHNLRDRIS_MASK 0xFFFF + + +#define MCDE_RISERR (MCDE_BASE + 0x120) +#define MCDE_RISERR_OVLFERRIS_SHIFT 16 +#define MCDE_RISERR_OVLFERRIS_MASK 0xFFFF +#define MCDE_RISERR_FUC1RIS 0x00000100 +#define MCDE_RISERR_FUC0RIS 0x00000080 +#define MCDE_RISERR_ROTBFERIS_SHIFT 5 +#define MCDE_RISERR_ROTBFERIS_MASK 0x3 +#define MCDE_RISERR_ROTAFERIS_SHIFT 3 +#define MCDE_RISERR_ROTAFERIS_MASK 0x3 +#define MCDE_RISERR_SCHBLCKDRIS 0x00000004 +#define MCDE_RISERR_FUBRIS 0x00000002 +#define MCDE_RISERR_FUARIS 0x00000001 + + +#define MCDE_MISPP (MCDE_BASE + 0x124) +#define MCDE_MISPP_ROTFDMIS_SHIFT 6 +#define MCDE_MISPP_ROTFDMIS_MASK 0x3 +#define MCDE_MISPP_VCMPC1MIS 0x00000020 +#define MCDE_MISPP_VCMPC0MIS 0x00000010 +#define MCDE_MISPP_VSCC1MIS 0x00000008 +#define MCDE_MISPP_VSCC0MIS 0x00000004 +#define MCDE_MISPP_VCMPBMIS 0x00000002 +#define MCDE_MISPP_VCMPAMIS 0x00000001 + + +#define MCDE_MISOVL (MCDE_BASE + 0x128) +#define MCDE_MISOVL_OVLFDMIS_SHIFT 16 +#define MCDE_MISOVL_OVLFDMIS_MASK 0xFFFF +#define MCDE_MISOVL_OVLRDMIS_SHIFT 0 +#define MCDE_MISOVL_OVLRDMIS_MASK 0xFFFF + + +#define MCDE_MISCHNL (MCDE_BASE + 0x12C) +#define MCDE_MISCHNL_CHNLAMIS_SHIFT 16 +#define MCDE_MISCHNL_CHNLAMIS_MASK 0xFFFF +#define MCDE_MISCHNL_CHNLRDMIS_SHIFT 0 +#define MCDE_MISCHNL_CHNLRDMIS_MASK 0xFFFF +#define MCDE_MISCHNL_CHNL_A 0x00000001 +#define MCDE_MISCHNL_CHNL_B 0x00000002 +#define MCDE_MISCHNL_CHNL_C0 0x00000004 +#define MCDE_MISCHNL_CHNL_C1 0x00000008 + + +#define MCDE_MISERR (MCDE_BASE + 0x130) +#define MCDE_MISERR_OVLFERMIS_SHIFT 16 +#define MCDE_MISERR_OVLFERMIS_MASK 0xFFFF +#define MCDE_MISERR_FUC1MIS 0x00000100 +#define MCDE_MISERR_FUC0MIS 0x00000080 +#define MCDE_MISERR_ROTBFEMIS_SHIFT 5 +#define MCDE_MISERR_ROTBFEMIS_MASK 0x3 +#define MCDE_MISERR_ROTAFEMIS_SHIFT 3 +#define MCDE_MISERR_ROTAFEMIS_MASK 0x3 +#define MCDE_MISERR_SCHBLCKDMIS 0x00000004 +#define MCDE_MISERR_FUBMIS 0x00000002 +#define MCDE_MISERR_FUAMIS 0x00000001 + + +#define MCDE_SISPP (MCDE_BASE + 0x134) +#define MCDE_SISOVL (MCDE_BASE + 0x138) +#define MCDE_SISCHNL (MCDE_BASE + 0x13C) +#define MCDE_SISERR (MCDE_BASE + 0x140) + + +#define MCDE_PID (MCDE_BASE + 0x1FC) +#define MCDE_PID_MAJOR_SHIFT 24 +#define MCDE_PID_MAJOR_MASK 0xFF +#define MCDE_PID_MINOR_SHIFT 16 +#define MCDE_PID_MINOR_MASK 0xFF +#define MCDE_PID_DEV_SHIFT 8 +#define MCDE_PID_DEV_MASK 0xFF +#define MCDE_PID_METALFIX_SHIFT 0 +#define MCDE_PID_METALFIX_MASK 0xFF + + +#define MCDE_EXTSRCA0 (MCDE_BASE + 0x200) +#define MCDE_EXTSRCA1 (MCDE_BASE + 0x204) +#define MCDE_EXTSRCA2 (MCDE_BASE + 0x2C8) + + +#define MCDE_EXTSRCCONF (MCDE_BASE + 0x20C) +#define MCDE_EXTSRCCONF_BEPO 0x00004000 +#define MCDE_EXTSRCCONF_BEBO 0x00002000 +#define MCDE_EXTSRCCONF_BGR 0x00001000 +#define MCDE_EXTSRCCONF_BPP_SHIFT 8 +#define MCDE_EXTSRCCONF_BPP_MASK 0xF +#define MCDE_EXTSRCCONF_PRI_OVLID_SHIFT 4 +#define MCDE_EXTSRCCONF_PRI_OVLID_MASK 0xF +#define MCDE_EXTSRCCONF_BUF_NB_SHIFT 2 +#define MCDE_EXTSRCCONF_BUF_NB_MASK 0x3 +#define MCDE_EXTSRCCONF_BUF_ID_SHIFT 0 +#define MCDE_EXTSRCCONF_BUF_ID_MASK 0x3 + + +#define MCDE_EXTSRCCR (MCDE_BASE + 0x210) +#define MCDE_EXTSRCCR_FORCE_FS_DIV 0x00000008 +#define MCDE_EXTSRCCR_FS_DIV_DISABLE 0x00000004 +#define MCDE_EXTSRCCR_MULTIOVL_CTRL 0x00000002 +#define MCDE_EXTSRCCR_SEL_MOD_SHIFT 0 +#define MCDE_EXTSRCCR_SEL_MOD_MASK 0x3 + + +#define MCDE_OVLCR (MCDE_BASE + 0x400) +#define MCDE_OVLCR_ROTBURSTSIZE_SHIFT 28 +#define MCDE_OVLCR_ROTBURSTSIZE_MASK 0xF +#define MCDE_OVLCR_MAXOUTSTANDING_SHIFT 24 +#define MCDE_OVLCR_MAXOUTSTANDING_MASK 0xF +#define MCDE_OVLCR_BURSTSIZE_SHIFT 20 +#define MCDE_OVLCR_BURSTSIZE_MASK 0xF +#define MCDE_OVLCR_STBPRIO_SHIFT 16 +#define MCDE_OVLCR_STBPRIO_MASK 0xF +#define MCDE_OVLCR_FETCH_ROPC_SHIFT 8 +#define MCDE_OVLCR_GETCH_ROPC_MASK 0xFF +#define MCDE_OVLCR_OVLB 0x00000080 +#define MCDE_OVLCR_OVLR 0x00000040 +#define MCDE_OVLCR_OVLF 0x00000020 +#define MCDE_OVLCR_ALPHAPMEN 0x00000010 +#define MCDE_OVLCR_CKEYEN 0x00000008 +#define MCDE_OVLCR_COLCCTRL_SHIFT 1 +#define MCDE_OVLCR_COLCCTRL_MASK 0x3 +#define MCDE_OVLCR_OVLEN 0x00000001 + + +#define MCDE_OVLCONF (MCDE_BASE + 0x404) +#define MCDE_OVLCONF_LPF_SHIFT 16 +#define MCDE_OVLCONF_LPF_MASK 0x7FF +#define MCDE_OVLCONF_EXTSRC_ID_SHIFT 11 +#define MCDE_OVLCONF_EXTSRC_ID_MASK 0xF +#define MCDE_OVLCONF_PPL_SHIFT 0 +#define MCDE_OVLCONF_PPL_MASK 0x7FF + + +#define MCDE_OVLCONF2 (MCDE_BASE + 0x408) +#define MCDE_OVLCONF2_PIXELFETCHWATERMARKLEVEL_SHIFT 16 +#define MCDE_OVLCONF2_PIXELFETCHWATERMARKLEVEL_MASK 0x1FFF +#define MCDE_OVLCONF2_PIXOFF_SHIFT 10 +#define MCDE_OVLCONF2_PIXOFF_MASK 0x3F +#define MCDE_OVLCONF2_OPQ 0x00000200 +#define MCDE_OVLCONF2_ALPHAVALUE_SHIFT 1 +#define MCDE_OVLCONF2_ALPHAVALUE_MASK 0xFF +#define MCDE_OVLCONF2_BP 0x00000001 + + +#define MCDE_OVLLJINC (MCDE_BASE + 0x40C) + + +#define MCDE_OVLCROP (MCDE_BASE + 0x410) +#define MCDE_OVLCROP_LMRGN_SHIFT 22 +#define MCDE_OVLCROP_LMRGN_MASK 0x3FF +#define MCDE_OVLCROP_TMRGN_SHIFT 0 +#define MCDE_OVLCROP_TMRGN_MASK 0x3FFFFF + + +#define MCDE_OVLCOMP (MCDE_BASE + 0x414) +#define MCDE_OVLCOMP_Z_SHIFT 27 +#define MCDE_OVLCOMP_Z_MASK 0xF +#define MCDE_OVLCOMP_YPOS_SHIFT 16 +#define MCDE_OVLCOMP_YPOS_MASK 0x7FF +#define MCDE_OVLCOMP_CH_ID_SHIFT 11 +#define MCDE_OVLCOMP_CH_ID_MASK 0xF +#define MCDE_OVLCOMP_XPOS_SHIFT 0 +#define MCDE_OVLCOMP_XPOS_MASK 0x7FF + + +#define MCDE_CHNLCONF (MCDE_BASE + 0x600) +#define MCDE_CHNLCONF_LPF_SHIFT 16 +#define MCDE_CHNLCONF_LPF_MASK 0x7FF +#define MCDE_CHNLCONF_PPL_SHIFT 0 +#define MCDE_CHNLCONF_PPL_MASK 0x7FF + + +#define MCDE_CHNLSTAT (MCDE_BASE + 0x604) +#define MCDE_CHNLSTAT_CHNLBLBCKGND_EN 0x00010000 +#define MCDE_CHNLSTAT_CHNLA 0x00000002 +#define MCDE_CHNLSTAT_CHNLRD 0x00000001 + + +#define MCDE_CHNLSYNCHMOD (MCDE_BASE + 0x608) +#define MCDE_CHNLSYNCHMOD_OUT_SYNCH_SRC_SHIFT 2 +#define MCDE_CHNLSYNCHMOD_OUT_SYNCH_SRC_MASK 0x7 +#define MCDE_CHNLSYNCHMOD_SRC_SYNCH_SHIFT 0 +#define MCDE_CHNLSYNCHMOD_SRC_SYNCH_MASK 0x3 + + +#define MCDE_CHNLSYNCHSW (MCDE_BASE + 0x60C) +#define MCDE_CHNLSYNCHSW_SW_TRIG 0x00000001 + + +#define MCDE_CHNLBCKGNDCOL (MCDE_BASE + 0x610) +#define MCDE_CHNLBCKGNDCOL_R_SHIFT 16 +#define MCDE_CHNLBCKGNDCOL_R_MASK 0xFF +#define MCDE_CHNLBCKGNDCOL_G_SHIFT 8 +#define MCDE_CHNLBCKGNDCOL_G_MASK 0xFF +#define MCDE_CHNLBCKGNDCOL_B_SHIFT 0 +#define MCDE_CHNLBCKGNDCOL_B_MASK 0xFF + + +#define MCDE_CHNLPRIO (MCDE_BASE + 0x614) +#define MCDE_CHNLPRIO_CHNLPRIO_SHIFT 0 +#define MCDE_CHNLPRIO_CHNLPRIO_MASK 0xF + + +#define MCDE_CR0 (MCDE_BASE + 0x800) +#define MCDE_CR0_ROTBURSTSIZE_SHIFT 25 +#define MCDE_CR0_ROTBURSTSIZE_MASK 0x7F +#define MCDE_CR0_ROTEN 0x01000000 +#define MCDE_CR0_ALPHABLEND_SHIFT 16 +#define MCDE_CR0_ALPHABLEND_MASK 0xFF +#define MCDE_CR0_OLEDEN 0x00008000 +#define MCDE_CR0_PALMODE 0x00004000 +#define MCDE_CR0_FLICKFORMAT 0x00002000 +#define MCDE_CR0_FLICKMODE_SHIFT 11 +#define MCDE_CR0_FLICKMODE_MASK 0x3 +#define MCDE_CR0_BLENDCTRL 0x00000400 +#define MCDE_CR0_KEYCTRL_SHIFT 7 +#define MCDE_CR0_KEYCTRL_MASK 0x7 +#define MCDE_CR0_GAMEN 0x00000040 +#define MCDE_CR0_DITHEN 0x00000020 +#define MCDE_CR0_PALEN 0x00000010 +#define MCDE_CR0_AFLICKEN 0x00000008 +#define MCDE_CR0_BLENDEN 0x00000004 +#define MCDE_CR0_POWEREN 0x00000002 +#define MCDE_CR0_FLOEN 0x00000001 + + +#define MCDE_CR1 (MCDE_BASE + 0x804) +#define MCDE_CR1_TEFFECTEN 0x80000000 +#define MCDE_CR1_CLKTYPE 0x40000000 +#define MCDE_CR1_BCD 0x20000000 +#define MCDE_CR1_OUTBPP_SHIFT 25 +#define MCDE_CR1_OUTBPP_MASK 0xF +#define MCDE_CR1_CDWIN_SHIFT 13 +#define MCDE_CR1_CDWIN_MASK 0xF +#define MCDE_CR1_CLKSEL_SHIFT 10 +#define MCDE_CR1_CLKSEL_MASK 0x7 +#define MCDE_CR1_PCD_SHIFT 0 +#define MCDE_CR1_PCD_MASK 0x3FF + + +#define MCDE_COLKEY (MCDE_BASE + 0x808) +#define MCDE_COLKEY_KEYA_SHIFT 24 +#define MCDE_COLKEY_KEYA_MASK 0xFF +#define MCDE_COLKEY_KEYR_SHIFT 16 +#define MCDE_COLKEY_KEYR_MASK 0xFF +#define MCDE_COLKEY_KEYG_SHIFT 8 +#define MCDE_COLKEY_KEYG_MASK 0xFF +#define MCDE_COLKEY_KEYB_SHIFT 0 +#define MCDE_COLKEY_KEYB_MASK 0xFF + + +#define MCDE_FCOLKEY (MCDE_BASE + 0x80C) +#define MCDE_FCOLKEY_FKEYA_SHIFT 24 +#define MCDE_FCOLKEY_FKEYA_MASK 0xFF +#define MCDE_FCOLKEY_FKEYR_SHIFT 16 +#define MCDE_FCOLKEY_FKEYR_MASK 0xFF +#define MCDE_FCOLKEY_FKEYG_SHIFT 8 +#define MCDE_FCOLKEY_FKEYG_MASK 0xFF +#define MCDE_FCOLKEY_FKEYB_SHIFT 0 +#define MCDE_FCOLKEY_FKEYB_MASK 0xFF + + +#define MCDE_RGBCONV1 (MCDE_BASE + 0x810) +#define MCDE_RGBCONV1_YR_RED_SHIFT 16 +#define MCDE_RGBCONV1_YR_RED_MASK 0x7FF +#define MCDE_RGBCONV1_YR_GREEN_SHIFT 0 +#define MCDE_RGBCONV1_YR_GREEN_MASK 0x7FF + + +#define MCDE_RGBCONV2 (MCDE_BASE + 0x814) +#define MCDE_RGBCONV2_YR_BLUE_SHIFT 16 +#define MCDE_RGBCONV2_YR_BLUE_MASK 0x7FF +#define MCDE_RGBCONV2_CR_RED_SHIFT 0 +#define MCDE_RGBCONV2_CR_RED_MASK 0x7FF + + +#define MCDE_RGBCONV3 (MCDE_BASE + 0x818) +#define MCDE_RGBCONV3_CR_GREEN_SHIFT 16 +#define MCDE_RGBCONV3_CR_GREEN_MASK 0x7FF +#define MCDE_RGBCONV3_CR_BLUE_SHIFT 0 +#define MCDE_RGBCONV3_CR_BLUE_MASK 0x7FF + + +#define MCDE_RGBCONV4 (MCDE_BASE + 0x81C) +#define MCDE_RGBCONV4_CB_RED_SHIFT 16 +#define MCDE_RGBCONV4_CB_RED_MASK 0x7FF +#define MCDE_RGBCONV4_CB_GREEN_SHIFT 0 +#define MCDE_RGBCONV4_CB_GREEN_MASK 0x7FF + + +#define MCDE_RGBCONV5 (MCDE_BASE + 0x820) +#define MCDE_RGBCONV5_CB_BLUE_SHIFT 16 +#define MCDE_RGBCONV5_CB_BLUE_MASK 0x7FF +#define MCDE_RGBCONV5_OFF_RED_SHIFT 0 +#define MCDE_RGBCONV5_OFF_RED_MASK 0x7FF + + +#define MCDE_RGBCONV6 (MCDE_BASE + 0x824) +#define MCDE_RGBCONV6_OFF_GREEN_SHIFT 16 +#define MCDE_RGBCONV6_OFF_GREEN_MASK 0x7FF +#define MCDE_RGBCONV6_OFF_BLUE_SHIFT 0 +#define MCDE_RGBCONV6_OFF_BLUE_MASK 0x7FF + + +#define MCDE_FFCOEF0 (MCDE_BASE + 0x828) +#define MCDE_FFCOEF0_TO_SHIFT 24 +#define MCDE_FFCOEF0_TO_MASK 0x0xF +#define MCDE_FFCOEF0_COEFF0_N3_SHIFT 16 +#define MCDE_FFCOEF0_COEFF0_N3_MASK 0xFF +#define MCDE_FFCOEF0_COEFF0_N2_SHIFT 8 +#define MCDE_FFCOEF0_COEFF0_N2_MASK 0xFF +#define MCDE_FFCOEF0_COEFF0_N1_SHIFT 0 +#define MCDE_FFCOEF0_COEFF0_N1_MASK 0xFF + + +#define MCDE_FFCOEF1 (MCDE_BASE + 0x82C) +#define MCDE_FFCOEF1_T1_SHIFT 24 +#define MCDE_FFCOEF1_T1_MASK 0x0xF +#define MCDE_FFCOEF1_COEFF1_N3_SHIFT 16 +#define MCDE_FFCOEF1_COEFF1_N3_MASK 0xFF +#define MCDE_FFCOEF1_COEFF1_N2_SHIFT 8 +#define MCDE_FFCOEF1_COEFF1_N2_MASK 0xFF +#define MCDE_FFCOEF1_COEFF1_N1_SHIFT 0 +#define MCDE_FFCOEF1_COEFF1_N1_MASK 0xFF + + +#define MCDE_FFCOEF2 (MCDE_BASE + 0x830) +#define MCDE_FFCOEF2_T2_SHIFT 24 +#define MCDE_FFCOEF2_T2_MASK 0x0xF +#define MCDE_FFCOEF2_COEFF2_N3_SHIFT 16 +#define MCDE_FFCOEF2_COEFF2_N3_MASK 0xFF +#define MCDE_FFCOEF2_COEFF2_N2_SHIFT 8 +#define MCDE_FFCOEF2_COEFF2_N2_MASK 0xFF +#define MCDE_FFCOEF2_COEFF2_N1_SHIFT 0 +#define MCDE_FFCOEF2_COEFF2_N1_MASK 0xFF + + +#define MCDE_TVCR (MCDE_BASE + 0x838) +#define MCDE_TVCR_AVRGEN 0x00000100 +#define MCDE_TVCR_SDTVMODE_SHIFT 6 +#define MCDE_TVCR_SDTVMODE_MASK 0x3 +#define MCDE_TVCR_TVMODE_SHIFT 3 +#define MCDE_TVCR_TVMODE_MASK 0x7 +#define MCDE_TVCR_IFIELD 0x00000004 +#define MCDE_TVCR_INTEREN 0x00000002 +#define MCDE_TVCR_SEL_MOD 0x00000001 + + +#define MCDE_TVBL1 (MCDE_BASE + 0x83C) +#define MCDE_TVBL1_BSL1_SHIFT 16 +#define MCDE_TVBL1_BSL1_MASK 0x7FF +#define MCDE_TVBL1_BEL1_SHIFT 0 +#define MCDE_TVBL1_BEL1_MASK 0x7FF + + +#define MCDE_TVISL (MCDE_BASE + 0x840) +#define MCDE_TVISL_FSL2_SHIFT 16 +#define MCDE_TVISL_FSL2_MASK 0x7FF +#define MCDE_TVISL_FSL1_SHIFT 0 +#define MCDE_TVISL_FSL1_MASK 0x7FF + + +#define MCDE_TVDVO (MCDE_BASE + 0x844) +#define MCDE_TVDVO_DVO2_SHIFT 16 +#define MCDE_TVDVO_DVO2_MASK 0x7FF +#define MCDE_TVDVO_DVO1_SHIFT 0 +#define MCDE_TVDVO_DVO1_MASK 0x7FF + + +#define MCDE_TVTIM1 (MCDE_BASE + 0x84C) +#define MCDE_TVTIM1_DHO_SHIFT 0 +#define MCDE_TVTIM1_DHO_MASK 0x7FF + + +#define MCDE_TVLBALW (MCDE_BASE + 0x850) +#define MCDE_TVLBALW_ALW_SHIFT 16 +#define MCDE_TVLBALW_ALW_MASK 0x7FF +#define MCDE_TVLBALW_LBW_SHIFT 0 +#define MCDE_TVLBALW_LBW_MASK 0x7FF + + +#define MCDE_TVBL2 (MCDE_BASE + 0x854) +#define MCDE_TVBL2_BSL2_SHIFT 16 +#define MCDE_TVBL2_BSL2_MASK 0x7FF +#define MCDE_TVBL2_BEL2_SHIFT 0 +#define MCDE_TVBL2_BEL2_MASK 0x7FF + + +#define MCDE_TVBLU (MCDE_BASE + 0x858) +#define MCDE_TVBLU_TVBCR_SHIFT 16 +#define MCDE_TVBLU_TVBCR_MASK 0xFF +#define MCDE_TVBLU_TVBCB_SHIFT 8 +#define MCDE_TVBLU_TVBCB_MASK 0xFF +#define MCDE_TVBLU_TVBLU_SHIFT 0 +#define MCDE_TVBLU_TVBLU_MASK 0xFF + + +#define MCDE_LDCTIM0 (MCDE_BASE + 0x85C) +#define MCDE_LDCTIM0_REVVAEN 0x80000000 +#define MCDE_LDCTIM0_REVTGEN 0x40000000 +#define MCDE_LDCTIM0_REVLOADSEL_SHIFT 28 +#define MCDE_LDCTIM0_REVLOADSEL_MASK 0x3 +#define MCDE_LDCTIM0_REVDEL1_SHIFT 24 +#define MCDE_LDCTIM0_REVDEL1_MASK 0xF +#define MCDE_LDCTIM0_REVDEL0_SHIFT 16 +#define MCDE_LDCTIM0_REVDEL0_MASK 0xFF +#define MCDE_LDCTIM0_PSVAEN 0x00008000 +#define MCDE_LDCTIM0_PSTGEN 0x00004000 +#define MCDE_LDCTIM0_PSLOADSEL_SHIFT 12 +#define MCDE_LDCTIM0_PSLOADSEL_MASK 0x3 +#define MCDE_LDCTIM0_PSDEL1_SHIFT 8 +#define MCDE_LDCTIM0_PSDEL1_MASK 0xF +#define MCDE_LDCTIM0_PSDEL0_SHIFT 0 +#define MCDE_LDCTIM0_PSDEL0_MASK 0xFF + + +#define MCDE_LCDTIM1 (MCDE_BASE + 0x860) +#define MCDE_LCDTIM1_IOE 0x00800000 +#define MCDE_LCDTIM1_IPC 0x00400000 +#define MCDE_LCDTIM1_IHS 0x00200000 +#define MCDE_LCDTIM1_IVS 0x00100000 +#define MCDE_LCDTIM1_IVP 0x00080000 +#define MCDE_LCDTIM1_ICLSPL 0x00040000 +#define MCDE_LCDTIM1_ICLREV 0x00020000 +#define MCDE_LCDTIM1_ICLSP 0x00010000 +#define MCDE_LCDTIM1_SPLVAEN 0x00008000 +#define MCDE_LCDTIM1_SPLTGEN 0x00004000 +#define MCDE_LCDTIM1_SPLLOADSEL_SHIFT 12 +#define MCDE_LCDTIM1_SPLLOADSEL_MASK 0x3 +#define MCDE_LCDTIM1_SPLDEL1_SHIFT 8 +#define MCDE_LCDTIM1_SPLDEL1_MASK 0xF +#define MCDE_LCDTIM1_SPLDEL0_SHIFT 0 +#define MCDE_LCDTIM1_SPLDEL0_MASK 0xFF + + +#define MCDE_DITCTRL (MCDE_BASE + 0x864) +#define MCDE_DITCTRL_FOFFY_SHIFT 10 +#define MCDE_DITCTRL_FOFFY_MASK 0x1F +#define MCDE_DITCTRL_FOFFX_SHIFT 5 +#define MCDE_DITCTRL_FOFFX_MASK 0x1F +#define MCDE_DITCTRL_MASK 0x00000010 +#define MCDE_DITCTRL_MODE_SHIFT 2 +#define MCDE_DITCTRL_MODE_MASK 0x3 +#define MCDE_DITCTRL_COMP 0x00000002 +#define MCDE_DITCTRL_TEMP 0x00000001 + + +#define MCDE_DITOFF (MCDE_BASE + 0x868) +#define MCDE_DITOFF_YB_SHIFT 24 +#define MCDE_DITOFF_YB_MASK 0x1F +#define MCDE_DITOFF_XB_SHIFT 16 +#define MCDE_DITOFF_XB_MASK 0x1F +#define MCDE_DITOFF_YG_SHIFT 8 +#define MCDE_DITOFF_YG_MASK 0x1F +#define MCDE_DITOFF_XG_SHIFT 0 +#define MCDE_DITOFF_XG_MASK 0x1F + + +#define MCDE_PAL0 (MCDE_BASE + 0x86C) +#define MCDE_PAL0_GREEN_SHIFT 16 +#define MCDE_PAL0_GREEN_MASK 0xFFF +#define MCDE_PAL0_BLUE_SHIFT 0 +#define MCDE_PAL0_BLUE_MASK 0xFFF + + +#define MCDE_PAL1 (MCDE_BASE + 0x870) +#define MCDE_PAL1_RED_SHIFT 0 +#define MCDE_PAL1_RED_MASK 0xFFF + + +#define MCDE_ROTADD0 (MCDE_BASE + 0x874) +//#define MCDE_ROTADD0_SHIFT 3 +//#define MCDE_ROTADD0_MASK +#define MCDE_ROTADD1 (MCDE_BASE + 0x878) + + +#define MCDE_ROTCONF (MCDE_BASE + 0x87C) +#define MCDE_ROTCONF_RD_ROPC_SHIFT 24 +#define MCDE_ROTCONF_RD_ROPC_MASK 0xFF +#define MCDE_ROTCONF_WR_ROPC_SHIFT 16 +#define MCDE_ROTCONF_WR_ROPC_MASK 0xFF +#define MCDE_ROTCONF_STRIP_WIDTH_SHIFT 8 +#define MCDE_ROTCONF_STRIP_WIDTH_MASK 0xFF +#define MCDE_ROTCONF_RD_MAXOUT_SHIFT 6 +#define MCDE_ROTCONF_RD_MAXOUT_MASK 0x3 +#define MCDE_ROTCONF_WR_MAXOUT_SHIFT 4 +#define MCDE_ROTCONF_WR_MAXOUT_MASK 0x3 +#define MCDE_ROTCONF_ROTDIR 0x00000008 +#define MCDE_ROTCONF_ROTBURSTSIZE_SHIFT 0 +#define MCDE_ROTCONF_ROTBURSTSIZE_MASK 0x7 + + +#define MCDE_SYNCHCONF (MCDE_BASE + 0x880) +#define MCDE_SYNCHCONF_SWINTVCNT_SHIFT 18 +#define MCDE_SYNCHCONF_SWINTVCNT_MASK 0x3FFF +#define MCDE_SYNCHCONF_SWINTVEVENT_SHIFT 16 +#define MCDE_SYNCHCONF_SWINTVEVENT_MASK 0x3 +#define MCDE_SYNCHCONF_HWREQVCNT_SHIFT 2 +#define MCDE_SYNCHCONF_HWREQVCNT_MASK 0x3FFF +#define MCDE_SYNCHCONF_HWREQVEVENT_SHIFT 0 +#define MCDE_SYNCHCONF_HWREQVEVENT_MASK 0x3 + + +#define MCDE_GAM0 (MCDE_BASE + 0x888) +#define MCDE_GAM0_BLUE_SHIFT 0 +#define MCDE_GAM0_BLUE_MASK 0x00FFFFFF + + +#define MCDE_GAM1 (MCDE_BASE + 0x88C) +#define MCDE_GAM1_GREEN_SHIFT 0 +#define MCDE_GAM1_GREEN_MASK 0x00FFFFFF + + +#define MCDE_GAM2 (MCDE_BASE + 0x890) +#define MCDE_GAM2_RED_SHIFT 0 +#define MCDE_GAM2_RED_MASK 0x00FFFFFF + + +#define MCDE_OLEDCONV1 (MCDE_BASE + 0x894) +#define MCDE_OLEDCONV1_ALPHA_GREEN_SHIFT 16 +#define MCDE_OLEDCONV1_ALPHA_GREEN_MASK 0x3FFF +#define MCDE_OLEDCONV1_ALPHA_RED_SHIFT 0 +#define MCDE_OLEDCONV1_ALPHA_RED_MASK 0x3FFF + + +#define MCDE_OLEDCONV2 (MCDE_BASE + 0x898) +#define MCDE_OLEDCONV2_BETA_RED_SHIFT 16 +#define MCDE_OLEDCONV2_BETA_RED_MASK 0x3FFF +#define MCDE_OLEDCONV2_ALPHA_BLUE_SHIFT 0 +#define MCDE_OLEDCONV2_ALPHA_BLUE_MASK 0x3FFF + + +#define MCDE_OLEDCONV3 (MCDE_BASE + 0x89C) +#define MCDE_OLEDCONV3_BETA_BLUE_SHIFT 16 +#define MCDE_OLEDCONV3_BETA_BLUE_MASK 0x3FFF +#define MCDE_OLEDCONV3_BETA_GREEN_SHIFT 0 +#define MCDE_OLEDCONV3_BETA_GREEN_MASK 0x3FFF + + +#define MCDE_OLEDCONV4 (MCDE_BASE + 0x8A0) +#define MCDE_OLEDCONV4_GAMMA_GREEN_SHIFT 16 +#define MCDE_OLEDCONV4_GAMMA_GREEN_MASK 0x3FFF +#define MCDE_OLEDCONV4_GAMMA_RED_SHIFT 0 +#define MCDE_OLEDCONV4_GAMMA_RED_MASK 0x3FFF + + +#define MCDE_OLEDCONV5 (MCDE_BASE + 0x8A4) +#define MCDE_OLEDCONV5_OFF_RED_SHIFT 16 +#define MCDE_OLEDCONV5_OFF_RED_MASK 0x3FFF +#define MCDE_OLEDCONV5_GAMMA_BLUE_SHIFT 0 +#define MCDE_OLEDCONV5_GAMMA_BLUE_MASK 0x3FFF + + +#define MCDE_OLEDCONV6 (MCDE_BASE + 0x8A8) +#define MCDE_OLEDCONV6_OFF_BLUE_SHIFT 16 +#define MCDE_OLEDCONV6_OFF_BLUE_MASK 0x3FFF +#define MCDE_OLEDCONV6_OFF_GREEN_SHIFT 0 +#define MCDE_OLEDCONV6_OFF_GREEN_MASK 0x3FFF + + +#define MCDE_CRC (MCDE_BASE + 0xC00) +#define MCDE_CRC_CLAMPC1EN 0x80000000 +#define MCDE_CRC_SYNCCTRL_SHIFT 29 +#define MCDE_CRC_SYNCCTRL_MASK 0x3 +#define MCDE_CRC_RES2POL 0x10000000 +#define MCDE_CRC_RES1POL 0x08000000 +#define MCDE_CRC_RD2POL 0x04000000 +#define MCDE_CRC_RD1POL 0x02000000 +#define MCDE_CRC_WR2POL 0x01000000 +#define MCDE_CRC_WR1POL 0x00800000 +#define MCDE_CRC_CD2POL 0x00400000 +#define MCDE_CRC_CD1POL 0x00200000 +#define MCDE_CRC_CS2POL 0x00100000 +#define MCDE_CRC_CS1POL 0x00080000 +#define MCDE_CRC_RESEN 0x00040000 +#define MCDE_CRC_CS2EN 0x00020000 +#define MCDE_CRC_CS1EN 0x00010000 +#define MCDE_CRC_YUVCONVC1EN 0x00008000 +#define MCDE_CRC_CLKSEL_SHIFT 13 +#define MCDE_CRC_CLKSEL_MASK 0x3 +#define MCDE_CRC_INBAND2 0x00001000 +#define MCDE_CRC_INBAND1 0x00000800 +#define MCDE_CRC_SIZE2 0x00000400 +#define MCDE_CRC_SIZE1 0x00000200 +#define MCDE_CRC_SYCEN1 0x00000100 +#define MCDE_CRC_SYCEN0 0x00000080 +#define MCDE_CRC_SYNCSEL 0x00000040 +#define MCDE_CRC_WMLVL2 0x00000020 +#define MCDE_CRC_WMLVL1 0x00000010 +#define MCDE_CRC_C2EN 0x00000008 +#define MCDE_CRC_C1EN 0x00000004 +#define MCDE_CRC_POWEREN 0x00000002 +#define MCDE_CRC_FLOEN 0x00000001 + + +#define MCDE_PBCCRC (MCDE_BASE + 0xC04) +#define MCDE_PBCCRC_BPP_SHIFT 13 +#define MCDE_PBCCRC_BPP_MASK 0x7 +#define MCDE_PBCCRC_PDCTRL 0x00001000 +#define MCDE_PBCCRC_PDM_SHIFT 8 +#define MCDE_PBCCRC_PDM_MASK 0x3 +#define MCDE_PBCCRC_BSDM_SHIFT 4 +#define MCDE_PBCCRC_BSDM_MASK 0x7 +#define MCDE_PBCCRC_BSCM_SHIFT 0 +#define MCDE_PBCCRC_BSCM_MASK 0x7 + + +#define MCDE_PBCBMRC (MCDE_BASE + 0xC0C) +#define MCDE_PBCBCRC (MCDE_BASE + 0xC34) + + +#define MCDE_VSCRC (MCDE_BASE + 0xC5C) +#define MCDE_VSCRC_VSDBL_SHIFT 29 +#define MCDE_VSCRC_VSDBL_MASK 0x7 +#define MCDE_VSCRC_VSSEL 0x10000000 +#define MCDE_VSCRC_VSPOL 0x08000000 +#define MCDE_VSCRC_VSPDIV_SHIFT 24 +#define MCDE_VSCRC_VSPDIV_MASK 0x7 +#define MCDE_VSCRC_VSPMAX_SHIFT 12 +#define MCDE_VSCRC_VSPMAX_MASK 0xFFF +#define MCDE_VSCRC_VSPMIN_SHIFT 0 +#define MCDE_VSCRC_VSPMIN_MASK 0xFFF + + +#define MCDE_SCTRC (MCDE_BASE + 0xC64) +#define MCDE_SCTRC_TRDELC_SHIFT 16 +#define MCDE_SCTRC_TRDELC_MASK 0xFFF +#define MCDE_SCTRC_SYNCDELC1_SHIFT 8 +#define MCDE_SCTRC_SYNCDELC1_MASK 0xFF +#define MCDE_SCTRC_SYNCDELC0_SHIFT 0 +#define MCDE_SCTRC_SYNCDELC0_MASK 0xFF + + +#define MCDE_SCSRC (MCDE_BASE + 0xC68) +#define MCDE_SCSRC_VSTAC1 0x00000002 +#define MCDE_SCSRC_VSTAC0 0x00000001 + + +#define MCDE_BCNR (MCDE_BASE + 0xC6C) +#define MCDE_BCNR_BCN_SHIFT 0 +#define MCDE_BCNR_BCN_MASK 0xFF + + +#define MCDE_CSCDTR (MCDE_BASE + 0xC74) +#define MCDE_CSCDTR_CSCDDEACT_SHIFT 8 +#define MCDE_CSCDTR_CSCDDEACT_MASK 0xFF +#define MCDE_CSCDTR_CSCDACT_SHIFT 0 +#define MCDE_CSCDTR_CSCDACT_MASK 0xFF + + +#define MCDE_RDWRTR (MCDE_BASE + 0xC7C) +#define MCDE_RDWRTR_MOTINT 0x00010000 +#define MCDE_RDWRTR_RWDEACT_SHIFT 8 +#define MCDE_RDWRTR_RWDEACT_MASK 0xFF +#define MCDE_RDWRTR_RWACT_SHIFT 0 +#define MCDE_RDWRTR_RWACT_MASK 0xFF + + +#define MCDE_DOTR (MCDE_BASE + 0xC84) +#define MCDE_DOTR_DODEACT_SHIFT 8 +#define MCDE_DOTR_DODEACT_MASK 0xFF +#define MCDE_DOTR_DOACT_SHIFT 0 +#define MCDE_DOTR_DOACT_MASK 0xFF + + +#define MCDE_WCMDC (MCDE_BASE + 0xC8C) +#define MCDE_WDATADC (MCDE_BASE + 0xC94) + + +#define MCDE_RDATADC (MCDE_BASE + 0xC9C) +#define MCDE_RDATADC_STARTREAD 0x00010000 +#define MCDE_RDATADC_DATAREADFROMDISPLAYMODULE_SHIFT 0 +#define MCDE_RDATADC_DATAREADFROMDISPLAYMODULE_MASK 0xFF + + +#define MCDE_STATC (MCDE_BASE + 0xCA4) +#define MCDE_STATC_FIFOCMDFULL1 0x00000200 +#define MCDE_STATC_FIFOCMDEMPTY1 0x00000100 +#define MCDE_STATC_FIFOFULL1 0x00000080 +#define MCDE_STATC_FIFOEMPTY1 0x00000040 +#define MCDE_STATC_STATBUSY1 0x00000020 +#define MCDE_STATC_FIFOCMDFULL0 0x00000010 +#define MCDE_STATC_FIFOCMDEMPTY0 0x00000008 +#define MCDE_STATC_FIFOFULL0 0x00000004 +#define MCDE_STATC_FIFOEMPTY0 0x00000002 +#define MCDE_STATC_STATBUSY0 0x00000001 + + +#define MCDE_CTRLC (MCDE_BASE + 0xCA8) +#define MCDE_CTRLC_FIFOWTRMRK_SHIFT 0 +#define MCDE_CTRLC_FIFOWTRMRK_MASK 0xFF + + +#define MCDE_DSICONF0 (MCDE_BASE + 0xE00) +#define MCDE_DSICONF0_PACKING_SHIFT 20 +#define MCDE_DSICONF0_PACKING_MASK 0x7 +#define MCDE_DSICONF0_DCSVID_NOTGEN 0x00040000 +#define MCDE_DSICONF0_BYTE_SWAP 0x00020000 +#define MCDE_DSICONF0_BIT_SWAP 0x00010000 +#define MCDE_DSICONF0_CMD8 0x00002000 +#define MCDE_DSICONF0_VID_MODE 0x00001000 +#define MCDE_DSICONF0_BLANKING_SHIFT 0 +#define MCDE_DSICONF0_BLANKING_MASK 0xFF + + +#define MCDE_DSIFRAME (MCDE_BASE + 0xE04) + +#define MCDE_DSIPKT (MCDE_BASE + 0xE08) +#define MCDE_DSIPKT_PACKET_SHIFT 0 +#define MCDE_DSIPKT_PACKET_MASK 0xFFFF + + +#define MCDE_DSISYNC (MCDE_BASE + 0xE0C) +#define MCDE_DSISYNC_SW_SHIFT 16 +#define MCDE_DSISYNC_SW_MASK 0xFFF +#define MCDE_DSISYNC_DMA_SHIFT 0 +#define MCDE_DSISYNC_DMA_MASK 0xFFF + + +#define MCDE_DSICMDW (MCDE_BASE + 0xE10) +#define MCDE_DSICMDW_CMDW_START_SHIFT 16 +#define MCDE_DSICMDW_CMDW_START_MASK 0xFFFF +#define MCDE_DSICMDW_CMDW_CONTINUE_SHIFT 0 +#define MCDE_DSICMDW_CMDW_CONTINUE_MASK 0xFFFF + + +#define MCDE_DSIDELAY0 (MCDE_BASE + 0xE14) +#define MCDE_DSIDELAY0_INTPKTDEL_SHIFT 0 +#define MCDE_DSIDELAY0_INTPKTDEL_MASK 0xFFFF + + +#define MCDE_DSIDELAY1 (MCDE_BASE + 0xE18) +#define MCDE_DSIDELAY1_FRAMESTARTDEL_SHIFT 16 +#define MCDE_DSIDELAY1_FRAMESTARTDEL_MASK 0xFF +#define MCDE_DSIDELAY1_TEREQDEL_SHIFT 0 +#define MCDE_DSIDELAY1_TEREQDEL_MASK 0xFFF + + diff --git a/arch/arm/mach-ux500/include/mach/mcde_common.h b/arch/arm/mach-ux500/include/mach/mcde_common.h new file mode 100755 index 00000000000..fb992a6967b --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/mcde_common.h @@ -0,0 +1,173 @@ +/*---------------------------------------------------------------------------*/ +/* Copyrighti (C) STEricsson 2009. */ +/* */ +/* This program is free software; you can redistribute it and/or modify it */ +/* under the terms of the GNU Lesser General Public License as published */ +/* by the Free Software Foundation; either version 2.1 of the License, */ +/* or (at your option)any later version. */ +/* */ +/* This program is distributed in the hope that it will be useful, but */ +/* WITHOUT ANY WARRANTY; without even the implied warranty of */ +/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See */ +/* the GNU Lesser General Public License for more details. */ +/* */ +/* You should have received a copy of the GNU Lesser General Public License */ +/* along with this program. If not, see <http://www.gnu.org/licenses/>. */ +/*---------------------------------------------------------------------------*/ + +#ifndef _MCDE_COMMON_H_ +#define _MCDE_COMMON_H_ +#include <linux/fb.h> +#include <linux/interrupt.h> +#include <linux/platform_device.h> +#include <linux/spinlock.h> +#include <linux/mm.h> +#include <linux/dma-mapping.h> + +#include <mach/bit_mask.h> +#include <mach/mcde.h> +#include <mach/mcde_reg.h> +#include <mach/dsi.h> +#include <mach/dsi_reg.h> + +#define MCDE_NAME "DRIVER MCDE" + +#define MCDE_DEFAULT_LOG_LEVEL 3 +#ifdef CONFIG_FB_NDK_MCDE +extern int mcde_debug; +module_param(mcde_debug, int, 0644); +#endif +#ifdef CONFIG_FB_NDK_MCDE +MODULE_PARM_DESC(mcde_debug,"Debug level for messages"); +#define dbgprintk(num, format, args...) \ + do { \ + if(num >= mcde_debug ) \ + printk("MCDE:"format, ##args); \ + } while(0) +#else +#define dbgprintk(num, format, args...) \ + do { \ + printk("MCDE:"format, ##args); \ + } while(0) +#endif + +#define MCDE_DEBUG_INFO 1 +#define MCDE_ERROR_INFO 3 + +/** Global data */ + +#define MAX_LPF 1280 +#define MAX_PPL 1920 +#define NUM_MCDE_FLOWS 4 +#ifdef CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT +#define NUM_OVERLAYS 6 +#define NUM_EXT_SRC 10 +#define NUM_MCDE_CHANNELS 4 +#else +#define NUM_OVERLAYS 16 +#define NUM_EXT_SRC 16 +#define NUM_MCDE_CHANNELS 16 +#endif /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */ +#define NUM_FLOWS_A_B 2 +#define NUM_DSI_LINKS 3 +#define NUM_DSI_CHANNEL 6 +#define MCDE_MAX_FRAMEBUFF 16 +#define COLCONV_COEFF_OFF 6 + +/** clcd events for double buffering */ +struct clcd_event_struct { + spinlock_t lock; + int event; + wait_queue_head_t wait; + unsigned int base; +}; + +/** bitmap of which overlays are in use (set) and unused (cleared) */ +//static u32 mcde_ovl_bmp; + +/** MCDE private struct - pointer available in fbinfo */ +struct mcdefb_info { + struct mcde_channel_data *chnl_info; + mcde_ch_id chid; + mcde_video_mode video_mode; + mcde_fifo_output fifoOutput; + mcde_output_conf output_conf; + mcde_dsi_clk_config clk_config; + mcde_ch_id dsi_formatter_plugged_channel[NUM_DSI_CHANNEL]; + mcde_dsi_channel mcdeDsiChnl; + mcde_out_bpp outbpp; + int bpp16_type; + u8 bgrinput; + u8 isHwInitalized; + u16 palette_size; + u32 cmap[16]; + + mcde_ch_id pixel_pipeline; + u32 vcomp_irq; + u32 dsi_formatter; + u32 dsi_mode; + + /** phy-virtual addresses allocated for framebuffer and overlays */ + struct mcde_addrmap buffaddr[MCDE_MAX_FRAMEBUFF*2]; + struct mcde_addrmap rotationbuffaddr0; + struct mcde_addrmap rotationbuffaddr1; + + /** total number of overlays used in the system */ + u8 tot_ovl_used; + + /** bitmap of which overlays are in use (set) and unused (cleared) */ + u16 mcde_cur_ovl_bmp; + u16 mcde_ovl_bmp_arr[MCDE_MAX_FRAMEBUFF]; + spinlock_t mcde_spin_lock; + + /** event for double buffering */ + struct clcd_event_struct clcd_event; + u8 tvout; + u32 actual_bpp; +#ifdef CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT + struct mcde_top_reg __iomem *regbase; +#else + struct mcde_register_base __iomem * regbase; +#endif /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */ + struct mcde_ext_src_reg __iomem * extsrc_regbase[NUM_EXT_SRC]; + struct mcde_ovl_reg __iomem * ovl_regbase[NUM_OVERLAYS]; +#ifdef CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT + struct mcde_chnl_conf_reg __iomem *ch_regbase1[NUM_MCDE_CHANNELS]; + struct mcde_chAB_reg __iomem *ch_regbase2[NUM_FLOWS_A_B]; + struct mcde_chC0C1_reg __iomem *ch_c_reg; +#else + struct mcde_ch_synch_reg __iomem *ch_regbase1[NUM_MCDE_CHANNELS]; + struct mcde_ch_reg __iomem *ch_regbase2[NUM_FLOWS_A_B]; + struct mcde_chc_reg __iomem *ch_c_reg; +#endif /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */ + struct mcde_dsi_reg __iomem *mcde_dsi_channel_reg[NUM_DSI_CHANNEL]; + volatile u32 __iomem *mcde_clkdsi; + struct dsi_link_registers __iomem *dsi_lnk_registers[NUM_DSI_LINKS]; + volatile u32 __iomem *prcm_mcde_clk; + volatile u32 __iomem *prcm_hdmi_clk; + volatile u32 __iomem *prcm_tv_clk; + dsi_link dsi_lnk_no; + dsi_link_context dsi_lnk_context; + struct dsi_link_conf dsi_lnk_conf; + + /* Added by QCSPWAN below for "pink display" */ +#ifdef CONFIG_DEBUG_FS + struct dentry *debugfs_dentry; + char debugfs_name[10]; +#endif + /* To serialize access from user space */ + struct semaphore fb_sem; + /* End QCSPWAN */ +}; + + +//volatile mcde_system_context g_mcde_system_context; + +#define NUM_TOTAL_MODES ARRAY_SIZE(mcde_modedb) + +mcde_error mcdesetdsiclk(dsi_link link, mcde_ch_id chid, mcde_dsi_clk_config clk_config); +mcde_error mcdesetfifoctrl(dsi_link link, mcde_ch_id chid, struct mcde_fifo_ctrl fifo_ctrl); +mcde_error mcdesetoutputconf(dsi_link link, mcde_ch_id chid, mcde_output_conf output_conf); +mcde_error mcdesetdsicommandword(dsi_link link,mcde_ch_id chid,mcde_dsi_channel dsichannel,u8 cmdbyte_lsb,u8 cmdbyte_msb); +mcde_error mcdesetdsiconf(dsi_link link, mcde_ch_id chid, mcde_dsi_channel dsichannel, mcde_dsi_conf dsi_conf); +#endif diff --git a/arch/arm/mach-ux500/include/mach/mcde_ioctls.h b/arch/arm/mach-ux500/include/mach/mcde_ioctls.h new file mode 100755 index 00000000000..605b430c0d9 --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/mcde_ioctls.h @@ -0,0 +1,737 @@ +/*----------------------------------------------------------------------------------*/ +/* copyright STEricsson, 2009. */ +/* */ +/* This program is free software; you can redistribute it and/or modify it under */ +/* the terms of the GNU General Public License as published by the Free */ +/* Software Foundation; either version 2.1 of the License, or (at your option) */ +/* any later version. */ +/* */ +/* This program is distributed in the hope that it will be useful, but WITHOUT */ +/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS */ +/* FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. */ +/* */ +/* You should have received a copy of the GNU General Public License */ +/* along with this program. If not, see <http://www.gnu.org/licenses/>. */ +/*----------------------------------------------------------------------------------*/ + +#ifndef _MCDE_IOCTLS_H_ +#define _MCDE_IOCTLS_H_ + +typedef enum +{ + COLOR_CONV_NONE = 0x0, + COLOR_CONV_YUV_RGB = 0x1, + COLOR_CONV_RGB_YUV = 0x2, + COLOR_CONV_YUV422_YUV444 = 0x3 +}mcde_colorconv_type; + +typedef enum +{ + MCDE_COL_CONV_DISABLE = 0x0, + MCDE_COL_CONV_NOT_SAT = 0x1, + MCDE_COL_CONV_SAT = 0x2, + MCDE_COL_CONV_RESERVED +}mcde_col_conv_ctrl; + +struct mcde_ovr_blend_ctrl +{ + char alpha_value; + char ovr_opaq; + char ovr_blend; + char ovr_zlevel; + unsigned int ovr_xpos; + unsigned int ovr_ypos; +}; + +typedef enum +{ + MCDE_ROTATE_BURST_WORD_1 = 0x0, + MCDE_ROTATE_BURST_WORD_2 = 0x1, + MCDE_ROTATE_BURST_WORD_4 = 0x2, + MCDE_ROTATE_BURST_WORD_8 = 0x3, + MCDE_ROTATE_BURST_WORD_16 = 0x04, + MCDE_ROTATE_BURST_WORD_RESERVED + }mcde_rotate_req; + +typedef enum +{ + MCDE_OUTSTND_REQ_1 = 0x0, + MCDE_OUTSTND_REQ_2 = 0x1, + MCDE_OUTSTND_REQ_4 = 0x2, + MCDE_OUTSTND_REQ_8 = 0x3, + MCDE_OUTSTND_REQ_16 = 0x4, + MCDE_OUTSTND_REQ_RESERVED +}mcde_outsnd_req; +typedef enum +{ + MCDE_BURST_WORD_1 = 0x00, + MCDE_BURST_WORD_2 = 0x01, + MCDE_BURST_WORD_4 = 0x02, + MCDE_BURST_WORD_8 = 0x03, + MCDE_BURST_WORD_16 = 0x04, + MCDE_BURST_WORD_HW_1 = 0x8, + MCDE_BURST_WORD_HW_2 = 0x09, + MCDE_BURST_WORD_HW_4 = 0x0A, + MCDE_BURST_WORD_HW_8 = 0x0B, + MCDE_BURST_WORD_HW_16 = 0x0C +}mcde_burst_req; +typedef enum +{ + MCDE_COLOR_KEY_DISABLE = 0x0, + MCDE_COLOR_KEY_ENABLE = 0x01 +}mcde_color_key_ctrl; +typedef enum +{ + MCDE_PAL_GAMA_DISABLE = 0x0, + MCDE_GAMA_ENABLE = 0x1, + MCDE_PAL_ENABLE = 0x2, + MCDE_PAL_GAMA_RESERVED +}mcde_pal_ctrl; +typedef enum +{ + MCDE_OVERLAY_DISABLE = 0x0, + MCDE_OVERLAY_ENABLE = 0x1 +}mcde_overlay_ctrl; +typedef enum +{ + MCDE_PIXEL_ALPHA_SOURCE = 0x0, + MCDE_CONST_ALPHA_SOURCE = 0x1 +}mcde_blend_ctrl; +typedef enum +{ + MCDE_OVR_OPAQUE_DISABLE = 0x0, + MCDE_OVR_OPAQUE_ENABLE = 0x1 +}mcde_ovr_opq_ctrl; +typedef enum +{ + MCDE_OVR_PREMULTIPLIED_ALPHA_DISABLE = 0x0, + MCDE_OVR_PREMULTIPLIED_ALPHA_ENABLE = 0x1 +}mcde_ovr_alpha_enable; +typedef enum +{ + MCDE_OVR_CLIP_DISABLE = 0x0, + MCDE_OVR_CLIP_ENABLE = 0x1 +}mcde_ovr_clip_enable; + +struct mcde_chconfig +{ + unsigned short lpf; + unsigned short ppl; +}; +typedef enum +{ + MCDE_LCD_TV_0 = 0x0, + MCDE_LCD_TV_1 = 0x1, + MCDE_MDIF_IN_0 = 0x2, + MCDE_MDIF_IN_1 = 0x3, + MCDE_MDIF_OUT_0 = 0x4, + MCDE_MDIF_OUT_1 = 0x5 +}mcde_synchro_out_interface; +typedef enum +{ + MCDE_SYNCHRO_OUTPUT_SOURCE = 0x0, + MCDE_SYNCHRO_AUTO = 0x1, + MCDE_SYNCHRO_SOFTWARE = 0x2, + MCDE_SYNCHRO_EXTERNAL_SOURCE = 0x3 +}mcde_synchro_source; +typedef enum +{ + MCDE_NO_ACTION = 0x0, + MCDE_NEW_FRAME_SYNCHRO = 0x1 +}mcde_sw_trigger; +typedef enum +{ + MCDE_VERTICAL_SYNCHRO = 0x00, + MCDE_BACK_PORCH = 0x01, + MCDE_ACTIVE_VIDEO = 0x02, + MCDE_FRONT_PORCH = 0x03 +}mcde_frame_events; +struct mcde_ch_bckgrnd_col +{ + unsigned char red; + unsigned char green; + unsigned char blue; +}; +typedef enum +{ + MCDE_TVCLK_EXTERNAL = 0x0, + MCDE_TVCLK_INTERNAL = 0x1 +}mcde_tv_clk; +typedef enum +{ + MCDE_PCD_ENABLE = 0x0, + MCDE_PCD_BYPASS = 0x1 +}mcde_bcd_ctrl; +typedef enum +{ + MCDE_BPP_1_TO_8 = 0x0, + MCDE_BPP_12 = 0x1, + MCDE_BPP_16 = 0x2, + MCDE_BPP_18 = 0x3, + MCDE_BPP_24 = 0x4 +}mcde_out_bpp; +typedef enum +{ + MCDE_BUS_16_CONF1 = 0x0, + MCDE_BUS_16_CONF2 = 0x1, + MCDE_BUS_16_CONF3 = 0x2, + MCDE_BUS_18_CONF1 = 0x3, + MCDE_BUS_18_CONF2 = 0x4, + MCDE_BUS_24 = 0x5 +}mcde_lcd_bus; +typedef enum +{ + MCDE_CLK_STBUS = 0x0, + MCDE_CLK_72 = 0x1, + MCDE_CLK_42 = 0x2, + MCDE_CLK_27 = 0x3, + MCDE_CLK_TVCLK1 = 0x4, + MCDE_CLK_TVCLK2 = 0x5 +}mcde_dpi2_clksel; + +struct mcde_chx_control1 +{ + mcde_tv_clk tv_clk; + mcde_bcd_ctrl bcd_ctrl; + mcde_out_bpp out_bpp; + unsigned short clk_per_line; + mcde_lcd_bus lcd_bus; + mcde_dpi2_clksel dpi2_clk; + unsigned short pcd; +}; +typedef enum +{ + MCDE_CLR_KEY_DISABLE = 0x0, + MCDE_ALPHA_RGB_KEY = 0x1, + MCDE_RGB_KEY = 0x2, + MCDE_FALPHA_FRGB_KEY = 0x4, + MCDE_FRGB_KEY = 0x5 +}mcde_key_ctrl; +typedef enum +{ + MCDE_COLORKEY_NORMAL = 0x0, + MCDE_COLORKEY_FORCE= 0x1 +}mcde_colorkey_type; +struct mcde_chx_color_key +{ + unsigned char alpha; + unsigned char red; + unsigned char green; + unsigned char blue; +}; +typedef enum +{ + MCDE_SDTV_656P = 0x0, + MCDE_HDTV_480P = 0x1, + MCDE_HDTV_720P = 0x2, + MCDE_TV_NOTUSED = 0x3, +}mcde_tvmode; +typedef enum +{ + MCDE_ACTIVE_HIGH = 0x0, + MCDE_ACTIVE_LOW = 0x1 +}mcde_signal_level; +typedef enum +{ + MCDE_MODE_LCD = 0x0, + MCDE_MODE_TV = 0x1 +}mcde_display_mode; +typedef enum +{ + MCDE_SCAN_PROGRESSIVE_MODE = 0x0, + MCDE_SCAN_INTERLACED_MODE = 0x1, +}mcde_scan_mode; + +typedef enum +{ + MCDE_TV_PAL = 0x0, + MCDE_TV_NTSC = 0x1, +}mcde_tv_mode; + +struct mcde_chnl_lcd_ctrl_reg +{ + unsigned short num_lines; + unsigned short ppl; + mcde_tvmode tv_mode; + mcde_signal_level ifield; + mcde_scan_mode scan_mode; + mcde_display_mode sel_mode; +}; +struct mcde_chnl_lcd_horizontal_timing +{ + unsigned short hbp; + unsigned short hfp; + unsigned short hsw; +}; +struct mcde_chnl_lcd_vertical_timing +{ + unsigned short vbp; + unsigned short vfp; + unsigned short vsw; +}; + +typedef enum +{ + MCDE_ANTIFLICKER_DISABLE = 0x0, + MCDE_ANTIFLICKER_ENABLE = 0x1 +}mcde_antiflicker_ctrl; + +typedef enum +{ + MCDE_PIXEL_ORDER_LITTLE = 0x0, + MCDE_PIXEL_ORDER_BIG = 0x1 +}mcde_pixel_order_in_byte; + +typedef enum +{ + MCDE_BYTE_LITTLE = 0x0, + MCDE_BYTE_BIG = 0x1 +}mcde_byte_endianity; + +typedef enum +{ + MCDE_COL_RGB = 0x0, + MCDE_COL_BGR = 0x1 +}mcde_rgb_format_sel; + +typedef enum +{ + MCDE_PAL_1_BIT = 0x0, + MCDE_PAL_2_BIT = 0x1, + MCDE_PAL_4_BIT = 0x2, + MCDE_PAL_8_BIT = 0x3, + MCDE_RGB444_12_BIT = 0x4, + MCDE_ARGB_16_BIT = 0x5, + MCDE_IRGB1555_16_BIT = 0x6, + MCDE_RGB565_16_BIT = 0x7, + MCDE_RGB_PACKED_24_BIT = 0x8, + MCDE_RGB_UNPACKED_24_BIT = 0x9, + MCDE_ARGB_32_BIT =0xA, + MCDE_YCbCr_8_BIT = 0xB +}mcde_bpp_ctrl; + +typedef enum +{ + MCDE_OVERLAY_0 = 0x0, + MCDE_OVERLAY_1 = 0x1, + MCDE_OVERLAY_2 = 0x2, + MCDE_OVERLAY_3 = 0x3, + MCDE_OVERLAY_4 = 0x4, + MCDE_OVERLAY_5 = 0x5, + MCDE_OVERLAY_6 = 0x6, + MCDE_OVERLAY_7 = 0x7 +}mcde_overlay_id; + +typedef enum +{ + MCDE_BUFFER_USED_NONE = 0x0, + MCDE_BUFFER_USED_1 = 0x1, + MCDE_BUFFER_USED_2 = 0x2, + MCDE_BUFFER_USED_3 = 0x3 +}mcde_num_buffer_used; + +typedef enum +{ + MCDE_BUFFER_ID_0 = 0x0, + MCDE_BUFFER_ID_1 = 0x1, + MCDE_BUFFER_ID_2 = 0x2, + MCDE_BUFFER_ID_RESERVED +}mcde_buffer_id; + +typedef enum +{ + MCDE_MASK_DISABLE = 0x0, + MCDE_MASK_ENABLE = 0x1 +}mcde_masking_bit_ctrl; + +typedef enum +{ + MCDE_DITHERING_RESET = 0x0, + MCDE_DITHERING_ACTIVATE = 0x1 +}mcde_dithering_control; +typedef enum +{ + MCDE_DITHERING_DISABLE = 0x0, + MCDE_DITHERING_ENABLE = 0x1 +}mcde_dithering_ctrl; +struct mcde_chx_dither_ctrl +{ + unsigned char y_offset; + unsigned char x_offset; + mcde_masking_bit_ctrl masking_ctrl; + unsigned char mode; + mcde_dithering_ctrl comp_dithering; + mcde_dithering_ctrl temp_dithering; +}; +struct mcde_chx_dithering_offset +{ + unsigned char y_offset_rb; + unsigned char x_offset_rb; + unsigned char y_offset_rg; + unsigned char x_offset_rg; +}; + +typedef enum{ + VMODE_640_350_85_P, + VMODE_640_400_85_P, + VMODE_720_400_85_P, + VMODE_640_480_60_P, + VMODE_640_480_CRT_60_P, + VMODE_240_320_60_P, + VMODE_320_240_60_P, + VMODE_712_568_60_P, + VMODE_640_480_75_P, + VMODE_640_480_85_P, +//#ifdef CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT + VMODE_480_864_60_P, +//#endif + VMODE_864_480_60_P, + VMODE_800_600_56_P, + VMODE_800_600_60_P, + VMODE_800_600_72_P, + VMODE_800_600_75_P, + VMODE_800_600_85_P, + VMODE_1024_768_60_P, + VMODE_1024_768_70_P, + VMODE_1024_768_75_P, + VMODE_1024_768_85_P, + VMODE_1152_864_75_P, + VMODE_1280_960_60_P, + VMODE_1280_960_85_P, + VMODE_1280_1024_60_P, + VMODE_1280_1024_75_P, + VMODE_1280_1024_85_P, + VMODE_1600_1200_60_P, + VMODE_1600_1200_65_P, + VMODE_1600_1200_70_P, + VMODE_1600_1200_75_P, + VMODE_1600_1200_85_P, + VMODE_1792_1344_60_P, + VMODE_1792_1344_75_P, + VMODE_1856_1392_60_P, + VMODE_1856_1392_75_P, + VMODE_1920_1440_60_P, + VMODE_1920_1440_75_P, + VMODE_720_480_60_P, + VMODE_720_480_60_I, + VMODE_720_576_50_P, + VMODE_720_576_50_I, + VMODE_1280_720_50_P, + VMODE_1280_720_60_P, + VMODE_1920_1080_50_I, + VMODE_1920_1080_60_I, + VMODE_1920_1080_60_P, +#ifdef CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT + VMODE_1920_1080_30_P, +#endif +}mcde_video_mode; +/***************************************************************************** +IOCTLs for access from user space +*******************************************************************************/ + +#define MCDE_IOC_MAGIC 'm' + +#define MCDE_IOCTL_OVERLAY_CREATE _IOWR(MCDE_IOC_MAGIC, 0x0,struct mcde_overlay_create) +#define MCDE_IOCTL_OVERLAY_REMOVE _IOR(MCDE_IOC_MAGIC, 0x1,unsigned long) +#define MCDE_IOCTL_COLOR_KEYING_ENABLE _IOWR(MCDE_IOC_MAGIC, 0x2,struct mcde_channel_color_key) +#define MCDE_IOCTL_COLOR_KEYING_DISABLE _IOR(MCDE_IOC_MAGIC, 0x3,unsigned long) +#define MCDE_IOCTL_COLOR_COVERSION_ENABLE _IOWR(MCDE_IOC_MAGIC, 0x4,struct mcde_conf_color_conv) +#define MCDE_IOCTL_COLOR_COVERSION_DISABLE _IOR(MCDE_IOC_MAGIC, 0x5,unsigned long) +#define MCDE_IOCTL_ROTATION_ENABLE _IOR(MCDE_IOC_MAGIC, 0x6,unsigned char) +#define MCDE_IOCTL_ROTATION_DISABLE _IOR(MCDE_IOC_MAGIC, 0x7,unsigned char) +#define MCDE_IOCTL_SET_VIDEOMODE _IOR(MCDE_IOC_MAGIC, 0x8, unsigned long) +#define MCDE_IOCTL_ALLOC_FRAMEBUFFER _IOWR(MCDE_IOC_MAGIC, 0x9,struct mcde_sourcebuffer_alloc) +#define MCDE_IOCTL_DEALLOC_FRAMEBUFFER _IOWR(MCDE_IOC_MAGIC, 0xA, unsigned long) +#define MCDE_IOCTL_CONFIGURE_EXTSRC _IOR(MCDE_IOC_MAGIC, 0xB,struct mcde_ext_conf) +#define MCDE_IOCTL_CONFIGURE_OVRLAY _IOR(MCDE_IOC_MAGIC, 0xC,struct mcde_conf_overlay) +#define MCDE_IOCTL_CONFIGURE_CHANNEL _IOR(MCDE_IOC_MAGIC, 0xD,struct mcde_ch_conf) +#define MCDE_IOCTL_CONFIGURE_PANEL _IOR(MCDE_IOC_MAGIC, 0xE,struct mcde_chnl_lcd_ctrl) +#define MCDE_IOCTL_MCDE_ENABLE _IOR(MCDE_IOC_MAGIC, 0xF,unsigned long) +#define MCDE_IOCTL_MCDE_DISABLE _IOR(MCDE_IOC_MAGIC, 0x10,unsigned long) +#define MCDE_IOCTL_CHANNEL_BLEND_ENABLE _IOWR(MCDE_IOC_MAGIC,0x11,struct mcde_blend_control) +#define MCDE_IOCTL_CHANNEL_BLEND_DISABLE _IOR(MCDE_IOC_MAGIC, 0x12,unsigned long) +#define MCDE_IOCTL_CONFIGURE_DENC _IOR(MCDE_IOC_MAGIC, 0x13,unsigned long) +#define MCDE_IOCTL_CONFIGURE_HDMI _IOR(MCDE_IOC_MAGIC, 0x14,unsigned long) +#define MCDE_IOCTL_SET_SOURCE_BUFFER _IOR(MCDE_IOC_MAGIC, 0x15,struct mcde_source_buffer) +#define MCDE_IOCTL_DITHERING_ENABLE _IOR(MCDE_IOC_MAGIC, 0x16,struct mcde_dithering_ctrl_conf) +#define MCDE_IOCTL_DITHERING_DISABLE _IOR(MCDE_IOC_MAGIC, 0x16,unsigned long) +#define MCDE_IOCTL_ANTIFLICKER_ENABLE _IOR(MCDE_IOC_MAGIC, 0x17,unsigned long) +#define MCDE_IOCTL_ANTIFLICKER_DISABLE _IOR(MCDE_IOC_MAGIC, 0x18,unsigned long) +#define MCDE_IOCTL_TEST_DSI_LPMODE _IOR(MCDE_IOC_MAGIC, 0x19,unsigned long) +#define MCDE_IOCTL_TEST_DSI_HSMODE _IOR(MCDE_IOC_MAGIC, 0x1A,unsigned long) +#define MCDE_IOCTL_SET_SCAN_MODE _IOWR(MCDE_IOC_MAGIC, 0x1B,unsigned long) +#define MCDE_IOCTL_GET_SCAN_MODE _IOR(MCDE_IOC_MAGIC, 0x1C,unsigned long) + +#define MCDE_IOCTL_TV_PLUG_STATUS _IOR(MCDE_IOC_MAGIC, 0x1D,unsigned long) +#define MCDE_IOCTL_TV_CHANGE_MODE _IOWR(MCDE_IOC_MAGIC, 0x1E,unsigned long) +#define MCDE_IOCTL_TV_GET_MODE _IOR(MCDE_IOC_MAGIC, 0x1F,unsigned long) + +/** + * struct mcde_overlay_create - To create overlay + * @xorig: frame buffer x-offset + * @yorig: frame buffer y-offset + * @xwidth: frame buffer x-width + * @yheight - frame buffer y-height + * @bpp: input source bits per pixel + * @fg: if set then overlay goes to foreground,else remains in background + * @key: unique framebuffer key returned by driver + * @bgrinput: if set then implies BGR input + * @usedefault: if set then uses base overlay buffer + * + * + **/ +struct mcde_overlay_create { + unsigned long xorig; + unsigned long yorig; + unsigned long xwidth; + unsigned long yheight; + char bpp; /** input source bits per pixel */ + char fg; /** if set then overlay goes to foreground,else remains in background */ + unsigned long key; /** unique framebuffer key returned by driver */ + unsigned long bgrinput; /** if set then implies BGR input */ + char usedefault; // if set then uses base overlay buffer +}; +/** + * struct mcde_addrmap - source frame buffer address map structure + * @cpuaddr: logical address of the framebuffer + * @dmaaddr: physical address of the framebuffer + * @bufflength: buffer length + * + * + **/ +struct mcde_addrmap { + unsigned long cpuaddr; + unsigned long dmaaddr; + unsigned long bufflength; +}; +/** + * struct mcde_source_buffer - source frame buffer addresses structure + * @buff_addr: frame buffer addresses structure + * @buffid: buffer id + * + * + **/ +struct mcde_source_buffer +{ + struct mcde_addrmap buffaddr; + unsigned char buffid; +}; +/** + * struct mcde_sourcebuffer_alloc - source frame buffer allocation structure + * @xwidth: frame buffer x-width + * @yheight: frame buffer y-height + * @bpp: input source bits per pixel + * @doubleBufferingEnabled: double buffer control + * @key: unique framebuffer key returned by driver + * @buff_addr: frame buffer addresses structure + * + * + **/ +struct mcde_sourcebuffer_alloc { + unsigned long xwidth; + unsigned long yheight; + char bpp; /** input source bits per pixel */ + char doubleBufferingEnabled; + unsigned long key; /** unique framebuffer key returned by driver */ + struct mcde_addrmap buff_addr; +}; + +/** + * struct mcde_dithering_ctrl_conf - Structure of overlay configuration + * @rot_burst_req: rotation burst request + * @outstnd_req: outstanding request + * @burst_req: burst request + * @priority: priority + * @color_key: color key control + * @pal_control: pal control + * @col_ctrl: color conversion control + * @convert_format: conversion format + * @ovr_state: overlay control + * @ovr_ypos: overlay y-position + * @ovr_xpos: overlay x-position + * @alpha: alpha control + * @alpha_value: alpha value + * @pixoff: pixel offset + * @ovr_opaq: overlay opaque control + * @ovr_blend: overlay blend control + * @watermark_level: watermark level + * @ovr_zlevel: foreground level + * @clip: clip control + * @ytlcoor: clip y-topleft coordinates + * @xtlcoor: clip x-topleft coordinates + * @ybrcoor: clip y-bottomright coordinates + * @xbrcoor: clip x-bottomright coordinates + * @xwidth: x-width + * @yheight: y-height + * @bpp: input bpp + * + * + **/ +struct mcde_conf_overlay { + mcde_rotate_req rot_burst_req; + mcde_outsnd_req outstnd_req; + mcde_burst_req burst_req; + unsigned char priority; + mcde_color_key_ctrl color_key; + mcde_pal_ctrl pal_control; + mcde_col_conv_ctrl col_ctrl; + mcde_colorconv_type convert_format; + mcde_overlay_ctrl ovr_state; + + unsigned short ovr_ypos; + unsigned short ovr_xpos; + + mcde_ovr_alpha_enable alpha; + unsigned char alpha_value; + unsigned char pixoff; + mcde_ovr_opq_ctrl ovr_opaq; + mcde_blend_ctrl ovr_blend; + unsigned long watermark_level; + unsigned char ovr_zlevel; + + mcde_ovr_clip_enable clip; + unsigned long ytlcoor; + unsigned long xtlcoor; + unsigned long ybrcoor; + unsigned long xbrcoor; + + unsigned long xwidth; + unsigned long yheight; + char bpp; /** input source bits per pixel */ + +}; +/** + * struct mcde_blend_control - channel configuration structure + * @chconfig: channel config structure + * @out_synch_interface: out sync interface + * @ch_synch_src: channel sync source + * @sw_trig: software trigger param + * @swint_vcnt: int count param + * @swint_vevent: event count param + * @chbckgrndcolor: channel background color + * @ch_priority: channel priority + * @control1: channel control structure + * + * + **/ +struct mcde_ch_conf +{ + struct mcde_chconfig chconfig; + mcde_synchro_out_interface out_synch_interface; + mcde_synchro_source ch_synch_src; + mcde_sw_trigger sw_trig; + unsigned short swint_vcnt; + mcde_frame_events swint_vevent; + unsigned short hwreq_vcnt; + mcde_frame_events hwreq_vevent; + struct mcde_ch_bckgrnd_col chbckgrndcolor; + unsigned char ch_priority; + struct mcde_chx_control1 control1; +}; +/** + * struct mcde_blend_control - color keying configuration structure + * @key_ctrl: color key control + * @color_key_type: color key type + * @color_key: channel color key structure + * + * + **/ +struct mcde_channel_color_key +{ + mcde_key_ctrl key_ctrl; + mcde_colorkey_type color_key_type; + struct mcde_chx_color_key color_key; +}; +/** + * struct mcde_conf_color_conv - color conversion configuration structure + * @convert_format: convert format type + * @col_ctrl: color conversion control + * + * + **/ +struct mcde_conf_color_conv +{ + mcde_colorconv_type convert_format; + mcde_col_conv_ctrl col_ctrl; +}; +/** + * struct mcde_blend_control - blend control configuration structure + * @blenden: blend enable + * @blend_ctrl: blend control + * @alpha_blend: alpha blend + * @ovr1_id: overlay1 ID + * @ovr2_id: overlay2 ID + * @ovr2_enable: overlay2 enable + * @ovr1_blend_ctrl: overlay1 blend control structure + * @ovr2_blend_ctrl: overlay2 blend control structure + * + * + **/ +struct mcde_blend_control +{ + char blenden; + char blend_ctrl; + char alpha_blend; + char ovr1_id; + char ovr2_id; + char ovr2_enable; + struct mcde_ovr_blend_ctrl ovr1_blend_ctrl; + struct mcde_ovr_blend_ctrl ovr2_blend_ctrl; + +}; +/** + * struct mcde_chnl_lcd_ctrl - LCD control structure + * @lcd_ctrl_reg: lcd control reg structure + * @lcd_horizontal_timing: lcd horizontal timing structure + * @lcd_vertical_timing: lcd vertical timing structure + * + * + **/ +struct mcde_chnl_lcd_ctrl +{ + struct mcde_chnl_lcd_ctrl_reg lcd_ctrl_reg; + struct mcde_chnl_lcd_horizontal_timing lcd_horizontal_timing; + struct mcde_chnl_lcd_vertical_timing lcd_vertical_timing; + +}; +/** + * struct mcde_ext_conf - External source configuration structure + * @ovr_pxlorder: overlay pixel order + * @endianity: byte endianity + * @rgb_format: format type + * @bpp: input bpp + * @provr_id: overlay id + * @buf_num: number of buffers used + * @buf_id: buffer id to be used + * + * + **/ +struct mcde_ext_conf +{ + mcde_pixel_order_in_byte ovr_pxlorder; + mcde_byte_endianity endianity; + mcde_rgb_format_sel rgb_format; + mcde_bpp_ctrl bpp; + mcde_overlay_id provr_id; + mcde_num_buffer_used buf_num; + mcde_buffer_id buf_id; +}; +/** + * struct mcde_dithering_ctrl_conf - Structure of dithering configuration + * @dithering_ctrl: dithering control + * @input_bpp: input bpp + * @output_bpp: output bpp + * @mcde_chx_dither_ctrl: structure of dithering control + * @mcde_chx_dithering_offset: structure of the dithering offset + * + * + **/ +struct mcde_dithering_ctrl_conf +{ + mcde_dithering_ctrl dithering_ctrl; + mcde_bpp_ctrl input_bpp; + mcde_out_bpp output_bpp; + struct mcde_chx_dither_ctrl mcde_chx_dither_ctrl; + struct mcde_chx_dithering_offset mcde_chx_dithering_offset; +}; +#endif diff --git a/arch/arm/mach-ux500/include/mach/mcde_reg.h b/arch/arm/mach-ux500/include/mach/mcde_reg.h new file mode 100755 index 00000000000..45a1a935670 --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/mcde_reg.h @@ -0,0 +1,794 @@ +/*---------------------------------------------------------------------------*/ +/* Copyrighti (C) STEricsson 2009. */ +/* */ +/* This program is free software; you can redistribute it and/or modify it */ +/* under the terms of the GNU Lesser General Public License as published */ +/* by the Free Software Foundation; either version 2.1 of the License, */ +/* or (at your option)any later version. */ +/* */ +/* This program is distributed in the hope that it will be useful, but */ +/* WITHOUT ANY WARRANTY; without even the implied warranty of */ +/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See */ +/* the GNU Lesser General Public License for more details. */ +/* */ +/* You should have received a copy of the GNU Lesser General Public License */ +/* along with this program. If not, see <http://www.gnu.org/licenses/>. */ +/*---------------------------------------------------------------------------*/ + +#ifndef _MCDEREG_H_ +#define _MCDEREG_H_ + +#include <linux/types.h> +#include <mach/bit_mask.h> + +/******************************************************************* + MCDE Control Register Fields +********************************************************************/ +#define MCDE_DISABLE 0x00000000 +#define MCDE_ENABLE 0x80000000 +#define MCDE_SET_BIT 0x1 +#define MCDE_CLEAR_BIT 0x0 +#define MCDE_CTRL_MCDEEN_MASK MASK_BIT31 +#define MCDE_CTRL_MCDEEN_SHIFT 31 +#define MCDE_CTRL_FABMUX_MASK MASK_BIT17 +#define MCDE_CTRL_FABMUX_SHIFT 17 +#define MCDE_CTRL_F01MUX_MASK MASK_BIT16 +#define MCDE_CTRL_F01MUX_SHIFT 16 +#define MCDE_CTRL_IFIFICTRL_MASK MASK_BIT15 +#define MCDE_CTRL_IFIFICTRL_SHIFT 15 +#define MCDE_CTRL_DPIA_EN_MASK MASK_BIT9 +#define MCDE_CTRL_DPIA_EN_SHIFT 9 +#define MCDE_CTRL_DPIB_EN_MASK MASK_BIT8 +#define MCDE_CTRL_DPIB_EN_SHIFT 8 +#define MCDE_CTRL_DBIC0_EN_MASK MASK_BIT7 +#define MCDE_CTRL_DBIC0_EN_SHIFT 7 +#define MCDE_CTRL_DBIC1_EN_MASK MASK_BIT6 +#define MCDE_CTRL_DBIC1_EN_SHIFT 6 +#define MCDE_DSIVID0_EN_MASK MASK_BIT5 +#define MCDE_DSIVID1_EN_MASK MASK_BIT4 +#define MCDE_DSIVID2_EN_MASK MASK_BIT3 +#define MCDE_DSICMD0_EN_MASK MASK_BIT2 +#define MCDE_DSICMD1_EN_MASK MASK_BIT1 +#define MCDE_DSICMD2_EN_MASK MASK_BIT0 +#define MCDE_DSIVID0_EN_SHIFT 5 +#define MCDE_DSIVID1_EN_SHIFT 4 +#define MCDE_DSIVID2_EN_SHIFT 3 +#define MCDE_DSICMD0_EN_SHIFT 2 +#define MCDE_DSICMD1_EN_SHIFT 1 +#define MCDE_SYNCMUX_MASK 0xFF +#define MCDE_TVA_DPIC0_LCDB_MASK 0x06 +#define MCDE_TVB_DPIC1_LCDA_MASK 0xD4 +#define MCDE_DPIC1_LCDA_MASK 0xF8 +#define MCDE_DPIC0_LCDB_MASK 0x07 +#define MCDE_LCDA_LCDB_MASK 0x00 +#define MCDE_DSI_MASK 0x01 +#define MCDE_OVR_ALPHAPMEN_SHIFT 6 +#define MCDE_OVR_CLIPEN_SHIFT 7 + +#define MCDE_CFG_OUTMUX4_MASK (MASK_BIT28 | MASK_BIT29 | MASK_BIT30) +#define MCDE_CFG_OUTMUX3_MASK (MASK_BIT25 | MASK_BIT26 | MASK_BIT27) +#define MCDE_CFG_OUTMUX2_MASK (MASK_BIT22 | MASK_BIT23 | MASK_BIT24) +#define MCDE_CFG_OUTMUX1_MASK (MASK_BIT19 | MASK_BIT20 | MASK_BIT21) +#define MCDE_CFG_OUTMUX0_MASK (MASK_BIT16 | MASK_BIT17 | MASK_BIT18) +#define MCDE_CFG_IFIFOCTRLWTRMRKLVL_MASK (MASK_BIT12 | MASK_BIT13 | MASK_BIT14) +#define MCDE_CFG_FSYNCTRLB_MASK MASK_BIT11 +#define MCDE_CFG_FSYNCTRLA_MASK MASK_BIT10 +#define MCDE_CFG_SWAP_B_C1_MASK MASK_BIT9 +#define MCDE_CFG_SWAP_A_C0_MASK MASK_BIT8 +#define MCDE_CFG_SYNCMUX7_MASK MASK_BIT7 +#define MCDE_CFG_SYNCMUX6_MASK MASK_BIT6 +#define MCDE_CFG_SYNCMUX5_MASK MASK_BIT5 +#define MCDE_CFG_SYNCMUX4_MASK MASK_BIT4 +#define MCDE_CFG_SYNCMUX3_MASK MASK_BIT3 +#define MCDE_CFG_SYNCMUX2_MASK MASK_BIT2 +#define MCDE_CFG_SYNCMUX1_MASK MASK_BIT1 +#define MCDE_CFG_SYNCMUX0_MASK MASK_BIT0 + +#define MCDE_CFG_OUTMUX4_SHIFT 28 +#define MCDE_CFG_OUTMUX3_SHIFT 25 +#define MCDE_CFG_OUTMUX2_SHIFT 22 +#define MCDE_CFG_OUTMUX1_SHIFT 19 +#define MCDE_CFG_OUTMUX0_SHIFT 16 +#define MCDE_CFG_IFIFOCTRLWTRMRKLVL_SHIFT 12 +#define MCDE_CFG_FSYNCTRLB_SHIFT 11 +#define MCDE_CFG_FSYNCTRLA_SHIFT 10 +#define MCDE_CFG_SWAP_B_C1_SHIFT 9 +#define MCDE_CFG_SWAP_A_C0_SHIFT 8 +#define MCDE_CFG_SYNCMUX7_SHIFT 7 +#define MCDE_CFG_SYNCMUX6_SHIFT 6 +#define MCDE_CFG_SYNCMUX5_SHIFT 5 +#define MCDE_CFG_SYNCMUX4_SHIFT 4 +#define MCDE_CFG_SYNCMUX3_SHIFT 3 +#define MCDE_CFG_SYNCMUX2_SHIFT 2 +#define MCDE_CFG_SYNCMUX1_SHIFT 1 +#define MCDE_CFG_SYNCMUX0_SHIFT 0 + + +/******************************************************************* + MCDE External Source Register Fields +********************************************************************/ +#define MCDE_EXT_BUFFER_MASK /*(MASK_HALFWORD1 | MASK_BYTE1 | MASK_QUARTET1 | MASK_BIT3)*/0xFFFFFFFF +#define MCDE_EXT_PRI_OVR_MASK MASK_QUARTET1 +#define MCDE_EXT_BUFFER_NUM_MASK (MASK_BIT2 | MASK_BIT3) +#define MCDE_EXT_BUFFER_ID_MASK (MASK_BIT0 | MASK_BIT1) +#define MCDE_EXT_FORCEFSDIV_MASK MASK_BIT4 +#define MCDE_EXT_FSDISABLE_MASK MASK_BIT3 +#define MCDE_EXT_OVR_CTRL_MASK MASK_BIT2 +#define MCDE_EXT_BUF_MODE_MASK (MASK_BIT0 | MASK_BIT1) +#define MCDE_EXT_BEPO_MASK MASK_BIT14 +#define MCDE_EXT_BEBO_MASK MASK_BIT13 +#define MCDE_EXT_BGR_MASK MASK_BIT12 +#define MCDE_EXT_BPP_MASK (MASK_BIT11 | MASK_BIT10 | MASK_BIT9 | MASK_BIT8) + + +#define MCDE_EXT_BUFFER_SHIFT 0 +#define MCDE_EXT_PRI_OVR_SHIFT SHIFT_QUARTET1 +#define MCDE_EXT_BUFFER_NUM_SHIFT 2 +#define MCDE_EXT_OVR_CTRL_SHIFT 2 +#define MCDE_EXT_FORCEFSDIV_SHIFT 4 +#define MCDE_EXT_FSDISABLE_SHIFT 3 +#define MCDE_EXT_BEPO_SHIFT 14 +#define MCDE_EXT_BEBO_SHIFT 13 +#define MCDE_EXT_BGR_SHIFT 12 +#define MCDE_EXT_BPP_SHIFT 8 +/******************************************************************* + MCDE Overlay Register Fields +********************************************************************/ +#define MCDE_OVR_OVLEN_MASK MASK_BIT0 +#define MCDE_OVR_COLCTRL_MASK (MASK_BIT1 | MASK_BIT2) +#define MCDE_OVR_PALCTRL_MASK (MASK_BIT3 | MASK_BIT4) +#define MCDE_OVR_CKEYEN_MASK (MASK_BIT5) +#define MCDE_OVR_STBPRIO_MASK MASK_QUARTET4 +#define MCDE_OVR_BURSTSZ_MASK MASK_QUARTET5 +#define MCDE_OVR_MAXREQ_MASK MASK_QUARTET6 +#define MCDE_OVR_ROTBURSTSIZE_MASK MASK_QUARTET7 +#define MCDE_OVR_BLEND_MASK MASK_BIT0 +#define MCDE_OVR_OPQ_MASK MASK_BIT9 +#define MCDE_OVR_INTERMDE_MASK MASK_BIT29 +#define MCDE_OVR_INTERON_MASK MASK_BIT28 +#define MCDE_OVR_ALPHAPMEN_MASK MASK_BIT6 +#define MCDE_OVR_CLIPEN_MASK MASK_BIT7 +#define MCDE_OVR_LPF_MASK (MASK_BYTE2 | MASK_BIT24 |MASK_BIT25 | MASK_BIT26) +#define MCDE_OVR_PPL_MASK (MASK_BYTE0 | MASK_BIT8 |MASK_BIT9 |MASK_BIT10) +#define MCDE_ALPHAVALUE_MASK (MASK_BYTE0 << 1) +/**#define MCDE_EXT_SRCID_MASK (MASK_BIT9 | MASK_BIT8 | MASK_BIT7 | MASK_BIT6)*/ +#define MCDE_EXT_SRCID_MASK (MASK_BIT14 | MASK_BIT13 | MASK_BIT12 | MASK_BIT11) +#define MCDE_PIXOFF_MASK (MASK_BIT10 | MASK_BIT11 |MASK_QUARTET3) +#define MCDE_OVR_ZLEVEL_MASK (MASK_BIT30 | MASK_BIT27 | MASK_BIT28 | MASK_BIT29) +#define MCDE_OVR_YPOS_MASK (MASK_BYTE2 | MASK_BIT24 | MASK_BIT25 | MASK_BIT26) +#define MCDE_OVR_CHID_MASK (MASK_BIT14 | MASK_BIT13 | MASK_BIT12 | MASK_BIT11) +#define MCDE_OVR_XPOS_MASK (MASK_BYTE0 | MASK_BIT8 |MASK_BIT9 |MASK_BIT10) +#define MCDE_OVR_READ_MASK MASK_BIT9 +#define MCDE_OVR_FETCH_MASK MASK_BIT8 +#define MCDE_OVR_BLOCKED_MASK MASK_BIT10 +//#define MCDE_OVR_READ_MASK MASK_BIT1 +//#define MCDE_OVR_FETCH_MASK MASK_BIT0 +#define MCDE_WATERMARK_MASK (MASK_BYTE2 | MASK_QUARTET6 | MASK_BIT28) +#define MCDE_LINEINCREMENT_MASK 0xFFFFFFFF +#define MCDE_YCLIP_MASK 0xFFFFFFFF +#define MCDE_XCLIP_MASK 0xFFFFFFFF +#define MCDE_XBRCOOR_MASK 0x7FF +#define MCDE_YBRCOOR_MASK 0x07FF0000 + +#define MCDE_OVR_COLCTRL_SHIFT 1 +#define MCDE_OVR_PALCTRL_SHIFT 3 +#define MCDE_OVR_CKEYEN_SHIFT 5 +#define MCDE_OVR_STBPRIO_SHIFT SHIFT_QUARTET4 +#define MCDE_OVR_BURSTSZ_SHIFT SHIFT_QUARTET5 +#define MCDE_OVR_MAXREQ_SHIFT SHIFT_QUARTET6 +#define MCDE_OVR_ROTBURSTSIZE_SHIFT SHIFT_QUARTET7 +#define MCDE_OVR_OPQ_SHIFT 9 +#define MCDE_OVR_INTERMDE_SHIFT 29 +#define MCDE_OVR_INTERON_SHIFT 28 +#define MCDE_OVR_LPF_SHIFT SHIFT_HALFWORD1 +#define MCDE_ALPHAVALUE_SHIFT 1 +//#define MCDE_EXT_SRCID_SHIFT 6 +#define MCDE_EXT_SRCID_SHIFT 11 +#define MCDE_OVR_ZLEVEL_SHIFT 27 +#define MCDE_OVR_YPOS_SHIFT SHIFT_HALFWORD1 +#define MCDE_OVR_CHID_SHIFT 11 +#define MCDE_OVR_READ_SHIFT 1 +#define MCDE_WATERMARK_SHIFT SHIFT_HALFWORD1 +#define MCDE_PIXOFF_SHIFT 10 +#define MCDE_LINEINCREMENT_SHIFT 0 +#define MCDE_YCLIP_SHIFT 0 +#define MCDE_XCLIP_SHIFT 0 +#define MCDE_YBRCOOR_SHIFT 16 + +/******************************************************************* + MCDE Channel Configuration Register Fields +********************************************************************/ +#define MCDE_INITDELAY_MASK MASK_HALFWORD1 +#define MCDE_PPDELAY_MASK MASK_HALFWORD0 +#define MCDE_SWINTVCNT_MASK (MASK_BYTE3 | MASK_QUARTET5 | MASK_BIT18 |MASK_BIT19) +#define MCDE_SWINTVEVENT_MASK (MASK_BIT16 | MASK_BIT17) +#define MCDE_HWREQVCNT_MASK (MASK_BYTE1 | MASK_QUARTET1 | MASK_BIT3 | MASK_BIT2) +#define MCDE_HWREQVEVENT_MASK (MASK_BIT0 | MASK_BIT1) +#define MCDE_OUTINTERFACE_MASK (MASK_BIT4 | MASK_BIT3 |MASK_BIT2) +#define MCDE_SRCSYNCH_MASK (MASK_BIT0 | MASK_BIT1) +#define MCDE_SW_TRIG_MASK MASK_BIT0 +#define MCDE_REDCOLOR_MASK MASK_BYTE2 +#define MCDE_GREENCOLOR_MASK MASK_BYTE1 +#define MCDE_BLUECOLOR_MASK MASK_BYTE0 +#define MCDE_CHPRIORITY_MASK MASK_QUARTET0 +#define MCDE_CHXLPF_MASK (0x03FF0000) +#define MCDE_CHXPPL_MASK (MASK_BYTE0 | MASK_BIT8 |MASK_BIT9 |MASK_BIT10) +#define MCDE_CHX_ABORT_MASK MASK_BIT1 +#define MCDE_CHX_READ_MASK MASK_BIT0 + +#define MCDE_INITDELAY_SHIFT SHIFT_HALFWORD1 +#define MCDE_SWINTVCNT_SHIFT 18 +#define MCDE_SWINTVEVENT_SHIFT SHIFT_HALFWORD1 +#define MCDE_HWREQVCNT_SHIFT 2 +#define MCDE_OUTINTERFACE_SHIFT 2 +#define MCDE_REDCOLOR_SHIFT SHIFT_HALFWORD1 +#define MCDE_GREENCOLOR_SHIFT SHIFT_BYTE1 +#define MCDE_CHPRIORITY_SHIFT SHIFT_QUARTET7 +#define MCDE_CHXLPF_SHIFT 16 +#define MCDE_CHX_ABORT_SHIFT 1 + +/******************************************************************* + MCDE Channel A/B Register Fields +********************************************************************/ +#define MCDE_CHX_BURSTSIZE_MASK (MASK_QUARTET6 & 0x07000000) +#define MCDE_CHX_ALPHA_MASK (MASK_BYTE2) +#define MCDE_CHX_ROTDIR_MASK (MASK_BIT15) +#define MCDE_CHX_GAMAEN_MASK (MASK_BIT14) +#define MCDE_FLICKFORMAT_MASK (MASK_BIT13) +#define MCDE_FLICKMODE_MASK (MASK_BIT11 | MASK_BIT12) +#define MCDE_BLENDCONTROL_MASK (MASK_BIT10) +#define MCDE_KEYCTRL_MASK (MASK_BIT7|MASK_BIT8|MASK_BIT9) +#define MCDE_ROTEN_MASK (MASK_BIT6) +#define MCDE_DITHEN_MASK (MASK_BIT5) +#define MCDE_CEAEN_MASK (MASK_BIT4) +#define MCDE_AFLICKEN_MASK (MASK_BIT3) +#define MCDE_BLENDEN_MASK (MASK_BIT2) +#define MCDE_CLK_MASK (MASK_BIT30) +#define MCDE_BCD_MASK (MASK_BIT29) +#define MCDE_OUTBPP_MASK (MASK_BIT25 |MASK_BIT26 | MASK_BIT27 | MASK_BIT28) +#define MCDE_CDWIN_MASK (MASK_BIT13 | MASK_BIT14 | MASK_BIT15) +#define MCDE_CLOCKSEL_MASK (MASK_BIT12 | MASK_BIT11 | MASK_BIT10) +#define MCDE_PCD_MASK (MASK_BYTE0 | MASK_BIT8 | MASK_BIT9) +#define MCDE_KEYA_MASK (MASK_BYTE3) +#define MCDE_KEYR_MASK (MASK_BYTE2) +#define MCDE_KEYG_MASK (MASK_BYTE1) +#define MCDE_KEYB_MASK (MASK_BYTE0) +#define MCDE_RGB_MASK1 (MASK_BYTE2 | MASK_BIT24 | MASK_BIT25) +#define MCDE_RGB_MASK2 (MASK_BYTE0 | MASK_BIT8 | MASK_BIT9) +#define MCDE_THRESHOLD_MASK (MASK_QUARTET6) +#define MCDE_COEFFN3_MASK (MASK_BYTE2) +#define MCDE_COEFFN2_MASK (MASK_BYTE1) +#define MCDE_COEFFN1_MASK (MASK_BYTE0) +#define MCDE_TV_LINES_MASK (MASK_BYTE2 | MASK_BIT24 | MASK_BIT25 | MASK_BIT26) +#define MCDE_TVMODE_MASK (MASK_BIT3 | MASK_BIT4) +#define MCDE_IFIELD_MASK (MASK_BIT2) +#define MCDE_INTEREN_MASK (MASK_BIT1) +#define MCDE_SELMODE_MASK (MASK_BIT0) +#define MCDE_BSL_MASK (MASK_BYTE2 | MASK_BIT24 | MASK_BIT25 | MASK_BIT26) +#define MCDE_BEL_MASK (MASK_BYTE0 | MASK_BIT8 | MASK_BIT9 | MASK_BIT10) +#define MCDE_FSL2_MASK (MASK_BYTE2 | MASK_BIT24 | MASK_BIT25 | MASK_BIT26) +#define MCDE_FSL1_MASK (MASK_BYTE0 | MASK_BIT8 | MASK_BIT9 | MASK_BIT10) +#define MCDE_DVO2_MASK (MASK_BYTE2 | MASK_BIT24 | MASK_BIT25 | MASK_BIT26) +#define MCDE_DVO1_MASK (MASK_BYTE0 | MASK_BIT8 | MASK_BIT9 | MASK_BIT10) +#define MCDE_SWH2_MASK (MASK_BYTE2 | MASK_BIT24 | MASK_BIT25 | MASK_BIT26) +#define MCDE_SWH1_MASK (MASK_BYTE0 | MASK_BIT8 | MASK_BIT9 | MASK_BIT10) +#define MCDE_SWW_MASK (MASK_BYTE2 | MASK_BIT24 | MASK_BIT25 | MASK_BIT26) +#define MCDE_DHO_MASK (MASK_BYTE0 | MASK_BIT8 | MASK_BIT9 | MASK_BIT10) +#define MCDE_ALW_MASK (MASK_BYTE2 | MASK_BIT24 | MASK_BIT25 | MASK_BIT26) +#define MCDE_LBW_MASK (MASK_BYTE0 | MASK_BIT8 | MASK_BIT9 | MASK_BIT10) +#define MCDE_TVBCR_MASK MASK_BYTE2 +#define MCDE_TVBCB_MASK MASK_BYTE1 +#define MCDE_TVBLU_MASK MASK_BYTE0 +#define MCDE_REVVAEN_MASK MASK_BIT31 +#define MCDE_REVTGEN_MASK MASK_BIT30 +#define MCDE_REVLOADSEL_MASK (MASK_BIT28 | MASK_BIT29) +#define MCDE_REVDEL1_MASK (MASK_QUARTET6) +#define MCDE_REVDEL0_MASK (MASK_BYTE2) +#define MCDE_PSVAEN_MASK (MASK_BIT15) +#define MCDE_PSTGEN_MASK (MASK_BIT14) +#define MCDE_PSLOADSEL_MASK (MASK_BIT12 | MASK_BIT13) +#define MCDE_PSDEL1_MASK (MASK_QUARTET2) +#define MCDE_PSDEL0_MASK (MASK_BYTE0) +#define MCDE_IOE_MASK (MASK_BIT23) +#define MCDE_IPC_MASK (MASK_BIT22) +#define MCDE_IHS_MASK (MASK_BIT21) +#define MCDE_IVS_MASK (MASK_BIT20) +#define MCDE_IVP_MASK (MASK_BIT19) +#define MCDE_ICLSPL_MASK (MASK_BIT18) +#define MCDE_ICLREV_MASK (MASK_BIT17) +#define MCDE_ICLSP_MASK (MASK_BIT16) +#define MCDE_SPLVAEN_MASK (MASK_BIT15) +#define MCDE_SPLTGEN_MASK (MASK_BIT14) +#define MCDE_SPLLOADSEL_MASK (MASK_BIT12 | MASK_BIT13) +#define MCDE_SPLDEL1_MASK (MASK_QUARTET2) +#define MCDE_SPLDEL0_MASK (MASK_BYTE0) +#define MCDE_FOFFY_MASK (MASK_BIT14 | MASK_BIT13 | MASK_BIT12 | MASK_BIT11 | MASK_BIT10) +#define MCDE_FOFFX_MASK (MASK_BIT5 | MASK_BIT6 | MASK_BIT7 | MASK_BIT8 | MASK_BIT9) +#define MCDE_MASK_BITCTRL_MASK (MASK_BIT4) +#define MCDE_MODE_MASK (MASK_BIT2 | MASK_BIT3) +#define MCDE_COMP_MASK (MASK_BIT1) +#define MCDE_TEMP_MASK (MASK_BIT0) +#define MCDE_YB_MASK (MASK_BIT28 | MASK_BIT27 | MASK_BIT26 | MASK_BIT25 | MASK_BIT24) +#define MCDE_XB_MASK (MASK_BIT20 | MASK_BIT19 | MASK_BIT18 | MASK_BIT17 | MASK_BIT16) +#define MCDE_YG_MASK (MASK_BIT12 | MASK_BIT11 | MASK_BIT10 | MASK_BIT9 | MASK_BIT8 | MASK_BIT7 | MASK_BIT6 | MASK_BIT5) +#define MCDE_XG_MASK (MASK_BIT0 | MASK_BIT1 | MASK_BIT2 | MASK_BIT3 | MASK_BIT4) +#define MCDE_ARED_MASK (MASK_BYTE2 | MASK_BIT24 | MASK_BIT25) +#define MCDE_GREEN_MASK (MASK_BYTE1) +#define MCDE_BLUE_MASK (MASK_BYTE0) +#define MCDE_RED_MASK (MASK_BYTE2) + +#define MCDE_CHX_BURSTSIZE_SHIFT SHIFT_QUARTET6 +#define MCDE_CHX_ALPHA_SHIFT SHIFT_HALFWORD1 +#define MCDE_CHX_ROTDIR_SHIFT 15 +#define MCDE_CHX_GAMAEN_SHIFT 14 +#define MCDE_FLICKFORMAT_SHIFT 13 +#define MCDE_FLICKMODE_SHIFT 11 +#define MCDE_BLENDCONTROL_SHIFT 10 +#define MCDE_KEYCTRL_SHIFT 7 +#define MCDE_ROTEN_SHIFT 6 +#define MCDE_DITHEN_SHIFT 5 +#define MCDE_CEAEN_SHIFT 4 +#define MCDE_AFLICKEN_SHIFT 3 +#define MCDE_BLENDEN_SHIFT 2 +#define MCDE_CLK_SHIFT 30 +#define MCDE_BCD_SHIFT 29 +#define MCDE_OUTBPP_SHIFT 25 +#define MCDE_CDWIN_SHIFT 13 +#define MCDE_CLOCKSEL_SHIFT 10 +#define MCDE_KEYA_SHIFT SHIFT_BYTE3 +#define MCDE_KEYR_SHIFT SHIFT_BYTE2 +#define MCDE_KEYG_SHIFT SHIFT_BYTE1 +#define MCDE_RGB_SHIFT SHIFT_HALFWORD1 +#define MCDE_THRESHOLD_SHIFT SHIFT_QUARTET6 +#define MCDE_COEFFN3_SHIFT SHIFT_BYTE2 +#define MCDE_COEFFN2_SHIFT SHIFT_BYTE1 +#define MCDE_COEFFN1_SHIFT (SHIFT_BYTE0) +#define MCDE_TV_LINES_SHIFT SHIFT_HALFWORD1 +#define MCDE_TVMODE_SHIFT 3 +#define MCDE_IFIELD_SHIFT 2 +#define MCDE_INTEREN_SHIFT 1 +#define MCDE_BSL_SHIFT 16 +#define MCDE_FSL2_SHIFT 16 +#define MCDE_DVO2_SHIFT 16 +#define MCDE_SWW_SHIFT 16 +#define MCDE_ALW_SHIFT 16 +#define MCDE_TVBCR_SHIFT SHIFT_BYTE2 +#define MCDE_TVBCB_SHIFT SHIFT_BYTE1 +#define MCDE_REVVAEN_SHIFT 31 +#define MCDE_REVTGEN_SHIFT 30 +#define MCDE_REVLOADSEL_SHIFT 28 +#define MCDE_REVDEL1_SHIFT SHIFT_QUARTET6 +#define MCDE_REVDEL0_SHIFT SHIFT_HALFWORD1 +#define MCDE_PSVAEN_SHIFT 15 +#define MCDE_PSTGEN_SHIFT 14 +#define MCDE_PSLOADSEL_SHIFT 12 +#define MCDE_PSDEL1_SHIFT 8 +#define MCDE_IOE_SHIFT 23 +#define MCDE_IPC_SHIFT 22 +#define MCDE_IHS_SHIFT 21 +#define MCDE_IVS_SHIFT 20 +#define MCDE_IVP_SHIFT 19 +#define MCDE_ICLSPL_SHIFT 18 +#define MCDE_ICLREV_SHIFT 17 +#define MCDE_ICLSP_SHIFT 16 +#define MCDE_SPLVAEN_SHIFT 15 +#define MCDE_SPLTGEN_SHIFT 14 +#define MCDE_SPLLOADSEL_SHIFT 12 +#define MCDE_SPLDEL1_SHIFT 8 +#define MCDE_FOFFY_SHIFT 10 +#define MCDE_FOFFX_SHIFT 5 +#define MCDE_MASK_BITCTRL_SHIFT 4 +#define MCDE_MODE_SHIFT 2 +#define MCDE_COMP_SHIFT 1 +#define MCDE_YB_SHIFT 24 +#define MCDE_XB_SHIFT SHIFT_HALFWORD1 +#define MCDE_YG_SHIFT 5 +#define MCDE_ARED_SHIFT SHIFT_HALFWORD1 +#define MCDE_GREEN_SHIFT SHIFT_BYTE1 +/******************************************************************* + MCDE Channel C Register Fields +********************************************************************/ +#define MCDE_SYNCCTRL_MASK (MASK_BIT30 | MASK_BIT29) +#define MCDE_RESEN_MASK (MASK_BIT18) +#define MCDE_CLKSEL_MASK (MASK_BIT14 | MASK_BIT13) +#define MCDE_SYNCSEL_MASK MASK_BIT6 +#define MCDE_RES2_MASK MASK_BIT28 +#define MCDE_RES1_MASK MASK_BIT27 +#define MCDE_RD2_MASK MASK_BIT26 +#define MCDE_RD1_MASK MASK_BIT25 +#define MCDE_WR2_MASK MASK_BIT24 +#define MCDE_WR1_MASK MASK_BIT23 +#define MCDE_CD2_MASK MASK_BIT22 +#define MCDE_CD1_MASK MASK_BIT21 +#define MCDE_CS2_MASK MASK_BIT20 +#define MCDE_CS1_MASK MASK_BIT19 +#define MCDE_CS2EN_MASK MASK_BIT17 +#define MCDE_CS1EN_MASK MASK_BIT16 +#define MCDE_INBAND2_MASK MASK_BIT12 +#define MCDE_INBAND1_MASK MASK_BIT11 +#define MCDE_BUSSIZE2_MASK MASK_BIT10 +#define MCDE_BUSSIZE1_MASK MASK_BIT9 +#define MCDE_SYNCEN2_MASK MASK_BIT8 +#define MCDE_SYNCEN1_MASK MASK_BIT7 +#define MCDE_WMLVL2_MASK MASK_BIT5 +#define MCDE_WMLVL1_MASK MASK_BIT4 +#define MCDE_C2EN_MASK MASK_BIT3 +#define MCDE_C1EN_MASK MASK_BIT2 +#define MCDE_POWEREN_MASK MASK_BIT1 +#define MCDE_FLOEN_MASK MASK_BIT0 +#define MCDE_PDCTRL_MASK (MASK_BIT10 |MASK_BIT11 | MASK_BIT12) +#define MCDE_DUPLEXER_MASK (MASK_BIT7 |MASK_BIT8 | MASK_BIT9) +#define MCDE_BSDM_MASK (MASK_BIT6 | MASK_BIT5 | MASK_BIT4) +#define MCDE_BSCM_MASK (MASK_BIT2 | MASK_BIT1 | MASK_BIT0) +#define MCDE_VSDBL_MASK (MASK_BIT29 | MASK_BIT30 | MASK_BIT31) +#define MCDE_VSSEL_MASK MASK_BIT28 +#define MCDE_VSPOL_MASK MASK_BIT27 +#define MCDE_VSPDIV_MASK (MASK_BIT24 | MASK_BIT25 | MASK_BIT26) +#define MCDE_VSPMAX_MASK (MASK_BYTE2 | MASK_QUARTET3) +#define MCDE_VSPMIN_MASK (MASK_BYTE0 | MASK_QUARTET2) +#define MCDE_TRDELC_MASK (MASK_BYTE2 | MASK_QUARTET6) +#define MCDE_SYNCDELC1_MASK (MASK_BYTE1) +#define MCDE_SYNCDELC0_MASK (MASK_BYTE0) +#define MCDE_VSTAC1_MASK MASK_BIT1 +#define MCDE_VSTAC0_MASK MASK_BIT0 +#define MCDE_BCN_MASK MASK_BYTE0 +#define MCDE_CSCDDEACT_MASK MASK_BYTE1 +#define MCDE_CSCDACT_MASK MASK_BYTE0 +#define MCDE_MOTINT_MASK MASK_BIT16 +#define MCDE_RWDEACT_MASK MASK_BYTE1 +#define MCDE_RWACT_MASK MASK_BYTE0 +#define MCDE_DODEACT_MASK MASK_BYTE1 +#define MCDE_DOACT_MASK MASK_BYTE0 +#define MCDE_READDATA_MASK MASK_HALFWORD0 +#define MCDE_DATACOMMANDMASK 0x01FFFFFF + +#define MCDE_SYNCCTRL_SHIFT 29 +#define MCDE_RESEN_SHIFT 18 +#define MCDE_CLKSEL_SHIFT 13 +#define MCDE_SYNCSEL_SHIFT 6 +#define MCDE_RES2_SHIFT 28 +#define MCDE_RES1_SHIFT 27 +#define MCDE_RD2_SHIFT 26 +#define MCDE_RD1_SHIFT 25 +#define MCDE_WR2_SHIFT 24 +#define MCDE_WR1_SHIFT 23 +#define MCDE_CD2_SHIFT 22 +#define MCDE_CD1_SHIFT 21 +#define MCDE_CS2_SHIFT 20 +#define MCDE_CS1_SHIFT 19 +#define MCDE_CS2EN_SHIFT 17 +#define MCDE_CS1EN_SHIFT 16 +#define MCDE_INBAND2_SHIFT 12 +#define MCDE_INBAND1_SHIFT 11 +#define MCDE_BUSSIZE2_SHIFT 10 +#define MCDE_BUSSIZE1_SHIFT 9 +#define MCDE_SYNCEN2_SHIFT 8 +#define MCDE_SYNCEN1_SHIFT 7 +#define MCDE_WMLVL2_SHIFT 5 +#define MCDE_WMLVL1_SHIFT 4 +#define MCDE_C2EN_SHIFT 3 +#define MCDE_C1EN_SHIFT 2 +#define MCDE_POWEREN_SHIFT 1 +#define MCDE_PDCTRL_SHIFT 12 +#define MCDE_DUPLEXER_SHIFT 7 +#define MCDE_BSDM_SHIFT 4 +#define MCDE_VSDBL_SHIFT 29 +#define MCDE_VSSEL_SHIFT 28 +#define MCDE_VSPOL_SHIFT 27 +#define MCDE_VSPDIV_SHIFT 24 +#define MCDE_VSPMAX_SHIFT 12 +#define MCDE_TRDELC_SHIFT SHIFT_HALFWORD1 +#define MCDE_SYNCDELC1_SHIFT SHIFT_BYTE1 +#define MCDE_VSTAC1_SHIFT 1 +#define MCDE_CSCDDEACT_SHIFT SHIFT_BYTE1 +#define MCDE_MOTINT_SHIFT SHIFT_HALFWORD1 +#define MCDE_RWDEACT_SHIFT 8 +#define MCDE_DODEACT_SHIFT SHIFT_BYTE1 + +/******************************************************************* + MCDE DSI Register Fields +********************************************************************/ +#define MCDE_PLLOUT_DIVSEL1_MASK (MASK_BIT22 | MASK_BIT23) +#define MCDE_PLLOUT_DIVSEL0_MASK (MASK_BIT20 | MASK_BIT21) +#define MCDE_PLL4IN_SEL_MASK (MASK_BIT16 | MASK_BIT17) +#define MCDE_TXESCDIV_SEL_MASK MASK_BIT8 +#define MCDE_TXESCDIV_MASK 0xFF +#define MCDE_CMDBYTE_LSB_MASK 0xFF +#define MCDE_CMDBYTE_MSB_MASK 0xFF00 +#define MCDE_DSI_SW_MASK 0xFFF0000 +#define MCDE_DSI_DMA_MASK 0xFFF +#define MCDE_DSI_PACK_MASK (MASK_BIT20 | MASK_BIT21 | MASK_BIT22) +#define MCDE_DSI_DCSVID_MASK MASK_BIT18 +#define MCDE_DSI_BYTE_SWAP_MASK MASK_BIT17 +#define MCDE_DSI_BIT_SWAP_MASK MASK_BIT16 +#define MCDE_DSI_CMD8_MASK MASK_BIT13 +#define MCDE_DSI_VID_MODE_MASK MASK_BIT12 +#define MCDE_BLANKING_MASK MASK_QUARTET0 +#define MCDE_DSI_FRAME_MASK (MASK_HALFWORD0 | MASK_BYTE2) +#define MCDE_DSI_PACKET_MASK MASK_HALFWORD0 + +#define MCDE_PLLOUT_DIVSEL1_SHIFT 22 +#define MCDE_PLLOUT_DIVSEL0_SHIFT 20 +#define MCDE_PLL4IN_SEL_SHIFT 16 +#define MCDE_TXESCDIV_SEL_SHIFT 8 +#define MCDE_CMDBYTE_MSB_SHIFT 8 +#define MCDE_DSI_SW_SHIFT 16 +#define MCDE_DSI_PACK_SHIFT 20 +#define MCDE_DSI_DCSVID_SHIFT 18 +#define MCDE_DSI_BYTE_SWAP_SHIFT 17 +#define MCDE_DSI_BIT_SWAP_SHIFT 16 +#define MCDE_DSI_CMD8_SHIFT 13 +#define MCDE_DSI_VID_MODE_SHIFT 12 + +/******************************************************************* + Register Structure +********************************************************************/ + +#ifdef CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT + +struct mcde_ext_src_reg +{ + volatile u32 mcde_extsrc_a0; + volatile u32 mcde_extsrc_a1; + volatile u32 mcde_extsrc_a2; + volatile u32 mcde_extsrc_conf; + volatile u32 mcde_extsrc_cr; + volatile u32 mcde_unused1[3]; +}; + +struct mcde_ovl_reg +{ + volatile u32 mcde_ovl_cr; + volatile u32 mcde_ovl_conf; + volatile u32 mcde_ovl_conf2; + volatile u32 mcde_ovl_ljinc; + volatile u32 mcde_ovl_crop; + volatile u32 mcde_ovl_comp; + volatile u32 mcde_unused1[2]; +}; + +struct mcde_chnl_conf_reg +{ + volatile u32 mcde_chnl_conf; + volatile u32 mcde_chnl_stat; + volatile u32 mcde_chnl_synchmod; + volatile u32 mcde_chnl_synchsw; + volatile u32 mcde_chnl_bckgndcol; + volatile u32 mcde_chnl_prio; + volatile u32 mcde_unused[2]; +}; + +struct mcde_chAB_reg +{ + volatile u32 mcde_cr0; + volatile u32 mcde_cr1; + volatile u32 mcde_colkey; + volatile u32 mcde_fcolkey; + volatile u32 mcde_rgbconv1; + volatile u32 mcde_rgbconv2; + volatile u32 mcde_rgbconv3; + volatile u32 mcde_rgbconv4; + volatile u32 mcde_rgbconv5; + volatile u32 mcde_rgbconv6; + volatile u32 mcde_ffcoef0; + volatile u32 mcde_ffcoef1; + volatile u32 mcde_ffcoef2; + volatile u32 mcde_unused1[1]; + volatile u32 mcde_tvcr; + volatile u32 mcde_tvbl1; + volatile u32 mcde_tvisl; + volatile u32 mcde_tvdvo; + volatile u32 mcde_unused2[1]; + volatile u32 mcde_tvtim1; + volatile u32 mcde_tvlbalw; + volatile u32 mcde_tvbl2; + volatile u32 mcde_tvblu; + volatile u32 mcde_lcdtim0; + volatile u32 mcde_lcdtim1; + volatile u32 mcde_ditctrl; + volatile u32 mcde_ditoff; + volatile u32 mcde_pal0; + volatile u32 mcde_pal1; + volatile u32 mcde_rotadd0; + volatile u32 mcde_rotadd1; + volatile u32 mcde_rot_conf; + volatile u32 mcde_synchconf; + volatile u32 mcde_unused3[1]; + volatile u32 mcde_gam0; + volatile u32 mcde_gam1; + volatile u32 mcde_gam2; + volatile u32 mcde_oledconv1; + volatile u32 mcde_oledconv2; + volatile u32 mcde_oledconv3; + volatile u32 mcde_oledconv4; + volatile u32 mcde_oledconv5; + volatile u32 mcde_oledconv6; + volatile u32 mcde_unused4[85]; +}; + +struct mcde_chC0C1_reg +{ + volatile u32 mcde_crc; + volatile u32 mcde_pbccrc[2]; + volatile u32 mcde_pbcbmrc0[5]; + volatile u32 mcde_pbcbmrc1[5]; + volatile u32 mcde_pbcbcrc0[2]; + volatile u32 mcde_unused1[3]; + volatile u32 mcde_pbcbcrc1[2]; + volatile u32 mcde_unused2[3]; + volatile u32 mcde_vscrc[2]; + volatile u32 mcde_sctrc; + volatile u32 mcde_scsrc; + volatile u32 mcde_bcnr[2]; + volatile u32 mcde_cscdtr[2]; + volatile u32 mcde_rdwrtr[2]; + volatile u32 mcde_dotr[2]; + volatile u32 mcde_wcmdc[2]; + volatile u32 mcde_wdatadc[2]; + volatile u32 mcde_rdatadc[2]; + volatile u32 mcde_statc; + volatile u32 mcde_ctrlc[2]; +}; + +struct mcde_dsi_reg +{ + volatile u32 mcde_dsi_conf0; + volatile u32 mcde_dsi_frame; + volatile u32 mcde_dsi_pkt; + volatile u32 mcde_dsi_sync; + volatile u32 mcde_dsi_cmdw; + volatile u32 mcde_dsi_delay0; + volatile u32 mcde_dsi_delay1; + volatile u32 mcde_unused1[1]; +}; + +struct mcde_top_reg +{ + volatile u32 mcde_cr; + volatile u32 mcde_conf0; + volatile u32 mcde_ssp; + volatile u32 mcde_reserved1[61]; + volatile u32 mcde_ais; + volatile u32 mcde_imscpp; + volatile u32 mcde_imscovl; + volatile u32 mcde_imscchnl; + volatile u32 mcde_imscerr; + volatile u32 mcde_rispp; + volatile u32 mcde_risovl; + volatile u32 mcde_rischnl; + volatile u32 mcde_riserr; + volatile u32 mcde_mispp; + volatile u32 mcde_misovl; + volatile u32 mcde_mischnl; + volatile u32 mcde_miserr; + volatile u32 mcde_sispp; + volatile u32 mcde_sisovl; + volatile u32 mcde_sischnl; + volatile u32 mcde_siserr; + volatile u32 mcde_reserved2[46]; + volatile u32 mcde_pid; +}; + +#else /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */ + +struct mcde_ext_src_reg +{ + volatile u32 mcde_extsrc_a0; + volatile u32 mcde_extsrc_a1; + volatile u32 mcde_extsrc_a2; + volatile u32 mcde_extsrc_conf; + volatile u32 mcde_extsrc_cr; + volatile u32 mcde_unused1[3]; +}; + +struct mcde_ovl_reg +{ + volatile u32 mcde_ovl_cr; + volatile u32 mcde_ovl_conf; + volatile u32 mcde_ovl_conf2; + volatile u32 mcde_ovl_ljinc; + volatile u32 mcde_ovl_crop; + volatile u32 mcde_ovl_top_left_clip; + volatile u32 mcde_ovl_bot_rht_clip; + volatile u32 mcde_ovl_comp; +}; + +struct mcde_ch_synch_reg +{ + volatile u32 mcde_ch_conf; + volatile u32 mcde_ch_stat; + volatile u32 mcde_chsyn_mod; + volatile u32 mcde_chsyn_sw; + volatile u32 mcde_chsyn_bck; + volatile u32 mcde_chsyn_prio; + volatile u32 mcde_unused3[2]; +}; + +struct mcde_ch_reg +{ + volatile u32 mcde_ch_cr0; + volatile u32 mcde_ch_cr1; + volatile u32 mcde_ch_colkey; + volatile u32 mcde_ch_fcolkey; + volatile u32 mcde_ch_rgbconv1; + volatile u32 mcde_ch_rgbconv2; + volatile u32 mcde_ch_rgbconv3; + volatile u32 mcde_ch_rgbconv4; + volatile u32 mcde_ch_rgbconv5; + volatile u32 mcde_ch_rgbconv6; + volatile u32 mcde_ch_ffcoef0; + volatile u32 mcde_ch_ffcoef1; + volatile u32 mcde_ch_ffcoef2; + volatile u32 unused; + volatile u32 mcde_ch_tvcr; + volatile u32 mcde_ch_tvbl1; + volatile u32 mcde_ch_tvisl; + volatile u32 mcde_ch_tvdvo; + volatile u32 mcde_ch_tvswh; + volatile u32 mcde_ch_tvtim1; + volatile u32 mcde_ch_tvbalw; + volatile u32 mcde_ch_tvbl2; + volatile u32 mcde_ch_tvblu; + volatile u32 mcde_ch_lcdtim0; + volatile u32 mcde_ch_lcdtim1; + volatile u32 mcde_ch_ditctrl; + volatile u32 mcde_ch_ditoff; + volatile u32 mcde_ch_pal; + volatile u32 mcde_ch_gam; + volatile u32 mcde_rotadd0; + volatile u32 mcde_rotadd1; + volatile u32 mcde_chsyn_con; + volatile u32 mcde_unused7[96]; +}; + +struct mcde_dsi_reg +{ + volatile u32 mcde_dsi_conf0; + volatile u32 mcde_dsi_frame; + volatile u32 mcde_dsi_pkt; + volatile u32 mcde_dsi_sync; + volatile u32 mcde_dsi_cmd; + volatile u32 mcde_reserved2[3]; +}; + +struct mcde_chc_reg +{ + volatile u32 mcde_chc_crc; + volatile u32 mcde_chc_pbcrc0; + volatile u32 mcde_chc_pbcrc1; + volatile u32 mcde_chc_pbcbmrc0[5]; + volatile u32 mcde_chc_pbcbmrc1[5]; + volatile u32 mcde_chc_pbcbcrc0[2]; + volatile u32 mcde_unused5[3]; + volatile u32 mcde_chc_pbcbcrc1[2]; + volatile u32 mcde_unused6[3]; + volatile u32 mcde_chc_vscrc[2]; + volatile u32 mcde_chc_sctrc; + volatile u32 mcde_chc_scsr; + volatile u32 mcde_chc_bcnr[2]; + volatile u32 mcde_chc_cscdtr[2]; + volatile u32 mcde_chc_rdwrtr[2]; + volatile u32 mcde_chc_dotr[2]; + volatile u32 mcde_chc_wcmd[2]; + volatile u32 mcde_chc_wd[2]; + volatile u32 mcde_chc_rdata[2]; +}; + +struct mcde_register_base +{ + volatile u32 mcde_cr; + volatile u32 mcde_cfg0; + volatile u32 mcde_reserved1[62]; + volatile u32 mcde_ais; + volatile u32 mcde_imsc; + volatile u32 mcde_ris; + volatile u32 mcde_mis; + volatile u32 mcde_sis; + volatile u32 mcde_ssi; + volatile u32 mcde_reserved2[57]; + volatile u32 mcde_pid; +}; + +#endif /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */ + +#endif diff --git a/arch/arm/mach-ux500/include/mach/memory.h b/arch/arm/mach-ux500/include/mach/memory.h new file mode 100755 index 00000000000..8a9d1324dec --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/memory.h @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2009 ST-Ericsson + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + +/* + * Physical DRAM offset. + */ +#define PHYS_OFFSET UL(0x00000000) +#define BUS_OFFSET UL(0x00000000) + +#define CONSISTENT_DMA_SIZE (32 << 20) + +#endif diff --git a/arch/arm/mach-ux500/include/mach/mmc.h b/arch/arm/mach-ux500/include/mach/mmc.h new file mode 100755 index 00000000000..3dd72603c7f --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/mmc.h @@ -0,0 +1,341 @@ +/* + * Overview: + * SD/EMMC driver for u8500 platform + * + * Copyright (C) 2009 ST Ericsson. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +/*------------------------------------------------------------------------- + * SDI controller configuration + * Kernel entry point for sdmmc/emmc chip + *------------------------------------------------------------------------- + * <VERSION>v1.0.0 + *------------------------------------------------------------------------- + */ +/*------------------------------i-----------------------------------------*/ + + +/* + * SDI Power register offset + */ +#define MMCIPOWER 0x000 +/* + * SDI Power register bits + */ +#define MCI_PWR_OFF 0x00 +#define MCI_PWR_UP 0x02 +#define MCI_PWR_ON 0x03 +#define MCI_STATE_ENABLE 0x38 +#define MCI_OPEN_DRAIN (1 << 6) +#define MCI_FBCLK_ENABLE (1 << 7) +#define MCI_POWER_IOS_MASK \ + (MCI_PWR_ON | MCI_DIREN_CMD | MCI_DIREN_DAT0 | MCI_DIREN_DAT2 | \ + MCI_DIREN_DAT31 | MCI_DIREN_DAT74 | MCI_OPEN_DRAIN) +#define MCI_DIREN_CMD (1<<3) +#define MCI_DIREN_DAT0 (1<<4) +#define MCI_DIREN_DAT2 (1<<2) +#define MCI_DIREN_DAT31 (1<<5) +#define MCI_DIREN_DAT74 (1<<8) +#define MCI_DIREN_1BIT (MCI_DIREN_CMD|MCI_DIREN_DAT0) +#define MCI_DIREN_4BIT (MCI_DIREN_CMD|MCI_DIREN_DAT0|MCI_DIREN_DAT31) +/* #define MCI_DIREN_8BIT (MCI_DIREN_CMD|MCI_DIREN_DAT0|MCI_DIREN_DAT31)*/ +#define MCI_DIREN_BIT (MCI_DIREN_CMD|MCI_DIREN_DAT0|MCI_DIREN_DAT31|\ + MCI_DIREN_DAT2|MCI_DIREN_DAT74) +/* + * SDI Clock register offset + */ +#define MMCICLOCK 0x004 +/* + * SDI Power register bits + */ +#define MCI_CLK_ENABLE (1 << 8) +#define MCI_CLK_PWRSAVE (1 << 9) +#define MCI_CLK_BYPASS (1 << 10) +#define MCI_BUS_WIDTH_1 (0 << 11) +#define MCI_BUS_WIDTH_4 (1 << 11) +#define MCI_BUS_WIDTH_8 (2 << 11) +#define MCI_HWFC_EN (1 << 14) +#define MCI_NEG_EDGE (1 << 13) +/* + * SDI Arguement register offset + */ +#define MMCIARGUMENT 0x008 +/* + * SDI Command register offset + */ +#define MMCICOMMAND 0x00c +/* + * SDI command register bits + */ +#define MCI_CPSM_RESPONSE (1 << 6) +#define MCI_CPSM_LONGRSP (1 << 7) +#define MCI_CPSM_INTERRUPT (1 << 8) +#define MCI_CPSM_PENDING (1 << 9) +#define MCI_CPSM_ENABLE (1 << 10) + +/* + * SDI RespCMD register offset + */ +#define MMCIRESPCMD 0x010 +/* + * SDI Response0 register offset + */ +#define MMCIRESPONSE0 0x014 +/* + * SDI Response1 register offset + */ +#define MMCIRESPONSE1 0x018 +/* + * SDI Response2 register offset + */ +#define MMCIRESPONSE2 0x01c +/* + * SDI Response3 register offset + */ +#define MMCIRESPONSE3 0x020 +/* + * SDI Datatimer register offset + */ +#define MMCIDATATIMER 0x024 +/* + * SDI DataLength register offset + */ +#define MMCIDATALENGTH 0x028 +/* + * SDI Data control register offset + */ +#define MMCIDATACTRL 0x02c +/* + * SDI Data control register bits + */ +#define MCI_DPSM_ENABLE (1 << 0) +#define MCI_DPSM_DIRECTION (1 << 1) +#define MCI_DPSM_MODE (1 << 2) +#define MCI_DPSM_DMAENABLE (1 << 3) +#define MCI_DPSM_DMAreqctl (1 << 12) +#define MCI_SDIO_ENABLE (1 << 11) + +/* + * SDI Data Count register offset + */ +#define MMCIDATACNT 0x030 +/* + * SDI Status register offset + */ +#define MMCISTATUS 0x034 +/* + * SDI Status register bits + */ +#define MCI_CMDCRCFAIL (1 << 0) +#define MCI_DATACRCFAIL (1 << 1) +#define MCI_CMDTIMEOUT (1 << 2) +#define MCI_DATATIMEOUT (1 << 3) +#define MCI_TXUNDERRUN (1 << 4) +#define MCI_RXOVERRUN (1 << 5) +#define MCI_CMDRESPEND (1 << 6) +#define MCI_CMDSENT (1 << 7) +#define MCI_DATAEND (1 << 8) +#define MCI_STBITERR (1 << 9) +#define MCI_DATABLOCKEND (1 << 10) +#define MCI_CMDACTIVE (1 << 11) +#define MCI_TXACTIVE (1 << 12) +#define MCI_RXACTIVE (1 << 13) +#define MCI_TXFIFOHALFEMPTY (1 << 14) +#define MCI_RXFIFOHALFFULL (1 << 15) +#define MCI_TXFIFOFULL (1 << 16) +#define MCI_RXFIFOFULL (1 << 17) +#define MCI_TXFIFOEMPTY (1 << 18) +#define MCI_RXFIFOEMPTY (1 << 19) +#define MCI_TXDATAAVLBL (1 << 20) +#define MCI_RXDATAAVLBL (1 << 21) +#define MCI_SDIOIT (1 << 22) +/* + * SDI Clear register offset + */ +#define MMCICLEAR 0x038 +#define MCI_CMDCRCFAILCLR (1 << 0) +#define MCI_DATACRCFAILCLR (1 << 1) +#define MCI_CMDTIMEOUTCLR (1 << 2) +#define MCI_DATATIMEOUTCLR (1 << 3) +#define MCI_TXUNDERRUNCLR (1 << 4) +#define MCI_RXOVERRUNCLR (1 << 5) +#define MCI_CMDRESPENDCLR (1 << 6) +#define MCI_CMDSENTCLR (1 << 7) +#define MCI_DATAENDCLR (1 << 8) +#define MCI_DATABLOCKENDCLR (1 << 10) +#define MCI_SDIOITCLR (1 << 22) +/* + * SDI Mask register offset + */ +#define MMCIMASK0 0x03c +/* + * SDI Mask register bits + */ +#define MCI_CMDCRCFAILMASK (1 << 0) +#define MCI_DATACRCFAILMASK (1 << 1) +#define MCI_CMDTIMEOUTMASK (1 << 2) +#define MCI_DATATIMEOUTMASK (1 << 3) +#define MCI_TXUNDERRUNMASK (1 << 4) +#define MCI_RXOVERRUNMASK (1 << 5) +#define MCI_CMDRESPENDMASK (1 << 6) +#define MCI_CMDSENTMASK (1 << 7) +#define MCI_DATAENDMASK (1 << 8) +#define MCI_DATABLOCKENDMASK (1 << 10) +#define MCI_CMDACTIVEMASK (1 << 11) +#define MCI_TXACTIVEMASK (1 << 12) +#define MCI_RXACTIVEMASK (1 << 13) +#define MCI_TXFIFOHALFEMPTYMASK (1 << 14) +#define MCI_RXFIFOHALFFULLMASK (1 << 15) +#define MCI_TXFIFOFULLMASK (1 << 16) +#define MCI_RXFIFOFULLMASK (1 << 17) +#define MCI_TXFIFOEMPTYMASK (1 << 18) +#define MCI_RXFIFOEMPTYMASK (1 << 19) +#define MCI_TXDATAAVLBLMASK (1 << 20) +#define MCI_RXDATAAVLBLMASK (1 << 21) +#define MCI_SDIOITMASK (1 << 22) + +#define MMCIMASK1 0x040 +#define MMCIFIFOCNT 0x048 +#define MMCIFIFO 0x080 /* to 0x0bc */ + +#define MCI_DATA_ERR \ + (MCI_RXOVERRUN | MCI_TXUNDERRUN | MCI_DATATIMEOUT | \ + MCI_DATACRCFAIL | MCI_STBITERR) +#define MCI_IRQENABLE \ + (MCI_CMDCRCFAIL | MCI_DATACRCFAIL | MCI_CMDTIMEOUT | \ + MCI_DATATIMEOUT | MCI_TXUNDERRUN | MCI_RXOVERRUN | \ + MCI_CMDRESPEND | MCI_CMDSENT | MCI_DATABLOCKEND) +#define MCI_DATA_IRQ (MCI_DATA_ERR | MCI_DATAEND) +#define MCI_XFER_IRQ_MASK \ + (MCI_TXFIFOEMPTY | MCI_TXFIFOHALFEMPTY | \ + MCI_RXFIFOHALFFULL | MCI_RXDATAAVLBL) +#define MCI_CMD_IRQ \ + (MCI_CMDCRCFAIL | MCI_CMDTIMEOUT | MCI_CMDRESPEND | \ + MCI_CMDSENT) +#define MCI_XFER_IRQ \ + (MCI_TXFIFOHALFEMPTY | MCI_RXFIFOHALFFULL) + +/* + * The size of the FIFO in bytes. + */ +#define MCI_FIFOSIZE 16 +#define MCI_FIFOHALFSIZE (MCI_FIFOSIZE / 2) +#define NR_SG 16 + +#define OCR_AVAIL (MMC_VDD_17_18 | MMC_VDD_18_19 | \ + /*MMC_VDD_28_29 |*/ \ + MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_32_33 | \ + MMC_VDD_33_34) +#define INVALID_PIPEID (-1) + +/** + * struct u8500_mmci_host - host device structure + * @base: pointer to the device baseaddress + * @mrq: pointer to the request structure + * @data: pointer to the data structure + * @mmc: pointer to the mmc_host structure + * @clk: pointer to the clock + * @data_xfered: variable which updates the data_transfered + * @lock: spinlock variable + * @sg_ptr: scatter list pointer + * + * host controller Internal device structure + */ +struct u8500_mmci_host { + void __iomem *base; + struct mmc_request *mrq; + struct mmc_command *cmd; + struct mmc_data *data; + struct mmc_host *mmc; + struct clk *clk; +#ifdef CONFIG_REGULATOR + struct regulator *regulator; +#endif + unsigned int data_xfered; + spinlock_t lock; + unsigned int mclk; + unsigned int cclk; + int (*card_detect_intr_value) (void); + unsigned int oldstat; + unsigned int dmach_mmc2mem; + unsigned int dmach_mem2mmc; + unsigned int dma_fifo_addr; + unsigned int dma_fifo_dev_type_rx; + unsigned int dma_fifo_dev_type_tx; + unsigned int level_shifter; + dma_addr_t dma; + unsigned long caps; /* Host capabilities */ + unsigned int sg_len; + /* pio stuff */ + struct scatterlist *sg_ptr; + unsigned int sg_off; + unsigned int size; + unsigned int *buffer; + unsigned int *dma_buffer; + void *dma_done; /* completion data */ + int devicemode; + unsigned int is_sdio; + int sdio_setirq; + int sdio_irqstatus; + int aligned_blksz; + int aligned_size; + struct mmc_board *board; + unsigned long reg_context[2]; +}; + +/* Define the current mode */ +#define MCI_DMAMODE 0x01 +#define MCI_POLLINGMODE 0x02 +#define MCI_INTERRUPTMODE 0x03 +#define MCI_ALLINTERRUPTS (0x007FFFFF) +#define MMCCLRSTATICFLAGS (0x000007FF) +#define MCI_MAXVOLTTRIAL (200) /* 200 times */ +#define MAX_FREQ (24000000) +#define MAX_DATA (64*512) +#define CLK_MAX 50000000 +#define CLK_DIV 0xFF +/* + * different card states + */ +enum card_state { + CARD_STATE_EMPTY = -1, + CARD_STATE_IDLE, + CARD_STATE_READY, + CARD_STATE_IDENT, + CARD_STATE_STBY, + CARD_STATE_TRAN, + CARD_STATE_DATA, + CARD_STATE_RCV, + CARD_STATE_PRG, + CARD_STATE_DIS, +}; +/* + * struct mmc_board - mmc board dependent structure + * @init: function pointer for mmc board related initialization + * @exit: function pointer for mmc board related de-initialization + * + * SDMMC platfoem dependent structure + */ +struct mmc_board { + int (*init) (struct amba_device *dev); + void (*exit) (struct amba_device *dev); + int (*set_power) (struct device *dev, int power_on); + int (*card_detect)(void (*callback)(void *parameter), void *); + int (*card_detect_intr_value) (void); + unsigned int dma_fifo_addr; + unsigned int dma_fifo_dev_type_rx; + unsigned int dma_fifo_dev_type_tx; + unsigned int level_shifter; + unsigned long caps; /* Host capabilities */ + int is_sdio; /* To check if the bus is SD/MMC or sdio */ +#ifdef CONFIG_REGULATOR + const char *supply; +#endif +}; + + diff --git a/arch/arm/mach-ux500/include/mach/msp.h b/arch/arm/mach-ux500/include/mach/msp.h new file mode 100755 index 00000000000..af512cd7b09 --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/msp.h @@ -0,0 +1,963 @@ +/* + * Copyright (c) 2009 STMicroelectronics + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + */ + +#ifndef _STM_MSP_HEADER +#define _STM_MSP_HEADER +#include <linux/device.h> +#include <linux/spinlock.h> +#include <linux/i2s/i2s.h> +#include <asm/dma.h> +#include <mach/dma.h> +#include <linux/irqreturn.h> +/* Generic config struct. Use the actual values defined below for global + * control register + */ +typedef enum { + MSP_MULTICHANNEL_DISABLED = 0, + MSP_MULTICHANNEL_ENABLED = 1 +} t_msp_multichannel_enable; + +typedef enum { + MSP_STATE_IDLE = 0, + MSP_STATE_CONFIGURED = 1, + MSP_STATE_RUN = 2, +} t_msp_state; + +typedef enum { + MSP_COMPARISON_DISABLED = 0, + MSP_COMPARISON_NONEQUAL_ENABLED = 2, + MSP_COMPARISON_EQUAL_ENABLED = 3 +} t_msp_rx_comparison_enable_mode; + +#define RMCEN_BIT 0 +#define RMCSF_BIT 1 +#define RCMPM_BIT 3 +#define TMCEN_BIT 5 +#define TNCSF_BIT 6 + +typedef struct { + t_msp_multichannel_enable rx_multichannel_enable; + t_msp_multichannel_enable tx_multichannel_enable; + t_msp_rx_comparison_enable_mode rx_comparison_enable_mode; + u8 padding; + u32 comparison_value; + u32 comparison_mask; + u32 rx_channel_0_enable; + u32 rx_channel_1_enable; + u32 rx_channel_2_enable; + u32 rx_channel_3_enable; + u32 tx_channel_0_enable; + u32 tx_channel_1_enable; + u32 tx_channel_2_enable; + u32 tx_channel_3_enable; +} t_msp_multichannel_config; + +enum msp_data_size { + MSP_DATA_SIZE_DEFAULT = -1, + MSP_DATA_SIZE_8BIT, + MSP_DATA_SIZE_10BIT, + MSP_DATA_SIZE_12BIT, + MSP_DATA_SIZE_14BIT, + MSP_DATA_SIZE_16BIT, + MSP_DATA_SIZE_20BIT, + MSP_DATA_SIZE_24BIT, + MSP_DATA_SIZE_32BIT, +}; + +/** + * struct msp_protocol_desc- MSP Protocol desc structure per MSP. + * @rx_phase_mode: rx_phase_mode whether single or dual. + * @tx_phase_mode: tx_phase_mode whether single or dual. + * @rx_phase2_start_mode: rx_phase2_start_mode whether imediate or after + * some delay. + * @tx_phase2_start_mode: tx_phase2_start_mode whether imediate or after + * some delay. + * @rx_bit_transfer_format: MSP or LSB. + * @tx_bit_transfer_format: MSP or LSB. + * @rx_frame_length_1: Frame1 length 1,2,3.. + * @rx_frame_length_2: Frame2 length 1,2,3.. + * @tx_frame_length_1: Frame1 length 1,2,3.. + * @tx_frame_length_2: Frame2 length 1,2,3.. + * @rx_element_length_1: Element1 length 1,2,... + * @rx_element_length_2: Element2 length 1,2,... + * @tx_element_length_1: Element1 length 1,2,... + * @tx_element_length_2: Element2 length 1,2,... + * @rx_data_delay: Delay in clk cycle after frame sync + * @tx_data_delay: Delay in clk cycle after frame sync + * @rx_clock_pol: Rxpol whether rising or falling.It indicates pol of bit clock. + * @tx_clock_pol: Txpol whether rising or falling.It indicates pol of bit clock. + * @rx_frame_sync_pol: Frame sync pol whether rising or Falling. + * @tx_frame_sync_pol: Frame sync pol whether rising or Falling. + * @rx_half_word_swap: Word swap half word, full word. + * @tx_half_word_swap: Word swap half word, full word. + * @compression_mode: Compression mode whether Alaw or Ulaw or disabled. + * @expansion_mode: Compression mode whether Alaw or Ulaw or disabled. + * @spi_clk_mode: Spi clock mode to be enabled or not. + * @spi_burst_mode: Spi burst mode to be enabled or not. + * @frame_sync_ignore: Frame sync to be ignored or not. Ignore in case of Audio + * codec acting as Master. + * @frame_period: Frame period (clk cycles) after which new frame sync occurs. + * @frame_width: Frame width (clk cycles) after which frame sycn changes state. + * @total_clocks_for_one_frame: No. of clk cycles per frame. + * + * Main Msp protocol descriptor data structure to be used to store various info + * in transmit or recevie configuration registers of an MSP. + */ + +struct msp_protocol_desc { + u32 rx_phase_mode; + u32 tx_phase_mode; + u32 rx_phase2_start_mode; + u32 tx_phase2_start_mode; + u32 rx_bit_transfer_format; + u32 tx_bit_transfer_format; + u32 rx_frame_length_1; + u32 rx_frame_length_2; + u32 tx_frame_length_1; + u32 tx_frame_length_2; + u32 rx_element_length_1; + u32 rx_element_length_2; + u32 tx_element_length_1; + u32 tx_element_length_2; + u32 rx_data_delay; + u32 tx_data_delay; + u32 rx_clock_pol; + u32 tx_clock_pol; + u32 rx_frame_sync_pol; + u32 tx_frame_sync_pol; + u32 rx_half_word_swap; + u32 tx_half_word_swap; + u32 compression_mode; + u32 expansion_mode; + u32 spi_clk_mode; + u32 spi_burst_mode; + u32 frame_sync_ignore; + u32 frame_period; + u32 frame_width; + u32 total_clocks_for_one_frame; +}; + +/** + * struct trans_data - MSP transfer data structure used during xfer. + * @message: i2s message. + * @msp: msp structure. + * @tx_handler: callback handler for transmit path. + * @rx_handler: callback handler for receive path. + * @tx_callback_data: callback data for transmit. + * @rx_callback_data: callback data for receive. + * + */ +struct trans_data { + struct i2s_message message; + struct msp_struct *msp; + irqreturn_t(*tx_handler) (void *data, int irq); + irqreturn_t(*rx_handler) (void *data, int irq); + void *tx_callback_data; + void *rx_callback_data; +}; + +/** + * struct msp_generic_config- MSP configuration structure used by i2s client. + * @input_clock_freq: Input clock frequency default is 48MHz. + * @rx_clock_sel: Receive clock selection (Provided by Sample Gen or external + * source). + * @tx_clock_sel: Transmit clock selection (Provided by Sample Gen or external. + * source). + * @srg_clock_sel: APB clock or clock dervied from Slave (Audio codec). + * @rx_frame_sync_pol: Receive frame sync polarity. + * @tx_frame_sync_pol: Transmit frame sync polarity. + * @rx_frame_sync_sel: Rx frame sync signal is provided by which source. + * External source or by frame generator logic. + * @tx_frame_sync_sel: Tx frame sync signal is provided by which source. + * External source or by frame generator logic. + * @rx_fifo_config: Receive fifo enable or not. + * @tx_fifo_config: Transmit fifo enable or not. + * @spi_clk_mode: In case of SPI protocol spi modes: Normal, Zero delay or + * half cycle delay. + * @spi_burst_mode: Spi burst mode is enabled or not. + * @loopback_enable: Loopback mode. + * @tx_data_enable: Transmit extra delay enable. + * @default_protocol_desc: Flag to indicate client defined protocol desc or + * statically defined in msp.h. + * @protocol_desc: Protocol desc structure filled by i2s client driver. + * In case client defined default_prtocol_desc as 0. + * @multichannel_configured: multichannel configuration structure. + * @multichannel_config: multichannel is enabled or not. + * @direction: Transmit, Receive or Both. + * @work_mode: Dma, Polling or Interrupt. + * @protocol: I2S, PCM, etc. + * @frame_freq: Sampling freq at which data is sampled. + * @frame_size: size of element. + * @data_size: data size which defines the format in which data is written on + * transmit or receive fifo. Only three modes 8,16,32 are supported. + * @def_elem_len: Flag to indicate whether default element length is to be used + * or should be changed acc to data size defined by user at run time. + * @handler: callback handler in case of interrupt or dma. + * @tx_callback_data: Callback data for transmit. + * @rx_callback_data: Callback data for receive. + * + * Main Msp configuration data structure used by i2s client driver to fill + * various info like data size, frequency etc. + */ +struct msp_generic_config { + unsigned int input_clock_freq; + unsigned int rx_clock_sel; + unsigned int tx_clock_sel; + unsigned int srg_clock_sel; + unsigned int rx_frame_sync_pol; + unsigned int tx_frame_sync_pol; + unsigned int rx_frame_sync_sel; + unsigned int tx_frame_sync_sel; + unsigned int rx_fifo_config; + unsigned int tx_fifo_config; + unsigned int spi_clk_mode; + unsigned int spi_burst_mode; + unsigned int loopback_enable; + unsigned int tx_data_enable; + unsigned int default_protocol_desc; + struct msp_protocol_desc protocol_desc; + int multichannel_configured; + t_msp_multichannel_config multichannel_config; + unsigned int direction; + unsigned int work_mode; + unsigned int protocol; + unsigned int frame_freq; + unsigned int frame_size; + enum msp_data_size data_size; + unsigned int def_elem_len; + irqreturn_t(*handler) (void *data, int err_or_data); + void *tx_callback_data; + void *rx_callback_data; + +}; + +/*** Protocols ***/ +enum { + MSP_I2S_PROTOCOL, + MSP_PCM_PROTOCOL, + MSP_PCM_COMPAND_PROTOCOL, + MSP_AC97_PROTOCOL, + MSP_MASTER_SPI_PROTOCOL, + MSP_SLAVE_SPI_PROTOCOL, + MSP_INVALID_PROTOCOL +}; + +/*** Sample Frequencies ***/ +/* These are no longer required, frequencies in Hz can be used directly */ +enum { + MSP_SAMPLE_FREQ_NOT_SUPPORTED = -1, + MSP_SAMPLE_FREQ_8KHZ = 8000, + MSP_SAMPLE_FREQ_12KHZ = 12000, + MSP_SAMPLE_FREQ_16KHZ = 16000, + MSP_SAMPLE_FREQ_24KHZ = 24000, + MSP_SAMPLE_FREQ_32KHZ = 32000, + MSP_SAMPLE_FREQ_44KHZ = 44000, + MSP_SAMPLE_FREQ_48KHZ = 48000, + MSP_SAMPLE_FREQ_64KHZ = 64000, + MSP_SAMPLE_FREQ_88KHZ = 88000, + MSP_SAMPLE_FREQ_96KHZ = 96000, + MSP_SAMPLE_FREQ_22KHZ = 22000, + MSP_SAMPLE_FREQ_11KHZ = 11000 +}; + +/*** Input Frequencies ***/ +/* These are no longer required, frequencies in Hz can be used directly */ +typedef enum { + MSP_INPUT_FREQ_1MHZ = 1000, + MSP_INPUT_FREQ_2MHZ = 2000, + MSP_INPUT_FREQ_3MHZ = 3000, + MSP_INPUT_FREQ_4MHZ = 4000, + MSP_INPUT_FREQ_5MHZ = 5000, + MSP_INPUT_FREQ_6MHZ = 6000, + MSP_INPUT_FREQ_8MHZ = 8000, + MSP_INPUT_FREQ_11MHZ = 11000, + MSP_INPUT_FREQ_12MHZ = 12000, + MSP_INPUT_FREQ_16MHZ = 16000, + MSP_INPUT_FREQ_22MHZ = 22000, + MSP_INPUT_FREQ_24MHZ = 24000, + MSP_INPUT_FREQ_48MHZ = 48000 +} t_msp_in_clock_freq; + +#define MSP_INPUT_FREQ_APB 48000000 + +/*** Stereo mode. Used for APB data accesses as 16 bits accesses (mono), + * 32 bits accesses (stereo). + ***/ +enum { + MSP_MONO, + MSP_STEREO +}; + +/* Direction (Transmit/Receive mode) */ +enum { + MSP_TRANSMIT_MODE, + MSP_RECEIVE_MODE, + MSP_BOTH_T_R_MODE +}; + +/* Dma mode should be used for large transfers, + * polling mode should be used for transfers of a few bytes + */ +enum { + MSP_DMA_MODE, + MSP_POLLING_MODE, + MSP_INTERRUPT_MODE +}; + +/* User client for the MSP */ +typedef enum { + MSP_NO_USER = 0, + MSP_USER_SPI, + MSP_USER_ALSA, + MSP_USER_SAA, +} t_msp_user; + +/*Flag structure for MSPx*/ +typedef struct { + struct semaphore lock; + t_msp_user user; +} msp_flag; + +/* User client for the MSP */ +typedef enum { + MSP_NO_MODE = 0, + MSP_MODE_SPI, + MSP_MODE_NON_SPI, +} t_msp_mode; + +/* Transmit and receive configuration register */ +#define MSP_BIG_ENDIAN 0x00000000 +#define MSP_LITTLE_ENDIAN 0x00001000 +#define MSP_UNEXPECTED_FS_ABORT 0x00000000 +#define MSP_UNEXPECTED_FS_IGNORE 0x00008000 +#define MSP_NON_MODE_BIT_MASK 0x00009000 + +/* Global configuration register +--------------------------------*/ +#define RX_ENABLE 0x00000001 +#define RX_FIFO_ENABLE 0x00000002 +#define RX_SYNC_SRG 0x00000010 +#define RX_CLK_POL_RISING 0x00000020 +#define RX_CLK_SEL_SRG 0x00000040 +#define TX_ENABLE 0x00000100 +#define TX_FIFO_ENABLE 0x00000200 +#define TX_SYNC_SRG_PROG 0x00001800 +#define TX_SYNC_SRG_AUTO 0x00001000 +#define TX_CLK_POL_RISING 0x00002000 +#define TX_CLK_SEL_SRG 0x00004000 +#define TX_EXTRA_DELAY_ENABLE 0x00008000 +#define SRG_ENABLE 0x00010000 +#define FRAME_GEN_ENABLE 0x00100000 +#define SRG_CLK_SEL_APB 0x00000000 +#define RX_FIFO_SYNC_HI 0x00000000 +#define TX_FIFO_SYNC_HI 0x00000000 +#define SPI_CLK_MODE_NORMAL 0x00000000 + +/* SPI Clock Modes enumertion + * SPI clock modes of MSP provides compatibility with + * the SPI protocol.MSP supports 2 SPI transfer formats. + * MSP_ZERO_DELAY_SPI_MODE:MSP transmits data over Tx/Rx + * Lines immediately after MSPTCK/MSPRCK rising/falling edge. + * MSP_HALF_CYCLE_DELY_SPI_MODE:MSP transmits data one-half cycle + * ahead of the rising/falling edge of the MSPTCK + */ +enum { + MSP_NON_SPI_PROTOCOL = 0, + MSP_ZERO_DELAY_SPI_MODE = 2, + MSP_HALF_CYCLE_DELY_SPI_MODE = 3 +}; + +#define MSP_FRAME_SIZE_AUTO -1 + + +#define MSP_DR 0x00 +#define MSP_GCR 0x04 +#define MSP_TCF 0x08 +#define MSP_RCF 0x0c +#define MSP_SRG 0x10 +#define MSP_FLR 0x14 +#define MSP_DMACR 0x18 + +#define MSP_IMSC 0x20 +#define MSP_RIS 0x24 +#define MSP_MIS 0x28 +#define MSP_ICR 0x2c +#define MSP_MCR 0x30 +#define MSP_RCV 0x34 +#define MSP_RCM 0x38 + +#define MSP_TCE0 0x40 +#define MSP_TCE1 0x44 +#define MSP_TCE2 0x48 +#define MSP_TCE3 0x4c + +#define MSP_RCE0 0x60 +#define MSP_RCE1 0x64 +#define MSP_RCE2 0x68 +#define MSP_RCE3 0x6c + +#define MSP_ITCR 0x80 +#define MSP_ITIP 0x84 +#define MSP_ITOP 0x88 +#define MSP_TSTDR 0x8c + +#define MSP_PID0 0xfe0 +#define MSP_PID1 0xfe4 +#define MSP_PID2 0xfe8 +#define MSP_PID3 0xfec + +#define MSP_CID0 0xff0 +#define MSP_CID1 0xff4 +#define MSP_CID2 0xff8 +#define MSP_CID3 0xffc + +/* Single or dual phase mode */ +enum { + MSP_SINGLE_PHASE, + MSP_DUAL_PHASE +}; + +/* Frame length +------------------*/ +enum { + MSP_FRAME_LENGTH_1 = 0, + MSP_FRAME_LENGTH_2 = 1, + MSP_FRAME_LENGTH_4 = 3, + MSP_FRAME_LENGTH_8 = 7, + MSP_FRAME_LENGTH_12 = 11, + MSP_FRAME_LENGTH_16 = 15, + MSP_FRAME_LENGTH_20 = 19, + MSP_FRAME_LENGTH_32 = 31, + MSP_FRAME_LENGTH_48 = 47, + MSP_FRAME_LENGTH_64 = 63 +}; + +/* Element length */ +enum { + MSP_ELEM_LENGTH_8 = 0, + MSP_ELEM_LENGTH_10 = 1, + MSP_ELEM_LENGTH_12 = 2, + MSP_ELEM_LENGTH_14 = 3, + MSP_ELEM_LENGTH_16 = 4, + MSP_ELEM_LENGTH_20 = 5, + MSP_ELEM_LENGTH_24 = 6, + MSP_ELEM_LENGTH_32 = 7 +}; +enum { + MSP_DATA_TRANSFER_WIDTH_BYTE, + MSP_DATA_TRANSFER_WIDTH_HALFWORD, + MSP_DATA_TRANSFER_WIDTH_WORD +}; +enum { + MSP_FRAME_SYNC_UNIGNORE = 0, + MSP_FRAME_SYNC_IGNORE = 1, + +}; +enum { + MSP_PHASE2_START_MODE_IMEDIATE, + MSP_PHASE2_START_MODE_FRAME_SYNC +}; +enum { + MSP_BTF_MS_BIT_FIRST = 0, + MSP_BTF_LS_BIT_FIRST = 1 +}; + +enum { + MSP_FRAME_SYNC_POL_ACTIVE_HIGH = 0, + MSP_FRAME_SYNC_POL_ACTIVE_LOW = 1 +}; +/* Data delay (in bit clock cycles) +---------------------------------------*/ +enum { + MSP_DELAY_0 = 0, + MSP_DELAY_1 = 1, + MSP_DELAY_2 = 2, + MSP_DELAY_3 = 3 +}; + +/* Configurations of clocks (transmit, receive or sample rate generator) +-------------------------------------------------------------------------*/ +enum { + MSP_FALLING_EDGE = 0, + MSP_RISING_EDGE = 1, +}; + +enum { + MSP_HWS_NO_SWAP = 0, + MSP_HWS_BYTE_SWAP_IN_WORD = 1, + MSP_HWS_BYTE_SWAP_IN_EACH_HALF_WORD = 2, + MSP_HWS_HALF_WORD_SWAP_IN_WORD = 3 +}; +enum { + MSP_COMPRESS_MODE_LINEAR = 0, + MSP_COMPRESS_MODE_MU_LAW = 2, + MSP_COMPRESS_MODE_A_LAW = 3 +}; +enum { + MSP_SPI_CLOCK_MODE_NON_SPI = 0, + MSP_SPI_CLOCK_MODE_ZERO_DELAY = 2, + MSP_SPI_CLOCK_MODE_HALF_CYCLE_DELAY = 3 +}; +enum { + MSP_SPI_BURST_MODE_DISABLE = 0, + MSP_SPI_BURST_MODE_ENABLE = 1 +}; +enum { + MSP_EXPAND_MODE_LINEAR = 0, + MSP_EXPAND_MODE_LINEAR_SIGNED = 1, + MSP_EXPAND_MODE_MU_LAW = 2, + MSP_EXPAND_MODE_A_LAW = 3 +}; +/* Protocol dependant parameters list */ +#define RX_ENABLE_MASK 0x00000001 +#define RX_FIFO_ENABLE_MASK 0x00000002 +#define RX_FRAME_SYNC_MASK 0x00000004 +#define DIRECT_COMPANDING_MASK 0x00000008 +#define RX_SYNC_SEL_MASK 0x00000010 +#define RX_CLK_POL_MASK 0x00000020 +#define RX_CLK_SEL_MASK 0x00000040 +#define LOOPBACK_MASK 0x00000080 +#define TX_ENABLE_MASK 0x00000100 +#define TX_FIFO_ENABLE_MASK 0x00000200 +#define TX_FRAME_SYNC_MASK 0x00000400 +#define TX_MSP_TDR_TSR 0x00000800 +#define TX_SYNC_SEL_MASK 0x00001800 +#define TX_CLK_POL_MASK 0x00002000 +#define TX_CLK_SEL_MASK 0x00004000 +#define TX_EXTRA_DELAY_MASK 0x00008000 +#define SRG_ENABLE_MASK 0x00010000 +#define SRG_CLK_POL_MASK 0x00020000 +#define SRG_CLK_SEL_MASK 0x000C0000 +#define FRAME_GEN_EN_MASK 0x00100000 +#define SPI_CLK_MODE_MASK 0x00600000 +#define SPI_BURST_MODE_MASK 0x00800000 + +#define RXEN_BIT 0 +#define RFFEN_BIT 1 +#define RFSPOL_BIT 2 +#define DCM_BIT 3 +#define RFSSEL_BIT 4 +#define RCKPOL_BIT 5 +#define RCKSEL_BIT 6 +#define LBM_BIT 7 +#define TXEN_BIT 8 +#define TFFEN_BIT 9 +#define TFSPOL_BIT 10 +#define TFSSEL_BIT 11 +#define TCKPOL_BIT 13 +#define TCKSEL_BIT 14 +#define TXDDL_BIT 15 +#define SGEN_BIT 16 +#define SCKPOL_BIT 17 +#define SCKSEL_BIT 18 +#define FGEN_BIT 20 +#define SPICKM_BIT 21 +#define TBSWAP_BIT 28 + +#define msp_rx_clkpol_bit(n) ((n & 1) << RCKPOL_BIT) +#define msp_tx_clkpol_bit(n) ((n & 1) << TCKPOL_BIT) +#define msp_spi_clk_mode_bits(n) ((n & 3) << SPICKM_BIT) + +/* Use this to clear the clock mode bits to non-spi */ +#define MSP_NON_SPI_CLK_MASK 0x00600000 + +#define P1ELEN_BIT 0 +#define P1FLEN_BIT 3 +#define DTYP_BIT 10 +#define ENDN_BIT 12 +#define DDLY_BIT 13 +#define FSIG_BIT 15 +#define P2ELEN_BIT 16 +#define P2FLEN_BIT 19 +#define P2SM_BIT 26 +#define P2EN_BIT 27 +#define FRAME_SYNC_BIT 15 + +#define msp_p1_elem_len_bits(n) (n & 0x00000007) +#define msp_p2_elem_len_bits(n) (((n) << P2ELEN_BIT) & 0x00070000) +#define msp_p1_frame_len_bits(n) (((n) << P1FLEN_BIT) & 0x00000378) +#define msp_p2_frame_len_bits(n) (((n) << P2FLEN_BIT) & 0x03780000) +#define msp_data_delay_bits(n) (((n) << DDLY_BIT) & 0x00003000) +#define msp_data_type_bits(n) (((n) << DTYP_BIT) & 0x00000600) +#define msp_p2_start_mode_bit(n) ((n << P2SM_BIT) & 0x04000000) +#define msp_p2_enable_bit(n) ((n << P2EN_BIT) & 0x08000000) +#define msp_set_endiannes_bit(n) ((n << ENDN_BIT) & 0x00001000) +#define msp_frame_sync_pol(n) ((n << TFSPOL_BIT) & 0x00000400) +#define msp_data_word_swap(n) ((n << TBSWAP_BIT) & 0x30000000) +#define msp_set_companding_mode(n) ((n << DTYP_BIT) & 0x00000c00) +#define msp_set_frame_sync_ignore(n) ((n << FRAME_SYNC_BIT) & 0x00008000) + +/* Flag register +--------------------*/ +#define RX_BUSY 0x00000001 +#define RX_FIFO_EMPTY 0x00000002 +#define RX_FIFO_FULL 0x00000004 +#define TX_BUSY 0x00000008 +#define TX_FIFO_EMPTY 0x00000010 +#define TX_FIFO_FULL 0x00000020 + +#define RBUSY_BIT 0 +#define RFE_BIT 1 +#define RFU_BIT 2 +#define TBUSY_BIT 3 +#define TFE_BIT 4 +#define TFU_BIT 5 + +/* Multichannel control register +---------------------------------*/ +#define RMCEN_BIT 0 +#define RMCSF_BIT 1 +#define RCMPM_BIT 3 +#define TMCEN_BIT 5 +#define TNCSF_BIT 6 + +/* Sample rate generator register +------------------------------------*/ +#define SCKDIV_BIT 0 +#define FRWID_BIT 10 +#define FRPER_BIT 16 + +#define SCK_DIV_MASK 0x0000003FF +#define frame_width_bits(n) (((n) << FRWID_BIT) & 0x0000FC00) +#define frame_period_bits(n) (((n) << FRPER_BIT) & 0x1FFF0000) + +/* DMA controller register +---------------------------*/ +#define RX_DMA_ENABLE 0x00000001 +#define TX_DMA_ENABLE 0x00000002 + +#define RDMAE_BIT 0 +#define TDMAE_BIT 1 + +/*Interrupt Register +-----------------------------------------*/ +#define RECEIVE_SERVICE_INT 0x00000001 +#define RECEIVE_OVERRUN_ERROR_INT 0x00000002 +#define RECEIVE_FRAME_SYNC_ERR_INT 0x00000004 +#define RECEIVE_FRAME_SYNC_INT 0x00000008 +#define TRANSMIT_SERVICE_INT 0x00000010 +#define TRANSMIT_UNDERRUN_ERR_INT 0x00000020 +#define TRANSMIT_FRAME_SYNC_ERR_INT 0x00000040 +#define TRANSMIT_FRAME_SYNC_INT 0x00000080 +#define ALL_INT 0x000000ff + +/* Protocol configuration values +* I2S: Single phase, 16 bits, 2 words per frame +-----------------------------------------------*/ +#define I2S_PROTOCOL_DESC \ +{ \ + MSP_SINGLE_PHASE, \ + MSP_SINGLE_PHASE, \ + MSP_PHASE2_START_MODE_IMEDIATE, \ + MSP_PHASE2_START_MODE_IMEDIATE, \ + MSP_BTF_MS_BIT_FIRST, \ + MSP_BTF_MS_BIT_FIRST, \ + MSP_FRAME_LENGTH_1, \ + MSP_FRAME_LENGTH_1, \ + MSP_FRAME_LENGTH_1, \ + MSP_FRAME_LENGTH_1, \ + MSP_ELEM_LENGTH_32, \ + MSP_ELEM_LENGTH_32, \ + MSP_ELEM_LENGTH_32, \ + MSP_ELEM_LENGTH_32, \ + MSP_DELAY_1, \ + MSP_DELAY_1, \ + MSP_RISING_EDGE, \ + MSP_RISING_EDGE, \ + MSP_FRAME_SYNC_POL_ACTIVE_HIGH, \ + MSP_FRAME_SYNC_POL_ACTIVE_HIGH, \ + MSP_HWS_NO_SWAP, \ + MSP_HWS_NO_SWAP, \ + MSP_COMPRESS_MODE_LINEAR, \ + MSP_EXPAND_MODE_LINEAR, \ + MSP_SPI_CLOCK_MODE_NON_SPI, \ + MSP_SPI_BURST_MODE_DISABLE, \ + MSP_FRAME_SYNC_IGNORE, \ + 31, \ + 15, \ + 32, \ +} +#define PCM_PROTOCOL_DESC \ +{ \ + MSP_DUAL_PHASE, \ + MSP_DUAL_PHASE, \ + MSP_PHASE2_START_MODE_FRAME_SYNC, \ + MSP_PHASE2_START_MODE_FRAME_SYNC, \ + MSP_BTF_MS_BIT_FIRST, \ + MSP_BTF_MS_BIT_FIRST, \ + MSP_FRAME_LENGTH_1, \ + MSP_FRAME_LENGTH_1, \ + MSP_FRAME_LENGTH_1, \ + MSP_FRAME_LENGTH_1, \ + MSP_ELEM_LENGTH_16, \ + MSP_ELEM_LENGTH_16, \ + MSP_ELEM_LENGTH_16, \ + MSP_ELEM_LENGTH_16, \ + MSP_DELAY_0, \ + MSP_DELAY_0, \ + MSP_FALLING_EDGE, \ + MSP_FALLING_EDGE, \ + MSP_FRAME_SYNC_POL_ACTIVE_HIGH, \ + MSP_FRAME_SYNC_POL_ACTIVE_HIGH, \ + MSP_HWS_NO_SWAP, \ + MSP_HWS_NO_SWAP, \ + MSP_COMPRESS_MODE_LINEAR, \ + MSP_EXPAND_MODE_LINEAR, \ + MSP_SPI_CLOCK_MODE_NON_SPI, \ + MSP_SPI_BURST_MODE_DISABLE, \ + MSP_FRAME_SYNC_IGNORE, \ + 255, \ + 0, \ + 256, \ +} +/* Companded PCM: Single phase, 8 bits, 1 word per frame +--------------------------------------------------------*/ +#define PCM_COMPAND_PROTOCOL_DESC \ +{ \ + MSP_SINGLE_PHASE, \ + MSP_SINGLE_PHASE, \ + MSP_PHASE2_START_MODE_FRAME_SYNC, \ + MSP_PHASE2_START_MODE_FRAME_SYNC, \ + MSP_BTF_MS_BIT_FIRST, \ + MSP_BTF_MS_BIT_FIRST, \ + MSP_FRAME_LENGTH_1, \ + MSP_FRAME_LENGTH_1, \ + MSP_FRAME_LENGTH_1, \ + MSP_FRAME_LENGTH_1, \ + MSP_ELEM_LENGTH_8, \ + MSP_ELEM_LENGTH_8, \ + MSP_ELEM_LENGTH_8, \ + MSP_ELEM_LENGTH_8, \ + MSP_DELAY_0, \ + MSP_DELAY_0, \ + MSP_FALLING_EDGE, \ + MSP_RISING_EDGE, \ + MSP_FRAME_SYNC_POL_ACTIVE_HIGH, \ + MSP_FRAME_SYNC_POL_ACTIVE_HIGH, \ + MSP_HWS_NO_SWAP, \ + MSP_HWS_NO_SWAP, \ + MSP_COMPRESS_MODE_LINEAR, \ + MSP_EXPAND_MODE_LINEAR, \ + MSP_SPI_CLOCK_MODE_NON_SPI, \ + MSP_SPI_BURST_MODE_DISABLE, \ + MSP_FRAME_SYNC_IGNORE, \ + 255, \ + 0, \ + 256, \ +} + +/* AC97: Double phase, 1 element of 16 bits during first phase, +* 12 elements of 20 bits in second phase. +--------------------------------------------------------------*/ +#define AC97_PROTOCOL_DESC \ +{ \ + MSP_DUAL_PHASE, \ + MSP_DUAL_PHASE, \ + MSP_PHASE2_START_MODE_FRAME_SYNC, \ + MSP_PHASE2_START_MODE_FRAME_SYNC, \ + MSP_BTF_MS_BIT_FIRST, \ + MSP_BTF_MS_BIT_FIRST, \ + MSP_FRAME_LENGTH_1, \ + MSP_FRAME_LENGTH_12, \ + MSP_FRAME_LENGTH_1, \ + MSP_FRAME_LENGTH_12, \ + MSP_ELEM_LENGTH_16, \ + MSP_ELEM_LENGTH_20, \ + MSP_ELEM_LENGTH_16, \ + MSP_ELEM_LENGTH_20, \ + MSP_DELAY_1, \ + MSP_DELAY_1, \ + MSP_FALLING_EDGE, \ + MSP_RISING_EDGE, \ + MSP_FRAME_SYNC_POL_ACTIVE_HIGH, \ + MSP_FRAME_SYNC_POL_ACTIVE_HIGH, \ + MSP_HWS_NO_SWAP, \ + MSP_HWS_NO_SWAP, \ + MSP_COMPRESS_MODE_LINEAR, \ + MSP_EXPAND_MODE_LINEAR, \ + MSP_SPI_CLOCK_MODE_NON_SPI, \ + MSP_SPI_BURST_MODE_DISABLE, \ + MSP_FRAME_SYNC_IGNORE, \ + 255, \ + 0, \ + 256, \ +} + +#define SPI_MASTER_PROTOCOL_DESC \ +{ \ + MSP_SINGLE_PHASE, \ + MSP_SINGLE_PHASE, \ + MSP_PHASE2_START_MODE_FRAME_SYNC, \ + MSP_PHASE2_START_MODE_FRAME_SYNC, \ + MSP_BTF_MS_BIT_FIRST, \ + MSP_BTF_MS_BIT_FIRST, \ + MSP_FRAME_LENGTH_1, \ + MSP_FRAME_LENGTH_1, \ + MSP_FRAME_LENGTH_1, \ + MSP_FRAME_LENGTH_1, \ + MSP_ELEM_LENGTH_8, \ + MSP_ELEM_LENGTH_8, \ + MSP_ELEM_LENGTH_8, \ + MSP_ELEM_LENGTH_8, \ + MSP_DELAY_1, \ + MSP_DELAY_1, \ + MSP_RISING_EDGE, \ + MSP_FALLING_EDGE, \ + MSP_FRAME_SYNC_POL_ACTIVE_HIGH, \ + MSP_FRAME_SYNC_POL_ACTIVE_HIGH, \ + MSP_HWS_NO_SWAP, \ + MSP_HWS_NO_SWAP, \ + MSP_COMPRESS_MODE_LINEAR, \ + MSP_EXPAND_MODE_LINEAR, \ + MSP_SPI_CLOCK_MODE_NON_SPI, \ + MSP_SPI_BURST_MODE_DISABLE, \ + MSP_FRAME_SYNC_IGNORE, \ + 255, \ + 0, \ + 256, \ +} + +#define SPI_SLAVE_PROTOCOL_DESC \ +{ \ + MSP_SINGLE_PHASE, \ + MSP_SINGLE_PHASE, \ + MSP_PHASE2_START_MODE_FRAME_SYNC, \ + MSP_PHASE2_START_MODE_FRAME_SYNC, \ + MSP_BTF_MS_BIT_FIRST, \ + MSP_BTF_MS_BIT_FIRST, \ + MSP_FRAME_LENGTH_1, \ + MSP_FRAME_LENGTH_1, \ + MSP_FRAME_LENGTH_1, \ + MSP_FRAME_LENGTH_1, \ + MSP_ELEM_LENGTH_8, \ + MSP_ELEM_LENGTH_8, \ + MSP_ELEM_LENGTH_8, \ + MSP_ELEM_LENGTH_8, \ + MSP_DELAY_1, \ + MSP_DELAY_1, \ + MSP_RISING_EDGE, \ + MSP_FALLING_EDGE, \ + MSP_FRAME_SYNC_POL_ACTIVE_HIGH, \ + MSP_FRAME_SYNC_POL_ACTIVE_HIGH, \ + MSP_HWS_NO_SWAP, \ + MSP_HWS_NO_SWAP, \ + MSP_COMPRESS_MODE_LINEAR, \ + MSP_EXPAND_MODE_LINEAR, \ + MSP_SPI_CLOCK_MODE_NON_SPI, \ + MSP_SPI_BURST_MODE_DISABLE, \ + MSP_FRAME_SYNC_IGNORE, \ + 255, \ + 0, \ + 256, \ +} + +#define MSP_FRAME_PERIOD_IN_MONO_MODE 256 +#define MSP_FRAME_PERIOD_IN_STEREO_MODE 32 +#define MSP_FRAME_WIDTH_IN_STEREO_MODE 16 + +/* No of registers to backup during + * suspend resume */ +#define MAX_MSP_BACKUP_REGS 36 + +typedef enum { + MSP_0_I2S_CONTROLLER = 1, + MSP_1_I2S_CONTROLLER, + MSP_2_I2S_CONTROLLER, +} t_i2s_controller; + +/** + * struct msp_struct - Main msp controller data structure per MSP. + * @work_mode: Mode i.e dma, polling or interrupt. + * @id: Controller id like MSP1 or MSP2 etc. + * @msp_io_error: To indicate error while transferring. + * @registers: MSP's register base address. + * @actual_data_size: Data size in which data needs to send or receive. + * @irq: MSP's irq number. + * @i2s_cont: MSP's Controller's structure pointer created per MSP. + * @gpio_alt_func: Gpio Alt function id of particular msp. + * @lock: semaphore lock acquired while configuring msp. + * @pipe_params_rx: Receive dma pipe structure. + * @pipe_params_tx: Transmit dma pipe structure. + * @msp_tx_dma_addr: Transmit Base Address of msp for DMA. + * @msp_rx_dma_addr: Receive Base Address of msp for DMA. + * @msp_base_addr: Physical Base Address of msp. + * @tx_pipeid: Txpipeid for DMA. + * @rx_pipeid: Rxpipeid for DMA. + * @msp_state: Current state of msp. + * @read: Function pointer for read, u8_msp_read,u16_msp_read,u32_msp_read. + * @write: Function pointer for write, u8_msp_write,u16_msp_write,u32_msp_write. + * @transfer: Function pointer for type of transfer i.e dma,polling or interrupt + * @xfer_data: MSP's transfer data structure. Contains info about current xfer. + * @plat_init: MSP's initialization function. + * @plat_exit: MSP's Exit function. + * @notify_timer: Timer used in Polling mode to prevent hang. + * @polling_flag: Flag used in error handling while polling. + * @def_elem_len: Flag indicates whether default elem len to be used in + * protocol_desc or not. + * + * Main Msp private data structure to be used to store various info of a + * particular MSP.Longer description + */ +struct msp_struct { + int work_mode; + t_i2s_controller id; + int msp_io_error; + void __iomem *registers; + enum msp_data_size actual_data_size; + int irq; + struct i2s_controller *i2s_cont; + u32 gpio_alt_func; + struct semaphore lock; + struct stm_dma_pipe_info pipe_params_rx; + struct stm_dma_pipe_info pipe_params_tx; + u32 msp_tx_dma_addr; + u32 msp_rx_dma_addr; + u32 msp_base_addr; + dmach_t tx_pipeid; + dmach_t rx_pipeid; + t_msp_state msp_state; + void (*read) (struct trans_data *xfer_data); + void (*write) (struct trans_data *xfer_data); + int (*transfer) (struct msp_struct *msp, struct i2s_message *message); + struct trans_data xfer_data; + int (*plat_init) (u32); + int (*plat_exit) (u32); + struct timer_list notify_timer; + int polling_flag; + int def_elem_len; + struct clk *clk; + unsigned int direction; + int users; + int loopback_enable; + u32 backup_regs[MAX_MSP_BACKUP_REGS]; +}; + +/** + * struct msp_i2s_platform_datat - Main msp controller platform data structure. + * @id: Controller id like MSP1 or MSP2 etc. + * @gpio_alt_func: Gpio Alt function id of particular msp. + * @msp_tx_dma_addr: Transmit Base Address of msp for DMA. + * @msp_rx_dma_addr: Receive Base Address of msp for DMA. + * @msp_base_addr: Physical Base Address of msp. + * msp_i2s_init@: MSP's initialization function. + * @msp_i2s_exit: MSP's Exit function. + * @backup_regs: used for backup registers during suspend resume. + * + * Platform data structure passed by devices.c file. + */ +struct msp_i2s_platform_data { + t_i2s_controller id; + u32 gpio_alt_func; + u32 msp_tx_dma_addr; + u32 msp_rx_dma_addr; + u32 msp_base_addr; + int (*msp_i2s_init) (u32); + int (*msp_i2s_exit) (u32); +}; + +#endif diff --git a/arch/arm/mach-ux500/include/mach/mtu.h b/arch/arm/mach-ux500/include/mach/mtu.h new file mode 100755 index 00000000000..d3725fec7de --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/mtu.h @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2009 ST-Ericsson + * MultiTimerUnit register definitions, copied from Nomadik 8815 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#ifndef __ASM_ARCH_MTU_H +#define __ASM_ARCH_MTU_H + +/* + * The MTU device hosts four different counters, with 4 set of + * registers. These are register names. + */ + +#define MTU_IMSC 0x00 /* Interrupt mask set/clear */ +#define MTU_RIS 0x04 /* Raw interrupt status */ +#define MTU_MIS 0x08 /* Masked interrupt status */ +#define MTU_ICR 0x0C /* Interrupt clear register */ + +/* per-timer registers take 0..3 as argument */ +#define MTU_LR(x) (0x10 + 0x10 * (x) + 0x00) /* Load value */ +#define MTU_VAL(x) (0x10 + 0x10 * (x) + 0x04) /* Current value */ +#define MTU_CR(x) (0x10 + 0x10 * (x) + 0x08) /* Control reg */ +#define MTU_BGLR(x) (0x10 + 0x10 * (x) + 0x0c) /* At next overflow */ + +/* bits for the control register */ +#define MTU_CRn_ENA 0x80 +#define MTU_CRn_PERIODIC 0x40 /* if 0 = free-running */ +#define MTU_CRn_PRESCALE_MASK 0x0c +#define MTU_CRn_PRESCALE_1 0x00 +#define MTU_CRn_PRESCALE_16 0x04 +#define MTU_CRn_PRESCALE_256 0x08 +#define MTU_CRn_32BITS 0x02 +#define MTU_CRn_ONESHOT 0x01 /* if 0 = wraps reloading from BGLR*/ + +/* Other registers are usual amba/primecell registers, currently not used */ +#define MTU_ITCR 0xff0 +#define MTU_ITOP 0xff4 + +#define MTU_PERIPH_ID0 0xfe0 +#define MTU_PERIPH_ID1 0xfe4 +#define MTU_PERIPH_ID2 0xfe8 +#define MTU_PERIPH_ID3 0xfeC + +#define MTU_PCELL0 0xff0 +#define MTU_PCELL1 0xff4 +#define MTU_PCELL2 0xff8 +#define MTU_PCELL3 0xffC + + +#ifdef CONFIG_LOCAL_TIMERS +extern void __iomem *twd_base; +#endif + +#endif /* __ASM_ARCH_MTU_H */ + diff --git a/arch/arm/mach-ux500/include/mach/prcmu-fw-api.h b/arch/arm/mach-ux500/include/mach/prcmu-fw-api.h new file mode 100755 index 00000000000..02dabe166cb --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/prcmu-fw-api.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2009 ST-Ericsson + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + */ + +#ifndef __MACH_PRCMU_FW_API_H +#define __MACH_PRCMU_FW_API_H + +#include <linux/interrupt.h> +#include "prcmu-fw-defs_v1.h" + +enum hw_acc_dev{ + HW_ACC_SVAMMDSP = 0, + HW_ACC_SVAPIPE = 1, + HW_ACC_SIAMMDSP = 2, + HW_ACC_SIAPIPE = 3, + HW_ACC_SGA = 4, + HW_ACC_B2R2 = 5, + HW_ACC_MCDE = 6, + HW_ACC_ESRAM1 = 7, + HW_ACC_ESRAM2 = 8, + HW_ACC_ESRAM3 = 9, + HW_ACC_ESRAM4 = 10, +}; + +int prcmu_get_boot_status(void); +int prcmu_set_rc_a2p(enum romcode_write_t); +enum romcode_read_t prcmu_get_rc_p2a(void); +int prcmu_set_fifo_4500wu(enum intr_wakeup_t); +enum ap_pwrst_t prcmu_get_xp70_current_state(void); +int prcmu_set_ap_mode(enum ap_pwrst_trans_t); +int prcmu_set_ddr_pwrst(enum ddr_pwrst_t); +int prcmu_set_arm_opp(enum arm_opp_t); +int prcmu_get_arm_opp(void); +int prcmu_set_ape_opp(enum ape_opp_t); +int prcmu_get_ape_opp(void); +int prcmu_set_hwacc(enum hw_acc_dev, enum hw_accst_t); +/*mbox_2_arm_stat_t prcmu_get_m2a_status(void); */ +/*mbox_to_arm_err_t prcmu_get_m2a_error(void); */ +enum dvfs_stat_t prcmu_get_m2a_dvfs_status(void); +enum mbox_2_arm_hwacc_pwr_stat_t prcmu_get_m2a_hwacc_status(void); +int prcmu_set_irq_wakeup(uint32_t); +int prcmu_apply_ap_state_transition(enum ap_pwrst_trans_t transition, + enum ddr_pwrst_t ddr_state_req, + int _4500_fifo_wakeup); + +int prcmu_i2c_read(u8, u8); +int prcmu_i2c_write(u8, u8, u8); +int prcmu_i2c_get_status(void); +int prcmu_i2c_get_bank(void); +int prcmu_i2c_get_reg(void); +int prcmu_i2c_get_val(void); + +int prcmu_ac_wake_req(void); +int prcmu_ac_sleep_req(void); +int prcmu_configure_wakeup_events(u32, u32); +int prcmu_get_wakeup_reason(u32 *, u8 *); +int prcmu_ack_wakeup_reason(void); +void prcmu_set_callback_cawakereq(void (*func)(u8)); +void prcmu_system_reset(void); +int prcmu_is_ca_wake_req_pending(void); +int prcmu_read_ack_mb7(void); +irqreturn_t prcmu_ack_mbox_irq_handler(int, void *); + +#endif /* __MACH_PRCMU_FW_API_V1_H */ diff --git a/arch/arm/mach-ux500/include/mach/prcmu-fw-defs_ed.h b/arch/arm/mach-ux500/include/mach/prcmu-fw-defs_ed.h new file mode 100755 index 00000000000..849bacf0f8f --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/prcmu-fw-defs_ed.h @@ -0,0 +1,415 @@ +/* + * Copyright (c) 2009 ST-Ericsson + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + */ + + + +#ifndef __MACH_PRCMU_FW_DEFS_ED_H +#define __MACH_PRCMU_FW_DEFS_ED_H + +/** + * enum state_t - ON/OFF state definition + * + * OFF: State is ON + * ON: State is OFF + */ +enum state_ed_t { + OFF_ED = 0x00, + ON_ED = 0x01 +}; + +/** + * enum clk_arm_t - ARM Cortex A9 clock schemes + * + * A9_OFF: + * A9_BOOT: + * A9_OPPT1: + * A9_OPPT2: + * A9_EXTCLK: + */ +enum clk_arm_ed_t { + A9_OFF_ED, + A9_BOOT_ED, + A9_OPPT1_ED, + A9_OPPT2_ED, + A9_EXTCLK_ED +}; + +/** + * enum clk_gen_t - GEN#0/GEN#1 clock schemes + * + * GEN_OFF: + * GEN_BOOT: + * GEN_OPPT1: + */ +enum clk_gen_ed_t { + GEN_OFF_ED, + GEN_BOOT_ED, + GEN_OPPT1_ED, +}; + +/* some information between arm and xp70 */ + +/** + * enum romcode_write_t - Romcode message written by A9 AND read by XP70 + * + * RDY_2_DS: Value set when ApDeepSleep state can be executed by XP70 + * RDY_2_XP70_RST: Value set when 0x0F has been successfully polled by the + * romcode. The xp70 will go into self-reset + */ +enum romcode_write_ed_t { + RDY_2_DS_ED = 0x09, + RDY_2_XP70_RST_ED = 0x10 +}; + +/** + * enum romcode_read_t - Romcode message written by XP70 and read by A9 + * + * INIT: Init value when romcode field is not used + * FS_2_DS: Value set when power state is going from ApExecute to + * ApDeepSleep + * END_DS: Value set when ApDeepSleep power state is reached coming from + * ApExecute state + * DS_TO_FS: Value set when power state is going from ApDeepSleep to + * ApExecute + * END_FS: Value set when ApExecute power state is reached coming from + * ApDeepSleep state + * SWR: Value set when power state is going to ApReset + * END_SWR: Value set when the xp70 finished executing ApReset actions and + * waits for romcode acknowledgment to go to self-reset + */ +enum romcode_read_ed_t { + INIT_ED = 0x00, + FS_2_DS_ED = 0x0A, + END_DS_ED = 0x0B, + DS_TO_FS_ED = 0x0C, + END_FS_ED = 0x0D, + SWR_ED = 0x0E, + END_SWR_ED = 0x0F +}; + +/** + * enum ap_pwrst_t - current power states defined in PRCMU firmware + * + * NO_PWRST: Current power state init + * AP_BOOT: Current power state is apBoot + * AP_EXECUTE: Current power state is apExecute + * AP_DEEP_SLEEP: Current power state is apDeepSleep + * AP_SLEEP: Current power state is apSleep + * AP_IDLE: Current power state is apIdle + * AP_RESET: Current power state is apReset + */ +enum ap_pwrst_ed_t { + NO_PWRST_ED = 0x00, + AP_BOOT_ED = 0x01, + AP_EXECUTE_ED = 0x02, + AP_DEEP_SLEEP_ED = 0x03, + AP_SLEEP_ED = 0x04, + AP_IDLE_ED = 0x05, + AP_RESET_ED = 0x06 +}; + +/** + * enum ap_pwrst_trans_t - Transition states defined in PRCMU firmware + * + * NO_TRANSITION: No power state transition + * APEXECUTE_TO_APSLEEP: Power state transition from ApExecute to ApSleep + * APIDLE_TO_APSLEEP: Power state transition from ApIdle to ApSleep + * APBOOT_TO_APEXECUTE: Power state transition from ApBoot to ApExecute + * APEXECUTE_TO_APDEEPSLEEP: Power state transition from ApExecute to + * ApDeepSleep + * APEXECUTE_TO_APIDLE: Power state transition from ApExecute to ApIdle + */ +enum ap_pwrst_trans_ed_t { + NO_TRANSITION_ED = 0x00, + APEXECUTE_TO_APSLEEP_ED = 0xFB, + APIDLE_TO_APSLEEP_ED = 0xFC, + APBOOT_TO_APEXECUTE_ED = 0xFD, + APEXECUTE_TO_APDEEPSLEEP_ED = 0xFE, + APEXECUTE_TO_APIDLE_ED = 0xFF +}; + +/** + * enum ddr_pwrst_t - DDR power states definition + * + * DDR_PWR_STATE_UNCHANGED: SDRAM and DDR controller state is unchanged + * TOBEDEFINED: to be defined + */ +enum ddr_pwrst_ed_t { + DDR_PWR_STATE_UNCHANGED_ED = 0x00, + TOBEDEFINED_ED = 0x01 +}; + +/** + * enum arm_opp_t - ARM OPP states definition + * + * ARM_NO_CHANGE: The ARM operating point is unchanged + * ARM_100_OPP: The new ARM operating point is arm100opp + * ARM_50_OPP: The new ARM operating point is arm100opp + * ARM_EXTCLK: The new ARM operating point is armExtClk + */ +enum arm_opp_ed_t { + ARM_NO_CHANGE_ED = 0x00, + ARM_100_OPP_ED = 0x01, + ARM_50_OPP_ED = 0x02, + ARM_EXTCLK_ED = 0x03 +}; + +/** + * enum ape_opp_t - APE OPP states definition + * + * APE_NO_CHANGE: The APE operating point is unchanged + * APE_100_OPP: The new APE operating point is ape100opp + */ +enum ape_opp_ed_t { + APE_NO_CHANGE_ED = 0x00, + APE_100_OPP_ED = 0x01 +}; + +/** + * enum hw_accst_t - State definition for hardware accelerator + * + * HW_NO_CHANGE: The hardware accelerator state must remain unchanged + * HW_OFF: The hardware accelerator must be switched off + * HW_OFF_RAMRET: The hardware accelerator must be switched off with its + * internal RAM in retention + * HW_ON: The hwa hadware accelerator hwa must be switched on + */ +enum hw_accst_ed_t { + HW_NO_CHANGE_ED = 0x00, + HW_OFF_ED = 0x01, + HW_OFF_RAMRET_ED = 0x02, + HW_ON_ED = 0x03 +}; + +/** + * enum mbox_2_arm_stat_t - Status messages definition for mbox_arm + * + * Status messages definition for mbox_arm coming from XP70 to ARM + * + * BOOT_TO_EXECUTEOK: The apBoot to apExecute state transition has been + * completed + * DEEPSLEEPOK: The apExecute to apDeepSleep state transition has been + * completed + * SLEEPOK: The apExecute to apSleep state transition has been completed + * IDLEOK: The apExecute to apIdle state transition has been completed + * SOFTRESETOK: The A9 watchdog/ SoftReset state has been completed + * SOFTRESETGO : The A9 watchdog/SoftReset state is on going + * BOOT_TO_EXECUTE: The apBoot to apExecute state transition is on going + * EXECUTE_TO_DEEPSLEEP: The apExecute to apDeepSleep state transition is on + * going + * DEEPSLEEP_TO_EXECUTE: The apDeepSleep to apExecute state transition is on + * going + * DEEPSLEEP_TO_EXECUTEOK: The apDeepSleep to apExecute state transition has + * been completed + * EXECUTE_TO_SLEEP: The apExecute to apSleep state transition is on going + * SLEEP_TO_EXECUTE: The apSleep to apExecute state transition is on going + * SLEEP_TO_EXECUTEOK: The apSleep to apExecute state transition has been + * completed + * EXECUTE_TO_IDLE: The apExecute to apIdle state transition is on going + * IDLE_TO_EXECUTE: The apIdle to apExecute state transition is on going + * IDLE_TO_EXECUTEOK: The apIdle to apExecute state transition has been + * completed + * INIT_STATUS: Status init + */ +enum mbox_2_arm_stat_ed_t { + BOOT_TO_EXECUTEOK_ED = 0xFF, + DEEPSLEEPOK_ED = 0xFE, + SLEEPOK_ED = 0xFD, + IDLEOK_ED = 0xFC, + SOFTRESETOK_ED = 0xFB, + SOFTRESETGO_ED = 0xFA, + BOOT_TO_EXECUTE_ED = 0xF9, + EXECUTE_TO_DEEPSLEEP_ED = 0xF8, + DEEPSLEEP_TO_EXECUTE_ED = 0xF7, + DEEPSLEEP_TO_EXECUTEOK_ED = 0xF6, + EXECUTE_TO_SLEEP_ED = 0xF5, + SLEEP_TO_EXECUTE_ED = 0xF4, + SLEEP_TO_EXECUTEOK_ED = 0xF3, + EXECUTE_TO_IDLE_ED = 0xF2, + IDLE_TO_EXECUTE_ED = 0xF1, + IDLE_TO_EXECUTEOK_ED = 0xF0, + INIT_STATUS_ED = 0x00 +}; + +/** + * enum mbox_2_armdvfs_stat_t - DVFS status messages definition + * + * DVFS status messages definition for mbox_arm coming from XP70 to ARM + * DVFS_GO: A state transition DVFS is on going + * DVFS_ARM100OPPOK: The state transition DVFS has been completed for 100OPP + * DVFS_ARM50OPPOK: The state transition DVFS has been completed for 50OPP + * DVFS_ARMEXTCLKOK: The state transition DVFS has been completed for EXTCLK + * DVFS_NOCHGTCLKOK: The state transition DVFS has been completed for + * NOCHGCLK + * DVFS_INITSTATUS: Value init + */ +enum mbox_2_armdvfs_stat_ed_t { + DVFS_GO_ED = 0xFF, + DVFS_ARM100OPPOK_ED = 0xFE, + DVFS_ARM50OPPOK_ED = 0xFD, + DVFS_ARMEXTCLKOK_ED = 0xFC, + DVFS_NOCHGTCLKOK_ED = 0xFB, + DVFS_INITSTATUS_ED = 0x00 +}; + +/** + * enum mbox_2_arm_hwacc_pwr_stat_t - Hardware Accelarator status message + * + * HWACC_PWRST_GO: A state transition on hardware accelerator is on going + * HWACC_PWRST_OK: The state transition on hardware accelerator has been + * completed + * HWACC_PWRSTATUS_INIT: Value init + */ +enum mbox_2_arm_hwacc_pwr_stat_ed_t { + HWACC_PWRST_GO_ED = 0xFF, + HWACC_PWRST_OK_ED = 0xFE, + HWACC_PWRSTATUS_INIT_ED = 0x00 +}; + +/** + * enum sva_mmdsp_stat_t - SVA MMDSP status messages + * + * SVA_MMDSP_GO: SVAMMDSP interrupt has happened + * SVA_MMDSP_INIT: Status init + */ +enum sva_mmdsp_stat_ed_t { + SVA_MMDSP_GO_ED = 0xFF, + SVA_MMDSP_INIT_ED = 0x00 +}; + +/** + * enum sia_mmdsp_stat_t - SIA MMDSP status messages + * + * SIA_MMDSP_GO: SIAMMDSP interrupt has happened + * SIA_MMDSP_INIT: Status init + */ +enum sia_mmdsp_stat_ed_t { + SIA_MMDSP_GO_ED = 0xFF, + SIA_MMDSP_INIT_ED = 0x00 +}; + +/** + * enum intr_wakeup_t - Configure STW4500 FIFO interrupt as wake-up + * + * INTR_NOT_AS_WAKEUP: The 4500 fifo interrupt is not configured as a + * wake-up event + * INTR_AS_WAKEUP: The 4500 fifo interrupt is configured as a wake-up event + */ +enum intr_wakeup_ed_t { + INTR_NOT_AS_WAKEUP_ED = 0x0, + INTR_AS_WAKEUP_ED = 0x1 +} intr_wakeup_ed_t; + +/** + * enum mbox_to_arm_err_t - Error messages definition + * + * Error messages definition for mbox_arm coming from XP70 to ARM + * + * INIT_ERR: Init value + * PLLARMLOCKP_ERR: PLLARM has not been correctly locked in given time + * PLLDDRLOCKP_ERR: PLLDDR has not been correctly locked in the given time + * PLLSOC0LOCKP_ERR: PLLSOC0 has not been correctly locked in the given time + * PLLSOC1LOCKP_ERR: PLLSOC1 has not been correctly locked in the given time + * ARMWFI_ERR: The ARM WFI has not been correctly executed in the given time + * SYSCLKOK_ERR: The SYSCLK is not available in the given time + * BOOT_ERR: Romcode has not validated the XP70 self reset in the given time + * ROMCODESAVECONTEXT: The Romcode didn.t correctly save it secure context + * VARMHIGHSPEEDVALTO_ERR: The ARM high speed supply value transfered + * through I2C has not been correctly executed in the given time + * VARMHIGHSPEEDACCESS_ERR: The command value of VarmHighSpeedVal transfered + * through I2C has not been correctly executed in the given time + * VARMLOWSPEEDVALTO_ERR:The ARM low speed supply value transfered through + * I2C has not been correctly executed in the given time + * VARMLOWSPEEDACCESS_ERR: The command value of VarmLowSpeedVal transfered + * through I2C has not been correctly executed in the given time + * VARMRETENTIONVALTO_ERR: The ARM retention supply value transfered through + * I2C has not been correctly executed in the given time + * VARMRETENTIONACCESS_ERR: The command value of VarmRetentionVal transfered + * through I2C has not been correctly executed in the given time + * VAPEHIGHSPEEDVALTO_ERR: The APE highspeed supply value transfered through + * I2C has not been correctly executed in the given time + * VSAFEHPVALTO_ERR: The SAFE high power supply value transfered through I2C + * has not been correctly executed in the given time + * VMODSEL1VALTO_ERR: The MODEM sel1 supply value transfered through I2C has + * not been correctly executed in the given time + * VMODSEL2VALTO_ERR: The MODEM sel2 supply value transfered through I2C has + * not been correctly executed in the given time + * VARMOFFACCESS_ERR: The command value of Varm ON/OFF transfered through + * I2C has not been correctly executed in the given time + * VAPEOFFACCESS_ERR: The command value of Vape ON/OFF transfered through + * I2C has not been correctly executed in the given time + * VARMRETACCES_ERR: The command value of Varm retention ON/OFF transfered + * through I2C has not been correctly executed in the given time + * CURAPPWRSTISNOTBOOT:Generated when Arm want to do power state transition + * ApBoot to ApExecute but the power current state is not Apboot + * CURAPPWRSTISNOTEXECUTE: Generated when Arm want to do power state + * transition from ApExecute to others power state but the + * power current state is not ApExecute + * CURAPPWRSTISNOTSLEEPMODE: Generated when wake up events are transmitted + * but the power current state is not ApDeepSleep/ApSleep/ApIdle + * CURAPPWRSTISNOTCORRECTDBG: Generated when wake up events are transmitted + * but the power current state is not correct + * ARMREGU1VALTO_ERR:The ArmRegu1 value transferred through I2C has not + * been correctly executed in the given time + * ARMREGU2VALTO_ERR: The ArmRegu2 value transferred through I2C has not + * been correctly executed in the given time + * VAPEREGUVALTO_ERR: The VApeRegu value transfered through I2C has not + * been correctly executed in the given time + * VSMPS3REGUVALTO_ERR: The VSmps3Regu value transfered through I2C has not + * been correctly executed in the given time + * VMODREGUVALTO_ERR: The VModemRegu value transfered through I2C has not + * been correctly executed in the given time + */ +enum mbox_to_arm_err_ed_t { + INIT_ERR_ED = 0x00, + PLLARMLOCKP_ERR_ED = 0x01, + PLLDDRLOCKP_ERR_ED = 0x02, + PLLSOC0LOCKP_ERR_ED = 0x03, + PLLSOC1LOCKP_ERR_ED = 0x04, + ARMWFI_ERR_ED = 0x05, + SYSCLKOK_ERR_ED = 0x06, + BOOT_ERR_ED = 0x07, + ROMCODESAVECONTEXT_ED = 0x08, + VARMHIGHSPEEDVALTO_ERR_ED = 0x10, + VARMHIGHSPEEDACCESS_ERR_ED = 0x11, + VARMLOWSPEEDVALTO_ERR_ED = 0x12, + VARMLOWSPEEDACCESS_ERR_ED = 0x13, + VARMRETENTIONVALTO_ERR_ED = 0x14, + VARMRETENTIONACCESS_ERR_ED = 0x15, + VAPEHIGHSPEEDVALTO_ERR_ED = 0x16, + VSAFEHPVALTO_ERR_ED = 0x17, + VMODSEL1VALTO_ERR_ED = 0x18, + VMODSEL2VALTO_ERR_ED = 0x19, + VARMOFFACCESS_ERR_ED = 0x1A, + VAPEOFFACCESS_ERR_ED = 0x1B, + VARMRETACCES_ERR_ED = 0x1C, + CURAPPWRSTISNOTBOOT_ED = 0x20, + CURAPPWRSTISNOTEXECUTE_ED = 0x21, + CURAPPWRSTISNOTSLEEPMODE_ED = 0x22, + CURAPPWRSTISNOTCORRECTDBG_ED = 0x23, + ARMREGU1VALTO_ERR_ED = 0x24, + ARMREGU2VALTO_ERR_ED = 0x25, + VAPEREGUVALTO_ERR_ED = 0x26, + VSMPS3REGUVALTO_ERR_ED = 0x27, + VMODREGUVALTO_ERR_ED = 0x28 +}; + +enum hw_acc_ed_t { + SVAMMDSP_ED = 0, + SVAPIPE_ED = 1, + SIAMMDSP_ED = 2, + SIAPIPE_ED = 3, + SGA_ED = 4, + B2R2MCDE_ED = 5, + ESRAM1_ED = 6, + ESRAM2_ED = 7, + ESRAM3_ED = 8, + ESRAM4_ED = 9 +} hw_acc_ed_t; + +#endif /* __MACH_PRCMU_FW_API_DEFS_ED_H */ diff --git a/arch/arm/mach-ux500/include/mach/prcmu-fw-defs_v1.h b/arch/arm/mach-ux500/include/mach/prcmu-fw-defs_v1.h new file mode 100755 index 00000000000..c1442a5c9c2 --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/prcmu-fw-defs_v1.h @@ -0,0 +1,549 @@ +/* + * Copyright (c) 2009 ST-Ericsson + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + */ + +#ifndef __MACH_PRCMU_FW_DEFS_V1_H +#define __MACH_PRCMU_FW_DEFS_V1_H + +#include <linux/interrupt.h> + +/** + * enum state_t - ON/OFF state definition + * @OFF: State is ON + * @ON: State is OFF + */ +enum state_t { + OFF = 0x00, + ON = 0x01 +}; +/** + * enum ret_state_t - general purpose On/Off/Retention states + * + */ +enum ret_state_t { + OFFST = 0, + ONST = 1, + RETST = 2 +}; + + +/** + * enum clk_arm_t - ARM Cortex A9 clock schemes + * @A9_OFF: + * @A9_BOOT: + * @A9_OPPT1: + * @A9_OPPT2: + * @A9_EXTCLK: + */ +enum clk_arm_t { + A9_OFF, + A9_BOOT, + A9_OPPT1, + A9_OPPT2, + A9_EXTCLK +}; + +/** + * enum clk_gen_t - GEN#0/GEN#1 clock schemes + * @GEN_OFF: + * @GEN_BOOT: + * @GEN_OPPT1: + */ +enum clk_gen_t { + GEN_OFF, + GEN_BOOT, + GEN_OPPT1, +}; + +/* some information between arm and xp70 */ + +/** + * enum romcode_write_t - Romcode message written by A9 AND read by XP70 + * @RDY_2_DS: Value set when ApDeepSleep state can be executed by XP70 + * @RDY_2_XP70_RST: Value set when 0x0F has been successfully polled by the + * romcode. The xp70 will go into self-reset + */ +enum romcode_write_t { + RDY_2_DS = 0x09, + RDY_2_XP70_RST = 0x10 +}; + +/** + * enum romcode_read_t - Romcode message written by XP70 and read by A9 + * @INIT: Init value when romcode field is not used + * @FS_2_DS: Value set when power state is going from ApExecute to + * ApDeepSleep + * @END_DS: Value set when ApDeepSleep power state is reached coming from + * ApExecute state + * @DS_TO_FS: Value set when power state is going from ApDeepSleep to + * ApExecute + * @END_FS: Value set when ApExecute power state is reached coming from + * ApDeepSleep state + * @SWR: Value set when power state is going to ApReset + * @END_SWR: Value set when the xp70 finished executing ApReset actions and + * waits for romcode acknowledgment to go to self-reset + */ +enum romcode_read_t { + INIT = 0x00, + FS_2_DS = 0x0A, + END_DS = 0x0B, + DS_TO_FS = 0x0C, + END_FS = 0x0D, + SWR = 0x0E, + END_SWR = 0x0F +}; + + +/** + * enum pingpong_t + * @PING: value is 0 + * @PONG: value is 1 + * + * implementation issue: the values are chosen the way that + * we can change from ping to pong (resp. pong to ping) by + * simply using the 'not' operator in C, e.g. toggling operation: + * t_PingPong p = ping; p = ~p; + */ +enum pingpong_t { + PING = 0x00, + PONG = 0xFF +}; + +/** + * enum wkup_reason_fdst_t + * @EVTWR: event has been read by ARM + * @EVTST: event has been sent by PRCMU FW + * @EVTRD: event has been written by PRCMU FW + */ +enum wkup_reason_fdst_t { + /* WRF has been written but neither sent nor read by the arm */ + EVTWR = 1, + /* WRF has been written and sent, but not yet read by the arm */ + EVTST = 2, + /* WRF has been written, sent and read by the arm */ + EVTRD = 0 +}; /* Wake-up reason Field State */ + + + +/** + * enum ap_pwrst_t - current power states defined in PRCMU firmware + * @NO_PWRST: Current power state init + * @AP_BOOT: Current power state is apBoot + * @AP_EXECUTE: Current power state is apExecute + * @AP_DEEP_SLEEP: Current power state is apDeepSleep + * @AP_SLEEP: Current power state is apSleep + * @AP_IDLE: Current power state is apIdle + * @AP_RESET: Current power state is apReset + */ +enum ap_pwrst_t { + NO_PWRST = 0x00, + AP_BOOT = 0x01, + AP_EXECUTE = 0x02, + AP_DEEP_SLEEP = 0x03, + AP_SLEEP = 0x04, + AP_IDLE = 0x05, + AP_RESET = 0x06 +}; + +/** + * enum ap_pwrst_trans_t - Transition states defined in PRCMU firmware + * @NO_TRANSITION: No power state transition + * @APEXECUTE_TO_APSLEEP: Power state transition from ApExecute to ApSleep + * @APIDLE_TO_APSLEEP: Power state transition from ApIdle to ApSleep + * @APBOOT_TO_APEXECUTE: Power state transition from ApBoot to ApExecute + * @APEXECUTE_TO_APDEEPSLEEP: Power state transition from ApExecute to + * ApDeepSleep + * @APEXECUTE_TO_APIDLE: Power state transition from ApExecute to ApIdle + */ +enum ap_pwrst_trans_t { + NO_TRANSITION = 0x00, + APEXECUTE_TO_APSLEEP = 0x01, + APIDLE_TO_APSLEEP = 0x02, + APBOOT_TO_APEXECUTE = 0x03, + APEXECUTE_TO_APDEEPSLEEP = 0x04, + APEXECUTE_TO_APIDLE = 0x05 +}; + +/** + * enum ddr_pwrst_t - DDR power states definition + * @DDR_PWR_STATE_UNCHANGED: SDRAM and DDR controller state is unchanged + * @DDR_PWR_STATE_ON: + * @DDR_PWR_STATE_OFFLOWLAT: + * @DDR_PWR_STATE_OFFHIGHLAT: + */ +enum ddr_pwrst_t { + DDR_PWR_STATE_UNCHANGED = 0x00, + DDR_PWR_STATE_ON = 0x01, + DDR_PWR_STATE_OFFLOWLAT = 0x02, + DDR_PWR_STATE_OFFHIGHLAT = 0x03 +}; + +/** + * enum arm_opp_t - ARM OPP states definition + * @ARM_NO_CHANGE: The ARM operating point is unchanged + * @ARM_100_OPP: The new ARM operating point is arm100opp + * @ARM_50_OPP: The new ARM operating point is arm100opp + * @ARM_EXTCLK: The new ARM operating point is armExtClk + */ +enum arm_opp_t { + ARM_NO_CHANGE = 0x00, + ARM_100_OPP = 0x02, + ARM_50_OPP = 0x03, + ARM_EXTCLK = 0x07 +}; + +/** + * enum ape_opp_t - APE OPP states definition + * @APE_NO_CHANGE: The APE operating point is unchanged + * @APE_100_OPP: The new APE operating point is ape100opp + */ +enum ape_opp_t { + APE_NO_CHANGE = 0x00, + APE_100_OPP = 0x02, + APE_50_OPP = 0x03 +}; + +/** + * enum hw_accst_t - State definition for hardware accelerator + * @HW_NO_CHANGE: The hardware accelerator state must remain unchanged + * @HW_OFF: The hardware accelerator must be switched off + * @HW_OFF_RAMRET: The hardware accelerator must be switched off with its + * internal RAM in retention + * @HW_ON: The hwa hadware accelerator hwa must be switched on + */ +enum hw_accst_t { + HW_NO_CHANGE = 0x00, + HW_OFF = 0x01, + HW_OFF_RAMRET = 0x02, + HW_ON = 0x03 +}; + +/** + * enum mbox_2_arm_stat_t - Status messages definition for mbox_arm + * @BOOT_TO_EXECUTEOK: The apBoot to apExecute state transition has been + * completed + * @DEEPSLEEPOK: The apExecute to apDeepSleep state transition has been + * completed + * @SLEEPOK: The apExecute to apSleep state transition has been completed + * @IDLEOK: The apExecute to apIdle state transition has been completed + * @SOFTRESETOK: The A9 watchdog/ SoftReset state has been completed + * @SOFTRESETGO : The A9 watchdog/SoftReset state is on going + * @BOOT_TO_EXECUTE: The apBoot to apExecute state transition is on going + * @EXECUTE_TO_DEEPSLEEP: The apExecute to apDeepSleep state transition is on + * going + * @DEEPSLEEP_TO_EXECUTE: The apDeepSleep to apExecute state transition is on + * going + * @DEEPSLEEP_TO_EXECUTEOK: The apDeepSleep to apExecute state transition has + * been completed + * @EXECUTE_TO_SLEEP: The apExecute to apSleep state transition is on going + * @SLEEP_TO_EXECUTE: The apSleep to apExecute state transition is on going + * @SLEEP_TO_EXECUTEOK: The apSleep to apExecute state transition has been + * completed + * @EXECUTE_TO_IDLE: The apExecute to apIdle state transition is on going + * @IDLE_TO_EXECUTE: The apIdle to apExecute state transition is on going + * @IDLE_TO_EXECUTEOK: The apIdle to apExecute state transition has been + * completed + * @INIT_STATUS: Status init + */ +enum ap_pwrsttr_status_t { + BOOT_TO_EXECUTEOK = 0xFF, + DEEPSLEEPOK = 0xFE, + SLEEPOK = 0xFD, + IDLEOK = 0xFC, + SOFTRESETOK = 0xFB, + SOFTRESETGO = 0xFA, + BOOT_TO_EXECUTE = 0xF9, + EXECUTE_TO_DEEPSLEEP = 0xF8, + DEEPSLEEP_TO_EXECUTE = 0xF7, + DEEPSLEEP_TO_EXECUTEOK = 0xF6, + EXECUTE_TO_SLEEP = 0xF5, + SLEEP_TO_EXECUTE = 0xF4, + SLEEP_TO_EXECUTEOK = 0xF3, + EXECUTE_TO_IDLE = 0xF2, + IDLE_TO_EXECUTE = 0xF1, + IDLE_TO_EXECUTEOK = 0xF0, + RDYTODS_RETURNTOEXE = 0xEF, + NORDYTODS_RETURNTOEXE = 0xEE, + EXETOSLEEP_RETURNTOEXE = 0xED, + EXETOIDLE_RETURNTOEXE = 0xEC, + INIT_STATUS = 0xEB, + + /*error messages */ + INITERROR = 0x00, + PLLARMLOCKP_ER = 0x01, + PLLDDRLOCKP_ER = 0x02, + PLLSOCLOCKP_ER = 0x03, + PLLSOCK1LOCKP_ER = 0x04, + ARMWFI_ER = 0x05, + SYSCLKOK_ER = 0x06, + I2C_NACK_DATA_ER = 0x07, + BOOT_ER = 0x08, + I2C_STATUS_ALWAYS_1 = 0x0A, + I2C_NACK_REG_ADDR_ER = 0x0B, + I2C_NACK_DATA0123_ER = 0x1B, + I2C_NACK_ADDR_ER = 0x1F, + CURAPPWRSTISNOT_BOOT = 0x20, + CURAPPWRSTISNOT_EXECUTE = 0x21, + CURAPPWRSTISNOT_SLEEPMODE = 0x22, + CURAPPWRSTISNOT_CORRECTFORIT10 = 0x23, + FIFO4500WUISNOT_WUPEVENT = 0x24, + PLL32KLOCKP_ER = 0x29, + DDRDEEPSLEEPOK_ER = 0x2A, + ROMCODEREADY_ER = 0x50, + WUPBEFOREDS = 0x51, + DDRCONFIG_ER = 0x52, + WUPBEFORESLEEP = 0x53, + WUPBEFOREIDLE = 0x54 +}; /* earlier called as mbox_2_arm_stat_t */ + + +/** + * enum dvfs_stat_t - DVFS status messages definition + * @DVFS_GO: A state transition DVFS is on going + * @DVFS_ARM100OPPOK: The state transition DVFS has been completed for 100OPP + * @DVFS_ARM50OPPOK: The state transition DVFS has been completed for 50OPP + * @DVFS_ARMEXTCLKOK: The state transition DVFS has been completed for EXTCLK + * @DVFS_NOCHGTCLKOK: The state transition DVFS has been completed for + * NOCHGCLK + * @DVFS_INITSTATUS: Value init + */ +enum dvfs_stat_t { + DVFS_GO = 0xFF, + DVFS_ARM100OPPOK = 0xFE, + DVFS_ARM50OPPOK = 0xFD, + DVFS_ARMEXTCLKOK = 0xFC, + DVFS_NOCHGTCLKOK = 0xFB, + DVFS_INITSTATUS = 0x00 +}; + +/** + * enum mbox_2_arm_hwacc_pwr_stat_t - Hardware Accelarator status message + * @HWACC_PWRST_GO: A state transition on hardware accelerator is on going + * @HWACC_PWRST_OK: The state transition on hardware accelerator has been + * completed + * @HWACC_PWRSTATUS_INIT: Value init + */ +enum mbox_2_arm_hwacc_pwr_stat_t { + HWACC_PWRST_GO = 0xFF, + HWACC_PWRST_OK = 0xFE, + HWACC_PWRSTATUS_INIT = 0x00 +}; + +/** + * enum sva_mmdsp_stat_t - SVA MMDSP status messages + * @SVA_MMDSP_GO: SVAMMDSP interrupt has happened + * @SVA_MMDSP_INIT: Status init + */ +enum sva_mmdsp_stat_t { + SVA_MMDSP_GO = 0xFF, + SVA_MMDSP_INIT = 0x00 +}; + +/** + * enum sia_mmdsp_stat_t - SIA MMDSP status messages + * @SIA_MMDSP_GO: SIAMMDSP interrupt has happened + * @SIA_MMDSP_INIT: Status init + */ +enum sia_mmdsp_stat_t { + SIA_MMDSP_GO = 0xFF, + SIA_MMDSP_INIT = 0x00 +}; + +/** + * enum intr_wakeup_t - Configure STW4500 FIFO interrupt as wake-up + * @NTR_NOT_AS_WAKEUP: The 4500 fifo interrupt is not configured as a + * wake-up event + * @INTR_AS_WAKEUP: The 4500 fifo interrupt is configured as a wake-up event + */ +enum intr_wakeup_t { + INTR_NOT_AS_WAKEUP = 0x0, + INTR_AS_WAKEUP = 0x1 +}; + +/** + * enum mbox_to_arm_err_t - Error messages definition + * @INIT_ERR: Init value + * @PLLARMLOCKP_ERR: PLLARM has not been correctly locked in given time + * @PLLDDRLOCKP_ERR: PLLDDR has not been correctly locked in the given time + * @PLLSOC0LOCKP_ERR: PLLSOC0 has not been correctly locked in the given time + * @PLLSOC1LOCKP_ERR: PLLSOC1 has not been correctly locked in the given time + * @ARMWFI_ERR: The ARM WFI has not been correctly executed in the given time + * @SYSCLKOK_ERR: The SYSCLK is not available in the given time + * @BOOT_ERR: Romcode has not validated the XP70 self reset in the given time + * @ROMCODESAVECONTEXT: The Romcode didn.t correctly save it secure context + * @VARMHIGHSPEEDVALTO_ERR: The ARM high speed supply value transfered + * through I2C has not been correctly executed in the given time + * @VARMHIGHSPEEDACCESS_ERR: The command value of VarmHighSpeedVal transfered + * through I2C has not been correctly executed in the given time + * @VARMLOWSPEEDVALTO_ERR:The ARM low speed supply value transfered through + * I2C has not been correctly executed in the given time + * @VARMLOWSPEEDACCESS_ERR: The command value of VarmLowSpeedVal transfered + * through I2C has not been correctly executed in the given time + * @VARMRETENTIONVALTO_ERR: The ARM retention supply value transfered through + * I2C has not been correctly executed in the given time + * @VARMRETENTIONACCESS_ERR: The command value of VarmRetentionVal transfered + * through I2C has not been correctly executed in the given time + * @VAPEHIGHSPEEDVALTO_ERR: The APE highspeed supply value transfered through + * I2C has not been correctly executed in the given time + * @VSAFEHPVALTO_ERR: The SAFE high power supply value transfered through I2C + * has not been correctly executed in the given time + * @VMODSEL1VALTO_ERR: The MODEM sel1 supply value transfered through I2C has + * not been correctly executed in the given time + * @VMODSEL2VALTO_ERR: The MODEM sel2 supply value transfered through I2C has + * not been correctly executed in the given time + * @VARMOFFACCESS_ERR: The command value of Varm ON/OFF transfered through + * I2C has not been correctly executed in the given time + * @VAPEOFFACCESS_ERR: The command value of Vape ON/OFF transfered through + * I2C has not been correctly executed in the given time + * @VARMRETACCES_ERR: The command value of Varm retention ON/OFF transfered + * through I2C has not been correctly executed in the given time + * @CURAPPWRSTISNOTBOOT:Generated when Arm want to do power state transition + * ApBoot to ApExecute but the power current state is not Apboot + * @CURAPPWRSTISNOTEXECUTE: Generated when Arm want to do power state + * transition from ApExecute to others power state but the + * power current state is not ApExecute + * @CURAPPWRSTISNOTSLEEPMODE: Generated when wake up events are transmitted + * but the power current state is not ApDeepSleep/ApSleep/ApIdle + * @CURAPPWRSTISNOTCORRECTDBG: Generated when wake up events are transmitted + * but the power current state is not correct + * @ARMREGU1VALTO_ERR:The ArmRegu1 value transferred through I2C has not + * been correctly executed in the given time + * @ARMREGU2VALTO_ERR: The ArmRegu2 value transferred through I2C has not + * been correctly executed in the given time + * @VAPEREGUVALTO_ERR: The VApeRegu value transfered through I2C has not + * been correctly executed in the given time + * @VSMPS3REGUVALTO_ERR: The VSmps3Regu value transfered through I2C has not + * been correctly executed in the given time + * @VMODREGUVALTO_ERR: The VModemRegu value transfered through I2C has not + * been correctly executed in the given time + */ +enum mbox_to_arm_err_t { + INIT_ERR = 0x00, + PLLARMLOCKP_ERR = 0x01, + PLLDDRLOCKP_ERR = 0x02, + PLLSOC0LOCKP_ERR = 0x03, + PLLSOC1LOCKP_ERR = 0x04, + ARMWFI_ERR = 0x05, + SYSCLKOK_ERR = 0x06, + BOOT_ERR = 0x07, + ROMCODESAVECONTEXT = 0x08, + VARMHIGHSPEEDVALTO_ERR = 0x10, + VARMHIGHSPEEDACCESS_ERR = 0x11, + VARMLOWSPEEDVALTO_ERR = 0x12, + VARMLOWSPEEDACCESS_ERR = 0x13, + VARMRETENTIONVALTO_ERR = 0x14, + VARMRETENTIONACCESS_ERR = 0x15, + VAPEHIGHSPEEDVALTO_ERR = 0x16, + VSAFEHPVALTO_ERR = 0x17, + VMODSEL1VALTO_ERR = 0x18, + VMODSEL2VALTO_ERR = 0x19, + VARMOFFACCESS_ERR = 0x1A, + VAPEOFFACCESS_ERR = 0x1B, + VARMRETACCES_ERR = 0x1C, + CURAPPWRSTISNOTBOOT = 0x20, + CURAPPWRSTISNOTEXECUTE = 0x21, + CURAPPWRSTISNOTSLEEPMODE = 0x22, + CURAPPWRSTISNOTCORRECTDBG = 0x23, + ARMREGU1VALTO_ERR = 0x24, + ARMREGU2VALTO_ERR = 0x25, + VAPEREGUVALTO_ERR = 0x26, + VSMPS3REGUVALTO_ERR = 0x27, + VMODREGUVALTO_ERR = 0x28 +}; + +enum hw_acc_t { + SVAMMDSP = 0, + SVAPIPE = 1, + SIAMMDSP = 2, + SIAPIPE = 3, + SGA = 4, + B2R2MCDE = 5, + ESRAM1 = 6, + ESRAM2 = 7, + ESRAM3 = 8, + ESRAM4 = 9 +}; + +enum reqmb0_header_t { + PWRSTTRH = 0, + WKUPCFGH = 1, + WKUPH = 2, + RDWKUPACKH = 3 +}; + +enum cs_pwrmgt_t { + PWRDNCS0 = 0, + WKUPCS0 = 1, + PWRDNCS1 = 2, + WKUPCS1 = 3 +}; + +enum reqmb2_header_t { + DPS_H = 0, + HW_ACCT_AUTO_PWR_H = 1, +}; + +/** + * enum reqmb4_header_t -Header type for mail box 4 + * @MEMSTH: The ARM can set what are the expected memory states depending on + * the AP power states. + * @PARTIALREFRESHH: ARM has to update MR16 & MR17 of SDRAM register, for + * partial-refresh of SDRAM, via this mailbox + * @AUTOREFRESHH: Enable to change cycle count before enabling automatic + * DDR self-refresh + * @CSPWRDNH: Enables to lock/unlock one of SDRAM memory cut in self-refresh + * In V2,this service will enable to put CS in pwrdn + * @SYSCLKH: Enables to switch SYSCLK ON/OFF on the AP side + * @USBWKUPH: Used to enable USB wakeup event of PRCMU + */ +enum reqmb4_header_t { + MEM_ST_H = 0, + PARTIAL_S_REFRESH_H = 1, + AUTO_REFRESH_H = 2, + CS_PWRDN_H = 3, + SYSCLK_H = 5, + AUTO_PWR_H = 6, + USB_WKUP_H = 7 +}; + +enum ack_mb4_status_t { + ACKMB4_INIT = 0, + SYSCLKON_OK = 1, + DDRON_OK = 2 +}; + +enum I2C_op_t { + I2CWRITE = 0, + I2CREAD = 1 +}; + +enum ack_mb5_status_t { + ACKMB5_INIT = 0x00, + I2C_WR_OK = 0x01, + I2C_RD_OK = 0x02, + SYSCLK_OK = 0x03, + I2C_TIMEOUT = 0x11, + SYSCLK_ER = 0x12, + /*Error Status resent by PRCM_HWI2C_SR*/ + I2CWR_NACK_DATA_ER = 0x07, + I2CWR_NACK_REG_ADDR_ER = 0x0B, + I2CRDWR_NACK_DATA0123_ER = 0x1B, + I2CWR_NACK_ADDR_ER = 0x1F, + I2CRD_NACK_ADDR_INIT_ER = 0x0F, + I2CRD_NACK_REG_ADDR_INIT_ER = 0x13, + I2CRD_NACK_ADDR_ER = 0x17 +}; + +enum ack_mb7_status_t { + MOD_SW_RESET_REQ = 0x03, + CA_SLEEP_REQ = 0x02, + HOST_PORT_ACK = 0x01, + ACKMB7_INIT = 0x00 +}; + +#endif /* __MACH_PRCMU_FW_DEFS_V1_H */ diff --git a/arch/arm/mach-ux500/include/mach/prcmu-regs.h b/arch/arm/mach-ux500/include/mach/prcmu-regs.h new file mode 100755 index 00000000000..6f4c36cd7f5 --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/prcmu-regs.h @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2009 ST-Ericsson + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + */ + + + +#ifndef __MACH_PRCMU_REGS_H +#define __MACH_PRCMU_REGS_H + +#include <mach/hardware.h> + +#define _PRCMU_BASE IO_ADDRESS(U8500_PRCMU_BASE) + +#define PRCM_ARM_PLLDIVPS (_PRCMU_BASE + 0x118) +#define PRCM_ARM_CHGCLKREQ (_PRCMU_BASE + 0x114) +#define PRCM_PLLARM_ENABLE (_PRCMU_BASE + 0x98) +#define PRCM_ARMCLKFIX_MGT (_PRCMU_BASE + 0x0) +#define PRCM_A9_RESETN_CLR (_PRCMU_BASE + 0x1f4) +#define PRCM_A9_RESETN_SET (_PRCMU_BASE + 0x1f0) +#define PRCM_ARM_LS_CLAMP (_PRCMU_BASE + 0x30c) +#define PRCM_SRAM_A9 (_PRCMU_BASE + 0x308) + +/* ARM WFI Standby signal register */ +#define PRCM_ARM_WFI_STANDBY (_PRCMU_BASE + 0x130) +#define PRCMU_IOCR (_PRCMU_BASE + 0x310) + + +/* CPU mailbox registers */ +#define PRCM_MBOX_CPU_VAL (_PRCMU_BASE + 0x0fc) +#define PRCM_MBOX_CPU_SET (_PRCMU_BASE + 0x100) +#define PRCM_MBOX_CPU_CLR (_PRCMU_BASE + 0x104) + +/* Dual A9 core interrupt management unit registers */ +#define PRCM_A9_MASK_REQ (_PRCMU_BASE + 0x328) +#define PRCM_A9_MASK_ACK (_PRCMU_BASE + 0x32c) +#define PRCM_ARMITMSK31TO0 (_PRCMU_BASE + 0x11c) +#define PRCM_ARMITMSK63TO32 (_PRCMU_BASE + 0x120) +#define PRCM_ARMITMSK95TO64 (_PRCMU_BASE + 0x124) +#define PRCM_ARMITMSK127TO96 (_PRCMU_BASE + 0x128) +#define PRCM_ARMITVAL31TO0 (_PRCMU_BASE + 0x260) +#define PRCM_ARMITVAL63TO32 (_PRCMU_BASE + 0x264) +#define PRCM_ARMITVAL95TO64 (_PRCMU_BASE + 0x268) +#define PRCM_ARMITVAL127TO96 (_PRCMU_BASE + 0x26C) + +#define PRCM_HOSTACCESS_REQ (_PRCMU_BASE + 0x334) +#define ARM_WAKEUP_MODEM 0x1 + +/* register for Ack mailbox interrupts */ +#define PRCM_ARM_IT1_CLEAR (_PRCMU_BASE + 0x48C) +#define PRCM_ARM_IT1_VAL (_PRCMU_BASE + 0x494) +#define PRCM_HOLD_EVT (_PRCMU_BASE + 0x174) + +#define PRCM_ITSTATUS0 (_PRCMU_BASE + 0x148) +#define PRCM_ITSTATUS1 (_PRCMU_BASE + 0x150) +#define PRCM_ITSTATUS2 (_PRCMU_BASE + 0x158) +#define PRCM_ITSTATUS3 (_PRCMU_BASE + 0x160) +#define PRCM_ITSTATUS4 (_PRCMU_BASE + 0x168) +#define PRCM_ITSTATUS5 (_PRCMU_BASE + 0x484) +#define PRCM_ITCLEAR5 (_PRCMU_BASE + 0x488) +#define PRCM_ARMIT_MASKXP70_IT (_PRCMU_BASE + 0x1018) + +/* System reset register */ +#define PRCM_APE_SOFTRST (_PRCMU_BASE + 0x228) + +/* Clock management */ +#define PRCM_YYCLKEN0_MGT_SET (_PRCMU_BASE + 0x510) +#define PRCM_YYCLKEN1_MGT_SET (_PRCMU_BASE + 0x514) +#define PRCM_YYCLKEN0_MGT_CLR (_PRCMU_BASE + 0x518) +#define PRCM_YYCLKEN1_MGT_CLR (_PRCMU_BASE + 0x51C) +#define PRCM_YYCLKEN0_MGT_VAL (_PRCMU_BASE + 0x520) +#define PRCM_YYCLKEN1_MGT_VAL (_PRCMU_BASE + 0x524) + +#define PRCM_SVAMMDSPCLK_MGT (_PRCMU_BASE + 0x008) +#define PRCM_SIAMMDSPCLK_MGT (_PRCMU_BASE + 0x00C) +#define PRCM_SGACLK_MGT (_PRCMU_BASE + 0x014) +#define PRCM_UARTCLK_MGT (_PRCMU_BASE + 0x018) +#define PRCM_MSP02CLK_MGT (_PRCMU_BASE + 0x01C) +#define PRCM_MSP1CLK_MGT (_PRCMU_BASE + 0x288) +#define PRCM_I2CCLK_MGT (_PRCMU_BASE + 0x020) +#define PRCM_SDMMCCLK_MGT (_PRCMU_BASE + 0x024) +#define PRCM_SLIMCLK_MGT (_PRCMU_BASE + 0x028) +#define PRCM_PER1CLK_MGT (_PRCMU_BASE + 0x02C) +#define PRCM_PER2CLK_MGT (_PRCMU_BASE + 0x030) +#define PRCM_PER3CLK_MGT (_PRCMU_BASE + 0x034) +#define PRCM_PER5CLK_MGT (_PRCMU_BASE + 0x038) +#define PRCM_PER6CLK_MGT (_PRCMU_BASE + 0x03C) +#define PRCM_PER7CLK_MGT (_PRCMU_BASE + 0x040) +#define PRCM_LCDCLK_MGT (_PRCMU_BASE + 0x044) +#define PRCM_BMLCLK_MGT (_PRCMU_BASE + 0x04C) +#define PRCM_HSITXCLK_MGT (_PRCMU_BASE + 0x050) +#define PRCM_HSIRXCLK_MGT (_PRCMU_BASE + 0x054) +#define PRCM_HDMICLK_MGT (_PRCMU_BASE + 0x058) +#define PRCM_APEATCLK_MGT (_PRCMU_BASE + 0x05C) +#define PRCM_APETRACECLK_MGT (_PRCMU_BASE + 0x060) +#define PRCM_MCDECLK_MGT (_PRCMU_BASE + 0x064) +#define PRCM_IPI2CCLK_MGT (_PRCMU_BASE + 0x068) +#define PRCM_DSIALTCLK_MGT (_PRCMU_BASE + 0x06C) +#define PRCM_DMACLK_MGT (_PRCMU_BASE + 0x074) +#define PRCM_B2R2CLK_MGT (_PRCMU_BASE + 0x078) +#define PRCM_TVCLK_MGT (_PRCMU_BASE + 0x07C) +#define PRCM_UNIPROCLK_MGT (_PRCMU_BASE + 0x278) +#define PRCM_SSPCLK_MGT (_PRCMU_BASE + 0x280) +#define PRCM_RNGCLK_MGT (_PRCMU_BASE + 0x284) +#define PRCM_UICCCLK_MGT (_PRCMU_BASE + 0x27C) + +#endif /* __MACH_PRCMU__REGS_H */ diff --git a/arch/arm/mach-ux500/include/mach/scu.h b/arch/arm/mach-ux500/include/mach/scu.h new file mode 100755 index 00000000000..492c98c4810 --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/scu.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2009 ST Ericsson. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __ASMARM_ARCH_SCU_H +#define __ASMARM_ARCH_SCU_H + +#include <mach/hardware.h> + +#define SCU_BASE U8500_SCU_BASE +/* + * * SCU registers + * */ +#define SCU_CTRL 0x00 +#define SCU_CONFIG 0x04 +#define SCU_CPU_STATUS 0x08 +#define SCU_INVALIDATE 0x0c +#define SCU_FPGA_REVISION 0x10 + +#endif diff --git a/arch/arm/mach-ux500/include/mach/setup.h b/arch/arm/mach-ux500/include/mach/setup.h new file mode 100644 index 00000000000..7da8d8d6a92 --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/setup.h @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2009 ST-Ericsson. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * These symbols are needed for board-specific files to call their + * own cpu-specific files + */ +#ifndef __ASM_ARCH_SETUP_H +#define __ASM_ARCH_SETUP_H + +#include <asm/mach/time.h> +#include <linux/init.h> + +struct sys_timer; +struct amba_device; + +extern void __init ux500_map_io(void); +extern void __init u5500_map_io(void); +extern void __init u8500_map_io(void); + +extern void __init ux500_init_devices(void); +extern void __init u5500_init_devices(void); +extern void __init u8500_init_devices(void); +extern void __init u8500_init_regulators(void); + +extern void __init u8500_init_irq(void); + +extern void __init amba_add_devices(struct amba_device *devs[], int num); + +extern struct sys_timer u8500_timer; + +#define __IO_DEV_DESC(x, sz) { \ + .virtual = IO_ADDRESS(x), \ + .pfn = __phys_to_pfn(x), \ + .length = sz, \ + .type = MT_DEVICE, \ +} + +#endif /* __ASM_ARCH_SETUP_H */ diff --git a/arch/arm/mach-ux500/include/mach/shrm.h b/arch/arm/mach-ux500/include/mach/shrm.h new file mode 100755 index 00000000000..99a5608c865 --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/shrm.h @@ -0,0 +1,33 @@ +/*----------------------------------------------------------------------------*/ +/* Copyright (C) ST Ericsson, 2009. */ +/* */ +/* This program is free software; you can redistribute it and/or modify it */ +/* under the terms of the GNU General Public License as published by the Free */ +/* Software Foundation; either version 2.1 of the License, or (at your option */ +/* any later version. */ +/* */ +/* This program is distributed in the hope that it will be useful, but WITHOUT*/ +/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */ +/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for */ +/*more details. */ +/* */ +/* You should have received a copy of the GNU General Public License */ +/* along with this program. If not, see <http://www.gnu.org/licenses/>. */ +/*----------------------------------------------------------------------------*/ + +#ifndef __SHM_DRIVER_IF_H__ +#define __SHM_DRIVER_IF_H__ + +#include <linux/device.h> + +struct shrm_plat_data { + + int *pshm_dev_data; + struct shm_device *shm_ctrlr; +}; + +typedef void (*rx_cb)(void *data, unsigned int length); +typedef void (*received_msg_handler)(unsigned char l2_header, \ + void *msg_ptr, unsigned int length); + +#endif diff --git a/arch/arm/mach-ux500/include/mach/smp.h b/arch/arm/mach-ux500/include/mach/smp.h new file mode 100755 index 00000000000..3c1ec85c7dc --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/smp.h @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2009 ST Ericsson. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#ifndef ASMARM_ARCH_SMP_H +#define ASMARM_ARCH_SMP_H + + +#include <asm/hardware/gic.h> + +#define hard_smp_processor_id() \ + ({ \ + unsigned int cpunum; \ + __asm__("mrc p15, 0, %0, c0, c0, 5" \ + : "=r" (cpunum)); \ + cpunum &= 0x0F; \ + }) + +/* + * We use IRQ1 as the IPI + */ +static inline void smp_cross_call(const struct cpumask *mask) +{ + gic_raise_softirq(mask, 1); +} + +/* + * Do nothing on MPcore. + */ +static inline void smp_cross_call_done(const struct cpumask *mask) +{ +} + +#endif diff --git a/arch/arm/mach-ux500/include/mach/ste_conn_devices.h b/arch/arm/mach-ux500/include/mach/ste_conn_devices.h new file mode 100755 index 00000000000..66846fc5276 --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/ste_conn_devices.h @@ -0,0 +1,227 @@ +/* + * file ste_conn_devices.h + * + * Copyright (C) ST-Ericsson AB 2010 + * + * Board specific device support for the Linux Bluetooth HCI H4 Driver + * for ST-Ericsson connectivity controller. + * License terms: GNU General Public License (GPL), version 2 + * + * Authors: + * Pär-Gunnar Hjälmdahl (par-gunnar.p.hjalmdahl@stericsson.com) for ST-Ericsson. + * Henrik Possung (henrik.possung@stericsson.com) for ST-Ericsson. + * Josef Kindberg (josef.kindberg@stericsson.com) for ST-Ericsson. + * Dariusz Szymszak (dariusz.xd.szymczak@stericsson.com) for ST-Ericsson. + * Kjell Andersson (kjell.k.andersson@stericsson.com) for ST-Ericsson. + */ + +#ifndef _STE_CONN_DEVICES_H_ +#define _STE_CONN_DEVICES_H_ + +#include <linux/types.h> +#include <linux/skbuff.h> + +#define STE_CONN_MAX_NAME_SIZE 30 + +/** STE_CONN_DEVICES_BT_CMD - Bluetooth HCI H4 channel for Bluetooth commands in the ST-Ericsson connectivity controller. + */ +#define STE_CONN_DEVICES_BT_CMD "ste_conn_bt_cmd\0" + +/** STE_CONN_DEVICES_BT_ACL - Bluetooth HCI H4 channel for Bluetooth ACL data in the ST-Ericsson connectivity controller. + */ +#define STE_CONN_DEVICES_BT_ACL "ste_conn_bt_acl\0" + +/** STE_CONN_DEVICES_BT_EVT - Bluetooth HCI H4 channel for Bluetooth events in the ST-Ericsson connectivity controller. + */ +#define STE_CONN_DEVICES_BT_EVT "ste_conn_bt_evt\0" + +/** STE_CONN_DEVICES_FM_RADIO - Bluetooth HCI H4 channel for FM radio in the ST-Ericsson connectivity controller. + */ +#define STE_CONN_DEVICES_FM_RADIO "ste_conn_fm_radio\0" + +/** STE_CONN_DEVICES_GNSS - Bluetooth HCI H4 channel for GNSS in the ST-Ericsson connectivity controller. + */ +#define STE_CONN_DEVICES_GNSS "ste_conn_gnss\0" + +/** STE_CONN_DEVICES_DEBUG - Bluetooth HCI H4 channel for internal debug data in the ST-Ericsson connectivity controller. + */ +#define STE_CONN_DEVICES_DEBUG "ste_conn_debug\0" + +/** STE_CONN_DEVICES_STE_TOOLS - Bluetooth HCI H4 channel for development tools data in the ST-Ericsson connectivity controller. + */ +#define STE_CONN_DEVICES_STE_TOOLS "ste_conn_ste_tools\0" + +/** STE_CONN_DEVICES_HCI_LOGGER - Bluetooth HCI H4 channel for logging all transmitted H4 packets (on all channels). + */ +#define STE_CONN_DEVICES_HCI_LOGGER "ste_conn_hci_logger\0" + +/** STE_CONN_DEVICES_US_CTRL - Bluetooth HCI H:4 channel + * for user space initialization and control of the ST-Ericsson connectivity controller. + */ +#define STE_CONN_DEVICES_US_CTRL "ste_conn_us_ctrl\0" + +/** STE_CONN_DEVICES_BT_AUDIO - Bluetooth HCI H:4 channel + * for Bluetooth audio configuration related commands in the ST-Ericsson connectivity controller. + */ +#define STE_CONN_DEVICES_BT_AUDIO "ste_conn_bt_audio\0" + +/** STE_CONN_DEVICES_FM_RADIO_AUDIO - HCI H:4 channel + * for FM audio configuration related commands in the ST-Ericsson connectivity controller. + */ +#define STE_CONN_DEVICES_FM_RADIO_AUDIO "ste_conn_fm_audio\0" + +/** STE_CONN_DEVICES_CORE- HCI H:4 channel + * for core configuration related commands in the ST-Ericsson connectivity controller. + */ +#define STE_CONN_DEVICES_CORE "ste_conn_core\0" + +/** STE_CONN_NO_CHAR_DEV - Module parameter for + * no character devices to be initiated. + */ +#define STE_CONN_NO_CHAR_DEV 0x00000000 + +/** STE_CONN_CHAR_DEV_BT - Module parameter for character device Bluetooth. + */ +#define STE_CONN_CHAR_DEV_BT 0x00000001 + +/** STE_CONN_CHAR_DEV_FM_RADIO - Module parameter for character device FM radio. + */ +#define STE_CONN_CHAR_DEV_FM_RADIO 0x00000002 + +/** STE_CONN_CHAR_DEV_GNSS - Module parameter for character device GNSS. + */ +#define STE_CONN_CHAR_DEV_GNSS 0x00000004 + +/** STE_CONN_CHAR_DEV_DEBUG - Module parameter for character device Debug. + */ +#define STE_CONN_CHAR_DEV_DEBUG 0x00000008 + +/** STE_CONN_CHAR_DEV_STE_TOOLS - Module parameter for character device STE tools. + */ +#define STE_CONN_CHAR_DEV_STE_TOOLS 0x00000010 + +/** STE_CONN_CHAR_DEV_CCD_DEBUG - Module parameter for character device CCD debug. + */ +#define STE_CONN_CHAR_DEV_CCD_DEBUG 0x00000020 + +/** STE_CONN_CHAR_DEV_HCI_LOGGER - Module parameter for character device HCI logger. + */ +#define STE_CONN_CHAR_DEV_HCI_LOGGER 0x00000040 + +/** STE_CONN_CHAR_DEV_US_CTRL - Module parameter for + * character device user space control. + */ +#define STE_CONN_CHAR_DEV_US_CTRL 0x00000080 + +/** STE_CONN_CHAR_TEST_DEV - Module parameter for character device test device. + */ +#define STE_CONN_CHAR_TEST_DEV 0x00000100 + +/** STE_CONN_CHAR_DEV_BT_AUDIO - Module parameter for character device BT CMD audio application. + */ +#define STE_CONN_CHAR_DEV_BT_AUDIO 0x00000200 + +/** STE_CONN_CHAR_DEV_FM_RADIO_AUDIO - Module parameter for character device FM audio application. + */ +#define STE_CONN_CHAR_DEV_FM_RADIO_AUDIO 0x00000400 + +/** STE_CONN_CHAR_DEV_CORE - Module parameter for character device core. + */ +#define STE_CONN_CHAR_DEV_CORE 0x00000800 + +/** STE_CONN_CHAR_TEST_DEV - Module parameter for all character devices to be initiated. + */ +#define STE_CONN_ALL_CHAR_DEVS 0xFFFFFFFF + +/** + * ste_conn_devices_get_h4_channel() - Get H4 channel by name. + * @name: Name of connectivity user. + * @h4_channel: HCI H4 channel to register to. + * + * Returns: + * 0 if there is no error. + * -ENXIO if channel was not found. + */ +extern int ste_conn_devices_get_h4_channel(char *name, int *h4_channel); + +/** + * ste_conn_devices_enable_chip() - Enable the controller. + */ +extern void ste_conn_devices_enable_chip(void); + +/** + * ste_conn_devices_disable_chip() - Disable the controller. + */ +extern void ste_conn_devices_disable_chip(void); + +/** + * ste_conn_devices_set_hci_revision() - Stores HCI revision info for the connected connectivity controller. + * @hci_version: HCI version from the controller. + * @hci_revision: HCI revision from the controller. + * @lmp_version: LMP version from the controller. + * @lmp_subversion: LMP subversion from the controller. + * @manufacturer: Manufacturer ID from the controller. + * + * See Bluetooth specification and white paper for used controller for details about parameters. + */ +extern void ste_conn_devices_set_hci_revision(uint8_t hci_version, + uint16_t hci_revision, + uint8_t lmp_version, + uint8_t lmp_subversion, + uint16_t manufacturer); + +/** + * ste_conn_devices_get_reset_cmd() - Get HCI reset command to use based on connected connectivity controller. + * @op_lsb: LSB of HCI opcode in generated packet. NULL if not needed. + * @op_msb: MSB of HCI opcode in generated packet. NULL if not needed. + * + * This command does not add the H4 channel header in front of the message. + * + * Returns: + * NULL if no command shall be sent, + * sk_buffer with command otherwise. + */ +extern struct sk_buff *ste_conn_devices_get_reset_cmd(uint8_t *op_lsb, uint8_t *op_msb); + +/** + * ste_conn_devices_get_power_switch_off_cmd() - Get HCI power switch off command to use based on connected connectivity controller. + * @op_lsb: LSB of HCI opcode in generated packet. NULL if not needed. + * @op_msb: MSB of HCI opcode in generated packet. NULL if not needed. + * + * This command does not add the H4 channel header in front of the message. + * + * Returns: + * NULL if no command shall be sent, + * sk_buffer with command otherwise. + */ +extern struct sk_buff *ste_conn_devices_get_power_switch_off_cmd(uint8_t *op_lsb, uint8_t *op_msb); + +/** + * ste_conn_devices_get_bt_enable_cmd() - Get HCI BT enable command to use based on connected connectivity controller. + * @op_lsb: LSB of HCI opcode in generated packet. NULL if not needed. + * @op_msb: MSB of HCI opcode in generated packet. NULL if not needed. + * @bt_enable: true if Bluetooth IP shall be enabled, false otherwise. + * + * This command does not add the H4 channel header in front of the message. + * + * Returns: + * NULL if no command shall be sent, + * sk_buffer with command otherwise. + */ +extern struct sk_buff *ste_conn_devices_get_bt_enable_cmd(uint8_t *op_lsb, uint8_t *op_msb, bool bt_enable); + +/** + * ste_conn_devices_init() - Initialize the board config. + * + * Returns: + * 0 if there is no error. + * Error codes from gpio_request and gpio_direction_output. + */ +extern int ste_conn_devices_init(void); + +/** + * ste_conn_devices_exit() - Exit function for the board config. + */ +extern void ste_conn_devices_exit(void); + +#endif /* _STE_CONN_DEVICES_H_ */ diff --git a/arch/arm/mach-ux500/include/mach/stmpe1601.h b/arch/arm/mach-ux500/include/mach/stmpe1601.h new file mode 100755 index 00000000000..c676f00b343 --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/stmpe1601.h @@ -0,0 +1,290 @@ +/* + * Overview: + * stmpe1601 gpio port expander register definitions + * + * Copyright (C) 2009 ST Ericsson. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License + */ + +#ifndef __STMPE1601_H_ +#define __STMPE1601_H_ + +#include <linux/gpio.h> + +/* + * STMPE interrupt numbers + */ +#if defined(CONFIG_MACH_U8500_MOP) +#define STMPE16010_INTR 218 /*GPIO_PIN_218- TODO*/ +#endif + +/*Register definition*/ + +/*System registers Index*/ +#define CHIP_ID_Index 0x80 +#define VERSION_ID_Index 0x81 +#define SYSCON_Index 0x02 +#define SYSCON_Index_2 0x03 + +/*Interrupt registers Index*/ +#define ICR_Msb_Index 0x10 /*Interrupt Control register*/ +#define ICR_Lsb_Index 0x11 +#define IER_Msb_Index 0x12 /*Interrupt Enable Mask register*/ +#define IER_Lsb_Index 0x13 +#define ISR_Msb_Index 0x14 /*Interrupt Status register*/ +#define ISR_Lsb_Index 0x15 +#define IEGPIOR_Msb_Index 0x16 /*Interrupt Enable GPIO Mask register*/ +#define IEGPIOR_Lsb_Index 0x17 +#define ISGPIOR_Msb_Index 0x18 /*Interrupt Status GPIO registers*/ +#define ISGPIOR_Lsb_Index 0x19 + + +/*Keypad Controller Registers*/ +#define KPC_COL_Index 0x60 /*Keypad column register I2C index*/ +#define KPC_ROW_Msb_Index 0x61 +#define KPC_ROW_Lsb_Index 0x62 +#define KPC_CTRL_Msb_Index 0x63 +#define KPC_CTRL_Lsb_Index 0x64 +#define KPC_COMBI_KEY_0 0x65 +#define KPC_COMBI_KEY_1 0x66 +#define KPC_COMBI_KEY_2 0x67 +#define KPC_DATA_BYTE0_Index 0x68 +#define KPC_DATA_BYTE1_Index 0x69 +#define KPC_DATA_BYTE2_Index 0x6a +#define KPC_DATA_BYTE3_Index 0x6b +#define KPC_DATA_BYTE4_Index 0x6c + +/*Gpio's defines*/ +/*GPIO Set Pin State register Index*/ +#define STMPE1601_GPIO_REG_OFFSET(offset) (0x80 + (offset)) +#define GPSR_Msb_Index STMPE1601_GPIO_REG_OFFSET(0x02) /* 0x82 */ +#define GPSR_Lsb_Index STMPE1601_GPIO_REG_OFFSET(0x03) /* 0x85 */ +/*GPIO Clear Pin State register Index*/ +#define GPCR_Msb_Index STMPE1601_GPIO_REG_OFFSET(0x04) /* 0x86 */ +#define GPCR_Lsb_Index STMPE1601_GPIO_REG_OFFSET(0x05) /* 0x87 */ +/*GPIO Monitor Pin register Index*/ +#define GPMR_Msb_Index STMPE1601_GPIO_REG_OFFSET(0x06) /* 0x88 */ +#define GPMR_Lsb_Index STMPE1601_GPIO_REG_OFFSET(0x07) /* 0x89 */ +/*GPIO Set Pin Direction register*/ +#define GPDR_Msb_Index STMPE1601_GPIO_REG_OFFSET(0x08) /* 0x8A */ +#define GPDR_Lsb_Index STMPE1601_GPIO_REG_OFFSET(0x09) /* 0x8B */ +/*GPIO Edge Detect Status register*/ +#define GPEDR_Msb_Index STMPE1601_GPIO_REG_OFFSET(0x0A) /* 0x8C */ +#define GPEDR_Lsb_Index STMPE1601_GPIO_REG_OFFSET(0x0B) /* 0x8D */ +/*GPIO Rising Edge register*/ +#define GPRER_Msb_Index STMPE1601_GPIO_REG_OFFSET(0x0C) /* 0x8E */ +#define GPRER_Lsb_Index STMPE1601_GPIO_REG_OFFSET(0x0D) /* 0x8F */ +/*GPIO Falling Edge register*/ +#define GPFER_Msb_Index STMPE1601_GPIO_REG_OFFSET(0x0E) /* 0x90 */ +#define GPFER_Lsb_Index STMPE1601_GPIO_REG_OFFSET(0x0F) /* 0x91 */ +/*GPIO Pull Up register*/ +#define GPPUR_Msb_Index STMPE1601_GPIO_REG_OFFSET(0x10) /* 0x92 */ +#define GPPUR_Lsb_Index STMPE1601_GPIO_REG_OFFSET(0x11) /* 0x93 */ + +/*GPIO Alternate Function register*/ +#define GPAFR_U_Msb_Index STMPE1601_GPIO_REG_OFFSET(0x12) /* 0x94 */ +#define GPAFR_U_Lsb_Index STMPE1601_GPIO_REG_OFFSET(0x13) /* 0x95 */ + +#define GPAFR_L_Msb_Index STMPE1601_GPIO_REG_OFFSET(0x14) /* 0x96 */ +#define GPAFR_L_Lsb_Index STMPE1601_GPIO_REG_OFFSET(0x15) /* 0x97 */ +/*Level translator enable register */ +#define GPLT_EN_Index STMPE1601_GPIO_REG_OFFSET(0x16) /* 0x98 */ +/*Level translator direction register */ +#define GPLT_DIR_Index STMPE1601_GPIO_REG_OFFSET(0x17) /* 0x99 */ + +#define STMPE1601_GPIO_INT 15 +#define KEYPAD_INT (STMPE1601_GPIO_INT+1) +#define STMPE1601_MAX_INT KEYPAD_INT + +/*gpio_cfg related define*/ +#define MAX_STMPE1601_GPIO 16 +/*max number of STMPE1601 gpio allowed*/ + +/*keypad related define*/ +#define STMPE1601_SCAN_ON 1 +#define STMPE1601_SCAN_OFF 0 + +#define STMPE1601_MASK_NO_KEY 0x78 /*code for no key*/ + +#define STMPE1601_KEY(col, row) (col + (row << 3)) +/*macro for key definition*/ + +/** +* typedef struct t_stmpe1601_key_config +* Keypad configuration, platform specific settings +*/ +typedef struct { + unsigned short columns; /* bit-field , 1=column used, 0=column + * not used + */ + unsigned short rows; /* bit-field , 1=row used, 0=row not used */ + unsigned char ncycles; /* number of cycles for key data updating */ + unsigned char debounce; /* de-bounce time (0-128)ms */ + unsigned char scan; /* scan status, ON or OFF*/ +} t_stmpe1601_key_config; + +/** +* typedef struct t_stmpe1601_key_status +* Data structure to save key status during last scan. +* E.g., no of keys pressed/released etc +*/ +typedef struct { + unsigned char button_pressed; /* number of button pressed */ + unsigned char button[5]; /* id of buttons, 0 to 77 */ + unsigned char button_released; /* number of button released */ + unsigned char released[5]; /* id of buttons released, 0 to 77 */ +} t_stmpe1601_key_status; + +/** +* typedef struct t_stmpe1601_device_config +* General configuration +*/ +typedef struct { + unsigned char sys_con; + unsigned char sys_con_2; + t_stmpe1601_key_config key_cfg; /*not used*/ +} t_stmpe1601_device_config; + +/** +* typedef struct t_stmpe1601_info +* general device info +*/ +typedef struct { + unsigned char chip_id; + unsigned char version_id; +} t_stmpe1601_info; + +/** +* typedef struct t_stmpe1601_syscon_ds +* data structire to save control register settings +*/ +typedef struct { + unsigned char syscon_data; + unsigned char syscon_2_data; +} t_stmpe1601_syscon_ds; + +/** +* typedef struct t_stmpe1601_interrupt_ds +* data structure to save interrupt controllder register values +*/ +typedef struct { + /*ICR register info*/ + unsigned char icr_msb_data; + unsigned char icr_lsb_data; + + /*IER register info*/ + unsigned char ier_msb_data; + unsigned char ier_lsb_data; + + /*ISR register info*/ + unsigned char isr_msb_data; + unsigned char isr_lsb_data; + + /*IEGPIOR register info*/ + unsigned char iegpior_msb_data; + unsigned char iegpior_lsb_data; + + /*ISGPIOR register info*/ + unsigned char isgpior_msb_data; + unsigned char isgpior_lsb_data; +} t_stmpe1601_interrupt_ds; + +/** +* typedef struct t_stmpe1601_kpc_ds +* Data structure to save kpd controller resgister values +*/ +typedef struct { + unsigned char kpc_col_data; + unsigned char kpc_row_msb_data; + unsigned char kpc_row_lsb_data; + unsigned char kpc_ctrl_msb_data; + unsigned char kpc_ctrl_lsb_data; + unsigned char kpc_data_byte0_data; + unsigned char kpc_data_byte1_data; + unsigned char kpc_data_byte2_data; + unsigned char kpc_data_byte3_data; + unsigned char kpc_data_byte4_data; + unsigned char kpc_data_byte5_data; +} t_stmpe1601_kpc_ds; + +/** +* struct stmpe1601_platform_data +* Pltform data to save gpio base address +* @gpio_base: start index for STMPE1601 expanded gpio: +* 268+24 for u8500 platform +* @irq: Interrupt no. for STMPE1601, For U8500 platform interrupt +* is through GPIO218 +*/ +struct stmpe1601_platform_data { + unsigned gpio_base; + int irq; +}; + +/* +* interrupt handler regiser and unregister functions +*/ + +/** +* stmpe1601_remove_callback() - remove a callback handler +* @irq: gpio number +* This funtion removes the callback handler for the client device +*/ +int stmpe1601_remove_callback(int irq); + +/** +* stmpe1601_set_callback() - install a callback handler +* @irq: gpio number +* @handler: funtion pointer to the callback handler +* @data: data pointer to be passed to the specific handler +* This funtion install the callback handler for the client device +*/ +int stmpe1601_set_callback(int irq, void *handler, void *data); + +/* +* keypad related functions +*/ + +/** + * stmpe1601_keypad_init - initialises Keypad matrix row and columns + * @kpconfig: keypad configuration for a platform + * This function configures keypad control registers of stmpe1601 + * The keypad driver should call this function to configure keypad matrix + * + */ +int stmpe1601_keypad_init(t_stmpe1601_key_config kpconfig); +/** + * stmpe1601_keypad_scan: start/stop keypad scannig + * @status: flag for enable/disable STMPE1601_SCAN_ON or STMPE1601_SCAN_OFF + * + */ +int stmpe1601_keypad_scan(unsigned char status); + +/** + * stmpe1601_keypressed : This function read keypad data registers + * @keys: o/p parameter, returns keys pressed. + * This function can be used in both polling or interrupt usage. + */ +int stmpe1601_keypressed(t_stmpe1601_key_status *keys); +/** + * stmpe1601_read_info() - read the chip information + * This function read stmpe1601 chip and version ID + * and returns error if chip id or version id is not correct. + * This function can be called to check if UIB is connected or not. + */ +int stmpe1601_read_info(void); + +/** +* stmpe1601_irqen() - enables corresponding interrupt mask +* @irq: interrupt no. +*/ +int stmpe1601_irqen(int irq); +/** +* stmpe1601_irqdis() - disables corresponding interrupt mask +* @irq: interrupt no. +**/ +int stmpe1601_irqdis(int irq); + +#endif diff --git a/arch/arm/mach-ux500/include/mach/stmpe2401.h b/arch/arm/mach-ux500/include/mach/stmpe2401.h new file mode 100755 index 00000000000..2a5765d4596 --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/stmpe2401.h @@ -0,0 +1,99 @@ +/* + * Overview: + * stmpe2401 gpio port expander register definitions + * + * Copyright (C) 2009 ST Ericsson. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License + */ +#ifndef __STMPE2401_H_ +#define __STMPE2401_H_ + +#include <linux/gpio.h> + +/*System control registers REG*/ +#define CHIP_ID_REG 0x80 +#define VERSION_ID_REG 0x81 +#define SYSCON_REG 0x02 + +/*Interrupt registers REG*/ +#define ICR_MSB_REG 0x10 +#define ICR_LSB_REG 0x11 +#define IER_MSB_REG 0x12 +#define IER_LSB_REG 0x13 +#define ISR_MSB_REG 0x14 +#define ISR_LSB_REG 0x15 +#define IEGPIOR_MSB_REG 0x16 +#define IEGPIOR_CSB_REG 0x17 +#define IEGPIOR_LSB_REG 0x18 +#define ISGPIOR_MSB_REG 0x19 +#define ISGPIOR_CSB_REG 0x1A +#define ISGPIOR_LSB_REG 0x1B + +/* GPIO Monitor Pin register REG */ +#define GPMR_MSB_REG 0xA2 +#define GPMR_CSB_REG 0xA3 +#define GPMR_LSB_REG 0xA4 + +/* GPIO Set Pin State register REG */ +#define GPSR_MSB_REG 0x83 +#define GPSR_CSB_REG 0x84 +#define GPSR_LSB_REG 0x85 + +/* GPIO Clear Pin State register REG */ +#define GPCR_MSB_REG 0x86 +#define GPCR_CSB_REG 0x87 +#define GPCR_LSB_REG 0x88 + +/* GPIO Set Pin Direction register */ +#define GPDR_MSB_REG 0x89 +#define GPDR_CSB_REG 0x8A +#define GPDR_LSB_REG 0x8B + +/* GPIO Edge Detect Status register */ +#define GPEDR_MSB_REG 0x8C +#define GPEDR_CSB_REG 0x8D +#define GPEDR_LSB_REG 0x8E + +/* GPIO Rising Edge register */ +#define GPRER_MSB_REG 0x8F +#define GPRER_CSB_REG 0x90 +#define GPRER_LSB_REG 0x91 + +/* GPIO Falling Edge register */ +#define GPFER_MSB_REG 0x92 +#define GPFER_CSB_REG 0x93 +#define GPFER_LSB_REG 0x94 + +/* GPIO Pull Up register */ +#define GPPUR_MSB_REG 0x95 +#define GPPUR_CSB_REG 0x96 +#define GPPUR_LSB_REG 0x97 + +/* GPIO Pull Down register */ +#define GPPDR_MSB_REG 0x98 +#define GPPDR_CSB_REG 0x99 +#define GPPDR_LSB_REG 0x9A + +/* GPIO Alternate Function register */ +#define GPAFR_U_MSB_REG 0x9b +#define GPAFR_U_CSB_REG 0x9c +#define GPAFR_U_LSB_REG 0x9d + +#define GPAFR_L_MSB_REG 0x9e +#define GPAFR_L_CSB_REG 0x9f +#define GPAFR_L_LSB_REG 0xA0 + +#define MAX_INT 24 + +struct stmpe2401_platform_data { + unsigned gpio_base; + int irq; +}; + +int stmpe2401_remove_callback(int irq); +int stmpe2401_set_callback(int irq, void *handler, void *data); + +#endif diff --git a/arch/arm/mach-ux500/include/mach/system.h b/arch/arm/mach-ux500/include/mach/system.h new file mode 100755 index 00000000000..dd2e7277d93 --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/system.h @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2009 ST Ericsson. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ +#ifndef __ASM_ARCH_SYSTEM_H +#define __ASM_ARCH_SYSTEM_H + +#include <mach/prcmu-fw-api.h> + +static inline void arch_idle(void) +{ + /* + * This should do all the clock switching + * and wait for interrupt tricks + */ + cpu_do_idle(); +} + +static inline void arch_reset(char mode) +{ +#ifdef CONFIG_UX500_SOC_DB8500 + prcmu_system_reset(); +#endif +} + +#endif diff --git a/arch/arm/mach-ux500/include/mach/tc35892.h b/arch/arm/mach-ux500/include/mach/tc35892.h new file mode 100755 index 00000000000..ede0ea47d32 --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/tc35892.h @@ -0,0 +1,183 @@ +/* + * Overview: + * tc35892 gpio port expander register definitions + * + * Copyright (C) 2009 ST Ericsson. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#ifndef __TC35892_H_ +#define __Tc35892_H_ + +#include <linux/gpio.h> + +/*System registers Index*/ + +#define MANFACTURE_Code_Index 0x80 +#define VERSION_ID_Index 0x81 +#define IOCFG_Index 0xA7 + +/*clock control registers*/ + +#define CLKMODE_Index 0x88 +#define CLKCFG_Index 0x89 +#define CLKEN_Index 0x8A + +/*Reset Control registers*/ + +#define RSTCTRL_Index 0x82 +#define EXTRSTN_Index 0x83 +#define RSTINTCLR_index 0x84 + +#define GPIO_OFFSET + +/* Interrupt registers Index*/ + +#define GPIO_IS0_Index 0xC9 +#define GPIO_IS1_Index 0xCA +#define GPIO_IS2_Index 0xCB + +#define GPIO_IBE0_Index 0xCC +#define GPIO_IBE1_Index 0xCD +#define GPIO_IBE2_Index 0xCE + +#define GPIO_IEV0_Index 0xCF +#define GPIO_IEV1_Index 0xD0 +#define GPIO_IEV2_Index 0xD1 + +#define GPIO_IE0_Index 0xD2 +#define GPIO_IE1_Index 0xD3 +#define GPIO_IE2_Index 0xD4 + +#define GPIO_RIS0_Index 0xD6 +#define GPIO_RIS1_Index 0xD7 +#define GPIO_RIS2_Index 0xD8 + +#define GPIO_MIS0_Index 0xD9 +#define GPIO_MIS1_Index 0xDA +#define GPIO_MIS2_Index 0xDB + +#define GPIO_IC0_Index 0xDC +#define GPIO_IC1_Index 0xDD +#define GPIO_IC2_Index 0xDE + + +/*GPIO's defines*/ +/*GPIO data register Index*/ +#define GPIO_DATA0_Index 0xC0 +#define GPIO_MASK0_Index 0xc1 + +#define GPIO_DATA1_Index 0xC2 +#define GPIO_MASK1_Index 0xc3 + +#define GPIO_DATA2_Index 0xC4 +#define GPIO_MASK2_Index 0xC5 + +/* GPIO direction register Index*/ + +#define GPIO_DIR0_Index 0xC6 +#define GPIO_DIR1_Index 0xC7 +#define GPIO_DIR2_Index 0xC8 + +/* GPIO Sync registers*/ + +#define GPIO_SYNC0_Index 0xE6 +#define GPIO_SYNC1_Index 0xE7 +#define GPIO_SYNC2_Index 0xE8 + +/*GPIO Wakeup registers*/ +#define GPIO_WAKE0_Index 0xE9 +#define GPIO_WAKE1_Index 0xEA +#define GPIO_WAKE2_Index 0xEB + +/*GPIO OpenDrain registers*/ +#define GPIO_ODM0_Index 0xE0 +#define GPIO_ODE0_Index 0xE1 +#define GPIO_ODM1_Index 0xE2 +#define GPIO_ODE1_Index 0xE3 +#define GPIO_ODM2_Index 0xE4 +#define GPIO_ODE2_Index 0xE5 + +/*PULL UP REGISTERS*/ +#define IOPC0_Index 0xAA +#define IOPC1_Index 0xAC +#define IOPC2_Index 0xAE + + + +#define MAX_TC35892_GPIO 24 + +#define MAX_INT_EXP 24 + +#define HIGH 1 +#define LOW 0 + +#define EDGE_SENSITIVE 0 +#define LEVEl_SENSITIVE 1 + +#define DISABLE_INTERRUPT 0 +#define ENABLE_INTERRUPT 1 + +#define TC35892_FALLING_EDGE_OR_LOWLEVEL 1 +#define TC35892_RISING_EDGE_OR_HIGHLEVEL 2 +#define TC35892_BOTH_EDGE 3 + +typedef enum { + EGPIO_PIN_0 = 268, + EGPIO_PIN_1, + EGPIO_PIN_2, + EGPIO_PIN_3, + EGPIO_PIN_4, + EGPIO_PIN_5, + EGPIO_PIN_6, + EGPIO_PIN_7, + EGPIO_PIN_8, + EGPIO_PIN_9, + EGPIO_PIN_10, + EGPIO_PIN_11, + EGPIO_PIN_12, + EGPIO_PIN_13, + EGPIO_PIN_14, + EGPIO_PIN_15, + EGPIO_PIN_16, + EGPIO_PIN_17, + EGPIO_PIN_18, + EGPIO_PIN_19, + EGPIO_PIN_20, + EGPIO_PIN_21, + EGPIO_PIN_22, + EGPIO_PIN_23 +} egpio_pin; + +typedef enum +{ + TC35892_OK = 0, + TC35892_BAD_PARAMETER = -2, + TC35892_FEAT_NOT_SUPPORTED = -3, + TC35892_INTERNAL_ERROR = -4, + TC35892_TIMEOUT_ERROR = -5, + TC35892_INITIALIZATION_ERROR = -6, + TC35892_I2C_ERROR = -7, + TC35892_ERROR = -8 +} t_tc35892_error; + +/** + * struct tc35892_platform_data - tc35892 platform dependent structure + * @gpio_base: starting number of the gpio pin + * @irq: irq number of the port expander + * + * tc35892 platfoem dependent structure + **/ +struct tc35892_platform_data { + unsigned gpio_base; + int irq; +}; + +int tc35892_remove_callback(int irq); +int tc35892_set_callback(int irq, void *handler, void *data); +t_tc35892_error tc35892_set_intr_enable (int pin_index,unsigned char intr_enable_disable); +t_tc35892_error tc35892_set_gpio_intr_conf (int pin_index,unsigned char edge_level_sensitive, unsigned char edge_level_type); +#endif diff --git a/arch/arm/mach-ux500/include/mach/timex.h b/arch/arm/mach-ux500/include/mach/timex.h new file mode 100755 index 00000000000..d43d0d73fbc --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/timex.h @@ -0,0 +1,13 @@ +#ifndef __ASM_ARCH_TIMEX_H +#define __ASM_ARCH_TIMEX_H + +/* + * This is incorrect for ED. Don't use in platform code. + * + * In generic code, this is only used in include/linux/jiffies.h to calculate + * ACTHZ. The value of ACTHZ stays the same whether CLOCK_TICK_RATE is + * 133.33Mhz or 100Mhz, so we leave it at 133.33Mhz. + */ +#define CLOCK_TICK_RATE 133330000 + +#endif diff --git a/arch/arm/mach-ux500/include/mach/u8500_acodec_ab8500.h b/arch/arm/mach-ux500/include/mach/u8500_acodec_ab8500.h new file mode 100755 index 00000000000..f92eaff759f --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/u8500_acodec_ab8500.h @@ -0,0 +1,227 @@ +/* Header file for u8500 audiocodec specific data structures, enums + * and private & public functions. + * Author: Deepak Karda + * Copyright (C) 2009 ST-Ericsson Pvt. Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef _U8500_ACODEC_STN4500_H_ +#define _U8500_ACODEC_STN4500_H_ + +#include <mach/ab8500_codec_p.h> +#include <mach/ab8500_codec.h> +#include <mach/ab8500.h> + +#define NUMBER_OUTPUT_DEVICE 5 +#define NUMBER_INPUT_DEVICE 10 +#define NUMBER_LOOPBACK_STATE 2 +#define NUMBER_SWITCH_STATE 2 +#define NUMBER_POWER_STATE 2 +#define NUMBER_TDM_MODE_STATE 2 +#define NUMBER_DIRECT_RENDERING_STATE 2 +#define NUMBER_PCM_RENDERING_STATE 3 + + +#define CODEC_MUTE 0x20 +#define DEFAULT_VOLUME 0x64 +#define DEFAULT_GAIN 0x32 +#define VOL_MAX 0x64 +#define VOL_MIN 0x00 +#define DEFAULT_OUTPUT_DEVICE AB8500_CODEC_DEST_HEADSET +#define DEFAULT_INPUT_DEVICE AB8500_CODEC_SRC_D_MICROPHONE_3 +#define DEFAULT_LOOPBACK_STATE DISABLE +#define DEFAULT_SWITCH_STATE DISABLE +#define DEFAULT_TDM8_CH_MODE_STATE DISABLE +#define DEFAULT_DIRECT_RENDERING_STATE DISABLE +#define DEFAULT_BURST_FIFO_STATE RENDERING_DISABLE +#define DEFAULT_FM_PLAYBACK_STATE RENDERING_DISABLE +#define DEFAULT_FM_TX_STATE RENDERING_DISABLE + + + +#define MIN_RATE_PLAYBACK 48000 +#define MAX_RATE_PLAYBACK 48000 +#define MIN_RATE_CAPTURE 48000 +#define MAX_RATE_CAPTURE 48000 +#define MAX_NO_OF_RATES 1 + +#define ALSA_MSP_BT_NUM 0 +#define ALSA_MSP_PCM_NUM 1 +#define ALSA_MSP_HDMI_NUM 2 + +typedef enum +{ + DISABLE, + ENABLE +}t_u8500_bool_state; + +typedef enum +{ + RENDERING_DISABLE, + RENDERING_ENABLE, + RENDERING_PENDING +}t_u8500_pmc_rendering_state; + +typedef enum +{ + ACODEC_CONFIG_REQUIRED, + ACODEC_CONFIG_NOT_REQUIRED +}t_u8500_acodec_config_need; + +typedef enum +{ + CLASSICAL_MODE, + TDM_8_CH_MODE +}t_u8500_mode; + + +typedef struct { + unsigned int left_volume; + unsigned int right_volume; + unsigned int mute_state; + t_u8500_bool_state power_state; +}u8500_io_dev_config_t; + +typedef enum { + NO_USER = 0, + USER_ALSA = 2, /*To make it equivalent to user id for MSP*/ + USER_SAA, +}t_acodec_user; + +typedef struct { + u8500_io_dev_config_t output_config[NUMBER_OUTPUT_DEVICE]; + u8500_io_dev_config_t input_config[NUMBER_INPUT_DEVICE]; + //t_acodec_user user; + t_acodec_user cur_user; +}t_u8500_codec_system_context; + +typedef enum { + T_CODEC_SAMPLING_FREQ_48KHZ = 48, +} acodec_sample_frequency; + + +struct acodec_configuration +{ + t_ab8500_codec_direction direction; + acodec_sample_frequency input_frequency; + acodec_sample_frequency output_frequency; + codec_msp_srg_clock_sel_type mspClockSel; + codec_msp_in_clock_freq_type mspInClockFreq; + u32 channels; + t_acodec_user user; + t_u8500_acodec_config_need acodec_config_need; + t_u8500_bool_state direct_rendering_mode; + irqreturn_t (*handler)(void *data, int irq); + void *tx_callback_data; + void *rx_callback_data; +}; + +typedef enum +{ + ACODEC_DISABLE_ALL, + ACODEC_DISABLE_TRANSMIT, + ACODEC_DISABLE_RECEIVE, +}t_acodec_disable; + +/*extern t_ab8500_codec_error u8500_acodec_set_volume(int input_vol_left, + int input_vol_right, + int output_vol_left, + int output_vol_right, t_acodec_user user);*/ + +extern t_ab8500_codec_error u8500_acodec_open(int stream_id); +//extern t_ab8500_codec_error u8500_acodec_pause_transfer(void); +//extern t_ab8500_codec_error u8500_acodec_unpause_transfer(void); +extern t_ab8500_codec_error u8500_acodec_send_data(void *data, size_t bytes, int dma_flag); +extern t_ab8500_codec_error u8500_acodec_receive_data(void *data, size_t bytes, int dma_flag); +extern t_ab8500_codec_error u8500_acodec_close(t_acodec_disable flag); + +extern t_ab8500_codec_error u8500_acodec_set_output_volume(t_ab8500_codec_dest dest_device, + int left_volume, + int right_volume, + t_acodec_user user); + +extern t_ab8500_codec_error u8500_acodec_get_output_volume(t_ab8500_codec_dest dest_device, + int *p_left_volume, + int *p_right_volume, + t_acodec_user user); + +extern t_ab8500_codec_error u8500_acodec_set_input_volume(t_ab8500_codec_src src_device, + int left_volume, + int right_volume, + t_acodec_user user); + +extern t_ab8500_codec_error u8500_acodec_get_input_volume(t_ab8500_codec_src src_device, + int *p_left_volume, + int *p_right_volume, + t_acodec_user user); + +extern t_ab8500_codec_error u8500_acodec_toggle_analog_lpbk(t_u8500_bool_state lpbk_state, + t_acodec_user user); + +extern t_ab8500_codec_error u8500_acodec_toggle_digital_lpbk(t_u8500_bool_state lpbk_state, + t_acodec_user user); + +extern t_ab8500_codec_error u8500_acodec_toggle_playback_mute_control(t_ab8500_codec_dest dest_device, + t_u8500_bool_state mute_state, + t_acodec_user user); +extern t_ab8500_codec_error u8500_acodec_toggle_capture_mute_control(t_ab8500_codec_src src_device, + t_u8500_bool_state mute_state, + t_acodec_user user); + +extern t_ab8500_codec_error u8500_acodec_enable_audio_mode(struct acodec_configuration *acodec_config); +/*extern t_ab8500_codec_error u8500_acodec_enable_voice_mode(struct acodec_configuration *acodec_config);*/ + + +extern t_ab8500_codec_error u8500_acodec_select_input(t_ab8500_codec_src input_device, t_acodec_user user); +extern t_ab8500_codec_error u8500_acodec_select_output(t_ab8500_codec_dest output_device, t_acodec_user user); + +extern t_ab8500_codec_error u8500_acodec_allocate_ad_slot(t_ab8500_codec_src input_device,t_u8500_mode mode); +extern t_ab8500_codec_error u8500_acodec_unallocate_ad_slot(t_ab8500_codec_src input_device,t_u8500_mode mode); +extern t_ab8500_codec_error u8500_acodec_allocate_da_slot(t_ab8500_codec_dest output_device,t_u8500_mode mode); +extern t_ab8500_codec_error u8500_acodec_unallocate_da_slot(t_ab8500_codec_dest output_device,t_u8500_mode mode); + +extern t_ab8500_codec_error u8500_acodec_set_src_power_cntrl(t_ab8500_codec_src input_device,t_u8500_bool_state pwr_state); +extern t_ab8500_codec_error u8500_acodec_set_dest_power_cntrl(t_ab8500_codec_dest output_device,t_u8500_bool_state pwr_state); + +extern t_u8500_bool_state u8500_acodec_get_src_power_state(t_ab8500_codec_src input_device); +extern t_u8500_bool_state u8500_acodec_get_dest_power_state(t_ab8500_codec_dest output_device); +extern t_ab8500_codec_error u8500_acodec_set_burst_mode_fifo(t_u8500_pmc_rendering_state fifo_state); + +extern t_ab8500_codec_error u8500_acodec_unsetuser(t_acodec_user user); +extern t_ab8500_codec_error u8500_acodec_setuser(t_acodec_user user); + +extern void codec_power_init(void); +extern void u8500_acodec_powerdown(void); + +//t_ab8500_codec_error acodec_msp_enable(t_touareg_codec_sample_frequency freq,int channels, t_acodec_user user); + + + +#define TRG_CODEC_ADDRESS_ON_SPI_BUS (0x0D) + +extern int ab8500_write(u8 block, u32 adr, u8 data); +extern int ab8500_read(u8 block, u32 adr); + +#if 0 + #define FUNC_ENTER() printk("\n -Enter : %s",__FUNCTION__) + #define FUNC_EXIT() printk("\n -Exit : %s",__FUNCTION__) +#else + #define FUNC_ENTER() + #define FUNC_EXIT() +#endif +#endif + diff --git a/arch/arm/mach-ux500/include/mach/u8500_tsc.h b/arch/arm/mach-ux500/include/mach/u8500_tsc.h new file mode 100755 index 00000000000..f7ba97992bc --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/u8500_tsc.h @@ -0,0 +1,216 @@ +/* + * Overview: + * Touch panel register definitions + * + * Copyright (C) 2009 ST Ericsson + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + + + +#ifndef _TOUCHP_NOMADIK_H +#define _TOUCHP_NOMADIK_H + +#include <mach/hardware.h> + +/** + * Touchpanel related macros declaration + */ +#define I2C3_TOUCHP_ADDRESS 0x5C/* I2C slave address */ +#define TOUCHP_IRQ 271/* PENIRQNO egpio3 */ +#define TOUCHP_CS0 270/* Chip select egpio2 */ + +#define DRIVER_TP1 "u8500_tp1" +/* + *TOUCH SCREEN DRIVER MACROS used for Power on Sequence + */ +#define TSC_INT_CLR 0xE8 +#define TSC_INT_MODE 0xE9 +#define TSC_GAIN 0xEA +#define TSC_OFFSET_MODE 0xEB +#define TSC_XY_EDGE 0xEC +#define TSC_RESET 0xED +#define TSC_CALIB 0xEE +#define TSC_DONE 0xEF +#define TSC_SENSOR_0_7 0xF0 +#define TSC_SENSOR_8_15 0xF1 +#define TSC_SENSOR_16_23 0xF2 +#define TSC_POS_MODE1 0xF3 +#define TSC_POS_MODE2 0xF4 +#define TSC_CLK_MODE 0xF5 +#define TSC_IDLE 0xFA +#define TSC_FILTER 0xFB +#define TSC_TH_ON 0xFC +#define TSC_TH_OFF 0xFD +#define TSC_INTR_STATUS 0x7B + +#define MAX_10BIT ((1<<10)-1) + +/* + * Resolutions + */ +/*Panel Resolution, Target size. (864*480)*/ +#define X_MAX (480) +#define Y_MAX (864) + +/*Touchpanel Resolution */ +#define TOUCH_XMAX 384 +#define TOUCH_YMAX 704 + +#define TRUE (1) +#define FALSE (0) + +#define SET (1) +#define CLR (0) + +#define START (0) +#define STOP (-1) + +/*Direction Indicator */ +#define DIR_INVALID (0) +#define DIR_LEFT (1) +#define DIR_RIGHT (2) +#define DIR_UP (3) +#define DIR_DOWN (4) + +/* Pinch */ +#define PINCH_KEEP (0) +#define PINCH_IN (1) +#define PINCH_OUT (2) + +/* Rotate */ +#define ROTATE_INVALID (0) +#define ROTATE_R_UR (1) +#define ROTATE_R_RD (2) +#define ROTATE_R_DL (3) +#define ROTATE_R_LU (4) +#define ROTATE_L_LD (5) +#define ROTATE_L_DR (6) +#define ROTATE_L_RU (7) +#define ROTATE_L_UL (8) + +/* Gesture Information */ +#define GES_FLICK 0x01 +#define GES_TAP 0x02 +#define GES_PINCH 0x03 +#define GES_DRAGDROP 0x04 +#define GES_TOUCHSTART 0x05 +#define GES_TOUCHEND 0x06 +#define GES_MOVE 0x07 +#define GES_ROTATE 0x08 +#define GES_UNKNOWN 0xff + +/* Tap times */ +#define TAP_SINGLE 0x01 +#define TAP_DOUBLE 0x02 +#define TAP_TRIPLE 0x03 + +/* Speed */ +#define LOWSPEED 1 +#define HIGHSPEED 2 +#define THRESHOLD_TAPLIMIT 60 +#define THRESHOLD_FLICK 60 +#define THRESHOLD_FLICK_SPEED 300 +#define THRESHOLD_PINCH_SPEED 3000 +#define THRESHOLD_DRAGDROP 100 +#define THRESHOLD_ROTATE 3 +#define THRESHOLD_ROTATE_HIST 8 +#define THRESHOLD_PINCH 500 +#define DIRHEADER 6 +#define DIRTRACEN 32 +#define SMA_N 80 +#define SMA_ARRAY 81 +#define THRESHOLD_SMA_N SMA_N +#define MULTITOUCH_SIN_N 6 +#define PENUP_TIMEOUT 10 /* msec */ + +/** + * Error handling messages + **/ +typedef enum { + TSC_OK = 0, + TSC_BAD_PARAMETER = -2, + TSC_FEAT_NOT_SUPPORTED = -3, + TSC_INTERNAL_ERROR = -4, + TSC_TIMEOUT_ERROR = -5, + TSC_INITIALIZATION_ERROR = -6, + TSC_I2C_ERROR = -7, + TSC_ERROR = -8 +} tsc_error; + +/** + * struct tp_device + * This is used to handle the platform data + **/ +struct tp_device { + int (*cs_en)(void); + int (*cs_dis)(void); + int (*irq_init)(void (*callback)(void *parameter), void *p); + int (*irq_exit)(void); + int (*pirq_en) (void); + int (*pirq_dis)(void); + int (*pirq_read_val)(void); + int (*board_href_v1)(void); + unsigned int irq; +}; + +/** + * struct touch_point + * This is used to hold the x and y co-ordinates of touch panel + **/ +struct touch_point { + signed short x; + signed short y; +}; + +/** + * struct gesture_info + * This is used to hold the gesture of the touch. + **/ +struct gesture_info { + signed short gesture_kind; + struct touch_point pt[2]; + signed short dir; + signed short times; + signed short speed; +}; + +struct u8500_tsc_data { + struct i2c_client *client; + struct tp_device *chip; + struct input_dev *pin_dev; + struct task_struct *touchp_tsk; + struct timer_list penirq_timer; + wait_queue_head_t touchp_event; + unsigned short touch_en; + struct work_struct workq; + struct gesture_info gesture_info; + signed long touch_count; + unsigned short touchflag; + bool touchp_flag; + unsigned char pre_tap_flag; + unsigned char flick_flag; + unsigned char touch_continue; + unsigned char pre_tap_flag_level; + signed short x1, y1; + signed short x2, y2; + unsigned char pinch_start; + struct touch_point tap_start_point; + unsigned char dir_trace[DIRHEADER+DIRTRACEN]; + unsigned char dir_idx; + unsigned char rotate_data[5][5]; + bool href_v1_flag; +}; + +int doCalibrate(struct i2c_client *i2c); +int getCalibStatus(struct i2c_client *i2c); +void init_config(struct u8500_tsc_data *data); +void get_touch(struct u8500_tsc_data *data); +void touch_calculation(struct gesture_info *p_gesture_info); +int get_touch_message(struct u8500_tsc_data *data); +void check_board(struct u8500_tsc_data *data); +#endif diff --git a/arch/arm/mach-ux500/include/mach/uart.h b/arch/arm/mach-ux500/include/mach/uart.h new file mode 100755 index 00000000000..a2dc5715bfe --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/uart.h @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2009 ST-Ericsson. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef _U8500_UART_H_ +#define _U8500_UART_H_ + +struct uart_amba_plat_data { + void (*init) (void); + void (*exit) (void); +}; + +#endif /* _U8500_UART_H_ */ diff --git a/arch/arm/mach-ux500/include/mach/uncompress.h b/arch/arm/mach-ux500/include/mach/uncompress.h new file mode 100755 index 00000000000..b2c9a5b3d97 --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/uncompress.h @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2009 ST Ericsson + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_UNCOMPRESS_H +#define __ASM_ARCH_UNCOMPRESS_H + +#include <asm/setup.h> +#include <linux/io.h> +#include <mach/hardware.h> + +#define U8500_UART_DR 0x80007000 +#define U8500_UART_LCRH 0x8000702c +#define U8500_UART_CR 0x80007030 +#define U8500_UART_FR 0x80007018 + +static void putc(const char c) +{ + /* Do nothing if the UART is not enabled. */ + if (!(readb(U8500_UART_CR) & 0x1)) + return; + + if (c == '\n') + putc('\r'); + + while (readb(U8500_UART_FR) & (1 << 5)) + barrier(); + writeb(c, U8500_UART_DR); +} + +static void flush(void) +{ + if (!(readb(U8500_UART_CR) & 0x1)) + return; + while (readb(U8500_UART_FR) & (1 << 3)) + barrier(); +} + +static inline void arch_decomp_setup(void) +{ +} + +#define arch_decomp_wdog() /* nothing to do here */ + +#endif /* __ASM_ARCH_UNCOMPRESS_H */ diff --git a/arch/arm/mach-ux500/include/mach/vmalloc.h b/arch/arm/mach-ux500/include/mach/vmalloc.h new file mode 100755 index 00000000000..86cdbbce184 --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/vmalloc.h @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2009 ST-Ericsson + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#define VMALLOC_END 0xf0000000 diff --git a/arch/arm/mach-ux500/localtimer.c b/arch/arm/mach-ux500/localtimer.c new file mode 100755 index 00000000000..b59e14697ca --- /dev/null +++ b/arch/arm/mach-ux500/localtimer.c @@ -0,0 +1,207 @@ +/* + * Copyright (C) 2009 ST Ericsson. + * This file is based on realview platform + * Copyright (C) 2002 ARM Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/delay.h> +#include <linux/device.h> +#include <linux/smp.h> +#include <linux/jiffies.h> +#include <linux/percpu.h> +#include <linux/clockchips.h> +#include <linux/irq.h> + +#include <asm/hardware/arm_twd.h> +#include <asm/hardware/gic.h> +#include <mach/hardware.h> +#include <asm/io.h> +#include <asm/irq.h> +#include <mach/mtu.h> + +static DEFINE_PER_CPU(struct clock_event_device, local_clockevent); + +/* + * Used on SMP for either the local timer or IPI_TIMER + */ +void local_timer_interrupt(void) +{ + struct clock_event_device *clk = &__get_cpu_var(local_clockevent); + + clk->event_handler(clk); +} + +#ifdef CONFIG_LOCAL_TIMERS + +/* set up by the platform code */ +void __iomem *twd_base; + +static unsigned long mpcore_timer_rate; + +static void local_timer_set_mode(enum clock_event_mode mode, + struct clock_event_device *clk) +{ + unsigned long ctrl; + + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + /* timer load already set up */ + ctrl = TWD_TIMER_CONTROL_ENABLE | TWD_TIMER_CONTROL_IT_ENABLE + | TWD_TIMER_CONTROL_PERIODIC; + break; + case CLOCK_EVT_MODE_ONESHOT: + /* period set, and timer enabled in 'next_event' hook */ + ctrl = TWD_TIMER_CONTROL_IT_ENABLE | TWD_TIMER_CONTROL_ONESHOT; + break; + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_SHUTDOWN: + default: + ctrl = 0; + } + + __raw_writel(ctrl, twd_base + TWD_TIMER_CONTROL); +} + +static int local_timer_set_next_event(unsigned long evt, + struct clock_event_device *unused) +{ + unsigned long ctrl = __raw_readl(twd_base + TWD_TIMER_CONTROL); + + __raw_writel(evt, twd_base + TWD_TIMER_COUNTER); + __raw_writel(ctrl | TWD_TIMER_CONTROL_ENABLE, + twd_base + TWD_TIMER_CONTROL); + + return 0; +} + +/* + * local_timer_ack: checks for a local timer interrupt. + * + * If a local timer interrupt has occurred, acknowledge and return 1. + * Otherwise, return 0. + */ +int local_timer_ack(void) +{ + if (__raw_readl(twd_base + TWD_TIMER_INTSTAT)) { + __raw_writel(1, twd_base + TWD_TIMER_INTSTAT); + return 1; + } + return 0; +} + +static void __cpuinit twd_calibrate_rate(void) +{ + unsigned long load, count; + u64 waitjiffies; + + /* + * If this is the first time round, we need to work out how fast + * the timer ticks + */ + if (mpcore_timer_rate == 0) { + printk("Calibrating local timer... "); + + /* Wait for a tick to start */ + waitjiffies = get_jiffies_64() + 1; + + while (get_jiffies_64() < waitjiffies) + udelay(10); + + /* OK, now the tick has started, let's get the timer going */ + waitjiffies += 5; + + /* enable, no interrupt or reload */ + __raw_writel(0x1, twd_base + TWD_TIMER_CONTROL); + + /* maximum value */ + __raw_writel(0xFFFFFFFFU, twd_base + TWD_TIMER_COUNTER); + + while (get_jiffies_64() < waitjiffies) + udelay(10); + + count = __raw_readl(twd_base + TWD_TIMER_COUNTER); + + mpcore_timer_rate = (0xFFFFFFFFU - count) * (HZ / 5); + + printk("%lu.%02luMHz.\n", mpcore_timer_rate / 1000000, + (mpcore_timer_rate / 100000) % 100); + } + + load = mpcore_timer_rate / HZ; + + __raw_writel(load, twd_base + TWD_TIMER_LOAD); +} + +extern struct mtu_struct mtu_timer_tick; + +/* + * Setup the local clock events for a CPU. + */ +void __cpuinit local_timer_setup(void) +{ + unsigned int cpu = smp_processor_id(); + struct clock_event_device *clk = &per_cpu(local_clockevent, cpu); + unsigned long flags; + + twd_calibrate_rate(); + + clk->name = "local_timer"; + clk->features = CLOCK_EVT_FEAT_PERIODIC | + CLOCK_EVT_FEAT_ONESHOT | + CLOCK_EVT_FEAT_C3STOP; + clk->rating = 550; + clk->set_mode = local_timer_set_mode; + clk->set_next_event = local_timer_set_next_event; + clk->irq = IRQ_LOCALTIMER; + clk->cpumask = cpumask_of(cpu); + clk->shift = 20; + clk->mult = div_sc(mpcore_timer_rate, NSEC_PER_SEC, + clk->shift); + clk->max_delta_ns = clockevent_delta2ns(0xffffffff, clk); + clk->min_delta_ns = clockevent_delta2ns(0xf, clk); + clk->broadcast = smp_timer_broadcast; + + /* Make sure our local interrupt controller has this enabled */ + local_irq_save(flags); + get_irq_chip(IRQ_LOCALTIMER)->unmask(IRQ_LOCALTIMER); + local_irq_restore(flags); + + clockevents_register_device(clk); +} + +/* + * take a local timer down + */ +void __cpuexit local_timer_stop(void) +{ + __raw_writel(0, twd_base + TWD_TIMER_CONTROL); +} + +#else /* CONFIG_LOCAL_TIMERS */ + +static void dummy_timer_set_mode(enum clock_event_mode mode, + struct clock_event_device *clk) +{ +} + +void __cpuinit local_timer_setup(void) +{ + unsigned int cpu = smp_processor_id(); + struct clock_event_device *clk = &per_cpu(local_clockevent, cpu); + + clk->name = "dummy_timer"; + clk->features = CLOCK_EVT_FEAT_DUMMY; + clk->rating = 200; + clk->set_mode = dummy_timer_set_mode; + clk->broadcast = smp_timer_broadcast; + clk->cpumask = cpumask_of(cpu); + clk->mult = 1; + + clockevents_register_device(clk); +} +#endif /* !CONFIG_LOCAL_TIMERS */ diff --git a/arch/arm/mach-ux500/mcde.c b/arch/arm/mach-ux500/mcde.c new file mode 100644 index 00000000000..c7746426b43 --- /dev/null +++ b/arch/arm/mach-ux500/mcde.c @@ -0,0 +1,763 @@ +/* + * Copyright (C) 2010 ST Ericsson + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + */ + +#include <linux/platform_device.h> +#include <linux/io.h> + +#include <mach/devices.h> +#include <mach/hardware.h> +#include <mach/mcde.h> +#include <mach/mcde_common.h> + +#ifdef CONFIG_FB_U8500_MCDE_CHANNELC0 +/* Channel C0 */ + +#ifdef CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT + +static struct resource mcde2_resources[] = { + [0] = { + .start = U8500_MCDE_BASE, + .end = U8500_MCDE_BASE + (U8500_MCDE_BASE_SIZE - 1), + .name = "mcde_top", + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = U8500_MCDE_EXTSRC_BASE, + .end = U8500_MCDE_EXTSRC_BASE + (U8500_MCDE_EXTSRC_SIZE - 1), + .name = "mcde_extsrc", + .flags = IORESOURCE_MEM, + }, + [2] = { + .start = U8500_MCDE_OVERLAY_BASE, + .end = U8500_MCDE_OVERLAY_BASE + (U8500_MCDE_OVERLAY_SIZE - 1), + .name = "mcde_overlay", + .flags = IORESOURCE_MEM, + }, + [3] = { + .start = U8500_MCDE_CHANNELC0_CONFIG_BASE, + .end = U8500_MCDE_CHANNELC0_CONFIG_BASE + (U8500_MCDE_CHANNEL_CONFIG_SIZE - 1), + .name = "mcde_chc0_config", + .flags = IORESOURCE_MEM, + }, + [4] = { + .start = U8500_MCDE_CHANNELC0C1_SPECIFIC_REGISTER_BASE, + .end = U8500_MCDE_CHANNELC0C1_SPECIFIC_REGISTER_BASE + (U8500_MCDE_CHANNELC0C1_SPECIFIC_REGISTER_SIZE - 1), + .name = "mcde_chc0c1_specific", + .flags = IORESOURCE_MEM, + }, + [5] = { + .start = U8500_MCDE_DSI_CHANNEL_BASE, + .end = U8500_MCDE_DSI_CHANNEL_BASE + (U8500_MCDE_DSI_CHANNEL_SIZE - 1), + .name = "mcde_dsi_channel", + .flags = IORESOURCE_MEM, + }, + [6] = { + .start = U8500_DSI_LINK1_BASE, + .end = U8500_DSI_LINK1_BASE + ((U8500_DSI_LINK_SIZE * U8500_DSI_LINK_COUNT) - 1), + .name = "dsi_link", + .flags = IORESOURCE_MEM, + }, + [7] = { + .start = PRCM_MCDECLK_MGT_REG, + .end = PRCM_MCDECLK_MGT_REG + (sizeof(u32) - 1), + .name = "prcm_mcde_clk", + .flags = IORESOURCE_MEM, + }, + [8] = { + .start = PRCM_HDMICLK_MGT_REG, + .end = PRCM_HDMICLK_MGT_REG + (sizeof(u32) - 1), + .name = "prcm_hdmi_clk", + .flags = IORESOURCE_MEM, + }, + [9] = { + .start = PRCM_TVCLK_MGT_REG, + .end = PRCM_TVCLK_MGT_REG + (sizeof(u32) - 1), + .name = "prcm_tv_clk", + .flags = IORESOURCE_MEM, + }, + [10] = { + .start = IRQ_DISP, + .end = IRQ_DISP, + .name = "mcde_irq", + .flags = IORESOURCE_IRQ + }, + [11] = { + .start = U8500_MCDE_CHANNELA_SPECIFIC_REGISTER_BASE, + .end = U8500_MCDE_CHANNELA_SPECIFIC_REGISTER_BASE + + (U8500_MCDE_CHANNELA_SPECIFIC_REGISTER_SIZE - 1), + .name = "cha_specific", + .flags = IORESOURCE_MEM, + }, + [12] = { + .start = U8500_MCDE_CHANNELB_SPECIFIC_REGISTER_BASE, + .end = U8500_MCDE_CHANNELB_SPECIFIC_REGISTER_BASE + + (U8500_MCDE_CHANNELB_SPECIFIC_REGISTER_SIZE - 1), + .name = "chb_specific", + .flags = IORESOURCE_MEM, + }, +}; + +#else /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */ + +static struct resource mcde2_resources[] = { + [0] = { + .start = U8500_MCDE_BASE, + .end = U8500_MCDE_BASE + (U8500_MCDE_REGISTER_SIZE - 1), + .name = "mcde_base", + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = U8500_MCDE_EXTSRC_BASE, + .end = U8500_MCDE_EXTSRC_BASE + (U8500_MCDE_EXTSRC_SIZE - 1), + .name = "mcde_extsrc_base", + .flags = IORESOURCE_MEM, + }, + [2] = { + .start = U8500_MCDE_OVL_BASE, + .end = U8500_MCDE_OVL_BASE + (U8500_MCDE_OVL_SIZE - 1), + .name = "mcde_overlay_base", + .flags = IORESOURCE_MEM, + }, + [3] = { + .start = U8500_MCDE_CHANNELC0_CONFIG_BASE, + .end = U8500_MCDE_CHANNELC0_CONFIG_BASE + + (U8500_MCDE_CHANNEL_CONFIG_SIZE - 1), + .name = "chc0_config", + .flags = IORESOURCE_MEM, + }, + [4] = { + .start = U8500_MCDE_CHANNELC_SPECIFIC_REGISTER_BASE, + .end = U8500_MCDE_CHANNELC_SPECIFIC_REGISTER_BASE + + (U8500_MCDE_CHANNELC_SPECIFIC_REGISTER_SIZE - 1), + .name = "chb_specific", + .flags = IORESOURCE_MEM, + }, + [5] = { + .start = U8500_MCDE_DSI_CHANNEL_BASE, + .end = U8500_MCDE_DSI_CHANNEL_BASE + (U8500_MCDE_DSI_SIZE - 1), + .name = "mcde_dsi_channel_base", + .flags = IORESOURCE_MEM, + }, + [6] = { + .start = U8500_DSI_LINK1_BASE, + .end = U8500_DSI_LINK1_BASE + + ((U8500_DSI_LINK_SIZE*U8500_DSI_LINK_COUNT) - 1), + .name = "dsi_link_base", + .flags = IORESOURCE_MEM, + }, + [7] = { + .start = PRCM_MCDECLK_MGT_REG, + .end = PRCM_MCDECLK_MGT_REG + (sizeof(u32) - 1), + .name = "prcm_mcde_clk", + .flags = IORESOURCE_MEM, + }, + [8] = { + .start = PRCM_HDMICLK_MGT_REG, + .end = PRCM_HDMICLK_MGT_REG + (sizeof(u32) - 1), + .name = "prcm_hdmi_clk", + .flags = IORESOURCE_MEM, + }, + [9] = { + .start = PRCM_TVCLK_MGT_REG, + .end = PRCM_TVCLK_MGT_REG + (sizeof(u32) - 1), + .name = "prcm_tv_clk", + .flags = IORESOURCE_MEM, + }, + [10] = { + .start = IRQ_DISP, + .end = IRQ_DISP, + .name = "mcde_irq", + .flags = IORESOURCE_IRQ + }, + [11] = { + .start = U8500_MCDE_CHANNELA_SPECIFIC_REGISTER_BASE, + .end = U8500_MCDE_CHANNELA_SPECIFIC_REGISTER_BASE + + (U8500_MCDE_CHANNEL_SPECIFIC_REGISTER_SIZE - 1), + .name = "cha_specific", + .flags = IORESOURCE_MEM, + }, +}; + +#endif /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */ + +static struct mcde_channel_data mcde2_channel_data = { + .channelid = CHANNEL_C0, + .nopan = 1, + .nowrap = 1, +#ifdef CONFIG_FB_U8500_MCDE_CHANNELC0 + .restype = CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_TYPE, + .inbpp = CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_BPP, + .outbpp = CONFIG_FB_U8500_MCDE_CHANNELC0_OUTPUT_BPP, + .bpp16_type = CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_TYPE, + .bgrinput = CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_BGR, +#else + .restype = "WVGA", + .inbpp = 16, + .outbpp = 0x2, + .bpp16_type = 1, + .bgrinput = 0x0, +#endif +}; + +struct platform_device u8500_mcde2_device = { + .name = "U8500-MCDE", + .id = 2, + .dev = { + .bus_id = "mcde_bus", + .coherent_dma_mask = ~0, + .platform_data = &mcde2_channel_data, + }, + .num_resources = ARRAY_SIZE(mcde2_resources), + .resource = mcde2_resources +}; +#endif /* CONFIG_FB_U8500_MCDE_CHANNELC0 */ + +#ifdef CONFIG_FB_U8500_MCDE_CHANNELC1 +/* Channel C1 */ + +#ifdef CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT + +static struct resource mcde3_resources[] = { + [0] = { + .start = U8500_MCDE_BASE, + .end = U8500_MCDE_BASE + (U8500_MCDE_BASE_SIZE - 1), + .name = "mcde_top", + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = U8500_MCDE_EXTSRC_BASE, + .end = U8500_MCDE_EXTSRC_BASE + (U8500_MCDE_EXTSRC_SIZE - 1), + .name = "mcde_extsrc", + .flags = IORESOURCE_MEM, + }, + [2] = { + .start = U8500_MCDE_OVERLAY_BASE, + .end = U8500_MCDE_OVERLAY_BASE + (U8500_MCDE_OVERLAY_SIZE - 1), + .name = "mcde_overlay", + .flags = IORESOURCE_MEM, + }, + [3] = { + .start = U8500_MCDE_CHANNELC1_CONFIG_BASE, + .end = U8500_MCDE_CHANNELC1_CONFIG_BASE + (U8500_MCDE_CHANNEL_CONFIG_SIZE - 1), + .name = "mcde_chc1_config", + .flags = IORESOURCE_MEM, + }, + [4] = { + .start = U8500_MCDE_CHANNELC0C1_SPECIFIC_REGISTER_BASE, + .end = U8500_MCDE_CHANNELC0C1_SPECIFIC_REGISTER_BASE + (U8500_MCDE_CHANNELC0C1_SPECIFIC_REGISTER_SIZE - 1), + .name = "mcde_chc0c1_specific", + .flags = IORESOURCE_MEM, + }, + [5] = { + .start = U8500_MCDE_DSI_CHANNEL_BASE, + .end = U8500_MCDE_DSI_CHANNEL_BASE + (U8500_MCDE_DSI_SIZE - 1), + .name = "mcde_dsi_channel", + .flags = IORESOURCE_MEM, + }, + [6] = { + .start = U8500_DSI_LINK1_BASE, + .end = U8500_DSI_LINK1_BASE + ((U8500_DSI_LINK_SIZE * U8500_DSI_LINK_COUNT) - 1), + .name = "dsi_link", + .flags = IORESOURCE_MEM, + }, + [7] = { + .start = PRCM_MCDECLK_MGT_REG, + .end = PRCM_MCDECLK_MGT_REG + (sizeof(u32) - 1), + .name = "prcm_mcde_clk", + .flags = IORESOURCE_MEM, + }, + [8] = { + .start = PRCM_HDMICLK_MGT_REG, + .end = PRCM_HDMICLK_MGT_REG + (sizeof(u32) - 1), + .name = "prcm_hdmi_clk", + .flags = IORESOURCE_MEM, + }, + [9] = { + .start = PRCM_TVCLK_MGT_REG, + .end = PRCM_TVCLK_MGT_REG + (sizeof(u32) - 1), + .name = "prcm_tv_clk", + .flags = IORESOURCE_MEM, + }, + [10] = { + .start = IRQ_DISP, + .end = IRQ_DISP, + .name = "mcde_irq", + .flags = IORESOURCE_IRQ + }, +}; + +#else /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */ + +static struct resource mcde3_resources[] = { + [0] = { + .start = U8500_MCDE_BASE, + .end = U8500_MCDE_BASE + (U8500_MCDE_REGISTER_SIZE - 1), + .name = "mcde_base", + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = U8500_MCDE_EXTSRC_BASE, + .end = U8500_MCDE_EXTSRC_BASE + (U8500_MCDE_EXTSRC_SIZE - 1), + .name = "mcde_extsrc_base", + .flags = IORESOURCE_MEM, + }, + [2] = { + .start = U8500_MCDE_OVL_BASE, + .end = U8500_MCDE_OVL_BASE + (U8500_MCDE_OVL_SIZE - 1), + .name = "mcde_overlay_base", + .flags = IORESOURCE_MEM, + }, + [3] = { + .start = U8500_MCDE_CHANNELC1_CONFIG_BASE, + .end = U8500_MCDE_CHANNELC1_CONFIG_BASE + + (U8500_MCDE_CHANNEL_CONFIG_SIZE - 1), + .name = "chc1_config", + .flags = IORESOURCE_MEM, + }, + [4] = { + .start = U8500_MCDE_CHANNELC_SPECIFIC_REGISTER_BASE, + .end = U8500_MCDE_CHANNELC_SPECIFIC_REGISTER_BASE + + (U8500_MCDE_CHANNELC_SPECIFIC_REGISTER_SIZE - 1), + .name = "chb_specific", + .flags = IORESOURCE_MEM, + }, + [5] = { + .start = U8500_MCDE_DSI_CHANNEL_BASE, + .end = U8500_MCDE_DSI_CHANNEL_BASE + (U8500_MCDE_DSI_SIZE - 1), + .name = "mcde_dsi_channel_base", + .flags = IORESOURCE_MEM, + }, + [6] = { + .start = U8500_DSI_LINK1_BASE, + .end = U8500_DSI_LINK1_BASE + + ((U8500_DSI_LINK_SIZE*U8500_DSI_LINK_COUNT) - 1), + .name = "dsi_link_base", + .flags = IORESOURCE_MEM, + }, + [7] = { + .start = PRCM_MCDECLK_MGT_REG, + .end = PRCM_MCDECLK_MGT_REG + (sizeof(u32) - 1), + .name = "prcm_mcde_clk", + .flags = IORESOURCE_MEM, + }, + [8] = { + .start = PRCM_HDMICLK_MGT_REG, + .end = PRCM_HDMICLK_MGT_REG + (sizeof(u32) - 1), + .name = "prcm_hdmi_clk", + .flags = IORESOURCE_MEM, + }, + [9] = { + .start = PRCM_TVCLK_MGT_REG, + .end = PRCM_TVCLK_MGT_REG + (sizeof(u32) - 1), + .name = "prcm_tv_clk", + .flags = IORESOURCE_MEM, + }, + [10] = { + .start = IRQ_DISP, + .end = IRQ_DISP, + .name = "mcde_irq", + .flags = IORESOURCE_IRQ + }, +}; + +#endif /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */ + +static struct mcde_channel_data mcde3_channel_data = { + .channelid = CHANNEL_C1, + .nopan = 1, + .nowrap = 1, +#ifdef CONFIG_FB_U8500_MCDE_CHANNELC1 + .restype = CONFIG_FB_U8500_MCDE_CHANNELC1_DISPLAY_TYPE, + .inbpp = CONFIG_FB_U8500_MCDE_CHANNELC1_INPUT_BPP, + .outbpp = CONFIG_FB_U8500_MCDE_CHANNELC1_OUTPUT_BPP, + .bpp16_type = CONFIG_FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_TYPE, + .bgrinput = CONFIG_FB_U8500_MCDE_CHANNELC1_INPUT_BGR, +#else + .restype = "WVGA", + .inbpp = 16, + .outbpp = 0x2, + .bpp16_type = 1, + .bgrinput = 0x0, +#endif +}; + +struct platform_device u8500_mcde3_device = { + .name = "U8500-MCDE", + .id = 3, + .dev = { + .bus_id = "mcde_bus", + .coherent_dma_mask = ~0, + .platform_data = &mcde3_channel_data, + }, + + .num_resources = ARRAY_SIZE(mcde3_resources), + .resource = mcde3_resources +}; +#endif /* CONFIG_FB_U8500_MCDE_CHANNELC1 */ + +#ifdef CONFIG_FB_U8500_MCDE_CHANNELB +/* Channel B */ + +#ifdef CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT + +static struct resource mcde1_resources[] = { + [0] = { + .start = U8500_MCDE_BASE, + .end = U8500_MCDE_BASE + (U8500_MCDE_BASE_SIZE - 1), + .name = "mcde_base", + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = U8500_MCDE_EXTSRC_BASE, + .end = U8500_MCDE_EXTSRC_BASE + (U8500_MCDE_EXTSRC_SIZE - 1), + .name = "mcde_extsrc", + .flags = IORESOURCE_MEM, + }, + [2] = { + .start = U8500_MCDE_OVERLAY_BASE, + .end = U8500_MCDE_OVERLAY_BASE + (U8500_MCDE_OVERLAY_SIZE - 1), + .name = "mcde_overlay", + .flags = IORESOURCE_MEM, + }, + [3] = { + .start = U8500_MCDE_CHANNELB_CONFIG_BASE, + .end = U8500_MCDE_CHANNELB_CONFIG_BASE + (U8500_MCDE_CHANNEL_CONFIG_SIZE - 1), + .name = "mcde_chb_config", + .flags = IORESOURCE_MEM, + }, + [4] = { + .start = U8500_MCDE_CHANNELB_SPECIFIC_REGISTER_BASE, + .end = U8500_MCDE_CHANNELB_SPECIFIC_REGISTER_BASE + (U8500_MCDE_CHANNELB_SPECIFIC_REGISTER_SIZE - 1), + .name = "mcde_chb_specific", + .flags = IORESOURCE_MEM, + }, + [5] = { + .start = U8500_MCDE_DSI_CHANNEL_BASE, + .end = U8500_MCDE_DSI_CHANNEL_BASE + (U8500_MCDE_DSI_SIZE - 1), + .name = "mcde_dsi_channel", + .flags = IORESOURCE_MEM, + }, + [6] = { + .start = U8500_DSI_LINK1_BASE, + .end = U8500_DSI_LINK1_BASE + ((U8500_DSI_LINK_SIZE*U8500_DSI_LINK_COUNT) - 1), + .name = "dsi_link", + .flags = IORESOURCE_MEM, + }, + [7] = { + .start = PRCM_MCDECLK_MGT_REG, + .end = PRCM_MCDECLK_MGT_REG + (sizeof(u32) - 1), + .name = "prcm_mcde_clk", + .flags = IORESOURCE_MEM, + }, + [8] = { + .start = PRCM_HDMICLK_MGT_REG, + .end = PRCM_HDMICLK_MGT_REG + (sizeof(u32) - 1), + .name = "prcm_hdmi_clk", + .flags = IORESOURCE_MEM, + }, + [9] = { + .start = PRCM_TVCLK_MGT_REG, + .end = PRCM_TVCLK_MGT_REG + (sizeof(u32) - 1), + .name = "prcm_tv_clk", + .flags = IORESOURCE_MEM, + }, + [10] = { + .start = IRQ_DISP, + .end = IRQ_DISP, + .name = "mcde_irq", + .flags = IORESOURCE_IRQ + }, +}; + +#else /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */ + +static struct resource mcde1_resources[] = { + [0] = { + .start = U8500_MCDE_BASE, + .end = U8500_MCDE_BASE + (U8500_MCDE_REGISTER_SIZE - 1), + .name = "mcde_base", + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = U8500_MCDE_EXTSRC_BASE, + .end = U8500_MCDE_EXTSRC_BASE + (U8500_MCDE_EXTSRC_SIZE - 1), + .name = "mcde_extsrc_base", + .flags = IORESOURCE_MEM, + }, + [2] = { + .start = U8500_MCDE_OVL_BASE, + .end = U8500_MCDE_OVL_BASE + (U8500_MCDE_OVL_SIZE - 1), + .name = "mcde_overlay_base", + .flags = IORESOURCE_MEM, + }, + [3] = { + .start = U8500_MCDE_CHANNELB_CONFIG_BASE, + .end = U8500_MCDE_CHANNELB_CONFIG_BASE + + (U8500_MCDE_CHANNEL_CONFIG_SIZE - 1), + .name = "chb_config", + .flags = IORESOURCE_MEM, + }, + [4] = { + .start = U8500_MCDE_CHANNELB_SPECIFIC_REGISTER_BASE, + .end = U8500_MCDE_CHANNELB_SPECIFIC_REGISTER_BASE + + (U8500_MCDE_CHANNEL_SPECIFIC_REGISTER_SIZE - 1), + .name = "chb_specific", + .flags = IORESOURCE_MEM, + }, + [5] = { + .start = U8500_MCDE_DSI_CHANNEL_BASE, + .end = U8500_MCDE_DSI_CHANNEL_BASE + (U8500_MCDE_DSI_SIZE - 1), + .name = "mcde_dsi_channel_base", + .flags = IORESOURCE_MEM, + }, + [6] = { + .start = U8500_DSI_LINK1_BASE, + .end = U8500_DSI_LINK1_BASE + + ((U8500_DSI_LINK_SIZE*U8500_DSI_LINK_COUNT) - 1), + .name = "dsi_link_base", + .flags = IORESOURCE_MEM, + }, + [7] = { + .start = PRCM_MCDECLK_MGT_REG, + .end = PRCM_MCDECLK_MGT_REG + (sizeof(u32) - 1), + .name = "prcm_mcde_clk", + .flags = IORESOURCE_MEM, + }, + [8] = { + .start = PRCM_HDMICLK_MGT_REG, + .end = PRCM_HDMICLK_MGT_REG + (sizeof(u32) - 1), + .name = "prcm_hdmi_clk", + .flags = IORESOURCE_MEM, + }, + [9] = { + .start = PRCM_TVCLK_MGT_REG, + .end = PRCM_TVCLK_MGT_REG + (sizeof(u32) - 1), + .name = "prcm_tv_clk", + .flags = IORESOURCE_MEM, + }, + [10] = { + .start = IRQ_DISP, + .end = IRQ_DISP, + .name = "mcde_irq", + .flags = IORESOURCE_IRQ + }, +}; + +#endif /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */ + +static struct mcde_channel_data mcde1_channel_data = { + .channelid = CHANNEL_B, + .nopan = 1, + .nowrap = 1, +#ifdef CONFIG_FB_U8500_MCDE_CHANNELB + .restype = CONFIG_FB_U8500_MCDE_CHANNELB_DISPLAY_TYPE, + .inbpp = CONFIG_FB_U8500_MCDE_CHANNELB_INPUT_BPP, + .outbpp = CONFIG_FB_U8500_MCDE_CHANNELB_OUTPUT_BPP, + .bpp16_type = CONFIG_FB_U8500_MCDE_CHANNELB_INPUT_16BPP_TYPE, + .bgrinput = CONFIG_FB_U8500_MCDE_CHANNELB_INPUT_BGR, +#else + .restype = "PAL", + .inbpp = 16, + .outbpp = 0x2, + .bpp16_type = 1, + .bgrinput = 0x0, +#endif +#ifdef CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT + .gpio_alt_func = GPIO_ALT_LCD_PANELB +#else + .gpio_alt_func = GPIO_ALT_LCD_PANELB_ED +#endif +}; + +struct platform_device u8500_mcde1_device = { + .name = "U8500-MCDE", + .id = 1, + .dev = { + .bus_id = "mcde_bus", + .coherent_dma_mask = ~0, + .platform_data = &mcde1_channel_data, + }, + .num_resources = ARRAY_SIZE(mcde1_resources), + .resource = mcde1_resources +}; +#endif /* CONFIG_FB_U8500_MCDE_CHANNELB */ + +#ifdef CONFIG_FB_U8500_MCDE_CHANNELA +/* Channel A */ + +#ifdef CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT + +static struct resource mcde0_resources[] = { + [0] = { + .start = U8500_MCDE_BASE, + .end = U8500_MCDE_BASE + (U8500_MCDE_BASE_SIZE - 1), + .name = "mcde_base", + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = U8500_MCDE_EXTSRC_BASE, + .end = U8500_MCDE_EXTSRC_BASE + (U8500_MCDE_EXTSRC_SIZE - 1), + .name = "mcde_extsrc", + .flags = IORESOURCE_MEM, + }, + [2] = { + .start = U8500_MCDE_OVERLAY_BASE, + .end = U8500_MCDE_OVERLAY_BASE + (U8500_MCDE_OVERLAY_SIZE - 1), + .name = "mcde_overlay", + .flags = IORESOURCE_MEM, + }, + [3] = { + .start = U8500_MCDE_CHANNELA_CONFIG_BASE, + .end = U8500_MCDE_CHANNELA_CONFIG_BASE + (U8500_MCDE_CHANNEL_CONFIG_SIZE - 1), + .name = "mcde_cha_config", + .flags = IORESOURCE_MEM, + }, + [4] = { + .start = U8500_MCDE_CHANNELA_SPECIFIC_REGISTER_BASE, + .end = U8500_MCDE_CHANNELA_SPECIFIC_REGISTER_BASE + (U8500_MCDE_CHANNELA_SPECIFIC_REGISTER_SIZE - 1), + .name = "mcde_cha_specific", + .flags = IORESOURCE_MEM, + }, + [5] = { + .start = U8500_MCDE_DSI_CHANNEL_BASE, + .end = U8500_MCDE_DSI_CHANNEL_BASE + (U8500_MCDE_DSI_SIZE - 1), + .name = "mcde_dsi_channel", + .flags = IORESOURCE_MEM, + }, + [6] = { + .start = U8500_DSI_LINK1_BASE, + .end = U8500_DSI_LINK1_BASE + ((U8500_DSI_LINK_SIZE * U8500_DSI_LINK_COUNT) - 1), + .name = "dsi_link", + .flags = IORESOURCE_MEM, + }, + [7] = { + .start = PRCM_MCDECLK_MGT_REG, + .end = PRCM_MCDECLK_MGT_REG + (sizeof(u32) - 1), + .name = "prcm_mcde_clk", + .flags = IORESOURCE_MEM, + }, + [8] = { + .start = PRCM_HDMICLK_MGT_REG, + .end = PRCM_HDMICLK_MGT_REG + (sizeof(u32) - 1), + .name = "prcm_hdmi_clk", + .flags = IORESOURCE_MEM, + }, + [9] = { + .start = PRCM_TVCLK_MGT_REG, + .end = PRCM_TVCLK_MGT_REG + (sizeof(u32) - 1), + .name = "prcm_tv_clk", + .flags = IORESOURCE_MEM, + }, + [10] = { + .start = IRQ_DISP, + .end = IRQ_DISP, + .name = "mcde_irq", + .flags = IORESOURCE_IRQ + }, +}; + +#else /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */ + +static struct resource mcde0_resources[] = { + [0] = { + .start = U8500_MCDE_BASE, + .end = U8500_MCDE_BASE + (U8500_MCDE_REGISTER_SIZE - 1), + .name = "mcde_base", + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = U8500_MCDE_EXTSRC_BASE, + .end = U8500_MCDE_EXTSRC_BASE + (U8500_MCDE_EXTSRC_SIZE - 1), + .name = "mcde_extsrc_base", + .flags = IORESOURCE_MEM, + }, + [2] = { + .start = U8500_MCDE_OVL_BASE, + .end = U8500_MCDE_OVL_BASE + (U8500_MCDE_OVL_SIZE - 1), + .name = "mcde_overlay_base", + .flags = IORESOURCE_MEM, + }, + [3] = { + .start = U8500_MCDE_CHANNELA_CONFIG_BASE, + .end = U8500_MCDE_CHANNELA_CONFIG_BASE + + (U8500_MCDE_CHANNEL_CONFIG_SIZE - 1), + .name = "cha_config", + .flags = IORESOURCE_MEM, + }, + [4] = { + .start = U8500_MCDE_CHANNELA_SPECIFIC_REGISTER_BASE, + .end = U8500_MCDE_CHANNELA_SPECIFIC_REGISTER_BASE + + (U8500_MCDE_CHANNEL_SPECIFIC_REGISTER_SIZE - 1), + .name = "cha_specific", + .flags = IORESOURCE_MEM, + }, + [5] = { + .start = U8500_MCDE_DSI_CHANNEL_BASE, + .end = U8500_MCDE_DSI_CHANNEL_BASE + (U8500_MCDE_DSI_SIZE - 1), + .name = "mcde_dsi_channel_base", + .flags = IORESOURCE_MEM, + }, + [6] = { + .start = U8500_DSI_LINK1_BASE, + .end = U8500_DSI_LINK1_BASE + + ((U8500_DSI_LINK_SIZE*U8500_DSI_LINK_COUNT) - 1), + .name = "dsi_link_base", + .flags = IORESOURCE_MEM, + }, + [7] = { + .start = PRCM_MCDECLK_MGT_REG, + .end = PRCM_MCDECLK_MGT_REG + (sizeof(u32) - 1), + .name = "prcm_mcde_clk", + .flags = IORESOURCE_MEM, + }, + [8] = { + .start = PRCM_HDMICLK_MGT_REG, + .end = PRCM_HDMICLK_MGT_REG + (sizeof(u32) - 1), + .name = "prcm_hdmi_clk", + .flags = IORESOURCE_MEM, + }, + [9] = { + .start = PRCM_TVCLK_MGT_REG, + .end = PRCM_TVCLK_MGT_REG + (sizeof(u32) - 1), + .name = "prcm_tv_clk", + .flags = IORESOURCE_MEM, + }, + [10] = { + .start = IRQ_DISP, + .end = IRQ_DISP, + .name = "mcde_irq", + .flags = IORESOURCE_IRQ + }, +}; + +#endif /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */ + +static struct mcde_channel_data mcde0_channel_data = { + .channelid = CHANNEL_A, + .nopan = 1, + .nowrap = 1, + .restype = CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_TYPE, + .inbpp = CONFIG_FB_U8500_MCDE_CHANNELA_INPUT_BPP, + .outbpp = CONFIG_FB_U8500_MCDE_CHANNELA_OUTPUT_BPP, + .bpp16_type = CONFIG_FB_U8500_MCDE_CHANNELA_INPUT_16BPP_TYPE, + .bgrinput = CONFIG_FB_U8500_MCDE_CHANNELA_INPUT_BGR, + .gpio_alt_func = GPIO_ALT_LCD_PANELA +}; + +struct platform_device u8500_mcde0_device = { + .name = "U8500-MCDE", + .id = 0, + .dev = { + .bus_id = "mcde_bus", + .coherent_dma_mask = ~0, + .platform_data = &mcde0_channel_data, + }, + .num_resources = ARRAY_SIZE(mcde0_resources), + .resource = mcde0_resources +}; +#endif /* CONFIG_FB_U8500_MCDE_CHANNELA */ diff --git a/arch/arm/mach-ux500/mop500-sdi.c b/arch/arm/mach-ux500/mop500-sdi.c new file mode 100644 index 00000000000..c1d3d97e046 --- /dev/null +++ b/arch/arm/mach-ux500/mop500-sdi.c @@ -0,0 +1,274 @@ +/* + * Copyright (C) 2010 ST-Ericsson + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + */ + +#include <linux/platform_device.h> +#include <linux/amba/bus.h> +#include <linux/mmc/host.h> +#include <linux/delay.h> + +#include <mach/devices.h> +#include <mach/mmc.h> +#include <mach/stmpe2401.h> +#include <mach/tc35892.h> +#include <mach/ab8500.h> + +/* + * SDI0 (SD/MMC card) + */ + +static int mmc_configure(struct amba_device *dev) +{ + int pin[2]; + int ret; + int i; + + /* Level-shifter GPIOs */ + if (MOP500_PLATFORM_ID == platform_id) { + pin[0] = EGPIO_PIN_18; + pin[1] = EGPIO_PIN_19; + } else if (HREF_PLATFORM_ID == platform_id) { + pin[0] = EGPIO_PIN_17; + pin[1] = EGPIO_PIN_18; + } else + BUG(); + + ret = gpio_request(pin[0], "level shifter"); + if (!ret) + ret = gpio_request(pin[1], "level shifter"); + + if (!ret) { + gpio_direction_output(pin[0], 1); + gpio_direction_output(pin[1], 1); + + gpio_set_value(pin[0], 1); + gpio_set_value(pin[1], 1); + } else + dev_err(&dev->dev, "unable to configure gpios\n"); + +#if defined(CONFIG_GPIO_TC35892) + if (HREF_PLATFORM_ID == platform_id) { + /* Enabling the card detection interrupt */ + tc35892_set_gpio_intr_conf(EGPIO_PIN_3, EDGE_SENSITIVE, + TC35892_BOTH_EDGE); + tc35892_set_intr_enable(EGPIO_PIN_3, ENABLE_INTERRUPT); + } +#endif + + for (i = 18; i <= 28; i++) { + gpio_set_value(i, GPIO_HIGH); + gpio_set_value(i, GPIO_PULLUP_DIS); + } + + stm_gpio_altfuncenable(GPIO_ALT_SDMMC); + return ret; +} + +static void mmc_set_power(struct device *dev, int power_on) +{ + if (platform_id == MOP500_PLATFORM_ID) + gpio_set_value(EGPIO_PIN_18, !!power_on); + else if (platform_id == HREF_PLATFORM_ID) + gpio_set_value(EGPIO_PIN_17, !!power_on); +} + +static void mmc_restore_default(struct amba_device *dev) +{ + +} + +static int mmc_card_detect(void (*callback)(void *parameter), void *host) +{ + /* + * Card detection interrupt request + */ +#if defined(CONFIG_GPIO_STMPE2401) + if (MOP500_PLATFORM_ID == platform_id) + stmpe2401_set_callback(EGPIO_PIN_16, callback, host); +#endif + +#if defined(CONFIG_GPIO_TC35892) + if (HREF_PLATFORM_ID == platform_id) { + tc35892_set_gpio_intr_conf(EGPIO_PIN_3, EDGE_SENSITIVE, TC35892_BOTH_EDGE); + tc35892_set_intr_enable(EGPIO_PIN_3, ENABLE_INTERRUPT); + tc35892_set_callback(EGPIO_PIN_3, callback, host); + } +#endif + return 0; +} + +static int mmc_get_carddetect_intr_value(void) +{ + int status = 0; + + if (MOP500_PLATFORM_ID == platform_id) + status = gpio_get_value(EGPIO_PIN_16); + else if (HREF_PLATFORM_ID == platform_id) + status = gpio_get_value(EGPIO_PIN_3); + + return status; +} + +static struct mmc_board mmc_data = { + .init = mmc_configure, + .exit = mmc_restore_default, + .set_power = mmc_set_power, + .card_detect = mmc_card_detect, + .card_detect_intr_value = mmc_get_carddetect_intr_value, + .dma_fifo_addr = U8500_SDI0_BASE + SD_MMC_TX_RX_REG_OFFSET, + .dma_fifo_dev_type_rx = DMA_DEV_SD_MMC0_RX, + .dma_fifo_dev_type_tx = DMA_DEV_SD_MMC0_TX, + .level_shifter = 1, + .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED | + MMC_CAP_MMC_HIGHSPEED, +}; + +/* + * SDI1 (SDIO WLAN) + */ + +/* sdio specific configurations */ +static int sdio_configure(struct amba_device *dev) +{ + int i; + gpio_direction_output(215,GPIO_HIGH); + gpio_set_value(215,GPIO_LOW); + mdelay(10); + gpio_set_value(213,GPIO_HIGH); + mdelay(10); + gpio_set_value(215,GPIO_HIGH); + mdelay(10); + gpio_set_value(213,GPIO_LOW); + mdelay(10); + + for (i = 208; i <= 214; i++) { + gpio_set_value(i, GPIO_HIGH); + gpio_set_value(i, GPIO_PULLUP_DIS); + } + + stm_gpio_altfuncenable(GPIO_ALT_SDIO); + + return 0; +} + +static void sdio_restore_default(struct amba_device *dev) +{ + stm_gpio_altfuncdisable(GPIO_ALT_SDIO); +} + +static struct mmc_board sdi1_data = { + .init = sdio_configure, + .exit = sdio_restore_default, + .dma_fifo_addr = U8500_SDI1_BASE + SD_MMC_TX_RX_REG_OFFSET, + .dma_fifo_dev_type_rx = DMA_DEV_SD_MM1_RX, + .dma_fifo_dev_type_tx = DMA_DEV_SD_MM1_TX, + .level_shifter = 0, +#ifdef CONFIG_U8500_SDIO_CARD_IRQ + .caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ), +#else + .caps = MMC_CAP_4_BIT_DATA, +#endif + .is_sdio = 1, +}; + +/* + * SDI2 (POPed eMMC on v1) + */ + +static int sdi2_init(struct amba_device *dev) +{ + int i; + + for (i = 128; i <= 138; i++) { + gpio_set_value(i, GPIO_HIGH); + gpio_set_value(i, GPIO_PULLUP_DIS); + } + stm_gpio_altfuncenable(GPIO_ALT_SDMMC2); + return 0; +} + +static void sdi2_exit(struct amba_device *dev) +{ + stm_gpio_altfuncdisable(GPIO_ALT_SDMMC2); +} + +static struct mmc_board sdi2_data = { + .init = sdi2_init, + .exit = sdi2_exit, + .dma_fifo_addr = U8500_SDI2_BASE + SD_MMC_TX_RX_REG_OFFSET, + .dma_fifo_dev_type_rx = DMA_DEV_SD_MMC2_RX, + .dma_fifo_dev_type_tx = DMA_DEV_SD_MMC2_TX, + .level_shifter = 0, + .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, +}; + +/* + * SDI4 (On-board EMMC) + */ + +static int emmc_configure(struct amba_device *dev) +{ + int i; + + for (i = 197; i <= 207; i++) { + gpio_set_value(i, GPIO_HIGH); + gpio_set_value(i, GPIO_PULLUP_DIS); + } + stm_gpio_altfuncenable(GPIO_ALT_EMMC); + +#ifndef CONFIG_REGULATOR + if (!cpu_is_u8500ed()) { + int val; + + /* On V1 MOP, regulator to on-board eMMC is off by default */ + val = ab8500_read(AB8500_REGU_CTRL2, + AB8500_REGU_VAUX12_REGU_REG); + ab8500_write(AB8500_REGU_CTRL2, AB8500_REGU_VAUX12_REGU_REG, + val | 0x4); + + val = ab8500_read(AB8500_REGU_CTRL2, + AB8500_REGU_VAUX2_SEL_REG); + ab8500_write(AB8500_REGU_CTRL2, AB8500_REGU_VAUX2_SEL_REG, + 0x0C); + } +#endif + + return 0; +} + +static void emmc_restore_default(struct amba_device *dev) +{ + stm_gpio_altfuncdisable(GPIO_ALT_EMMC); +} + +static struct mmc_board emmc_data = { + .init = emmc_configure, + .exit = emmc_restore_default, + .dma_fifo_addr = U8500_SDI4_BASE + SD_MMC_TX_RX_REG_OFFSET, + .dma_fifo_dev_type_rx = DMA_DEV_SD_MM4_RX, + .dma_fifo_dev_type_tx = DMA_DEV_SD_MM4_TX, + .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA | MMC_CAP_MMC_HIGHSPEED, +#ifdef CONFIG_REGULATOR + .supply = "v-eMMC" /* tying to VAUX1 regulator */ +#endif +}; + +static int __init mop500_sdi_init(void) +{ + if (!cpu_is_u8500ed()) + u8500_register_amba_device(&ux500_sdi2_device, &sdi2_data); + + u8500_register_amba_device(&ux500_sdi4_device, &emmc_data); + u8500_register_amba_device(&ux500_sdi0_device, &mmc_data); +#ifdef CONFIG_U8500_SDIO + u8500_register_amba_device(&ux500_sdi1_device, &sdi1_data); +#endif + + return 0; +} + +fs_initcall(mop500_sdi_init); diff --git a/arch/arm/mach-ux500/mop500_devices.c b/arch/arm/mach-ux500/mop500_devices.c new file mode 100755 index 00000000000..239f013b140 --- /dev/null +++ b/arch/arm/mach-ux500/mop500_devices.c @@ -0,0 +1,965 @@ +/* + * Copyright (C) 2009 ST Ericsson. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + */ +#include <linux/types.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/amba/bus.h> +#include <linux/i2c.h> +#include <linux/hsi.h> +#include <linux/i2s/i2s.h> +#include <linux/gpio.h> +#include <linux/input.h> + +#include <asm/mach/arch.h> +#include <asm/mach/irq.h> +#include <asm/mach/map.h> +#include <asm/mach-types.h> + +#include <mach/devices.h> +#include <mach/kpd.h> +#include <mach/stmpe2401.h> +#include <mach/stmpe1601.h> +#include <mach/tc35892.h> +#include <mach/av8100_p.h> +#include <mach/ab8500.h> +#include <mach/mmc.h> +#include <mach/setup.h> +#include <mach/i2c-stm.h> + +#include <mach/u8500_tsc.h> + +#define IRQ_KP 1 /*To DO*/ + +int href_v1_board; +extern int platform_id; + +#define MOP500_PLATFORM_ID 0 +#define HREF_PLATFORM_ID 1 + +/* + * This is only non-static because MCDE accesses it directly. Make this static + * once MCDE is fixed to not depend on these variables. + */ +int platform_id = MOP500_PLATFORM_ID; + +/* we have equally similar boards with very minimal + * changes, so we detect the platform during boot + */ +static int __init board_id_setup(char *str) +{ + if (!str) + return 1; + + switch (*str) { + case '0': + printk(KERN_INFO "MOP500 platform\n"); + platform_id = MOP500_PLATFORM_ID; + break; + case '1': + printk(KERN_INFO "HREF platform\n"); + platform_id = HREF_PLATFORM_ID; + break; + default: + printk(KERN_INFO "Unknown board_id=%c\n", *str); + break; + }; + + return 1; +} +__setup("board_id=", board_id_setup); + +static struct stmpe2401_platform_data stmpe_data = { + .gpio_base = 268, + .irq = GPIO_TO_IRQ(217), +}; + +static struct av8100_platform_data av8100_plat_data = { + .irq = GPIO_TO_IRQ(192), +}; + +static struct stmpe1601_platform_data stmpe1601_data = { + .gpio_base = (268 + 24), /* 268 GPIOs + 24 extended GPIOs ofSTMPE2401*/ + .irq = GPIO_TO_IRQ(218), +}; + +static struct tc35892_platform_data tc35892_data = { + .gpio_base = 268, + .irq = GPIO_TO_IRQ(217), +}; + +static struct i2c_board_info __initdata nmdk_i2c0_egpio_devices[] = { + { + /* stmpe2401 @ 0x84(w),0x85(r) */ + I2C_BOARD_INFO("stmpe2401", 0x42), + .platform_data = &stmpe_data, + } +}; + +static struct i2c_board_info __initdata nmdk_i2c0_egpio1_devices[] = { + { + + I2C_BOARD_INFO("tc35892", 0x42), + .platform_data = &tc35892_data, + } +}; + +/** + * Touch panel related platform specific initialization + */ +#if defined(CONFIG_U8500_TSC) + +/** + * tp_gpio_board_init : configure the voltage for touch + * panel controller. This function can be used to configure + * the voltage for touch panel controller. + */ +int tp_gpio_board_init(void) +{ + int val; +#ifdef CONFIG_TOUCHP_EXT_CLK + void __iomem *clk_base; + unsigned int clk_value; +#endif +#ifndef CONFIG_REGULATOR + /** Set the voltage for Bu21013 controller */ + val = ab8500_read(AB8500_REGU_CTRL2, AB8500_REGU_VAUX12_REGU_REG); + + ab8500_write(AB8500_REGU_CTRL2, AB8500_REGU_VAUX12_REGU_REG, + (val | 0x1)); + + val = ab8500_read(AB8500_REGU_CTRL2, AB8500_REGU_VAUX1_SEL_REG); + + ab8500_write(AB8500_REGU_CTRL2, AB8500_REGU_VAUX1_SEL_REG, 0x0C); +#endif +#ifdef CONFIG_TOUCHP_EXT_CLK + stm_gpio_altfuncenable(GPIO_ALT_TP_SET_EXT_CLK); + clk_base = (void __iomem *)IO_ADDRESS(U8500_PRCMU_BASE + 0x1CC); + clk_value = readl(clk_base); + writel(0x880000, clk_base); + clk_value = readl(clk_base); +#endif + if (platform_id == MOP500_PLATFORM_ID) { + /** why set directtion is not working ~ FIXME */ + /* gpio_direction_output(270,1); */ + gpio_set_value(TOUCHP_CS0, 1); + } else { + if (platform_id == HREF_PLATFORM_ID) { + gpio_direction_output(EGPIO_PIN_13, 1); + gpio_set_value(EGPIO_PIN_13, 1); + } + } + return 0; +} + +/** + * tp_gpio_board_init : deconfigures the touch panel controller + * This function can be used to deconfigures the chip selection + * for touch panel controller. + */ +int tp_gpio_board_exit(void) +{ + if (platform_id == MOP500_PLATFORM_ID) { + /** why set directtion is not working ~ FIXME */ + /* gpio_direction_output(270,1); */ + gpio_set_value(TOUCHP_CS0, 0); + } else if (platform_id == HREF_PLATFORM_ID) { + gpio_direction_output(EGPIO_PIN_13, 0); + gpio_set_value(EGPIO_PIN_13, 0); + } + return 0; +} + +/** + * tp_init_irq : sets the callback for touch panel controller + * @parameter: function pointer for touch screen callback handler. + * @data: data to be passed for touch panel callback handler. + * This function can be used to set the callback handler for + * touch panel controller. + */ +int tp_init_irq(void (*callback)(void *parameter), void *data) +{ + int retval = 0; + + if (platform_id == MOP500_PLATFORM_ID) { + retval = stmpe2401_set_callback(TOUCHP_IRQ, callback, + (void *)data); + if (retval < 0) + printk(KERN_ERR " stmpe2401_set_callback failed \n"); + } else if (platform_id == HREF_PLATFORM_ID) { + if (href_v1_board == 0) { + retval = tc35892_set_callback(EGPIO_PIN_12, callback, + (void *)data); + if (retval < 0) + printk(KERN_ERR " tc35892_set_callback failed \n"); + } + } + return retval; +} + +/** + * tp_exit_irq : removes the callback for touch panel controller + * This function can be used to removes the callback handler for + * touch panel controller. + */ +int tp_exit_irq(void) +{ + int retval = 0; + if (platform_id == MOP500_PLATFORM_ID) + stmpe2401_remove_callback(TOUCHP_IRQ); + else if (platform_id == HREF_PLATFORM_ID) { + if (href_v1_board == 0) + tc35892_remove_callback(EGPIO_PIN_12); + } + return retval; +} + +/** + * tp_pen_down_irq_enable : enable the interrupt for touch panel controller + * This function can be used to enable the interrupt for touch panel controller. + */ +int tp_pen_down_irq_enable(void) +{ + int retval = 0; + if (platform_id == MOP500_PLATFORM_ID) { + /* do nothing */ + } else if (platform_id == HREF_PLATFORM_ID) { + if (href_v1_board == 0) { + retval = tc35892_set_gpio_intr_conf(EGPIO_PIN_12, + EDGE_SENSITIVE, TC35892_FALLING_EDGE_OR_LOWLEVEL); + if (retval < 0) + printk(KERN_ERR " tc35892_set_gpio_intr_conf failed\n"); + retval = tc35892_set_intr_enable(EGPIO_PIN_12, + ENABLE_INTERRUPT); + if (retval < 0) + printk(KERN_ERR " tc35892_set_intr_enable failed \n"); + } + } + return retval; +} + +/** + * tp_pen_down_irq_disable : disable the interrupt + * This function can be used to disable the interrupt for + * touch panel controller. + */ +int tp_pen_down_irq_disable(void) +{ + int retval = 0; + if (platform_id == MOP500_PLATFORM_ID) { + /* do nothing */ + } else if (platform_id == HREF_PLATFORM_ID) { + if (href_v1_board == 0) { + retval = tc35892_set_intr_enable(EGPIO_PIN_12, + DISABLE_INTERRUPT); + if (retval < 0) + printk(KERN_ERR " tc35892_set_intr_enable failed \n"); + } + } + return retval; +} + +/** + * tp_read_pin_val : get the interrupt pin value + * This function can be used to get the interrupt pin value for touch panel + * controller. + */ +int tp_read_pin_val(void) +{ + int data = 0; + unsigned int touch_gpio_pin = 84; + + if (platform_id == MOP500_PLATFORM_ID) + data = gpio_get_value(TOUCHP_IRQ); + else if (platform_id == HREF_PLATFORM_ID) { + if (href_v1_board == 0) + data = gpio_get_value(EGPIO_PIN_12); + else + data = gpio_get_value(touch_gpio_pin); + } + return data; +} +/** + * tp_board_href_v1 : update the href v1 flag + * This function can be used to update the board. + */ +int tp_board_href_v1(void) +{ + unsigned int touch_gpio_pin = 84; + if (platform_id == HREF_PLATFORM_ID) { + if (u8500_is_earlydrop()) + href_v1_board = 0; + else + href_v1_board = gpio_get_value(touch_gpio_pin); + } else + href_v1_board = 0; + return href_v1_board; +} + +static struct tp_device tsc_plat_device = { + .cs_en = tp_gpio_board_init, + .cs_dis = tp_gpio_board_exit, + .irq_init = tp_init_irq, + .irq_exit = tp_exit_irq, + .pirq_en = tp_pen_down_irq_enable, + .pirq_dis = tp_pen_down_irq_disable, + .pirq_read_val = tp_read_pin_val, + .board_href_v1 = tp_board_href_v1, + .irq = GPIO_TO_IRQ(84), +}; +#endif + +static struct i2c_board_info __initdata u8500_i2c0_devices[] = { + { + I2C_BOARD_INFO("stmpe1601", 0x40), + .platform_data = &stmpe1601_data, + }, + { + I2C_BOARD_INFO("av8100", 0x70), + .platform_data = &av8100_plat_data, + }, + { + /* FIXME - address TBD, TODO */ + I2C_BOARD_INFO("uib-kpd", 0x45), + }, + { + /* Audio step-up */ + I2C_BOARD_INFO("tps61052", 0x33), + } +}; +static struct i2c_board_info __initdata u8500_i2c1_devices[] = { + { + /* GPS - Address TBD, FIXME */ + I2C_BOARD_INFO("gps", 0x68), + }, + { + /* AB3550 */ + I2C_BOARD_INFO("ab3550", 0x4A), + } +}; + +static struct i2c_board_info __initdata u8500_i2c2_devices[] = { + { + /* ST 3D accelerometer @ 0x3A(w),0x3B(r) */ + I2C_BOARD_INFO("lis302dl", 0x1D), + }, + { + /* ASAHI KASEI AK8974 magnetometer, addr TBD FIXME */ + I2C_BOARD_INFO("ak8974", 0x1), + }, + { + /* Rohm BH1780GLI light sensor addr TBD, FIXME */ + I2C_BOARD_INFO("bh1780gli", 0x45), + }, + { + /* RGB LED driver, there are 1st and 2nd, TODO */ + I2C_BOARD_INFO("lp5521tmx", 0x33), + } +}; + +static struct i2c_board_info __initdata u8500_i2c3_devices[] = { + { + /* NFC - Address TBD, FIXME */ + I2C_BOARD_INFO("nfc", 0x68), + }, +#if defined(CONFIG_U8500_TSC) + { + /* Touschscreen */ + I2C_BOARD_INFO(DRIVER_TP1, I2C3_TOUCHP_ADDRESS), + .platform_data = &tsc_plat_device, + }, +#endif + +}; + +#ifdef CONFIG_KEYPAD_U8500 + +#define DEBUG_KP(x) +/* #define DEBUG_KP(x) printk x */ +/* Keypad platform specific code */ +#ifdef CONFIG_U8500_KEYPAD_DEBUG + +#define KEYPAD_NAME "KEYPAD" + +#undef NMDK_DEBUG +#undef NMDK_DEBUG_PFX +#undef NMDK_DBG + +#define NMDK_DEBUG CONFIG_U8500_KEYPAD_DEBUG +#define NMDK_DEBUG_PFX KEYPAD_NAME +#define NMDK_DBG KERN_ERR + +#endif + +/** + * Keypad related platform specific constants + * These values may be modified for fine tuning + */ +#define KPD_NB_ROWS 0xFF +#define KPD_NB_COLUMNS 0xFF +#define KEYPAD_DEBOUNCE_PERIOD_STUIB 64 /* Debounce time 64ms */ +#define NB_SCAN_CYCLES 8 + +/* spinlock_t cr_lock = SPIN_LOCK_UNLOCKED; */ +static DEFINE_SPINLOCK(cr_lock); + +extern irqreturn_t u8500_kp_intrhandler(/*int irq,*/ void *dev_id); + +/** + * u8500_kp_results_autoscan : This function gets scanned key data from stmpe + * @keys : o/p parameter, returns keys pressed. + * This function can be used in both polling or interrupt usage. + */ +int u8500_kp_results_autoscan(struct keypad_t *kp) +{ + int err; + t_stmpe1601_key_status keys; + u8 kcode, i; + static int keyp_cnt; + /** + * read key data from stmpe1601 + */ + err = stmpe1601_keypressed(&keys); + if (keys.button_pressed) { + for (i = 0; i < keys.button_pressed; i++) { + kcode = kp->board->kcode_tbl[(keys.button[i] & 0x7) * + 8 + ((keys.button[i] >> 3) & 0x7)]; + input_report_key(kp->inp_dev, kcode, 1); + if (kcode == KEY_RESERVED) + printk(KERN_ERR "Error in key detection." + " Key not present"); + DEBUG_KP(("\nkey (%d, %d)-->DOWN, kcode = %d", + (keys.button[i] >> 3) & 0x7, + (keys.button[i] & 0x7), kcode)); + keyp_cnt++; + } + } + if (keys.button_released) { + for (i = 0; i < keys.button_released; i++) { + kcode = kp->board->kcode_tbl[(keys.released[i] & 0x7) * + 8 + ((keys.released[i] >> 3) & 0x7)]; + input_report_key(kp->inp_dev, kcode, 0); + if (kcode == KEY_RESERVED) + printk(KERN_ERR "Error in key detection." + " Key not present"); + DEBUG_KP(("\nkey (%d, %d)-->UP, kcode = %d", + (keys.released[i] >> 3) & 0x7, + (keys.released[i] & 0x7), kcode)); + keyp_cnt--; + } + } + if (keys.button_pressed || keys.button_released) + DEBUG_KP(("\nkp_results_autoscan keyp_cnt = %d, pressed = %d ", + "released = %d\n", + keyp_cnt, keys.button_pressed, keys.button_released)); + return keyp_cnt; +} + +/** + * u8500_kp_intrhandler - keypad interrupt handler + * @dev_id : platform data + * checks for valid interrupt, disables interrupt to avoid any nested interrupt + * starts work queue for further key processing with debouncing logic + */ +irqreturn_t u8500_kp_intrhandler(/*int irq, */void *dev_id) +{ + struct keypad_t *kp = (struct keypad_t *)dev_id; + /* printk("\n Kp interrupt"); */ + /* if (irq != kp->irq) return IRQ_NONE; */ + if (!(test_bit(KPINTR_LKBIT, &kp->lockbits))) { + set_bit(KPINTR_LKBIT, &kp->lockbits); + + if (kp->board->irqdis_int) + kp->board->irqdis_int(kp); + + /* schedule_delayed_work(&kp->kscan_work, + kp->board->debounce_period); */ + schedule_work(&kp->kscan_work); + } + return IRQ_HANDLED; +} + +/** + * u8500_kp_init_key_hardware - keypad hardware initialization + * @kp keypad configuration for this platform + * Initializes the keypad hardware specific parameters. + * This function will be called by u8500_keypad_init function during init + * Initialize keypad interrupt handler for interrupt mode operation if enabled + * Initialize Keyscan matrix + * + */ +int u8500_kp_init_key_hardware(struct keypad_t *kp) +{ + int err; + t_stmpe1601_key_config kpconfig; + + DEBUG_KP(("u8500_kp_init_key_hardware\n")); + /* + * Check if stmpe1601 is initialised properly, otherwise exit from here + */ + err = stmpe1601_read_info(); + if (err) { + printk(KERN_ERR "\n Error in keypad init, keypad controller" + "not initialised."); + return -EIO; + } + /* setup Columns GPIOs (inputs) */ + kpconfig.columns = kp->board->kcol; /* 0xFF 8 columns */ + kpconfig.rows = kp->board->krow; /* 0xFF 8 rows */ + /* 8, number of cycles for key data updating */ + kpconfig.ncycles = NB_SCAN_CYCLES; + /* de-bounce time 64 ms */ + kpconfig.debounce = kp->board->debounce_period; + kpconfig.scan = STMPE1601_SCAN_OFF; + err = stmpe1601_keypad_init(kpconfig); + if (err) + printk(KERN_ERR "Couldn't setup keypad configuration\n"); + + if (!kp->mode) { + /* + * true if interrupt mode operation + */ + DEBUG_KP(("\nsetting up keypad interrupt & " + "enable keypad intr\n")); + err = stmpe1601_set_callback(kp->board->irq, + u8500_kp_intrhandler, (void *)kp); + if (err) { + printk(KERN_ERR "\nCouldn't setup keypad callback\n"); + return err; + } + err = kp->board->irqen(kp); + if (err) { + printk(KERN_ERR "Couldn't enable the keypad " + "source interrupt\n"); + return err; + } + } + err = stmpe1601_keypad_scan(STMPE1601_SCAN_ON); + if (err) + printk(KERN_ERR "Couldn't enable keypad scan\n"); + + return 0; +} + +/** + * u8500_kp_exit_key_hardware- keypad hardware exit function + * + * This function will be called by u8500_keypad_exit function during module + * exit, frees keypad interrupt if enabled + */ +int u8500_kp_exit_key_hardware(struct keypad_t *kp) +{ + int err; + + DEBUG_KP(("nomadik_kp_exit_key_hardware\n")); + err = stmpe1601_keypad_scan(STMPE1601_SCAN_OFF); + if (err) + printk(KERN_ERR "Couldn't disable keypad scan\n"); + + if (!kp->mode) { /* true if interrupt mode operation */ + err = kp->board->irqdis(kp); + if (err) { + printk(KERN_ERR "Couldn't disable keypad callback\n"); + return err; + } + err = stmpe1601_remove_callback(kp->board->irq); + if (err) { + printk(KERN_ERR "Couldn't remove keypad callback\n"); + return err; + } + } + return 0; +} +/** + * u8500_kp_key_irqdis- disables keypad interrupt + * + * disables keypad interrupt + */ +int u8500_kp_key_irqdis(struct keypad_t *kp) +{ + unsigned long flags; + /* Enable KEYPAD interrupt of STMPE 1601 */ + int err; + /* DEBUG_KP(("u8500_kp_key_irqdis\n")); */ + err = stmpe1601_irqdis(kp->board->irq); + /* err = stmpe1601_intsrc_set_state(STMPE1601_0, + STMPE1601_KEYPAD_IRQ, STMPE1601_DISABLE_INTERRUPT );*/ + if (err) { + printk(KERN_ERR "Error in disabling Keypad Interrupt."); + return err; + } + spin_lock_irqsave(&cr_lock, flags); + kp->board->int_status = KP_INT_DISABLED; + spin_unlock_irqrestore(&cr_lock, flags); + return 0; +} + +/** + * u8500_kp_key_irqen- enables keypad interrupt + * + * enables keypad interrupt + */ +int u8500_kp_key_irqen(struct keypad_t *kp) +{ + unsigned long flags; + /* Enable KEYPAD interrupt of STMPE 1601*/ + int err; + /* DEBUG_KP(("u8500_kp_key_irqen\n")); */ + err = stmpe1601_irqen(kp->board->irq); + /* err = stmpe1601_intsrc_set_state(STMPE1601_0, STMPE1601_KEYPAD_IRQ, + STMPE1601_ENABLE_INTERRUPT ); */ + if (err) + printk(KERN_ERR "Error in enabling Keypad Interrupt.= %d", err); + spin_lock_irqsave(&cr_lock, flags); + kp->board->int_status = KP_INT_ENABLED; + spin_unlock_irqrestore(&cr_lock, flags); + return 0; +} + + +/* + * Initializes the key scan table (lookup table) as per pre-defined the scan + * codes to be passed to upper layer with respective key codes + */ +u8 const kpd_lookup_tbl[MAX_KPROW][MAX_KPROW] = { + {KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, + KEY_RESERVED, KEY_9, KEY_RESERVED, KEY_RESERVED}, + {KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, + KEY_POWER, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED}, + {KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_7, + KEY_VOLUMEUP, KEY_RIGHT, KEY_BACK, KEY_RESERVED}, + {KEY_RESERVED, KEY_3, KEY_RESERVED, KEY_DOWN, + KEY_LEFT, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED}, + {KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_UP, + KEY_RESERVED, KEY_RESERVED, KEY_SEND, KEY_RESERVED}, + {KEY_MENU, KEY_RESERVED, KEY_END, KEY_VOLUMEDOWN, + KEY_0, KEY_1, KEY_RESERVED, KEY_RESERVED}, + {KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, + KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_ENTER}, + {KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, + KEY_RESERVED, KEY_RESERVED, KEY_2, KEY_RESERVED} +}; + +/* + * Key table for a complete 8X8 keyboard +{KEY_ESC, KEY_F1, KEY_F2, KEY_F3, KEY_F4, KEY_F5, KEY_F6, KEY_SPACE}, +{KEY_GRAVE, KEY_1, KEY_2, KEY_3, KEY_4, KEY_5, KEY_6, KEY_7}, +{KEY_8, KEY_9, KEY_0, KEY_MINUS, KEY_EQUAL, KEY_BACKSPACE, KEY_INSERT, +KEY_HOME}, +{KEY_TAB, KEY_Q, KEY_W, KEY_E, KEY_R, KEY_T, KEY_Y, KEY_U}, +{KEY_I, KEY_O, KEY_P, KEY_LEFTBRACE, KEY_RIGHTBRACE, KEY_BACKSLASH, +KEY_DELETE, KEY_END}, +{KEY_CAPSLOCK, KEY_A, KEY_S, KEY_D, KEY_F, KEY_G, KEY_H, KEY_J}, +{KEY_K, KEY_L, KEY_SEMICOLON, KEY_APOSTROPHE, KEY_ENTER, KEY_DOT, +KEY_COMMA, KEY_SLASH}, +{KEY_LEFTSHIFT, KEY_Z, KEY_X, KEY_C, KEY_V, KEY_B, KEY_N, KEY_M} +}; +*/ +static struct keypad_device keypad_board = { + .init = u8500_kp_init_key_hardware, + .exit = u8500_kp_exit_key_hardware, + .irqen = u8500_kp_key_irqen, + .irqdis_int = u8500_kp_key_irqdis, + /* .irqdis = u8500_kp_key_irqdis, */ + /* .autoscan_disable = u8500_kp_disable_autoscan, */ + .autoscan_results = u8500_kp_results_autoscan, + /* .autoscan_en=u8500_kp_autoscan_en, */ + .kcode_tbl = (u8 *) kpd_lookup_tbl, + .krow = KPD_NB_ROWS, + .kcol = KPD_NB_COLUMNS, + .debounce_period = KEYPAD_DEBOUNCE_PERIOD_STUIB, + .irqtype = 0, + .irq = KEYPAD_INT, + /* .irq=GPIO_TO_IRQ(KEYPAD_INT), */ + .int_status = KP_INT_DISABLED, + .int_line_behaviour = INT_LINE_NOTSET, + .enable_wakeup = true, +}; + +static struct resource keypad_resources[] = { + [0] = { + .start = KEYPAD_INT, + .end = KEYPAD_INT, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device keypad_device = { + .name = "u8500-kp", + .id = 0, + .dev = { + .platform_data = &keypad_board, + }, + .num_resources = ARRAY_SIZE(keypad_resources), + .resource = keypad_resources, +}; +#endif /* CONFIG_KEYPAD_U8500 */ + +static struct i2s_board_info stm_i2s_board_info[] __initdata = { + { + .modalias = "i2s_device.0", + .platform_data = NULL, + .id = (MSP_0_CONTROLLER - 1), + .chip_select = 0, + }, + { + .modalias = "i2s_device.1", + .platform_data = NULL, + .id = (MSP_1_CONTROLLER - 1), + .chip_select = 1, + }, + { + /* + * XXX mop500_devices.c did not have this originally, and this + * was in device.c. Required? + */ + .modalias = "i2s_device.2", + .platform_data = NULL, /* can be fill some data */ + .id = (MSP_2_CONTROLLER - 1), + .chip_select = 2, + } + +}; + +static struct i2c_platform_data u8500_i2c0_data = { + .gpio_alt_func = GPIO_ALT_I2C_0, + .name = "i2c0", + .own_addr = I2C0_LP_OWNADDR, + .mode = I2C_FREQ_MODE_STANDARD, + .clk_freq = 100000, + .slave_addressing_mode = I2C_7_BIT_ADDRESS, + .digital_filter_control = I2C_DIGITAL_FILTERS_OFF, + .dma_sync_logic_control = I2C_DISABLED, + .start_byte_procedure = I2C_DISABLED, + .slave_data_setup_time = 0xE, + .bus_control_mode = I2C_BUS_MASTER_MODE, + .i2c_loopback_mode = I2C_DISABLED, + .xfer_mode = I2C_TRANSFER_MODE_INTERRUPT, + .high_speed_master_code = 0, + .i2c_tx_int_threshold = 1, + .i2c_rx_int_threshold = 1 +}; + +static struct i2c_platform_data u8500_i2c1_data = { + .gpio_alt_func = GPIO_ALT_I2C_1, + .name = "i2c1", + .own_addr = I2C1_LP_OWNADDR, + .mode = I2C_FREQ_MODE_STANDARD, + .clk_freq = 100000, + .slave_addressing_mode = I2C_7_BIT_ADDRESS, + .digital_filter_control = I2C_DIGITAL_FILTERS_OFF, + .dma_sync_logic_control = I2C_DISABLED, + .start_byte_procedure = I2C_DISABLED, + .slave_data_setup_time = 0xE, + .bus_control_mode = I2C_BUS_MASTER_MODE, + .i2c_loopback_mode = I2C_DISABLED, + .xfer_mode = I2C_TRANSFER_MODE_INTERRUPT, + .high_speed_master_code = 0, + .i2c_tx_int_threshold = 1, + .i2c_rx_int_threshold = 1 +}; + +static struct i2c_platform_data u8500_i2c2_data = { + .gpio_alt_func = GPIO_ALT_I2C_2, + .name = "i2c2", + .own_addr = I2C2_LP_OWNADDR, + .mode = I2C_FREQ_MODE_STANDARD, + .clk_freq = 100000, + .slave_addressing_mode = I2C_7_BIT_ADDRESS, + .digital_filter_control = I2C_DIGITAL_FILTERS_OFF, + .dma_sync_logic_control = I2C_DISABLED, + .start_byte_procedure = I2C_DISABLED, + .slave_data_setup_time = 0xE, + .bus_control_mode = I2C_BUS_MASTER_MODE, + .i2c_loopback_mode = I2C_DISABLED, + .xfer_mode = I2C_TRANSFER_MODE_INTERRUPT, + .high_speed_master_code = 0, + .i2c_tx_int_threshold = 1, + .i2c_rx_int_threshold = 1 +}; + +static struct i2c_platform_data u8500_i2c3_data = { + .gpio_alt_func = GPIO_ALT_I2C_3, + .name = "i2c3", + .own_addr = I2C3_LP_OWNADDR, + .mode = I2C_FREQ_MODE_STANDARD, + .clk_freq = 100000, + .slave_addressing_mode = I2C_7_BIT_ADDRESS, + .digital_filter_control = I2C_DIGITAL_FILTERS_OFF, + .dma_sync_logic_control = I2C_DISABLED, + .start_byte_procedure = I2C_DISABLED, + .slave_data_setup_time = 0xE, + .bus_control_mode = I2C_BUS_MASTER_MODE, + .i2c_loopback_mode = I2C_DISABLED, + .xfer_mode = I2C_TRANSFER_MODE_INTERRUPT, + .high_speed_master_code = 0, + .i2c_tx_int_threshold = 1, + .i2c_rx_int_threshold = 1 +}; + +static struct i2c_platform_data u8500_i2c4_data = { + .gpio_alt_func = GPIO_ALT_I2C_4, + .name = "i2c4", + .own_addr = I2C4_LP_OWNADDR, + .mode = I2C_FREQ_MODE_STANDARD, + .clk_freq = 100000, + .slave_addressing_mode = I2C_7_BIT_ADDRESS, + .digital_filter_control = I2C_DIGITAL_FILTERS_OFF, + .dma_sync_logic_control = I2C_DISABLED, + .start_byte_procedure = I2C_DISABLED, + .slave_data_setup_time = 0xE, + .bus_control_mode = I2C_BUS_MASTER_MODE, + .i2c_loopback_mode = I2C_DISABLED, + .xfer_mode = I2C_TRANSFER_MODE_INTERRUPT, + .high_speed_master_code = 0, + .i2c_tx_int_threshold = 1, + .i2c_rx_int_threshold = 1 +}; + +static struct hsi_board_info __initdata stm_hsi_devices[] = { + {.type = "HSI_LOOPBACK", .flags = 0, .controller_id = 0, + .chan_num = 0, .mode = 1}, + {.type = "HSI_LOOPBACK", .flags = 0, .controller_id = 1, + .chan_num = 0, .mode = 1}, + {.type = "HSI_LOOPBACK", .flags = 0, .controller_id = 0, + .chan_num = 1, .mode = 1}, + {.type = "HSI_LOOPBACK", .flags = 0, .controller_id = 1, + .chan_num = 1, .mode = 1}, + {.type = "HSI_LOOPBACK", .flags = 0, .controller_id = 0, + .chan_num = 2, .mode = 1}, + {.type = "HSI_LOOPBACK", .flags = 0, .controller_id = 1, + .chan_num = 2, .mode = 1}, + {.type = "HSI_LOOPBACK", .flags = 0, .controller_id = 0, + .chan_num = 3, .mode = 1}, + {.type = "HSI_LOOPBACK", .flags = 0, .controller_id = 1, + .chan_num = 3, .mode = 1}, +}; + +static struct platform_device ab8500_gpadc_device = { + .name = "ab8500_gpadc" +}; + +static struct platform_device ab8500_bm_device = { + .name = "ab8500_bm" +}; + +static struct platform_device *u8500_platform_devices[] __initdata = { + /*TODO - add platform devices here */ +#ifdef CONFIG_KEYPAD_U8500 + &keypad_device, +#endif + +}; + +static struct amba_device *amba_board_devs[] __initdata = { + &ux500_uart0_device, + &ux500_uart1_device, + &ux500_uart2_device, + &u8500_ssp0_device, + &u8500_ssp1_device, + &ux500_spi0_device, + &u8500_msp2_spi_device, +}; + +static struct platform_device *platform_board_devs[] __initdata = { + &u8500_msp0_device, + &u8500_msp1_device, + &u8500_msp2_device, + &u8500_hsit_device, + &u8500_hsir_device, + &u8500_shrm_device, + &u8500_ab8500_device, + &ab8500_gpadc_device, + &ab8500_bm_device, + &ux500_musb_device, +#ifdef CONFIG_FB_U8500_MCDE_CHANNELC0 + &u8500_mcde2_device, +#endif /* CONFIG_FB_U8500_MCDE_CHANNELC0 */ +#ifdef CONFIG_FB_U8500_MCDE_CHANNELC1 + &u8500_mcde3_device, +#endif /* CONFIG_FB_U8500_MCDE_CHANNELC1 */ +#ifdef CONFIG_FB_U8500_MCDE_CHANNELB + &u8500_mcde1_device, +#endif /* CONFIG_FB_U8500_MCDE_CHANNELB */ +#ifdef CONFIG_FB_U8500_MCDE_CHANNELA + &u8500_mcde0_device, +#endif /* CONFIG_FB_U8500_MCDE_CHANNELA */ + &ux500_b2r2_device, + &u8500_pmem_device, + &u8500_pmem_mio_device, + &u8500_pmem_hwb_device, +}; + +static void __init mop500_platdata_init(void) +{ +} + + +static void __init mop500_i2c_init(void) +{ + u8500_register_device(&u8500_i2c0_device, &u8500_i2c0_data); + u8500_register_device(&ux500_i2c1_device, &u8500_i2c1_data); + u8500_register_device(&ux500_i2c2_device, &u8500_i2c2_data); + u8500_register_device(&ux500_i2c3_device, &u8500_i2c3_data); + + if (!u8500_is_earlydrop()) + u8500_register_device(&u8500_i2c4_device, &u8500_i2c4_data); +} + +static void __init mop500_init_machine(void) +{ + u8500_init_regulators(); + u8500_init_devices(); + + mop500_platdata_init(); + + amba_add_devices(amba_board_devs, ARRAY_SIZE(amba_board_devs)); + platform_add_devices(platform_board_devs, ARRAY_SIZE(platform_board_devs)); + + mop500_i2c_init(); + + /* enable RTC as a wakeup capable */ + device_init_wakeup(&ux500_rtc_device.dev, true); + + stm_gpio_altfuncenable(GPIO_ALT_UART_0_NO_MODEM); + stm_gpio_altfuncenable(GPIO_ALT_UART_1); + stm_gpio_altfuncenable(GPIO_ALT_UART_2); + + if (MOP500_PLATFORM_ID == platform_id) + i2c_register_board_info(0, nmdk_i2c0_egpio_devices, + ARRAY_SIZE(nmdk_i2c0_egpio_devices)); + else if (HREF_PLATFORM_ID == platform_id) + i2c_register_board_info(0, nmdk_i2c0_egpio1_devices, + ARRAY_SIZE(nmdk_i2c0_egpio1_devices)); + + i2c_register_board_info(0, u8500_i2c0_devices, + ARRAY_SIZE(u8500_i2c0_devices)); + i2c_register_board_info(1, u8500_i2c1_devices, + ARRAY_SIZE(u8500_i2c1_devices)); + i2c_register_board_info(2, u8500_i2c2_devices, + ARRAY_SIZE(u8500_i2c2_devices)); + i2c_register_board_info(3, u8500_i2c3_devices, + ARRAY_SIZE(u8500_i2c3_devices)); + i2s_register_board_info(stm_i2s_board_info, + ARRAY_SIZE(stm_i2s_board_info)); + hsi_register_board_info(stm_hsi_devices, ARRAY_SIZE(stm_hsi_devices)); + + platform_add_devices(u8500_platform_devices, + ARRAY_SIZE(u8500_platform_devices)); +} + +MACHINE_START(NOMADIK, "ST-Ericsson U8500 Platform") + /* Maintainer: ST-Ericsson */ + .phys_io = UX500_UART2_BASE, + .io_pg_offst = (IO_ADDRESS(UX500_UART2_BASE) >> 18) & 0xfffc, + .boot_params = 0x00000100, + .map_io = u8500_map_io, + .init_irq = u8500_init_irq, + .timer = &u8500_timer, + .init_machine = mop500_init_machine, +MACHINE_END diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c new file mode 100755 index 00000000000..8349b0c87c8 --- /dev/null +++ b/arch/arm/mach-ux500/platsmp.c @@ -0,0 +1,224 @@ +/* + * Copyright (C) 2009 ST Ericsson. + * this file is heavily based on ARM realview platform + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/init.h> +#include <linux/errno.h> +#include <linux/delay.h> +#include <linux/device.h> +#include <linux/jiffies.h> +#include <linux/smp.h> + +#include <asm/cacheflush.h> +#include <mach/scu.h> +#include <mach/hardware.h> +#include <asm/io.h> + +extern void u8500_secondary_startup(void); + +/* + * control for which core is the next to come out of the secondary + * boot "holding pen" + */ +volatile int __cpuinitdata pen_release = -1; + +static unsigned int __init get_core_count(void) +{ + unsigned int ncores; + + ncores = __raw_readl(IO_ADDRESS(UX500_SCU_BASE) + SCU_CONFIG); + + return (ncores & 0x03) + 1; +} + +/* + * Setup the SCU + */ +static void scu_enable(void) +{ + u32 scu_ctrl; + + scu_ctrl = __raw_readl(IO_ADDRESS(UX500_SCU_BASE) + SCU_CTRL); + scu_ctrl |= 1; + __raw_writel(scu_ctrl, IO_ADDRESS(UX500_SCU_BASE) + SCU_CTRL); +} + +static DEFINE_SPINLOCK(boot_lock); + +void __cpuinit platform_secondary_init(unsigned int cpu) +{ + trace_hardirqs_off(); + /* + * the primary core may have used a "cross call" soft interrupt + * to get this processor out of WFI in the BootMonitor - make + * sure that we are no longer being sent this soft interrupt + */ + smp_cross_call_done(cpumask_of(cpu)); + + /* + * if any interrupts are already enabled for the primary + * core (e.g. timer irq), then they will not have been enabled + * for us: do so + */ + gic_cpu_init(0, (void __iomem *)IO_ADDRESS(UX500_GIC_CPU_BASE)); + + /* + * let the primary processor know we're out of the + * pen, then head off into the C entry point + */ + pen_release = -1; + smp_wmb(); + + /* + * Synchronise with the boot thread. + */ + spin_lock(&boot_lock); + spin_unlock(&boot_lock); +} + +int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + unsigned long timeout; + + /* + * set synchronisation state between this boot processor + * and the secondary one + */ + spin_lock(&boot_lock); + + /* + * The secondary processor is waiting to be released from + * the holding pen - release it, then wait for it to flag + * that it has been released by resetting pen_release. + * + * Note that "pen_release" is the hardware CPU ID, whereas + * "cpu" is Linux's internal ID. + */ + flush_cache_all(); + outer_clean_range(__pa(&secondary_data), __pa(&secondary_data) + 1); + pen_release = cpu; + flush_cache_all(); + outer_clean_range(__pa(&pen_release), __pa(&pen_release) + 1); + + /* + * XXX + * + * This is a later addition to the booting protocol: the + * bootMonitor now puts secondary cores into WFI, so + * wakeup_secondary() no longer gets the cores moving; we need + * to send a soft interrupt to wake the secondary core. + * Use smp_cross_call() for this, since there's little + * point duplicating the code here + */ + smp_cross_call(cpumask_of(cpu)); + + timeout = jiffies + (1 * HZ); + while (time_before(jiffies, timeout)) { + smp_rmb(); + if (pen_release == -1) + break; + + udelay(10); + } + /* + * now the secondary core is starting up let it run its + * calibrations, then wait for it to finish + */ + spin_unlock(&boot_lock); + + return pen_release != -1 ? -ENOSYS : 0; +} + +static void __init wakeup_secondary(void) +{ + extern void secondary_startup(void); + + /* nobody is to be released from the pen yet */ + pen_release = -1; + /* + * write the address of secondary startup into the backram0 + * register at offset 0x1FF4, then write magic number(0xA1FEED01) + * to the backram0 register at offset 0x1FF0, which is what + * BootMonitor is waiting for + */ +#define U8500_CPU1_JUMPADDR_OFFSET 0x1FF4 + __raw_writel(virt_to_phys(u8500_secondary_startup), + (void __iomem *)IO_ADDRESS(UX500_BACKUPRAM0_BASE) + + U8500_CPU1_JUMPADDR_OFFSET); +#define U8500_CPU1_WAKEMAGIC_OFFSET 0x1FF0 + __raw_writel(0xA1FEED01, + (void __iomem *)IO_ADDRESS(UX500_BACKUPRAM0_BASE) + + U8500_CPU1_WAKEMAGIC_OFFSET); + mb(); +} + +/* + * Initialise the CPU possible map early - this describes the CPUs + * which may be present or become present in the system. + */ +void __init smp_init_cpus(void) +{ + unsigned int i, ncores = get_core_count(); + + for (i = 0; i < ncores; i++) + cpu_set(i, cpu_possible_map); +} + +void __init smp_prepare_cpus(unsigned int max_cpus) +{ + unsigned int ncores = get_core_count(); + unsigned int cpu = smp_processor_id(); + int i; + + /* sanity check */ + if (ncores == 0) { + printk(KERN_ERR + "U8500: strange CM count of 0? Default to 1\n"); + + ncores = 1; + } + + if (ncores > NR_CPUS) { + printk(KERN_WARNING + "U8500: no. of cores (%d) greater than configured " + "maximum of %d - clipping\n", + ncores, NR_CPUS); + ncores = NR_CPUS; + } + + smp_store_cpu_info(cpu); + + /* + * are we trying to boot more cores than exist? + */ + if (max_cpus > ncores) + max_cpus = ncores; + + /* + * Enable the local timer for primary CPU + */ +#ifdef CONFIG_LOCAL_TIMERS + local_timer_setup(); +#endif + /* + * Initialise the present map, which describes the set of CPUs + * actually populated at the present time. + */ + for (i = 0; i < max_cpus; i++) + cpu_set(i, cpu_present_map); + + /* + * Do we need any more CPUs? If so, then let them know where + * to start. Note that, on modern versions of MILO, the "poke" + * doesn't actually do anything until each individual core is + * sent a soft interrupt to get it out of WFI + */ + if (max_cpus > 1) { + scu_enable(); + wakeup_secondary(); + } +} diff --git a/arch/arm/mach-ux500/pm.c b/arch/arm/mach-ux500/pm.c new file mode 100755 index 00000000000..f753ef11eea --- /dev/null +++ b/arch/arm/mach-ux500/pm.c @@ -0,0 +1,78 @@ +/* + * Copyright 2009 STMicroelectronics. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + */ + +/* U8500 platform suspend/resume support */ + +#include <linux/init.h> +#include <linux/module.h> +#include <linux/suspend.h> +#include <linux/errno.h> +#include <linux/time.h> + +#include <asm/memory.h> +#include <asm/system.h> + +#include <mach/prcmu-fw-api.h> + +static int u8500_pm_begin(suspend_state_t state) +{ + return 0; +} + +static int u8500_pm_prepare(void) +{ + return 0; +} + +static int u8500_pm_enter(suspend_state_t state) +{ + int ret; + + switch (state) { + case PM_SUSPEND_STANDBY: + prcmu_apply_ap_state_transition(APEXECUTE_TO_APIDLE, + DDR_PWR_STATE_UNCHANGED, 0); + ret = 0; + break; + case PM_SUSPEND_MEM: + prcmu_apply_ap_state_transition(APEXECUTE_TO_APSLEEP, + DDR_PWR_STATE_UNCHANGED, 0); + ret = 0; + break; + default: + ret = -EINVAL; + } + + return ret; +} + +static void u8500_pm_finish(void) +{ + +} + +static int u8500_pm_valid(suspend_state_t state) +{ + return (state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY); +} + +static struct platform_suspend_ops u8500_pm_ops = { + .begin = u8500_pm_begin, + .prepare = u8500_pm_prepare, + .enter = u8500_pm_enter, + .finish = u8500_pm_finish, + .valid = u8500_pm_valid, +}; + +static int __init u8500_pm_init(void) +{ + suspend_set_ops(&u8500_pm_ops); + return 0; +} + +device_initcall(u8500_pm_init); diff --git a/arch/arm/mach-ux500/prcmu-fw.c b/arch/arm/mach-ux500/prcmu-fw.c new file mode 100755 index 00000000000..44208066790 --- /dev/null +++ b/arch/arm/mach-ux500/prcmu-fw.c @@ -0,0 +1,1992 @@ +/* + * Copyright 2009 ST-Ericsson. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + */ + +/* Routines to talk to PRCMU firmware services */ + +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/delay.h> +#include <linux/errno.h> +#include <linux/err.h> +#include <linux/ktime.h> +#include <linux/spinlock.h> +#include <linux/io.h> + +#include <mach/hardware.h> +#include <mach/prcmu-regs.h> +#include "prcmu-fw_ed.h" +#include "prcmu-fw_v1.h" + +#define NAME "PRCMU" +#define PM_DEBUG 0 +#define dbg_printk(format, arg...) (PM_DEBUG & 1) ? \ + (printk(KERN_ALERT NAME ": " format , ## arg)) : \ + ({do {} while (0); }) + +void __iomem *rtc_register_base ; + +struct hw_usage{ + char b2r2:1; + char mcde:1; + char esram1:1; + char esram2:1; + char esram3:1; + char esram4:1; +}; +struct hw_usage hw_usg_state = {0}; + +/* TASKLET declarations */ +static void prcmu_ack_mb7_status_tasklet(unsigned long); +DECLARE_TASKLET(prcmu_ack_mb7_tasklet, prcmu_ack_mb7_status_tasklet, 0); + +static void prcmu_ack_mb0_wkuph_status_tasklet(unsigned long); +DECLARE_TASKLET(prcmu_ack_mb0_wkuph_tasklet, \ + prcmu_ack_mb0_wkuph_status_tasklet, 0); + + +/* WAITQUEUES */ +DECLARE_WAIT_QUEUE_HEAD(ack_mb0_queue); +DECLARE_WAIT_QUEUE_HEAD(ack_mb5_queue); +DECLARE_WAIT_QUEUE_HEAD(ack_mb7_queue); + +/* Global var to determine if ca_wake_req is pending or not */ +static int ca_wake_req_pending; + +/* function pointer for shrm callback sequence for modem waking up arm */ +static void (*prcmu_ca_wake_req_shrm_callback)(u8); + +/* function pointer for shrm callback sequence for modem requesting reset */ +static void (*prcmu_modem_reset_shrm)(void); + +static int prcmu_set_hwacc_st(enum hw_acc_t hw_acc, enum hw_accst_t hw_accst); + +/* Internal functions */ + +/** + * _wait_for_req_complete () - used for PWRSTTRH for AckMb0 and AckMb1 on V1 + * @num: Mailbox number to operate on + * + * Polling loop to ensure that PRCMU FW has completed the requested op + */ +int _wait_for_req_complete(enum mailbox_t num) +{ + int timeout = 1000; + + if (u8500_is_earlydrop()) { + + /* Clear any error/status */ + writel(0, PRCM_ACK_MB0_ED); + /* Set an interrupt to XP70 */ + writel(1 << num, PRCM_MBOX_CPU_SET); + /* As of now only polling method, need to check if interrupt + * possible ?? TODO */ + while ((readl(PRCM_MBOX_CPU_VAL) & (1 << num)) && timeout--) + cpu_relax(); + + if (!timeout) + return -EBUSY; + else + return readl(PRCM_ACK_MB0_ED); + + + } else { + + /* checking any already on-going transaction */ + while ((readl(PRCM_MBOX_CPU_VAL) & (1 << num)) && timeout--) + cpu_relax(); + + timeout = 1000; + + + /* Clear any error/status */ + if (num == REQ_MB0) + writeb(0, PRCM_ACK_MB0_AP_PWRST_STATUS); + else if (num == REQ_MB1) + writel(0, PRCM_ACK_MB1); + else if (num == REQ_MB2) + writel(0, PRCM_ACK_MB2); + + + + /* Set an interrupt to XP70 */ + writel(1 << num, PRCM_MBOX_CPU_SET); + /* As of now only polling method, need to check if interrupt + * possible ?? TODO */ + while ((readl(PRCM_MBOX_CPU_VAL) & (1 << num)) && timeout--) + cpu_relax(); + + + if (!timeout) + return -EBUSY; + + return 0; + + } + +} + +/** + * prcmu_request_mailbox0 - request op on mailbox0 + * @req: mailbox0 type param + * + * Fill up the mailbox 0 required fields and call polling loop + */ +int prcmu_request_mailbox0(union req_mb0_t *req) +{ + if (u8500_is_earlydrop()) { + writel(req->complete_field, PRCM_REQ_MB0_ED); + return _wait_for_req_complete(REQ_MB0_ED); + + } else { + writel(req->complete_field, PRCM_REQ_MB0); + return _wait_for_req_complete(REQ_MB0); + } +} + +/** + * prcmu_request_mailbox1 - request op on mailbox1 + * @req: mailbox1 type param + * + * Fill up the mailbox 1 required fields and call polling loop + */ +int prcmu_request_mailbox1(union req_mb1_t *req) +{ + if (u8500_is_earlydrop()) { + writew(req->complete_field, PRCM_REQ_MB1_ED); + return _wait_for_req_complete(REQ_MB1_ED); + } else { + writew(req->complete_field, PRCM_REQ_MB1); + return _wait_for_req_complete(REQ_MB1); + } +} + +/** + * prcmu_request_mailbox2 - request op on mailbox2 + * @req: mailbox2 type param + * + * Fill up the mailbox 2 required fields and call polling loop + */ +int prcmu_request_mailbox2(union req_mb2_t *req) +{ + if (u8500_is_earlydrop()) { + writel(req->complete_field[0], PRCM_REQ_MB2_ED); + writel(req->complete_field[1], PRCM_REQ_MB2_ED + 4); + writel(req->complete_field[2], PRCM_REQ_MB2_ED + 8); + return _wait_for_req_complete(REQ_MB2_ED); + + } else { + writel(req->complete_field[0], PRCM_REQ_MB2); + writel(req->complete_field[1], PRCM_REQ_MB2 + 4); + writel(req->complete_field[2], PRCM_REQ_MB2 + 8); + return _wait_for_req_complete(REQ_MB2); + } + +} + +/* Exported APIs */ + +/** + * prcmu_get_boot_status - PRCMU boot status checking + * Returns: the current PRCMU boot status + */ +int prcmu_get_boot_status(void) +{ + if (u8500_is_earlydrop()) + return readb(PRCM_BOOT_STATUS_ED); + else + return readb(PRCM_BOOT_STATUS); +} +EXPORT_SYMBOL(prcmu_get_boot_status); + +/** + * prcmu_set_rc_a2p - This function is used to run few power state sequences + * @val: Value to be set, i.e. transition requested + * Returns: 0 on success, -EINVAL on invalid argument + * + * This function is used to run the following power state sequences - + * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep + */ +int prcmu_set_rc_a2p(enum romcode_write_t val) +{ + if (u8500_is_earlydrop()) { + if (val < RDY_2_DS_ED || val > RDY_2_XP70_RST_ED) + return -EINVAL; + writeb(val, PRCM_ROMCODE_A2P_ED); + return 0; + } + + + if (val < RDY_2_DS || val > RDY_2_XP70_RST) + return -EINVAL; + writeb(val, PRCM_ROMCODE_A2P); + return 0; +} +EXPORT_SYMBOL(prcmu_set_rc_a2p); + +/** + * prcmu_get_rc_p2a - This function is used to get power state sequences + * Returns: the power transition that has last happened + * + * This function can return the following transitions- + * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep + */ +enum romcode_read_t prcmu_get_rc_p2a(void) +{ + if (u8500_is_earlydrop()) + return readb(PRCM_ROMCODE_P2A_ED); + + + return readb(PRCM_ROMCODE_P2A); +} +EXPORT_SYMBOL(prcmu_get_rc_p2a); + +/** + * prcmu_get_current_mode - Return the current XP70 power mode + * Returns: Returns the current AP(ARM) power mode: init, + * apBoot, apExecute, apDeepSleep, apSleep, apIdle, apReset + */ +enum ap_pwrst_t prcmu_get_xp70_current_state(void) +{ + if (u8500_is_earlydrop()) + return readb(PRCM_AP_PWR_STATE_ED); + + + return readb(PRCM_XP70_CUR_PWR_STATE); +} +EXPORT_SYMBOL(prcmu_get_xp70_current_state); + +/** + * prcmu_set_ap_mode - set the appropriate AP power mode + * @ap_pwrst_trans: Transition to be requested to move to new AP power mode + * Returns: 0 on success, non-zero on failure + * + * This function set the appropriate AP power mode. + * The caller can check the status following this call. + */ +int prcmu_set_ap_mode(enum ap_pwrst_trans_t ap_pwrst_trans) +{ + union req_mb0_t request = { {0} }; + + if (u8500_is_earlydrop()) { + if (ap_pwrst_trans + && (ap_pwrst_trans < APEXECUTE_TO_APSLEEP_ED + || ap_pwrst_trans > APEXECUTE_TO_APIDLE_ED)) + return -EINVAL; + request.req_field.ap_pwrst_trans = ap_pwrst_trans; + return prcmu_request_mailbox0(&request); + } + + if (ap_pwrst_trans + && (ap_pwrst_trans < APEXECUTE_TO_APSLEEP + || ap_pwrst_trans > APEXECUTE_TO_APIDLE)) + return -EINVAL; + request.req_field.ap_pwrst_trans = ap_pwrst_trans; + return prcmu_request_mailbox0(&request); +} +EXPORT_SYMBOL(prcmu_set_ap_mode); + +/** + * prcmu_set_fifo_4500wu - Configures 4500 fifo interrupt as wake-up events + * @fifo_4500wu: The 4500 fifo interrupt to be configured as wakeup or not + * Returns: 0 on success, non-zero on failure + * + * This function de/configures 4500 fifo interrupt as wake-up events + * The caller can check the status following this call. + */ +int prcmu_set_fifo_4500wu(enum intr_wakeup_t fifo_4500wu) +{ + union req_mb0_t request = { {0} }; + + if (u8500_is_earlydrop()) { + if (fifo_4500wu < INTR_NOT_AS_WAKEUP_ED \ + || fifo_4500wu > INTR_AS_WAKEUP_ED) + return -EINVAL; + request.req_field.fifo_4500wu = fifo_4500wu; + return prcmu_request_mailbox0(&request); + } + + if (fifo_4500wu < INTR_NOT_AS_WAKEUP || fifo_4500wu > INTR_AS_WAKEUP) + return -EINVAL; + request.req_field.fifo_4500wu = fifo_4500wu; + return prcmu_request_mailbox0(&request); +} +EXPORT_SYMBOL(prcmu_set_fifo_4500wu); + +/** + * prcmu_set_ddr_pwrst - set the appropriate DDR power mode + * @ddr_pwrst: Power mode of DDR to which DDR needs to be switched + * Returns: 0 on success, non-zero on failure + * + * This function is not supported on ED by the PRCMU firmware + */ +int prcmu_set_ddr_pwrst(enum ddr_pwrst_t ddr_pwrst) +{ + union req_mb0_t request = { {0} }; + + if (u8500_is_earlydrop()) { + if (ddr_pwrst < DDR_PWR_STATE_UNCHANGED_ED || \ + ddr_pwrst > TOBEDEFINED_ED) + return -EINVAL; + request.req_field.ddr_pwrst = ddr_pwrst; + return prcmu_request_mailbox0(&request); + } + + if (ddr_pwrst < DDR_PWR_STATE_UNCHANGED || \ + ddr_pwrst > DDR_PWR_STATE_OFFHIGHLAT) + return -EINVAL; + request.req_field.ddr_pwrst = ddr_pwrst; + return prcmu_request_mailbox0(&request); +} +EXPORT_SYMBOL(prcmu_set_ddr_pwrst); + +/** + * prcmu_set_arm_opp - set the appropriate ARM OPP + * @arm_opp: The new ARM operating point to which transition is to be made + * Returns: 0 on success, non-zero on failure + * + * This function set the appropriate ARM operation mode + * The caller can check the status following this call. + * NOTE : THE PRCMU DOES NOT ISSUE AN IT TO ARM FOR A DVFS + * XISITION REQUEST. HENCE WE DO NOT NEED A MAILBOX + * TIMEOUT WAIT HERE FOR OPP DVFS + */ +int prcmu_set_arm_opp(enum arm_opp_t arm_opp) +{ + int timeout = 200; + enum arm_opp_t current_arm_opp; + + if (u8500_is_earlydrop()) { + if (arm_opp < ARM_NO_CHANGE_ED || arm_opp > ARM_EXTCLK_ED) + return -EINVAL; + /* check for any ongoing AP state transitions */ + while ((readl(PRCM_MBOX_CPU_VAL) & 1) && timeout--) + cpu_relax(); + if (!timeout) + return -EBUSY; + /* check for any ongoing ARM DVFS */ + timeout = 200; + while ((readb(PRCM_M2A_DVFS_STAT_ED) == 0xff) && timeout--) + cpu_relax(); + if (!timeout) + return -EBUSY; + + /* Clear any error/status */ + writel(0, PRCM_ACK_MB0_ED); + + writeb(arm_opp, PRCM_ARM_OPP_ED); + writeb(APE_NO_CHANGE, PRCM_APE_OPP_ED); + writel(2, PRCM_MBOX_CPU_SET); + + timeout = 1000; + while ((readl(PRCM_MBOX_CPU_VAL) & 2) && timeout--) + cpu_relax(); + + /* TODO: read mbox to ARM error here.. */ + return 0; + } + + + if (arm_opp < ARM_NO_CHANGE || arm_opp > ARM_EXTCLK) + return -EINVAL; + + /* check for any ongoing AP state transitions */ + while ((readl(PRCM_MBOX_CPU_VAL) & 1) && timeout--) + cpu_relax(); + if (!timeout) + return -EBUSY; + + /* check for any ongoing ARM DVFS */ + timeout = 200; + while ((readb(PRCM_ACK_MB1_CURR_DVFS_STATUS) == 0xff) && timeout--) + cpu_relax(); + if (!timeout) + return -EBUSY; + + /* clear the mailbox */ + writel(0, PRCM_ACK_MB1); + + /* write 0x0 into the header for ARM/APE operating point mgmt */ + writel(0x0, _PRCM_MBOX_HEADER); + + /* write ARMOPP request into the mailbox */ + writel(arm_opp, PRCM_REQ_MB1_ARMOPP); + writel(APE_NO_CHANGE, PRCM_REQ_MB1_APEOPP); + + _wait_for_req_complete(REQ_MB1); + + current_arm_opp = readb(PRCM_ACK_MB1_CURR_ARMOPP); + if (arm_opp != current_arm_opp) { + printk(KERN_WARNING + "u8500-prcm : requested ARM DVFS Not Complete\n"); + return -EINVAL; + } + + return 0; +} +EXPORT_SYMBOL(prcmu_set_arm_opp); + +/** + * prcmu_get_arm_opp - get the appropriate ARM OPP + * + * Returns: the current ARM OPP + */ +int prcmu_get_arm_opp(void) +{ + return readb(PRCM_ACK_MB1_CURR_ARMOPP); +} +EXPORT_SYMBOL(prcmu_get_arm_opp); + +/** + * prcmu_set_ape_opp - set the appropriate APE OPP + * @ape_opp: The new APE operating point to which transition is to be made + * Returns: 0 on success, non-zero on failure + * + * This function set the appropriate APE operation mode + * The caller can check the status following this call. + */ +int prcmu_set_ape_opp(enum ape_opp_t ape_opp) +{ + int timeout = 200; + enum ape_opp_t current_ape_opp; + + if (ape_opp < APE_NO_CHANGE || ape_opp > APE_50_OPP) + return -EINVAL; + + /* check for any ongoing AP state transitions */ + while ((readl(PRCM_MBOX_CPU_VAL) & 1) && timeout--) + cpu_relax(); + if (!timeout) + return -EBUSY; + + /* check for any ongoing ARM DVFS */ + timeout = 200; + while ((readb(PRCM_ACK_MB1_CURR_DVFS_STATUS) == 0xff) && timeout--) + cpu_relax(); + if (!timeout) + return -EBUSY; + + /* clear the mailbox */ + writel(0, PRCM_ACK_MB1); + + /* write 0x0 into the header for ARM/APE operating point mgmt */ + writel(0x0, _PRCM_MBOX_HEADER); + + /* write ARMOPP request into the mailbox */ + writel(ARM_NO_CHANGE, PRCM_REQ_MB1_ARMOPP); + writel(ape_opp, PRCM_REQ_MB1_APEOPP); + + /* trigger the XP70 IT11 to the XP70 */ + writel(PRCM_XP70_TRIG_IT11, PRCM_MBOX_CPU_SET); + + timeout = 1000; + while ((readl(PRCM_MBOX_CPU_VAL) & PRCM_XP70_TRIG_IT11) + && timeout--) + cpu_relax(); + + current_ape_opp = readb(PRCM_ACK_MB1_CURR_APEOPP); + if (ape_opp != current_ape_opp) { + printk(KERN_WARNING + "u8500-prcm : requested APE DVFS Not Complete\n"); + return -EINVAL; + } + + return 0; +} +EXPORT_SYMBOL(prcmu_set_ape_opp); + +/** + * prcmu_get_arm_opp - get the appropriate ARM OPP + * + * Returns: the current ARM OPP + */ +int prcmu_get_ape_opp(void) +{ + return readb(PRCM_ACK_MB1_CURR_APEOPP); +} +EXPORT_SYMBOL(prcmu_get_ape_opp); + + +int prcmu_set_hwacc(enum hw_acc_dev hw_acc, enum hw_accst_t hw_accst) +{ + enum hw_acc_t hw_acc_device; + + /* check on which device is being used */ + switch (hw_acc) { + case HW_ACC_SVAMMDSP: + hw_acc_device = SVAMMDSP; + break; + case HW_ACC_SVAPIPE: + hw_acc_device = SVAPIPE; + break; + case HW_ACC_SIAMMDSP: + hw_acc_device = SIAMMDSP; + break; + case HW_ACC_SIAPIPE: + hw_acc_device = SIAPIPE; + break; + case HW_ACC_SGA: + hw_acc_device = SGA; + break; + case HW_ACC_B2R2: + if (hw_accst == HW_ON) + hw_usg_state.b2r2 = 1; + else if (hw_accst == HW_OFF) + hw_usg_state.b2r2 = 0; + + if (hw_usg_state.mcde == 1) + return -EINVAL; + hw_acc_device = B2R2MCDE; + break; + case HW_ACC_MCDE: + if (hw_accst == HW_ON) + hw_usg_state.mcde = 1; + else if (hw_accst == HW_OFF) + hw_usg_state.mcde = 0; + + if (hw_usg_state.b2r2 == 1) + return -EINVAL; + hw_acc_device = B2R2MCDE; + break; + case HW_ACC_ESRAM1: + if (hw_accst == HW_ON) + hw_usg_state.esram1 = 1; + else if (hw_accst == HW_OFF) + hw_usg_state.esram1 = 0; + + if (hw_usg_state.esram2 == 1) + return -EINVAL; + hw_acc_device = ESRAM1; + break; + case HW_ACC_ESRAM2: + if (hw_accst == HW_ON) + hw_usg_state.esram2 = 1; + else if (hw_accst == HW_OFF) + hw_usg_state.esram2 = 0; + + if (hw_usg_state.esram1 == 1) + return -EINVAL; + hw_acc_device = ESRAM2; + break; + case HW_ACC_ESRAM3: + if (hw_accst == HW_ON) + hw_usg_state.esram3 = 1; + else if (hw_accst == HW_OFF) + hw_usg_state.esram3 = 0; + + if (hw_usg_state.esram4 == 1) + return -EINVAL; + hw_acc_device = ESRAM3; + break; + case HW_ACC_ESRAM4: + if (hw_accst == HW_ON) + hw_usg_state.esram4 = 1; + else if (hw_accst == HW_OFF) + hw_usg_state.esram4 = 0; + + if (hw_usg_state.esram3 == 1) + return -EINVAL; + hw_acc_device = ESRAM4; + break; + default: + return -EINVAL; + }; + return prcmu_set_hwacc_st(hw_acc_device, hw_accst); +} +EXPORT_SYMBOL(prcmu_set_hwacc); + + +/** + * prcmu_set_ape_opp - set the appropriate h/w accelerator to power mode + * @hw_acc: the hardware accelerator being considered + * @hw_accst: The new h/w accelerator state(on/off/retention) + * Returns: 0 on success, non-zero on failure + * + * This function set the appropriate hardware accelerator to the requested + * power mode. + * The caller can check the status following this call. + */ +static int prcmu_set_hwacc_st(enum hw_acc_t hw_acc, enum hw_accst_t hw_accst) +{ + union req_mb2_t request; + int err = 0; + if (u8500_is_earlydrop()) { + if (hw_acc < SVAMMDSP_ED || hw_acc > ESRAM4_ED || + hw_accst < HW_NO_CHANGE_ED || hw_accst \ + > HW_ON_ED) + return -EINVAL; + memset(&request, 0x0, sizeof(request)); + request.hw_accst_list[hw_acc].hw_accst = hw_accst; + return prcmu_request_mailbox2(&request); + } + + if (hw_acc < SVAMMDSP || hw_acc > ESRAM4 || + hw_accst < HW_NO_CHANGE || hw_accst > HW_ON) + return -EINVAL; + + /* write the header into mailbox 2 */ + writeb(DPS_H, PRCM_MBOX_HEADER_REQ_MB2); + /* fill out the request */ + writel(0x0, PRCM_REQ_MB2_DPS_SVAMMDSP); + writel(0x0, PRCM_REQ_MB2_DPS_SGA); + writeb(hw_accst, PRCM_REQ_MB2 + hw_acc); + /* request for completion */ + err = _wait_for_req_complete(REQ_MB2); + printk("\n readb(PRCM_ACK_MB2) = %x\n", readb(PRCM_ACK_MB2));\ + if (readb(PRCM_ACK_MB2) == HWACC_PWRST_OK) + err = 0; + else + err = -EINVAL; + return err; +} + +/** + * prcmu_get_m2a_status - Get the status or transition of the last request + * Returns: The status from MBOX to ARM during the last request. + * See the list of status/transitions for details. + */ +enum mbox_2_arm_stat_ed_t prcmu_get_m2a_status(void) +{ + return readb(PRCM_M2A_STATUS_ED); +} +EXPORT_SYMBOL(prcmu_get_m2a_status); + +/** + * prcmu_get_m2a_error - Get the error that occured in last request + * Returns: The error from MBOX to ARM during the last request. + * See the list of errors for details. + */ +enum mbox_to_arm_err_ed_t prcmu_get_m2a_error(void) +{ + return readb(PRCM_M2A_ERROR_ED); +} +EXPORT_SYMBOL(prcmu_get_m2a_error); + +/** + * prcmu_get_m2a_dvfs_status - Get the state of DVFS transition + * Returns: Either that state transition on DVFS is on going + * or completed, 0 if not used. + */ +enum dvfs_stat_t prcmu_get_m2a_dvfs_status(void) +{ + if (u8500_is_earlydrop()) + return readb(PRCM_M2A_DVFS_STAT_ED); + + + return 0; +} +EXPORT_SYMBOL(prcmu_get_m2a_dvfs_status); + +/** + * prcmu_get_m2a_hwacc_status - Get the state of HW Accelerator + * Returns: Either that state transition on hardware accelerator + * is on going or completed, 0 if not used. + */ +enum mbox_2_arm_hwacc_pwr_stat_t prcmu_get_m2a_hwacc_status(void) +{ + if (u8500_is_earlydrop()) + return readb(PRCM_M2A_HWACC_STAT_ED); + + + return 0; +} +EXPORT_SYMBOL(prcmu_get_m2a_hwacc_status); + +/** + * prcmu_set_irq_wakeup - set the ARM IRQ wake-up events + * @irq: ARM IRQ that needs to be set as wake up source + * Returns: 0 on success, -EINVAL on invalid argument + */ +int prcmu_set_irq_wakeup(uint32_t irq) +{ + unsigned long mask_reg; + + + if (irq < 32) { + mask_reg = PRCM_ARMITMSK31TO0; + } else if (irq < 64) { + mask_reg = PRCM_ARMITMSK63TO32; + irq -= 32; + } else if (irq < 96) { + mask_reg = PRCM_ARMITMSK95TO64; + irq -= 64; + } else if (irq < 128) { + mask_reg = PRCM_ARMITMSK127TO96; + irq -= 96; + } else + return -EINVAL; + + writel(1 << irq | readl((volatile unsigned long *)(mask_reg)), + (volatile unsigned long *)(mask_reg)); + return 0; +} +EXPORT_SYMBOL(prcmu_set_irq_wakeup); + +/* FIXME : Make these generic enough to pass backup + * addresses for re-using the same functions + * for sleep/deep sleep modes + */ +/* Context Backups for ApSleep */ +unsigned int PRCC_backup[15]; + +#define _PRCC_CLK_RST1_BASE IO_ADDRESS(U8500_PER1_BASE + 0xF000) +#define _PRCC_CLK_RST2_BASE IO_ADDRESS(U8500_PER2_BASE + 0xF000) +#define _PRCC_CLK_RST3_BASE IO_ADDRESS(U8500_PER3_BASE + 0xF000) +#define _PRCC_CLK_RST5_BASE IO_ADDRESS(U8500_PER5_BASE + 0x1F000) +#define _PRCC_CLK_RST6_BASE IO_ADDRESS(U8500_PER6_BASE + 0xF000) +#define _PRCC_CLK_RST7_BASE IO_ADDRESS(U8500_PER7_BASE_ED + 0xF000) + +void pm_save_config_PRCC(void) +{ + uint8_t i = 0; + + PRCC_backup[i++] = readl(_PRCC_CLK_RST1_BASE + 0x10); + PRCC_backup[i++] = readl(_PRCC_CLK_RST1_BASE + 0x14); + PRCC_backup[i++] = readl(_PRCC_CLK_RST2_BASE + 0x10); + PRCC_backup[i++] = readl(_PRCC_CLK_RST2_BASE + 0x14); + PRCC_backup[i++] = readl(_PRCC_CLK_RST3_BASE + 0x10); + PRCC_backup[i++] = readl(_PRCC_CLK_RST3_BASE + 0x14); + PRCC_backup[i++] = readl(_PRCC_CLK_RST5_BASE + 0x10); + PRCC_backup[i++] = readl(_PRCC_CLK_RST5_BASE + 0x14); + PRCC_backup[i++] = readl(_PRCC_CLK_RST6_BASE + 0x10); + PRCC_backup[i++] = readl(_PRCC_CLK_RST6_BASE + 0x14); + PRCC_backup[i++] = readl(_PRCC_CLK_RST7_BASE + 0x10); + PRCC_backup[i++] = readl(_PRCC_CLK_RST7_BASE + 0x14); +} + +void pm_restore_config_PRCC(void) +{ + uint8_t i = 0; + + writel(PRCC_backup[i++], _PRCC_CLK_RST1_BASE + 0x0); + writel(PRCC_backup[i++], _PRCC_CLK_RST1_BASE + 0x8); + writel(PRCC_backup[i++], _PRCC_CLK_RST2_BASE + 0x0); + writel(PRCC_backup[i++], _PRCC_CLK_RST2_BASE + 0x8); + writel(PRCC_backup[i++], _PRCC_CLK_RST3_BASE + 0x0); + writel(PRCC_backup[i++], _PRCC_CLK_RST3_BASE + 0x8); + writel(PRCC_backup[i++], _PRCC_CLK_RST5_BASE + 0x0); + writel(PRCC_backup[i++], _PRCC_CLK_RST5_BASE + 0x8); + writel(PRCC_backup[i++], _PRCC_CLK_RST6_BASE + 0x0); + writel(PRCC_backup[i++], _PRCC_CLK_RST6_BASE + 0x8); + writel(PRCC_backup[i++], _PRCC_CLK_RST7_BASE + 0x0); + writel(PRCC_backup[i++], _PRCC_CLK_RST7_BASE + 0x8); +} + +void __iomem *uart_backup_base, *uart_register_base; + +/* TODO : return success value to let decide to proceed + * for low power request or not + */ +void pm_save_config_UART(void) +{ + uart_register_base = ioremap(U8500_UART2_BASE, SZ_4K); + if (!uart_register_base) { + printk(KERN_WARNING + "u8500-prcm : cannot allocate uart register base\n"); + } + + uart_backup_base = kzalloc(SZ_4K, GFP_KERNEL); + if (!uart_backup_base) { + printk(KERN_WARNING + "u8500-prcm : cannot allocate uart register backup base\n"); + } + + /* Copy UART config */ + memcpy(uart_backup_base, uart_register_base, SZ_4K); +} + +void __iomem *ab8500_backup_base, *ab8500_register_base; + +void pm_restore_config_UART(void) +{ + memcpy(uart_register_base, uart_backup_base, SZ_4K); +} + +/* Deep Sleep context save */ + +/* public context backup */ +/* TODO : remove hard coded backup RAM addresses */ +void a9ss_save_public_config(void) +{ + int val; + + /* this happens for CPU0 only as of now */ + /* CP15 SCTLR */ + __asm__ __volatile__( + "mrc p15, 0, %0, c1, c1, 2" + : "=r" (val) + : + : "cc"); + writel(val, IO_ADDRESS(0x80151F80)); + + /* CP15 TTBR0 */ + __asm__ __volatile__( + "mrc p15, 0, %0, c2, c0, 0" + : "=r" (val) + : + : "cc"); + writel(val, IO_ADDRESS(0x80151F84)); + + /* CP15 TTBR1 */ + __asm__ __volatile__( + "mrc p15, 0, %0, c2, c0, 1" + : "=r" (val) + : + : "cc"); + writel(val, IO_ADDRESS(0x80151F88)); + + /* CP15 TTBCR */ + __asm__ __volatile__( + "mrc p15, 0, %0, c2, c0, 2" + : "=r" (val) + : + : "cc"); + writel(val, IO_ADDRESS(0x80151F8C)); + + /* CP15 DACR */ + __asm__ __volatile__( + "mrc p15, 0, %0, c3, c0, 0" + : "=r" (val) + : + : "cc"); + writel(val, IO_ADDRESS(0x80151F90)); + + /* CPSR */ + __asm__ __volatile__( + "mrs %0, cpsr" + : "=r" (val) + : + : "cc"); + writel(val, IO_ADDRESS(0x80151F98)); + + return; +} + +void a9ss_restore_public_config(void) +{ + int val; + + /* CPSR */ + val = readl(IO_ADDRESS(0x80151F98)); + __asm__ __volatile__( + "msr cpsr, %0" + : + : "r" (val)); + + /* CP15 DACR */ + val = readl(IO_ADDRESS(0x80151F90)); + __asm__ __volatile__( + "mcr p15, 0, %0, c3, c0, 0" + : + : "r" (val)); + + /* CP15 TTBCR */ + val = readl(IO_ADDRESS(0x80151F8C)); + __asm__ __volatile__( + "mcr p15, 0, %0, c2, c0, 2" + : + : "r" (val)); + + /* CP15 TTBR1 */ + val = readl(IO_ADDRESS(0x80151F88)); + __asm__ __volatile__( + "mcr p15, 0, %0, c2, c0, 1" + : + : "r" (val)); + + /* CP15 TTBR0 */ + val = readl(IO_ADDRESS(0x80151F84)); + __asm__ __volatile__( + "mcr p15, 0, %0, c2, c0, 0" + : + : "r" (val)); + + /* CP15 SCTLR */ + val = readl(IO_ADDRESS(0x80151F80)); + __asm__ __volatile__( + "mrc p15, 0, %0, c1, c1, 2" + : + : "r" (val)); + + return; +} + +/* ARM SCU backup */ +#include <mach/scu.h> +unsigned int scu_backup_config[5]; + +void a9ss_save_scu_config(void) +{ + scu_backup_config[0] = __raw_readl(IO_ADDRESS(U8500_SCU_BASE) + + SCU_CTRL); + scu_backup_config[1] = __raw_readl(IO_ADDRESS(U8500_SCU_BASE) + + SCU_CONFIG); + scu_backup_config[2] = __raw_readl(IO_ADDRESS(U8500_SCU_BASE) + + SCU_CPU_STATUS); + scu_backup_config[3] = __raw_readl(IO_ADDRESS(U8500_SCU_BASE) + + SCU_INVALIDATE); + + return; +} + +void a9ss_restore_scu_config(void) +{ + __raw_writel(scu_backup_config[0], IO_ADDRESS(U8500_SCU_BASE) + + SCU_CTRL); + __raw_writel(scu_backup_config[1], IO_ADDRESS(U8500_SCU_BASE) + + SCU_CONFIG); + __raw_writel(scu_backup_config[2], IO_ADDRESS(U8500_SCU_BASE) + + SCU_CPU_STATUS); + __raw_writel(scu_backup_config[3], IO_ADDRESS(U8500_SCU_BASE) + + SCU_INVALIDATE); + + return; +} + +/** + * prcmu_apply_ap_state_transition - PRCMU State Transition function + * @transition: Transition to be requested to move to new AP power mode + * @ddr_state_req: Power mode of DDR to which DDR needs to be switched + * @_4500_fifo_wakeup: 4500 fifo interrupt to be configured as wakeup or not + * Returns: 0 on success, -EINVAL on failure + * + * NOTES: This routine assumes that ARM side housekeeping that + * needs to be done before entering sleep/deep-sleep, eg. the routines + * begin(), prepare() in platform_suspend_ops have done their job + * this routine only makes the required state transition and post-transition + * ARM side handling e.g. calling WFI for the non-boot cpus for idle/sleep + * or either waiting for the go-ahead from the deep-sleep secure interrupt + * handler and then setting the romcode before entering wfi. The typical + * users of this routine are the CPUIdle and LDM suspend ie. pm_suspend(). + * The accelerators also need this service but currently this routine does + * not support it. This also assumes that the non-boot cpu's are in wfi + * and not wfe. + */ +/* FIXME : get these from platform/header files instead */ +/* GIC BAse Address */ +#define GIC_BASE_ADDR IO_ADDRESS(0xA0411000) + +/* ITs enabled for GIC. 104 is due to skipping of the STI and PPI sets. + * Rfer page 648 of the DB8500V1 spec v2.5 + */ +#define DIST_ENABLE_SET (GIC_BASE_ADDR + 0x104) +#define DIST_PENDING_SET (GIC_BASE_ADDR + 0x200) +#define DIST_ENABLE_CLEAR (GIC_BASE_ADDR + 0x180) +#define DIST_ACTIVE_BIT (GIC_BASE_ADDR + 0x304) + +#define PRCM_DEBUG_NOPWRDOWN_VAL IO_ADDRESS(0x80157194) +#define PRCM_POWER_STATE_VAL IO_ADDRESS(0x8015725C) + +int prcmu_apply_ap_state_transition(enum ap_pwrst_trans_t transition, + enum ddr_pwrst_t ddr_state_req, + int _4500_fifo_wakeup) +{ + int ret = 0; + int sync = 0; + unsigned int val = 0, timeout = 0, tmp ; + + if (u8500_is_earlydrop()) { + /* The PRCMU does do state transition validation, so we wl not + repeat it, just go ahead and call it */ + if (transition == APBOOT_TO_APEXECUTE_ED) + sync = 1; + + val = (ddr_state_req << 16) | (_4500_fifo_wakeup << 8) | \ + transition; + writel(val, PRCM_REQ_MB0_ED); + writel(1, PRCM_MBOX_CPU_SET); + + while ((readl(PRCM_MBOX_CPU_VAL) & 1) && sync) + cpu_relax(); + + switch (transition) { + + case APEXECUTE_TO_APSLEEP_ED: + case APEXECUTE_TO_APIDLE_ED: + __asm__ __volatile__("dsb\n\t" "wfi\n\t" \ + : : : "memory"); + break; + case APEXECUTE_TO_APDEEPSLEEP_ED: + printk(KERN_INFO "TODO: deep sleep \n"); + break; + case APBOOT_TO_APEXECUTE_ED: + break; + default: + ret = -EINVAL; + } + return ret; + } + + switch (transition) { + case APEXECUTE_TO_APSLEEP: + + /* PROGRAM THE ITMASK* registers for a Sleep */ + writel(0x00000000, PRCM_ARMITMSK31TO0); + writel(0x00000100, PRCM_ARMITMSK63TO32); + writel(0x00000000, PRCM_ARMITMSK95TO64); + writel(0x00000000, PRCM_ARMITMSK127TO96); + + /* probe the GIC if its already frozen */ + tmp = readl(PRCM_A9_MASK_ACK); + if (tmp & 0x00000001) + printk(KERN_WARNING "GIC is already frozen\n"); + + /* write to GIC freeze */ + tmp = readl(PRCM_A9_MASK_REQ); + tmp |= 0x01; + writel(tmp, PRCM_A9_MASK_REQ); + + /* we wait for a random timeout. as of now the + * the GIC freeze isnt ACKed; so wait + */ + timeout = 100; + while (timeout--) + cpu_relax(); + + /* PROGRAM WAKEUP EVENTS */ + /* write CfgWkUpsH in the Header */ + writeb(WKUPCFGH, PRCM_MBOX_HEADER_REQ_MB0); + + /* write to the mailbox */ + /* E8500Wakeup_ARMITMGMT Bit (1<<17). it is interpreted by + * the firmware to set the register prcm_armit_maskxp70_it + * (which is btw secure and thus only accessed by the xp70) + */ + writel((1<<17), PRCM_REQ_MB0_WKUP_8500); + writel(0x0, PRCM_REQ_MB0_WKUP_4500); + + /* SIGNAL MAILBOX */ + /* set the MBOX_CPU_SET bit to set an IT to xP70 */ + writel(1 << 0, PRCM_MBOX_CPU_SET); + + /* wait for corresponding MB0X_CPU_VAL bit to be cleared */ + while ((readl(PRCM_MBOX_CPU_VAL) & (1 << 0)) && timeout--) + cpu_relax(); + if (!timeout) { + printk(KERN_INFO + "Timeout in prcmu_configure_wakeup_events!!\n"); + return -EBUSY; + } + + /* CREATE MAILBOX FOR EXECUTE TO IDLE POWER TRANSITION */ + /* Write PwrStTrH=0 header to request a Power state xsition */ + writeb(0x0, PRCM_MBOX_HEADER_REQ_MB0); + + /* write request to the MBOX0 */ + writeb(APEXECUTE_TO_APSLEEP, PRCM_REQ_MB0_PWRSTTRH_APPWRST); + writeb(OFF, PRCM_REQ_MB0_PWRSTTRH_APPLLST); + writeb(ON, PRCM_REQ_MB0_PWRSTTRH_ULPCLKST); + writeb(0x56, PRCM_REQ_MB0_PWRSTTRH_BYTEFILL); + + /* As per the sync logic, we are supposed to be the final CPU. + * If the other CPU isnt in wfi, better exit by putting + * ourselves in wfi + */ + if (smp_processor_id()) { + if (!(readl(PRCM_ARM_WFI_STANDBY) & 0x8)) { + __asm__ __volatile__( + "dsb\n\t" "wfi\n\t" : : : "memory"); + return 0; + } + } else /* running on CPU0, check for CPU1 WFI standby */ { + if (!(readl(PRCM_ARM_WFI_STANDBY) & 0x10)) { + __asm__ __volatile__( + "dsb\n\t" "wfi\n\t" : : : "memory"); + return 0; + } + } + + /* Enable RTC-INT in the GIC */ + if (!(readl(PRCM_ARMITMSK31TO0) & 0x40000)) + writel((readl(PRCM_ARMITMSK31TO0) | 0x40000), + PRCM_ARMITMSK31TO0); + + + /* FIXME : later on, the ARM should not request a Idle if one + * of the ITSTATUS0/5 are still alive!!! + */ + if (readl(PRCM_ITSTATUS0) == 0x80) { + printk(KERN_WARNING "PRCM_ITSTATUS0 Not cleared\n"); + __asm__ __volatile__( + "dsb\n\t" "wfi\n\t" : : : "memory"); + return -EBUSY; + } + + /* + * + * REQUEST POWER XSITION + * + */ + + /* clear ACK MB0 */ + writeb(0x0, PRCM_ACK_MB0); + + /* trigger the XP70 IT10 to the XP70 */ + writel(1, PRCM_MBOX_CPU_SET); + + timeout = 200; + while (timeout--) + cpu_relax(); + + printk(KERN_INFO "u8500-prcm : To Deep Sleep\n"); + + /* Context Saving beings */ + + pm_save_config_PRCC(); + + pm_save_config_UART(); + + a9ss_save_public_config(); + + a9ss_save_scu_config(); + + /* TODO : take a backup of the SP and the public rom code + * entry point + */ + + /* here comes the wfi */ + __asm__ __volatile__( + "dsb\n\t" "wfi\n\t" : : : "memory"); + + a9ss_restore_scu_config(); + + a9ss_restore_public_config(); + + /* Restore PRCC Configs */ + pm_restore_config_PRCC(); + + /* Restore UART Configs */ + pm_restore_config_UART(); + + if (readb(PRCM_ACK_MB0_AP_PWRST_STATUS) == 0xF3) + printk(KERN_INFO "u8500-prcm : Woken from Sleep OK\n"); + + break; + case APEXECUTE_TO_APIDLE: + /* Copy the current GIC set enable config as wakeup */ + for (val = 0; val < 4; val++) { + tmp = readl(DIST_ENABLE_SET + (val * 4)); + writel(tmp, PRCM_ARMITMSK31TO0 + (val * 4)); + } + + /* PROGRAM WAKEUP EVENTS */ + /* write CfgWkUpsH in the Header */ + writeb(WKUPCFGH, PRCM_MBOX_HEADER_REQ_MB0); + + /* write to the mailbox */ + /* E8500Wakeup_ARMITMGMT Bit (1<<17). it is interpreted by + * the firmware to set the register prcm_armit_maskxp70_it + * (which is btw secure and thus only accessed by the xp70) + */ + writel((1<<17), PRCM_REQ_MB0_WKUP_8500); + writel(0x0, PRCM_REQ_MB0_WKUP_4500); + _wait_for_req_complete(REQ_MB0); + +#if 0 + /* SIGNAL MAILBOX */ + /* set the MBOX_CPU_SET bit to set an IT to xP70 */ + writel(1 << 0, PRCM_MBOX_CPU_SET); + + /* wait for corresponding MB0X_CPU_VAL bit to be cleared */ + while ((readl(PRCM_MBOX_CPU_VAL) & (1 << 0)) && timeout--) + cpu_relax(); + if (!timeout) { + printk(KERN_INFO + "Timeout in prcmu_configure_wakeup_events!!\n"); + return -EBUSY; + } +#endif + /* CREATE MAILBOX FOR EXECUTE TO IDLE POWER TRANSITION */ + /* Write PwrStTrH=0 header to request a Power state xsition */ + writeb(0x0, PRCM_MBOX_HEADER_REQ_MB0); + + /* write request to the MBOX0 */ + writeb(APEXECUTE_TO_APIDLE, PRCM_REQ_MB0_PWRSTTRH_APPWRST); + writeb(ON, PRCM_REQ_MB0_PWRSTTRH_APPLLST); + writeb(ON, PRCM_REQ_MB0_PWRSTTRH_ULPCLKST); + writeb(0x55, PRCM_REQ_MB0_PWRSTTRH_BYTEFILL); + + /* As per the sync logic, we are supposed to be the final CPU. + * If the other CPU isnt in wfi, better exit by putting + * ourselves in wfi + */ + if (smp_processor_id()) { + if (!(readl(PRCM_ARM_WFI_STANDBY) & 0x8)) { + __asm__ __volatile__( + "dsb\n\t" "wfi\n\t" : : : "memory"); + return 0; + } + } else /* running on CPU0, check for CPU1 WFI standby */ { + if (!(readl(PRCM_ARM_WFI_STANDBY) & 0x10)) { + __asm__ __volatile__( + "dsb\n\t" "wfi\n\t" : : : "memory"); + return 0; + } + } + + /* FIXME : temporary hack to let UART2 interrupts enable the + * wake-up from ARM + */ + if (!(readl(PRCM_ARMITMSK31TO0) & 0x04000000)) + writel((readl(PRCM_ARMITMSK31TO0) | 0x04000000), + PRCM_ARMITMSK31TO0); + + /* FIXME : tempoeary hack to wake up from RTC */ + if (!(readl(PRCM_ARMITMSK31TO0) & 0x40000)) + writel((readl(PRCM_ARMITMSK31TO0) | 0x40000), + PRCM_ARMITMSK31TO0); + + /* FIXME : later on, the ARM should not request a Idle if one + * of the ITSTATUS0/5 are still alive!!! + */ + if (readl(PRCM_ITSTATUS0) == 0x80) { + printk(KERN_WARNING "PRCM_ITSTATUS0 Not cleared\n"); + __asm__ __volatile__( + "dsb\n\t" "wfi\n\t" : : : "memory"); + return -EBUSY; + } + + /* + * + * REQUEST POWER XSITION + * + */ + + /* clear ACK MB0 */ + writeb(0x0, PRCM_ACK_MB0); + + /* trigger the XP70 IT10 to the XP70 */ + writel(1, PRCM_MBOX_CPU_SET); + + /* here comes the wfi */ + __asm__ __volatile__("dsb\n\t" "wfi\n\t" : : : "memory"); + + writeb(RDWKUPACKH, PRCM_MBOX_HEADER_REQ_MB0); + + /* Set an interrupt to XP70 */ + writel(1 , PRCM_MBOX_CPU_SET); + while ((readl(PRCM_MBOX_CPU_VAL) & 1) && timeout--) + cpu_relax(); + if (!timeout) + return -EBUSY; + + break; + case APEXECUTE_TO_APDEEPSLEEP: + /* PROGRAM THE ITMASK* registers for deep sleep */ + writel(0x00000000, PRCM_ARMITMSK31TO0); + writel(0x00000100, PRCM_ARMITMSK63TO32); + writel(0x00000000, PRCM_ARMITMSK95TO64); + writel(0x00000000, PRCM_ARMITMSK127TO96); + + /* we skip the GIC freeze due to the FIQ being + * not handled by the ARM later on + */ + + /* PROGRAM WAKEUP EVENTS */ + /* write CfgWkUpsH in the Header */ + writeb(WKUPCFGH, PRCM_MBOX_HEADER_REQ_MB0); + + /* write to the mailbox */ + /* E8500Wakeup_ARMITMGMT Bit (1<<17). it is interpreted by + * the firmware to set the register prcm_armit_maskxp70_it + * (which is btw secure and thus only accessed by the xp70) + */ + writel((1<<17), PRCM_REQ_MB0_WKUP_8500); + writel(0x0, PRCM_REQ_MB0_WKUP_4500); + + /* SIGNAL MAILBOX */ + /* set the MBOX_CPU_SET bit to set an IT to xP70 */ + writel(1 << 0, PRCM_MBOX_CPU_SET); + + /* wait for corresponding MB0X_CPU_VAL bit to be cleared */ + while ((readl(PRCM_MBOX_CPU_VAL) & (1 << 0)) && timeout--) + cpu_relax(); + if (!timeout) { + printk(KERN_INFO + "Timeout in prcmu_configure_wakeup_events!!\n"); + return -EBUSY; + } + + /* CREATE MAILBOX FOR EXECUTE TO IDLE POWER TRANSITION */ + /* Write PwrStTrH=0 header to request a Power state xsition */ + writeb(0x0, PRCM_MBOX_HEADER_REQ_MB0); + + /* write request to the MBOX0 */ + writeb(APEXECUTE_TO_APDEEPSLEEP, PRCM_REQ_MB0_PWRSTTRH_APPWRST); + writeb(OFF, PRCM_REQ_MB0_PWRSTTRH_APPLLST); + writeb(ON, PRCM_REQ_MB0_PWRSTTRH_ULPCLKST); + writeb(0x56, PRCM_REQ_MB0_PWRSTTRH_BYTEFILL); + + /* As per the sync logic, we are supposed to be the final CPU. + * If the other CPU isnt in wfi, better exit by putting + * ourselves in wfi + */ + if (smp_processor_id()) { + if (!(readl(PRCM_ARM_WFI_STANDBY) & 0x8)) { + __asm__ __volatile__( + "dsb\n\t" "wfi\n\t" : : : "memory"); + return 0; + } + } else /* running on CPU0, check for CPU1 WFI standby */ { + if (!(readl(PRCM_ARM_WFI_STANDBY) & 0x10)) { + __asm__ __volatile__( + "dsb\n\t" "wfi\n\t" : : : "memory"); + return 0; + } + } + + /* Enable RTC-INT in the GIC */ + if (!(readl(PRCM_ARMITMSK31TO0) & 0x40000)) + writel((readl(PRCM_ARMITMSK31TO0) | 0x40000), + PRCM_ARMITMSK31TO0); + + + /* FIXME : later on, the ARM should not request a Idle if one + * of the ITSTATUS0/5 are still alive!!! + */ + if (readl(PRCM_ITSTATUS0) == 0x80) { + printk(KERN_WARNING "PRCM_ITSTATUS0 Not cleared\n"); + __asm__ __volatile__( + "dsb\n\t" "wfi\n\t" : : : "memory"); + return -EBUSY; + } + + /* + * + * REQUEST POWER XSITION + * + */ + + /* clear ACK MB0 */ + writeb(0x0, PRCM_ACK_MB0); + + /* trigger the XP70 IT10 to the XP70 */ + writel(1, PRCM_MBOX_CPU_SET); + + timeout = 200; + while (timeout--) + cpu_relax(); + + printk(KERN_INFO "u8500-prcm : To Sleep\n"); + + /* Restore PRCC configs */ + pm_save_config_PRCC(); + + pm_save_config_UART(); + + a9ss_save_public_config(); + + /* here comes the wfi */ + __asm__ __volatile__( + "dsb\n\t" "wfi\n\t" : : : "memory"); + + /* Restore PRCC Configs */ + pm_restore_config_PRCC(); + + /* Restore UART Configs */ + pm_restore_config_UART(); + + if (readb(PRCM_ACK_MB0_AP_PWRST_STATUS) == 0xF3) + printk(KERN_INFO "u8500-prcm : Woken from Sleep OK\n"); + + break; + + printk(KERN_INFO "TODO: deep sleep \n"); + break; + case APBOOT_TO_APEXECUTE: + break; + default: + ret = -EINVAL; + } + return ret; + + +} +EXPORT_SYMBOL(prcmu_apply_ap_state_transition); + + + +/** + * prcmu_i2c_read - PRCMU - 4500 communication using PRCMU I2C + * @reg: - db8500 register bank to be accessed + * @slave: - db8500 register to be accessed + * Returns: ACK_MB5 value containing the status + */ +int prcmu_i2c_read(u8 reg, u8 slave) +{ + uint8_t i2c_status; + uint8_t i2c_val; + + dbg_printk("\nprcmu_4500_i2c_read: \ + bank=%x;reg=%x;\n", reg, slave); + + /* code related to FW 1_0_0_16 */ + writeb(I2CREAD, PRCM_REQ_MB5_I2COPTYPE); + writeb(reg, PRCM_REQ_MB5_I2CREG); + writeb(slave, PRCM_REQ_MB5_I2CSLAVE); + writeb(0, PRCM_REQ_MB5_I2CVAL); + + /* clear any previous ack */ + writel(0, PRCM_ACK_MB5); + + /* Set an interrupt to XP70 */ + writel(PRCM_XP70_TRIG_IT17, PRCM_MBOX_CPU_SET); + + dbg_printk("\n readl PRCM_ARM_IT1_VAL = %d \ + ", readb(PRCM_ARM_IT1_VAL)); + dbg_printk("\nwaiting at wait queue"); + + + /* wait for interrupt */ + wait_event_interruptible(ack_mb5_queue, \ + !(readl(PRCM_MBOX_CPU_VAL) & (PRCM_XP70_TRIG_IT17))); + + dbg_printk("\nAfter wait queue"); + + /* retrieve values */ + dbg_printk("ack-mb5:transfer status = %x\n", \ + readb(PRCM_ACK_MB5 + 0x1)); + dbg_printk("ack-mb5:reg_add = %x\n", readb(PRCM_ACK_MB5 + 0x2)); + dbg_printk("ack-mb5:slave_add = %x\n", \ + readb(PRCM_ACK_MB5 + 0x2)); + dbg_printk("ack-mb5:reg_val = %d\n", readb(PRCM_ACK_MB5 + 0x3)); + + + /* return ack_mb5.req_field.reg_val for a + req->req_field.I2C_op == I2C_READ */ + + i2c_status = readb(PRCM_ACK_MB5 + 0x1); + i2c_val = readb(PRCM_ACK_MB5 + 0x3); + + + if (i2c_status == I2C_RD_OK) + return i2c_val; + else { + + printk(KERN_INFO "prcmu_request_mailbox5:read return status = \ + %d\n", i2c_status); + return -EINVAL; + } + +} +EXPORT_SYMBOL(prcmu_i2c_read); + + +/** + * prcmu_i2c_write - PRCMU-db8500 communication using PRCMU I2C + * @reg: - db8500 register bank to be accessed + * @slave: - db800 register to be written to + * @reg_data: - the data to write + * Returns: ACK_MB5 value containing the status + */ +int prcmu_i2c_write(u8 reg, u8 slave, u8 reg_data) +{ + uint8_t i2c_status; + + /* NOTE : due to the I2C workaround, use + * MB5 for data, MB4 for the header + */ + + /* request I2C workaround header 0x0F */ + writeb(0x0F, PRCM_MBOX_HEADER_REQ_MB4); + + /* prepare the data for mailbox 5 */ + + /* register bank and I2C command */ + writeb((reg << 1) | I2CWRITE, PRCM_REQ_MB5 + 0x0); + /* APE_I2C comm. specifics */ + writeb((1 << 3) | 0x0, PRCM_REQ_MB5 + 0x1); + writeb(slave, PRCM_REQ_MB5_I2CSLAVE); + writeb(reg_data, PRCM_REQ_MB5_I2CVAL); + + /* we request the mailbox 4 */ + writel(PRCM_XP70_TRIG_IT14, PRCM_MBOX_CPU_SET); + + /* we wait for ACK mailbox 5 */ + /* FIXME : regularise this code with mailbox constants */ + while ((readl(PRCM_ARM_IT1_VAL) & (0x1 << 5)) != (0x1 << 5)) + cpu_relax(); + + /* we clear the ACK mailbox 5 interrupt */ + writel((0x1 << 5), PRCM_ARM_IT1_CLEAR); + + i2c_status = readb(PRCM_ACK_MB5 + 0x1); + if (i2c_status == I2C_WR_OK) + return I2C_WR_OK; + else { + printk(KERN_INFO "ape-i2c: i2c_status : 0x%x\n", i2c_status); + return -EINVAL; + } +} +EXPORT_SYMBOL(prcmu_i2c_write); + +int prcmu_i2c_get_status() +{ + return readb(PRCM_ACK_MB5_STATUS); +} +EXPORT_SYMBOL(prcmu_i2c_get_status); + +int prcmu_i2c_get_bank() +{ + return readb(PRCM_ACK_MB5_BANK); +} +EXPORT_SYMBOL(prcmu_i2c_get_bank); + +int prcmu_i2c_get_reg() +{ + return readb(PRCM_ACK_MB5_REG); +} +EXPORT_SYMBOL(prcmu_i2c_get_reg); + +int prcmu_i2c_get_val() +{ + return readb(PRCM_ACK_MB5_VAL); +} +EXPORT_SYMBOL(prcmu_i2c_get_val); + + + +/** + * prcmu_ac_wake_req - should be called whenever ARM wants to wakeup Modem + * + * Mailbox used : AckMb7 + * ACK : HostPortAck + */ +int prcmu_ac_wake_req() +{ + u32 prcm_hostaccess = readl(PRCM_HOSTACCESS_REQ); + prcm_hostaccess = prcm_hostaccess | ARM_WAKEUP_MODEM; + + /* 1. write to the PRCMU host_port_req register */ + writel(prcm_hostaccess, PRCM_HOSTACCESS_REQ); + + /* 2. wait for HostPortAck message in AckMb7 + wait_event_interruptible(ack_mb7_queue, (readl(PRCM_ARM_IT1_VAL) + & (1<<7))); + */ + + if (prcmu_read_ack_mb7() == HOST_PORT_ACK) + return 0; + else { + dbg_printk(KERN_INFO "\nprcmu_ac_wake_req: ack_mb7 \ + status = %x", prcmu_read_ack_mb7()); + return -EINVAL; + } + + + +} +EXPORT_SYMBOL(prcmu_ac_wake_req); + +/** + * prcmu_ac_sleep_req - called when ARM no longer needs to talk to modem + * + * Mailbox used - None + * ACK - None + */ +int prcmu_ac_sleep_req() +{ + /* clear the PRCMU host_port_req register */ + u32 orig_val = readl(PRCM_HOSTACCESS_REQ); + orig_val = orig_val & 0xFFFFFFFE; + + writel(orig_val, PRCM_HOSTACCESS_REQ); + + return 0; +} +EXPORT_SYMBOL(prcmu_ac_sleep_req); + + + +/** + * prcmu_configure_wakeup_events - configure 8500 and 4500 hw events on which + * PRCMU should wakeup AP + * + * Mailbox : PRCM_REQ_MB0 + * Header : WKUPCFGH + * ACK : None + */ +int prcmu_configure_wakeup_events(u32 event_8500_mask, \ + u32 event_4500_mask) +{ + int err = 0; + + /* write CfgWkUpsH in the Header */ + writeb(WKUPCFGH, PRCM_MBOX_HEADER_REQ_MB0); + + /* write to the mailbox */ + writel(event_8500_mask, PRCM_REQ_MB0_WKUP_8500); + writel(event_4500_mask, PRCM_REQ_MB0_WKUP_4500); + + err = _wait_for_req_complete(REQ_MB0); + + if (err) { + dbg_printk(KERN_INFO "\nTimeout configure_wakeup_events\n"); + } else { + dbg_printk(KERN_INFO "\nprcmu_configure_wakeup_events \ + done successfully!!\n"); + } + + /* No ack for this service. Directly return */ + return err; + + + +} +EXPORT_SYMBOL(prcmu_configure_wakeup_events); + + +/** + * prcmu_get_wakeup_reason - Retrieve the event which caused AP wakeup + * @event_8500: - corresponds to 8500 events + * @event_4500: - corresponds to 4500 events + * + * + * Mailbox : PRCM_ACK_MB0 + * Header : WKUPH + * ACK : None + */ +int prcmu_get_wakeup_reason(u32 *event_8500, u8 *event_4500 /* 20 bytes */) +{ + int i = 0; + + /* read the Rdp field */ + u8 rdp = readb(PRCM_ACK_MB0_PINGPONG_RDP); + + /* right now, some issues present in ping pong from fw side :) */ + /* read the event fields */ + + if (rdp) { + *event_8500 = readl(PRCM_ACK_MB0_WK1_EVENT_8500); + for (i = 0; i < PRCM_ACK_MB0_EVENT_4500_NUMBERS; i++) + event_4500[i] = readb(PRCM_ACK_MB0_WK1_EVENT_4500 + i); + } else { + *event_8500 = readl(PRCM_ACK_MB0_WK0_EVENT_8500); + for (i = 0; i < PRCM_ACK_MB0_EVENT_4500_NUMBERS; i++) + event_4500[i] = readb(PRCM_ACK_MB0_WK0_EVENT_4500 + i); + } + + /* No ack. Directly return */ + return 0; +} +EXPORT_SYMBOL(prcmu_get_wakeup_reason); + + +/** + * prcmu_ack_wakeup_reason - Arm acks to PRCMU that it read the wakeup reason + * + * + * Mailbox used : PRCM_ACK_MB0 + * Header used : RDWKUPACKH + * ACK : None + */ +int prcmu_ack_wakeup_reason() +{ + int err = 0; + + /* Acknowledge the wakeup events */ + writeb(RDWKUPACKH, PRCM_MBOX_HEADER_REQ_MB0); + err = _wait_for_req_complete(REQ_MB0); + + return err; +} +EXPORT_SYMBOL(prcmu_ack_wakeup_reason); + + +/** + * prcmu_is_ca_wake_req_pending - determine if ca_wake_req is pending + * + * Mailbox used - None + * Ack - None + * + * To be used by shrm driver to check if any ca_wake_req is pending + * initially and service the request accordingly. + */ +int prcmu_is_ca_wake_req_pending(void) +{ + int retval = ca_wake_req_pending; + if (ca_wake_req_pending) + ca_wake_req_pending--; + + return retval; +} +EXPORT_SYMBOL(prcmu_is_ca_wake_req_pending); + +/** + * prcmu_set_callback_cawakereq - callback of shrm for ca_wake_req + * @*func: Function pointer of shrm + * + * To call the registered shrm callback whenever ca_wake_req is got + */ +void prcmu_set_callback_cawakereq(void (*func)(u8)) +{ + prcmu_ca_wake_req_shrm_callback = func; +} +EXPORT_SYMBOL(prcmu_set_callback_cawakereq); + + +/** + * prcmu_set_callback_modem_reset_request - Set the callback function to call + * when modem requests for Reset + * + * Mailbox used - None + * Ack - None + */ +void prcmu_set_callback_modem_reset_request(void (*func)(void)) +{ + prcmu_modem_reset_shrm = func; +} +EXPORT_SYMBOL(prcmu_set_callback_modem_reset_request); + +/** + * prcmu_system_reset - System reset + * + * Sets the APE_SOFRST register which fires interrupt to fw + */ +void prcmu_system_reset(void) +{ + writel(1, PRCM_APE_SOFTRST); +} +EXPORT_SYMBOL(prcmu_system_reset); + +/** + * prcmu_read_ack_mb7 - Read the AckMb7 Status message + * + * + * Mailbox : AckMb7 + * Header : None + * ACK : None + * associated IT : prcm_arm_it1_val[7] + */ +int prcmu_read_ack_mb7() +{ + return readb(PRCM_ACK_MB7); +} +EXPORT_SYMBOL(prcmu_read_ack_mb7); + + +/** + * prcmu_ack_mb0_wkuph_status_tasklet - tasklet for ack mb0 IRQ + * @tasklet_data: tasklet data + * + * Tasklet for handling wakeup events given by IRQ corresponding to + * AckMb0 + */ +void prcmu_ack_mb0_wkuph_status_tasklet(unsigned long tasklet_data) +{ + uint32_t event_8500 = 0; + unsigned char event_4500[20]; + + prcmu_get_wakeup_reason(&event_8500, event_4500); + +#if 0 + dbg_printk("\n Inside prcmu_ack_mb0_wkuph_status_tasklet \n"); + dbg_printk("\n\nAcknowledging by RDWKUPACKH\n\n"); + prcmu_ack_wakeup_reason(); +#endif + + /* ca_wake_req signal - modem wakes up ARM */ + if (event_8500 & (1 << 5)) { + /* call shrm driver callback */ + if (prcmu_ca_wake_req_shrm_callback != NULL) + (*prcmu_ca_wake_req_shrm_callback)(1); + else { + printk(KERN_INFO "\n prcmu: SHRM callback for \ + ca_wake_req not registered!!\n"); + } + } +} + +/** + * prcmu_ack_mb7_status_tasklet - tasklet for mb7 IRQ + * @tasklet_data: tasklet data + * + * Tasklet for handling IPC communication related to AckMb7 + */ +void prcmu_ack_mb7_status_tasklet(unsigned long tasklet_data) +{ + /* read the ack mb7 value and carry out actions accordingly */ + u8 ack_mb7 = readb(PRCM_ACK_MB7); + + switch (ack_mb7) { + case MOD_SW_RESET_REQ: + /*forward the reset request to ARM */ + break; + case CA_SLEEP_REQ: + /* modem no longer requires to communicate + * with ARM so ARM can go to sleep */ + if (prcmu_ca_wake_req_shrm_callback != NULL) + (*prcmu_ca_wake_req_shrm_callback)(0); + else { + printk(KERN_INFO "\n prcmu: SHRM callback for \ + ca_wake_req not registered!!\n"); + } + break; + case HOST_PORT_ACK: + /* modem up.ARM can communicate to modem */ + /* wake_up_interruptible- prcmu_arm_wakeup_modem api*/ + wake_up_interruptible(&ack_mb7_queue); + break; + }; + +} + +/** + * prcmu_ack_mbox_irq_handler - IRQ handler for Ack mailboxes + * @irq: the irq number + * + * IRQ Handler for the Ack Mailboxes + * Find out the arm_it1_val bit and carry out the tasks + * accordingly + */ +irqreturn_t prcmu_ack_mbox_irq_handler(int irq, void *ctrlr) +{ + uint8_t prcm_arm_it1_val = 0; + + dbg_printk("\nInside prcmu_ack_mbox_irq_handler !!\n"); + + /* check the prcm_arm_it1_val register to find which ACK mailbox is + * filled by PRCMU fw */ + prcm_arm_it1_val = readb(PRCM_ARM_IT1_VAL); + + dbg_printk(" prcm_arm_it1_val = %d ", prcm_arm_it1_val); + + if (prcm_arm_it1_val & (1 << 0)) { + dbg_printk("\n Inside IRQ handler for Ack mb0 "); + wake_up_interruptible(&ack_mb0_queue); + + dbg_printk("\n readb(PRCM_MBOX_HEADER_ACK_MB0) = %x", \ + readb(PRCM_MBOX_HEADER_ACK_MB0)); + + /*read the header */ + if ((readb(PRCM_MBOX_HEADER_ACK_MB0)) == PWRSTTRH) { + /* call the callback for AckMb0_PWRSTTRH */ + /*tasklet_schedule(&prcmu_ack_mb0_pwrst_tasklet);*/ + /* call wake_up_event_interruptible for mb0 */ + dbg_printk("\n Inside IRQ handler for Ack mb0 \ + PWRSTTRH and waking up "); + + } else if ((readb(PRCM_MBOX_HEADER_ACK_MB0)) == WKUPH) { + dbg_printk("\n IRQ handler for Ack mb0 WKUPH "); + tasklet_schedule(&prcmu_ack_mb0_wkuph_tasklet); + + } + } else if (prcm_arm_it1_val & (1<<1)) + dbg_printk("\n IRQ handler for Ack mb1\n"); + else if (prcm_arm_it1_val & (1<<2)) + dbg_printk("\n IRQ handler for Ack mb2\n"); + else if (prcm_arm_it1_val & (1<<3)) + dbg_printk("\n IRQ handler for Ack mb3\n"); + else if (prcm_arm_it1_val & (1<<4)) + dbg_printk("\n IRQ handler for Ack mb4\n"); + else if (prcm_arm_it1_val & (1<<5)) { + /* No header reading required */ + /* call wake_up_event_interruptible for mb5 transaction */ + dbg_printk("\nInside prcmu IRQ handler for mb5 "); + wake_up_interruptible(&ack_mb5_queue); + } else if (prcm_arm_it1_val & (1<<6)) + dbg_printk("\n IRQ handler for Ack mb6\n"); + else if (prcm_arm_it1_val & (1<<7)) { + /* No header reading required */ + dbg_printk("\n IRQ handler for Ack mb7\n"); + tasklet_schedule(&prcmu_ack_mb7_tasklet); + } + + /* clear arm_it1_val bits */ + writeb(255, PRCM_ARM_IT1_CLEAR); + return IRQ_HANDLED; +} + + +/** + * prcmu_fw_init - arch init call for the Linux PRCMU fw init logic + * + */ +static int prcmu_fw_init(void) +{ + int err = 0; + /* configure the wake-up events */ + u32 event_8500 = 0x0; + u32 event_4500 = 0x0; + int prcm_arm_it1_val = 0; + + if (u8500_is_earlydrop()) { + int i; + int status = prcmu_get_boot_status(); + if (status != 0xFF || status != 0x2F) { + printk("PRCMU Firmware not ready\n"); + return -EIO; + } + /* This can be enabled once PRCMU fw flashing is default */ + prcmu_apply_ap_state_transition(APBOOT_TO_APEXECUTE_ED, + DDR_PWR_STATE_UNCHANGED_ED, 0); + + /* for the time being assign wake-up duty to all interrupts */ + /* Enable all interrupts as wake-up source */ + for (i = 0; i < 128; i++) + prcmu_set_irq_wakeup(i); + + return 0; + } + + /* configure the wakeup events */ + event_8500 = (1 << 5); + event_4500 = 0x0; + prcmu_configure_wakeup_events(event_8500, event_4500); + dbg_printk("(WkUpCfgOk=0xEA)PRCM_ACK_MB0_AP_PWRST_STATUS = %x\n", + readb(PRCM_ACK_MB0_AP_PWRST_STATUS)); + + /* retrieve the current interrupt status from PRCMU FW */ + prcm_arm_it1_val = readb(PRCM_ARM_IT1_VAL); + if (prcm_arm_it1_val && (1 << 0)) { + /* clear the arm_it1_val to low the IT#47 */ + writeb(0xFF, PRCM_ARM_IT1_CLEAR); + + /* init irqs */ + err = request_irq(IRQ_PRCM_ACK_MBOX, + prcmu_ack_mbox_irq_handler, IRQF_TRIGGER_RISING, + "prcmu_ack_mbox", NULL); + if (err < 0) { + printk(KERN_ERR "\nFailed to allocate \ + IRQ_PRCM_ACK_MBOX!!\n"); + err = -EBUSY; + free_irq(IRQ_PRCM_ACK_MBOX, NULL); + goto err_return; + } + + /* check for any existing wakeup events */ + if (readb(PRCM_MBOX_HEADER_ACK_MB0) == WKUPH) { + /* check here for the wakeup source for cawakereq + debugging on-going with fw for ping-pong. + Currently, its not possible to read source of + wakeup event correctly from fw mailbox */ + + /* increment pending flag for the shrm driver + to check */ + ca_wake_req_pending++; + + /* acknowledge reading the wakeup reason to fw */ + prcmu_ack_wakeup_reason(); + } + } + + + if (prcmu_get_xp70_current_state() == AP_BOOT) + prcmu_apply_ap_state_transition(APBOOT_TO_APEXECUTE, \ + DDR_PWR_STATE_UNCHANGED, 0); + else if (prcmu_get_xp70_current_state() == AP_EXECUTE) { + printk(KERN_INFO "PRCMU firmware booted.\n"); + } else { + printk(KERN_WARNING "WARNING - PRCMU firmware not yet booted!!!\n"); + return -ENODEV; + } + +err_return: + return err; +} + +arch_initcall(prcmu_fw_init); diff --git a/arch/arm/mach-ux500/prcmu-fw_ed.h b/arch/arm/mach-ux500/prcmu-fw_ed.h new file mode 100755 index 00000000000..1a1f8d8fc6b --- /dev/null +++ b/arch/arm/mach-ux500/prcmu-fw_ed.h @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2009 ST-Ericsson + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + */ + + + +#ifndef __MACH_PRCMU_FW_ED_H +#define __MACH_PRCMU_FW_ED_H + +#include <mach/prcmu-fw-defs_ed.h> + +#define _PRCMU_TCDM_BASE_ED IO_ADDRESS(U8500_PRCMU_TCDM_BASE) +#define PRCM_BOOT_STATUS_ED (_PRCMU_TCDM_BASE + 0xFFF) +#define PRCM_ROMCODE_A2P_ED (_PRCMU_TCDM_BASE + 0xFFE) +#define PRCM_ROMCODE_P2A_ED (_PRCMU_TCDM_BASE + 0xFFD) +#define PRCM_AP_PWR_STATE_ED (_PRCMU_TCDM_BASE + 0xFFC) +#define PRCM_NOT_USED_ED (_PRCMU_TCDM_BASE + 0xFFB) + +#define PRCM_REQ_MB0_ED (_PRCMU_TCDM_BASE + 0xFF8) +#define PRCM_DDRPWR_ST_ED (PRCM_REQ_MB0 + 0x2) /* 0xFFA */ +#define PRCM_4500_FIFOWU_ED (PRCM_REQ_MB0 + 0x1) /* 0xFF9 */ +#define PRCM_APPWR_STTR_ED (PRCM_REQ_MB0 + 0x0) /* 0xFF8 */ + +#define PRCM_REQ_MB1_ED (_PRCMU_TCDM_BASE + 0xFF6) +#define PRCM_APE_OPP_ED (PRCM_REQ_MB1 + 0x1) /* 0xFF7 */ +#define PRCM_ARM_OPP_ED (PRCM_REQ_MB1 + 0x0) /* 0xFF6 */ + +#define PRCM_REQ_MB2_ED (_PRCMU_TCDM_BASE + 0xFEC) /* 0xFEC - 0xFF5 */ + +#define PRCM_ACK_MB0_ED (_PRCMU_TCDM_BASE + 0xFE8) +#define PRCM_M2A_STATUS_ED (PRCM_ACK_MB0 + 0x3) /* 0xFEB */ +#define PRCM_M2A_ERROR_ED (PRCM_ACK_MB0 + 0x2) /* 0xFEA */ +#define PRCM_M2A_DVFS_STAT_ED (PRCM_ACK_MB0 + 0x1) /* 0xFE9 */ +#define PRCM_M2A_HWACC_STAT_ED (PRCM_ACK_MB0 + 0x0) /* 0xFE8 */ + +#define PRCM_REQ_MB6_ED (_PRCMU_TCDM_BASE + 0xFE7) +#define PRCM_SVAMMDSPSTATUS_ED PRCM_REQ_MB6 + +#define PRCM_REQ_MB7_ED 0xFE6 +#define PRCM_SIAMMDSPSTATUS_ED PRCM_REQ_MB7 + +enum mailbox_ed_t { + REQ_MB0_ED = 0, /* Uses XP70_IT_EVENT_10 */ + REQ_MB1_ED = 1, /* Uses XP70_IT_EVENT_11 */ + REQ_MB2_ED = 2, /* Uses XP70_IT_EVENT_12 */ +}; + +/* Union declaration */ + +/* ARM to XP70 mailbox definition */ +union req_mb0_ed_t { + struct { + enum ap_pwrst_trans_ed_t ap_pwrst_trans:8; + enum intr_wakeup_ed_t fifo_4500wu:8; + enum ddr_pwrst_ed_t ddr_pwrst:8; + unsigned int unused:8; + } req_field; + unsigned int complete_field; +}; + +/* mailbox definition for ARM/APE operation */ +union req_mb1_ed_t { + struct { + enum arm_opp_ed_t arm_opp:8; + enum ape_opp_ed_t ape_opp:8; + } req_field; + unsigned short complete_field; +}; + +/* mailbox definition for hardware accelerator */ +union req_mb2_ed_t { + struct { + enum hw_accst_ed_t hw_accst:8; + } hw_accst_list[ESRAM4_ED + 1]; + unsigned int complete_field[3]; +}; + +struct arm_irq_mask_ed_t { + unsigned int arm_irq_mask[4]; +}; + +#endif /* __MACH_PRCMU_FW_ED_H */ diff --git a/arch/arm/mach-ux500/prcmu-fw_v1.h b/arch/arm/mach-ux500/prcmu-fw_v1.h new file mode 100755 index 00000000000..512608bbcf2 --- /dev/null +++ b/arch/arm/mach-ux500/prcmu-fw_v1.h @@ -0,0 +1,174 @@ +/* + * Copyright 2009 ST-Ericsson. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + */ + +#ifndef __MACH_PRCMU_FW_V1_H +#define __MACH_PRCMU_FW_V1_H + +#include <mach/prcmu-fw-api.h> +#include <mach/prcmu-fw-defs_v1.h> + +#define _PRCMU_TCDM_BASE IO_ADDRESS(U8500_PRCMU_TCDM_BASE) +#define PRCM_BOOT_STATUS (_PRCMU_TCDM_BASE + 0xFFF) +#define PRCM_ROMCODE_A2P (_PRCMU_TCDM_BASE + 0xFFE) +#define PRCM_ROMCODE_P2A (_PRCMU_TCDM_BASE + 0xFFD) +#define PRCM_XP70_CUR_PWR_STATE (_PRCMU_TCDM_BASE + 0xFFC) /* 4 BYTES */ + + +#define _PRCM_MBOX_HEADER (_PRCMU_TCDM_BASE + 0xFE8)/*16 bytes*/ +#define PRCM_MBOX_HEADER_REQ_MB0 (_PRCM_MBOX_HEADER + 0x0) +#define PRCM_MBOX_HEADER_REQ_MB1 (_PRCM_MBOX_HEADER + 0x1) +#define PRCM_MBOX_HEADER_REQ_MB2 (_PRCM_MBOX_HEADER + 0x2) +#define PRCM_MBOX_HEADER_REQ_MB3 (_PRCM_MBOX_HEADER + 0x3) +#define PRCM_MBOX_HEADER_REQ_MB4 (_PRCM_MBOX_HEADER + 0x4) +#define PRCM_MBOX_HEADER_REQ_MB5 (_PRCM_MBOX_HEADER + 0x5) +#define PRCM_MBOX_HEADER_REQ_MB6 (_PRCM_MBOX_HEADER + 0x6) +#define PRCM_MBOX_HEADER_REQ_MB7 (_PRCM_MBOX_HEADER + 0x7) +#define PRCM_MBOX_HEADER_ACK_MB0 (_PRCM_MBOX_HEADER + 0x8) +#define PRCM_MBOX_HEADER_ACK_MB1 (_PRCM_MBOX_HEADER + 0x9) +#define PRCM_MBOX_HEADER_ACK_MB2 (_PRCM_MBOX_HEADER + 0xA) +#define PRCM_MBOX_HEADER_ACK_MB3 (_PRCM_MBOX_HEADER + 0xB) +#define PRCM_MBOX_HEADER_ACK_MB4 (_PRCM_MBOX_HEADER + 0xC) +#define PRCM_MBOX_HEADER_ACK_MB5 (_PRCM_MBOX_HEADER + 0xD) +#define PRCM_MBOX_HEADER_ACK_MB6 (_PRCM_MBOX_HEADER + 0xE) +#define PRCM_MBOX_HEADER_ACK_MB7 (_PRCM_MBOX_HEADER + 0xF) + +/*Req Mailboxes */ +#define PRCM_REQ_MB0 (_PRCMU_TCDM_BASE + 0xFDC) /* 12 bytes */ +#define PRCM_REQ_MB1 (_PRCMU_TCDM_BASE + 0xFD0) /* 12 bytes */ +#define PRCM_REQ_MB2 (_PRCMU_TCDM_BASE + 0xFC0) /* 16 bytes */ +#define PRCM_REQ_MB3 (_PRCMU_TCDM_BASE + 0xE4C) /* 372 bytes */ +#define PRCM_REQ_MB4 (_PRCMU_TCDM_BASE + 0xE48) /* 4 bytes */ +#define PRCM_REQ_MB5 (_PRCMU_TCDM_BASE + 0xE44) /* 4 bytes */ +#define PRCM_REQ_MB6 (_PRCMU_TCDM_BASE + 0xE40) /* 4 bytes */ +#define PRCM_REQ_MB7 (_PRCMU_TCDM_BASE + 0xE3C) /* 4 bytes */ + +/*Ack Mailboxes */ +#define PRCM_ACK_MB0 (_PRCMU_TCDM_BASE + 0xE08) /* 52 bytes */ +#define PRCM_ACK_MB1 (_PRCMU_TCDM_BASE + 0xE04) /* 4 bytes */ +#define PRCM_ACK_MB2 (_PRCMU_TCDM_BASE + 0xE00) /* 4 bytes */ +#define PRCM_ACK_MB3 (_PRCMU_TCDM_BASE + 0xDFC) /* 4 bytes */ +#define PRCM_ACK_MB4 (_PRCMU_TCDM_BASE + 0xDF8) /* 4 bytes */ +#define PRCM_ACK_MB5 (_PRCMU_TCDM_BASE + 0xDF4) /* 4 bytes */ +#define PRCM_ACK_MB6 (_PRCMU_TCDM_BASE + 0xDF0) /* 4 bytes */ +#define PRCM_ACK_MB7 (_PRCMU_TCDM_BASE + 0xDEC) /* 4 bytes */ + +/* Mailbox 0 REQs */ +#define PRCM_REQ_MB0_PWRSTTRH (PRCM_REQ_MB0 + 0x0) +#define PRCM_REQ_MB0_PWRSTTRH_APPWRST (PRCM_REQ_MB0 + 0x0) +#define PRCM_REQ_MB0_PWRSTTRH_APPLLST (PRCM_REQ_MB0 + 0x1) +#define PRCM_REQ_MB0_PWRSTTRH_ULPCLKST (PRCM_REQ_MB0 + 0x2) +#define PRCM_REQ_MB0_PWRSTTRH_BYTEFILL (PRCM_REQ_MB0 + 0x3) +#define PRCM_REQ_MB0_WKUP_8500 (PRCM_REQ_MB0 + 0x4) +#define PRCM_REQ_MB0_WKUP_4500 (PRCM_REQ_MB0 + 0x8) + + +/* Mailbox 0 ACKs */ +#define PRCM_ACK_MB0_AP_PWRST_STATUS (PRCM_ACK_MB0 + 0x0) +#define PRCM_ACK_MB0_PINGPONG_RDP (PRCM_ACK_MB0 + 0x1) +#define PRCM_ACK_MB0_WK0_EVENT_8500 (PRCM_ACK_MB0 + 0x4) +#define PRCM_ACK_MB0_WK0_EVENT_4500 (PRCM_ACK_MB0 + 0x8) +#define PRCM_ACK_MB0_WK1_EVENT_8500 (PRCM_ACK_MB0 + 0x28) +#define PRCM_ACK_MB0_WK1_EVENT_4500 (PRCM_ACK_MB0 + 0x32) +#define PRCM_ACK_MB0_EVENT_4500_NUMBERS 20 + + +/* Mailbox 1 Requests */ +#define PRCM_REQ_MB1_ARMOPP (PRCM_REQ_MB1 + 0x0) +#define PRCM_REQ_MB1_APEOPP (PRCM_REQ_MB1 + 0x1) +#define PRCM_REQ_MB1_BOOSTOPP (PRCM_REQ_MB1 + 0x2) + +/* Mailbox 1 ACKs */ +#define PRCM_ACK_MB1_CURR_ARMOPP (PRCM_ACK_MB1 + 0x0) +#define PRCM_ACK_MB1_CURR_APEOPP (PRCM_ACK_MB1 + 0x1) +#define PRCM_ACK_MB1_CURR_BOOSTOPP (PRCM_ACK_MB1 + 0x2) +#define PRCM_ACK_MB1_CURR_DVFS_STATUS (PRCM_ACK_MB1 + 0x3) + +/* Mailbox 2 REQs */ +#define PRCM_REQ_MB2_DPS_SVAMMDSP (PRCM_REQ_MB2 + 0x0) +#define PRCM_REQ_MB2_DPS_SVAPIPE (PRCM_REQ_MB2 + 0x1) +#define PRCM_REQ_MB2_DPS_SIAMMDSP (PRCM_REQ_MB2 + 0x2) +#define PRCM_REQ_MB2_DPS_SIAPIPE (PRCM_REQ_MB2 + 0x3) +#define PRCM_REQ_MB2_DPS_SGA (PRCM_REQ_MB2 + 0x4) +#define PRCM_REQ_MB2_DPS_B2R2MCDE (PRCM_REQ_MB2 + 0x5) +#define PRCM_REQ_MB2_DPS_ESRAM12 (PRCM_REQ_MB2 + 0x6) +#define PRCM_REQ_MB2_DPS_ESRAM34 (PRCM_REQ_MB2 + 0x7) + +/* Mailbox 2 ACKs */ +#define PRCM_ACK_MB2_DPS_STATUS (PRCM_ACK_MB2 + 0x0) + +/* Mailbox 5 Requests */ +#define PRCM_REQ_MB5_I2COPTYPE (PRCM_REQ_MB5 + 0x0) +#define PRCM_REQ_MB5_I2CREG (PRCM_REQ_MB5 + 0x1) +#define PRCM_REQ_MB5_I2CSLAVE (PRCM_REQ_MB5 + 0x2) +#define PRCM_REQ_MB5_I2CVAL (PRCM_REQ_MB5 + 0x3) + +/* Mailbox 5 ACKs */ +#define PRCM_ACK_MB5_STATUS (PRCM_ACK_MB5 + 0x0) +#define PRCM_ACK_MB5_BANK (PRCM_ACK_MB5 + 0x1) +#define PRCM_ACK_MB5_REG (PRCM_ACK_MB5 + 0x2) +#define PRCM_ACK_MB5_VAL (PRCM_ACK_MB5 + 0x3) + + + +/* FIXME : Need to Cleanup Code */ + +#define PRCM_SVAMMDSPSTATUS PRCM_REQ_MB6 +#define PRCM_SIAMMDSPSTATUS PRCM_REQ_MB7 + + +#define PRCM_XP70_TRIG_IT10 (1 << 0) +#define PRCM_XP70_TRIG_IT11 (1 << 1) +#define PRCM_XP70_TRIG_IT12 (1 << 2) +#define PRCM_XP70_TRIG_IT14 (1 << 4) +#define PRCM_XP70_TRIG_IT17 (1 << 5) + +enum mailbox_t { + REQ_MB0 = 0, /* Uses XP70_IT_EVENT_10 */ + REQ_MB1 = 1, /* Uses XP70_IT_EVENT_11 */ + REQ_MB2 = 2, /* Uses XP70_IT_EVENT_12 */ + REQ_MB5 = 5, /* Uses XP70_IT_EVENT_17 */ +}; + +/* Union declaration */ + + + +/* ARM to XP70 mailbox definition */ +union req_mb0_t { + struct { + enum ap_pwrst_trans_t ap_pwrst_trans:8; + enum intr_wakeup_t fifo_4500wu:8; + enum ddr_pwrst_t ddr_pwrst:8; + unsigned int unused:8; + } req_field; + unsigned int complete_field; +}; + +/* mailbox definition for ARM/APE operation */ +union req_mb1_t { + struct { + enum arm_opp_t arm_opp:8; + enum ape_opp_t ape_opp:8; + } req_field; + unsigned short complete_field; +}; + +/* mailbox definition for hardware accelerator */ +union req_mb2_t { + struct { + enum hw_accst_t hw_accst:8; + } hw_accst_list[ESRAM4 + 1]; + unsigned int complete_field[3]; +}; + +struct arm_irq_mask_t { + unsigned int arm_irq_mask[4]; +}; + + +#endif /* __MACH_PRCMU_FW_V1_H */ diff --git a/arch/arm/mach-ux500/regulator.c b/arch/arm/mach-ux500/regulator.c new file mode 100644 index 00000000000..085af6138c8 --- /dev/null +++ b/arch/arm/mach-ux500/regulator.c @@ -0,0 +1,305 @@ +/* + * Copyright (C) 2009 ST Ericsson. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + * + * U8500 machine specific regulators + * + * Supplies on the AB8500 which are dedicated to AB8500 and AB8500 devices + * are included here as machine specific - + * VARM, VMODEM, VAPE, VMSPS3(VSAFE), VPLL, VANA, VBBN/VBBP + * + * following points must be noted : + * - VARM,VMODEM and VSAFE wont be accountable to the framework. + * - VAPE cannot be turned off as it is the interconnect supply. + * - the EPODs for multimedia are modelled as regulators derived from VAPE. + * + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/err.h> +#include <linux/regulator/driver.h> +#include <linux/regulator/consumer.h> + +#include <mach/ab8500.h> +#include <mach/prcmu-fw-api.h> + +#define U8500_NUM_REGULATORS (5) + +#define DB8500_DCDC_VAPE (0) +#define DB8500_LDO_VANA (1) + +#define REGULATOR_ENABLED (1) +#define REGULATOR_DISABLED (0) + +uint32_t vape_mode = REGULATOR_MODE_NORMAL; + +struct regulator_priv { + unsigned int status; + unsigned int operating_point; + unsigned int opp_mode_dep_count; +}; + +static int dcdc_vape_get_voltage(struct regulator_dev *rdev) +{ + /* returning a dummy non-zero to support optimum_mode* + * helpers + */ + return 1; +} + +static int dcdc_vape_set_mode(struct regulator_dev *rdev, unsigned int mode) +{ + int regulator_id; + struct regulator_priv *priv = rdev_get_drvdata(rdev); + + regulator_id = rdev_get_id(rdev); + if (regulator_id >= U8500_NUM_REGULATORS) + return -EINVAL; + + dev_dbg(rdev_get_dev(rdev), "set_mode = %d\n", mode); + + /* + * we map here the various mode as + * REGULATOR_MODE_IDLE - AP 50OPP + * REGULATOR_MODE_NORMAL - AP 100OPP + * + */ + switch (mode) { + case REGULATOR_MODE_IDLE: + if (priv->operating_point == APE_50_OPP) + return 0; + /* request PRCMU for a transition to 50OPP */ + if (prcmu_set_ape_opp(APE_50_OPP)) { + dev_dbg(rdev_get_dev(rdev), + "APE 50OPP DVFS failed\n"); + return -EINVAL; + } + priv->operating_point = APE_50_OPP; + break; + case REGULATOR_MODE_NORMAL: + if (priv->operating_point == APE_100_OPP) + return 0; + /* request PRCMU for a transition to 50OPP */ + if (prcmu_set_ape_opp(APE_100_OPP)) { + dev_dbg(rdev_get_dev(rdev), + "APE 100OPP DVFS failed\n"); + return -EINVAL; + } + priv->operating_point = APE_100_OPP; + break; + default: + break; + } + + return 0; +} + +static int dcdc_vape_get_mode(struct regulator_dev *rdev) +{ + dev_dbg(rdev_get_dev(rdev), + "get_mode returning %d\n", vape_mode); + + return vape_mode; + +} + +static unsigned int dcdc_vape_get_optimum_mode(struct regulator_dev *rdev, + int input_uV, int output_uV, int load_uA) +{ + int regulator_id; + struct regulator_priv *priv = rdev_get_drvdata(rdev); + + regulator_id = rdev_get_id(rdev); + if (regulator_id >= U8500_NUM_REGULATORS) + return -EINVAL; + + dev_dbg(rdev_get_dev(rdev), "get_optimum_mode: \ + input_uV=%d output_uV=%d load_uA=%d\n", + input_uV, output_uV, load_uA); + + /* load_uA will be non-zero if any non-dvfs client is active */ + if (load_uA) + priv->opp_mode_dep_count++; + else + priv->opp_mode_dep_count--; + + if (priv->opp_mode_dep_count) { + return REGULATOR_MODE_NORMAL; + } else { + return REGULATOR_MODE_IDLE; + } +} + +static int dcdc_vape_enable(struct regulator_dev *rdev) +{ + int regulator_id; + struct regulator_priv *priv = rdev_get_drvdata(rdev); + + regulator_id = rdev_get_id(rdev); + if (regulator_id >= U8500_NUM_REGULATORS) + return -EINVAL; + + priv->status = REGULATOR_ENABLED; + + return 0; +} + +static int dcdc_vape_disable(struct regulator_dev *rdev) +{ + int regulator_id; + struct regulator_priv *priv = rdev_get_drvdata(rdev); + + regulator_id = rdev_get_id(rdev); + if (regulator_id >= U8500_NUM_REGULATORS) + return -EINVAL; + + priv->status = REGULATOR_DISABLED; + + return 0; + +} + +static int dcdc_vape_is_enabled(struct regulator_dev *rdev) +{ + int regulator_id; + struct regulator_priv *priv = rdev_get_drvdata(rdev); + + regulator_id = rdev_get_id(rdev); + if (regulator_id >= U8500_NUM_REGULATORS) + return -EINVAL; + + return priv->status; +} + +static int ldo_vana_enable(struct regulator_dev *rdev) +{ + int regulator_id; + + regulator_id = rdev_get_id(rdev); + if (regulator_id >= U8500_NUM_REGULATORS) + return -EINVAL; + prcmu_i2c_write(AB8500_REGU_CTRL2, + AB8500_REGU_VPLLVANA_REGU_REG, 0x05); + return 0; +}; + +static int ldo_vana_disable(struct regulator_dev *rdev) +{ + int regulator_id; + + regulator_id = rdev_get_id(rdev); + if (regulator_id >= U8500_NUM_REGULATORS) + return -EINVAL; + + return 0; +} + +static struct regulator_ops dcdc_vape_ops = { + .get_voltage = dcdc_vape_get_voltage, + .set_mode = dcdc_vape_set_mode, + .get_mode = dcdc_vape_get_mode, + .get_optimum_mode = dcdc_vape_get_optimum_mode, + .enable = dcdc_vape_enable, + .disable = dcdc_vape_disable, + .is_enabled = dcdc_vape_is_enabled, +}; + +static struct regulator_ops ldo_vana_ops = { + .enable = ldo_vana_enable, + .disable = ldo_vana_disable, +}; + +static struct regulator_desc db8500_desc[U8500_NUM_REGULATORS] = { + { + .name = "DCDC-VAPE", + .id = DB8500_DCDC_VAPE, + .ops = &dcdc_vape_ops, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE, + }, + { + .name = "LDO-VANA", + .id = DB8500_LDO_VANA, + .ops = &ldo_vana_ops, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE, + }, +}; + +static int __devinit db8500_regulator_probe(struct platform_device *pdev) +{ + struct regulator_dev *rdev; + struct regulator_priv *priv; + + priv = kzalloc(sizeof(struct regulator_priv), GFP_KERNEL); + if (!priv) { + dev_dbg(&pdev->dev, "couldn't alloctae priv!!\n"); + return -EINVAL; + } + + priv->status = 0; + priv->operating_point = 0; + priv->opp_mode_dep_count = 0; + + /* TODO : pass the regulator specific data to register */ + rdev = regulator_register(&db8500_desc[pdev->id], &pdev->dev, priv); + if (IS_ERR(rdev)) { + dev_dbg(&pdev->dev, "couldn't register regulator\n"); + return PTR_ERR(rdev); + } + + platform_set_drvdata(pdev, rdev); + + return 0; +} + +static int __devexit db8500_regulator_remove(struct platform_device *pdev) +{ + struct regulator_dev *reg_dev = platform_get_drvdata(pdev); + + regulator_unregister(reg_dev); + + return 0; +} + +static struct platform_driver db8500_regulator_driver = { + .driver = { + .name = "db8500-regulator", + }, + .probe = db8500_regulator_probe, + .remove = __devexit_p(db8500_regulator_remove), +}; + +static int __init db8500_regulator_init(void) +{ + int ret = 0; + + ret = platform_driver_register(&db8500_regulator_driver); + if (ret) { + printk(KERN_INFO "db8500_regulator : platform_driver_register fails\n"); + return -ENODEV; + } + + return 0; +} + +static void __exit db8500_regulator_exit(void) +{ + platform_driver_unregister(&db8500_regulator_driver); +} + +/* replacing subsys_call as we want amba devices to be "powered" on */ +arch_initcall(db8500_regulator_init); +module_exit(db8500_regulator_exit); + +MODULE_AUTHOR("STMicroelectronics/STEricsson"); +MODULE_DESCRIPTION("DB8500 voltage framework"); +MODULE_LICENSE("GPL"); + + + diff --git a/arch/arm/mach-ux500/ste_conn_devices.c b/arch/arm/mach-ux500/ste_conn_devices.c new file mode 100755 index 00000000000..219b7057f0f --- /dev/null +++ b/arch/arm/mach-ux500/ste_conn_devices.c @@ -0,0 +1,388 @@ +/* + * file ste_conn_devices.c + * + * Copyright (C) ST-Ericsson AB 2010 + * + * Board specific device support for the Linux Bluetooth HCI H:4 Driver + * for ST-Ericsson connectivity controller. + * License terms: GNU General Public License (GPL), version 2 + * + * Authors: + * Pär-Gunnar Hjälmdahl (par-gunnar.p.hjalmdahl@stericsson.com) for ST-Ericsson. + * Henrik Possung (henrik.possung@stericsson.com) for ST-Ericsson. + * Josef Kindberg (josef.kindberg@stericsson.com) for ST-Ericsson. + * Dariusz Szymszak (dariusz.xd.szymczak@stericsson.com) for ST-Ericsson. + * Kjell Andersson (kjell.k.andersson@stericsson.com) for ST-Ericsson. + */ + +#include <linux/string.h> +#include <linux/types.h> +#include <linux/skbuff.h> +#include <asm-generic/errno-base.h> +#include <mach/ste_conn_devices.h> +#include <linux/module.h> +#include <linux/gpio.h> + +/** STE_CONN_H4_CHANNEL_BT_CMD - Bluetooth HCI H:4 channel + * for Bluetooth commands in the ST-Ericsson connectivity controller. + */ +#define STE_CONN_H4_CHANNEL_BT_CMD 0x01 + +/** STE_CONN_H4_CHANNEL_BT_ACL - Bluetooth HCI H:4 channel + * for Bluetooth ACL data in the ST-Ericsson connectivity controller. + */ +#define STE_CONN_H4_CHANNEL_BT_ACL 0x02 + +/** STE_CONN_H4_CHANNEL_BT_EVT - Bluetooth HCI H:4 channel + * for Bluetooth events in the ST-Ericsson connectivity controller. + */ +#define STE_CONN_H4_CHANNEL_BT_EVT 0x04 + +/** STE_CONN_H4_CHANNEL_FM_RADIO - Bluetooth HCI H:4 channel + * for FM radio in the ST-Ericsson connectivity controller. + */ +#define STE_CONN_H4_CHANNEL_FM_RADIO 0x08 + +/** STE_CONN_H4_CHANNEL_GNSS - Bluetooth HCI H:4 channel + * for GNSS in the ST-Ericsson connectivity controller. + */ +#define STE_CONN_H4_CHANNEL_GNSS 0x09 + +/** STE_CONN_H4_CHANNEL_DEBUG - Bluetooth HCI H:4 channel + * for internal debug data in the ST-Ericsson connectivity controller. + */ +#define STE_CONN_H4_CHANNEL_DEBUG 0x0B + +/** STE_CONN_H4_CHANNEL_STE_TOOLS - Bluetooth HCI H:4 channel + * for development tools data in the ST-Ericsson connectivity controller. + */ +#define STE_CONN_H4_CHANNEL_STE_TOOLS 0x0D + +/** STE_CONN_H4_CHANNEL_HCI_LOGGER - Bluetooth HCI H:4 channel + * for logging all transmitted H4 packets (on all channels). + */ +#define STE_CONN_H4_CHANNEL_HCI_LOGGER 0xFA + +/** STE_CONN_H4_CHANNEL_US_CTRL - Bluetooth HCI H:4 channel + * for user space control of the ST-Ericsson connectivity controller. + */ +#define STE_CONN_H4_CHANNEL_US_CTRL 0xFC + +/** STE_CONN_H4_CHANNEL_CORE - Bluetooth HCI H:4 channel + * for user space control of the ST-Ericsson connectivity controller. + */ +#define STE_CONN_H4_CHANNEL_CORE 0xFD + + +/** BT_ENABLE_GPIO - GPIO to enable/disable the BT module. + */ +#define BT_ENABLE_GPIO (GPIO(170)) + +/** GBF_ENA_RESET_GPIO - GPIO to enable/disable the controller. + */ +#define GBF_ENA_RESET_GPIO (GPIO(171)) + +/** GBF_ENA_RESET_NAME - Name of GPIO for enabling/disabling. + */ +#define GBF_ENA_RESET_NAME "gbf_ena_reset" + +/** GBF_ENA_RESET_NAME - Name of GPIO for enabling/disabling. + */ +#define BT_ENABLE_NAME "bt_enable" + +#define STE_CONN_ERR(fmt, arg...) printk(KERN_ERR "STE_CONN %s: " fmt "\n" , __func__ , ## arg) + +/* Bluetooth Opcode Group Field */ +#define HCI_BT_OGF_LINK_CTRL 0x01 +#define HCI_BT_OGF_LINK_POLICY 0x02 +#define HCI_BT_OGF_CTRL_BB 0x03 +#define HCI_BT_OGF_LINK_INFO 0x04 +#define HCI_BT_OGF_LINK_STATUS 0x05 +#define HCI_BT_OGF_LINK_TESTING 0x06 +#define HCI_BT_OGF_VS 0x3F + +#define MAKE_FIRST_BYTE_IN_CMD(__ocf) ((uint8_t)(__ocf & 0x00FF)) +#define MAKE_SECOND_BYTE_IN_CMD(__ogf, __ocf) ((uint8_t)(__ogf << 2) | ((__ocf >> 8) & 0x0003)) + +/* Bluetooth Opcode Command Field */ +#define HCI_BT_OCF_RESET 0x0003 +#define HCI_BT_OCF_VS_POWER_SWITCH_OFF 0x0140 +#define HCI_BT_OCF_VS_SYSTEM_RESET 0x0312 +#define HCI_BT_OCF_VS_BT_ENABLE 0x0310 + +/* Bluetooth HCI command lengths */ +#define HCI_BT_LEN_RESET 0x03 +#define HCI_BT_LEN_VS_POWER_SWITCH_OFF 0x09 +#define HCI_BT_LEN_VS_SYSTEM_RESET 0x03 +#define HCI_BT_LEN_VS_BT_ENABLE 0x04 + +#define H4_HEADER_LENGTH 0x01 + +#define LOWEST_STLC2690_HCI_REV 0x0600 +#define LOWEST_CG2900_HCI_REV 0x0700 + +/** + * struct ste_conn_device_id - Structure for connecting H4 channel to named user. + * @name: Name of device. + * @h4_channel: HCI H:4 channel used by this device. + */ +struct ste_conn_device_id { + char *name; + int h4_channel; +}; + +static uint8_t ste_conn_hci_version; +static uint8_t ste_conn_lmp_version; +static uint8_t ste_conn_lmp_subversion; +static uint16_t ste_conn_hci_revision; +static uint16_t ste_conn_manufacturer; + +/* + * ste_conn_devices() - Array containing available H4 channels for current + * ST-Ericsson Connectivity controller. + */ +struct ste_conn_device_id ste_conn_devices[] = { + {STE_CONN_DEVICES_BT_CMD, STE_CONN_H4_CHANNEL_BT_CMD}, + {STE_CONN_DEVICES_BT_ACL, STE_CONN_H4_CHANNEL_BT_ACL}, + {STE_CONN_DEVICES_BT_EVT, STE_CONN_H4_CHANNEL_BT_EVT}, + {STE_CONN_DEVICES_GNSS, STE_CONN_H4_CHANNEL_GNSS}, + {STE_CONN_DEVICES_FM_RADIO, STE_CONN_H4_CHANNEL_FM_RADIO}, + {STE_CONN_DEVICES_DEBUG, STE_CONN_H4_CHANNEL_DEBUG}, + {STE_CONN_DEVICES_STE_TOOLS, STE_CONN_H4_CHANNEL_STE_TOOLS}, + {STE_CONN_DEVICES_HCI_LOGGER, STE_CONN_H4_CHANNEL_HCI_LOGGER}, + {STE_CONN_DEVICES_US_CTRL, STE_CONN_H4_CHANNEL_US_CTRL}, + {STE_CONN_DEVICES_BT_AUDIO, STE_CONN_H4_CHANNEL_BT_CMD}, + {STE_CONN_DEVICES_FM_RADIO_AUDIO, STE_CONN_H4_CHANNEL_FM_RADIO}, + {STE_CONN_DEVICES_CORE, STE_CONN_H4_CHANNEL_CORE} +}; + +#define STE_CONN_NBR_OF_DEVS 12 + +int ste_conn_devices_get_h4_channel(char *name, int *h4_channel) +{ + int i; + int err = -ENXIO; + + *h4_channel = -1; + + for (i = 0; *h4_channel == -1 && i < STE_CONN_NBR_OF_DEVS; i++) { + if (0 == strncmp(name, ste_conn_devices[i].name, STE_CONN_MAX_NAME_SIZE)) { + /* Device found. Return H4 channel */ + *h4_channel = ste_conn_devices[i].h4_channel; + err = 0; + } + } + + return err; +} + +void ste_conn_devices_enable_chip(void) +{ + gpio_set_value(GBF_ENA_RESET_GPIO, GPIO_HIGH); +} + +void ste_conn_devices_disable_chip(void) +{ + gpio_set_value(GBF_ENA_RESET_GPIO, GPIO_LOW); +} + +void ste_conn_devices_set_hci_revision(uint8_t hci_version, + uint16_t hci_revision, + uint8_t lmp_version, + uint8_t lmp_subversion, + uint16_t manufacturer) +{ + ste_conn_hci_version = hci_version; + ste_conn_hci_revision = hci_revision; + ste_conn_lmp_version = lmp_version; + ste_conn_lmp_subversion = lmp_subversion; + ste_conn_manufacturer = manufacturer; +} + +struct sk_buff *ste_conn_devices_get_reset_cmd(uint8_t *op_lsb, uint8_t *op_msb) +{ + struct sk_buff *skb = NULL; + uint8_t *data = NULL; + + if (LOWEST_CG2900_HCI_REV <= ste_conn_hci_revision) { + /* CG2900 used. Send System reset */ + skb = alloc_skb(HCI_BT_LEN_VS_SYSTEM_RESET + H4_HEADER_LENGTH, GFP_KERNEL); + if (skb) { + skb_reserve(skb, H4_HEADER_LENGTH); + data = skb_put(skb, HCI_BT_LEN_VS_SYSTEM_RESET); + data[0] = MAKE_FIRST_BYTE_IN_CMD(HCI_BT_OCF_VS_SYSTEM_RESET); + data[1] = MAKE_SECOND_BYTE_IN_CMD(HCI_BT_OGF_VS, HCI_BT_OCF_VS_SYSTEM_RESET); + data[2] = 0x00; + } else { + STE_CONN_ERR("Could not allocate skb"); + } + } else { + /* STLC 2690 or older used. Send HCI reset */ + skb = alloc_skb(HCI_BT_LEN_RESET + H4_HEADER_LENGTH, GFP_KERNEL); + if (skb) { + skb_reserve(skb, H4_HEADER_LENGTH); + data = skb_put(skb, HCI_BT_LEN_RESET); + data[0] = MAKE_FIRST_BYTE_IN_CMD(HCI_BT_OCF_RESET); + data[1] = MAKE_SECOND_BYTE_IN_CMD(HCI_BT_OGF_CTRL_BB, HCI_BT_OCF_RESET); + data[2] = 0x00; + } else { + STE_CONN_ERR("Could not allocate skb"); + } + } + + if (skb) { + if (op_lsb) { + *op_lsb = data[0]; + } + if (op_msb) { + *op_msb = data[1]; + } + } + + return skb; +} + +struct sk_buff *ste_conn_devices_get_power_switch_off_cmd(uint8_t *op_lsb, uint8_t *op_msb) +{ + struct sk_buff *skb = NULL; + uint8_t *data = NULL; + + if (LOWEST_CG2900_HCI_REV <= ste_conn_hci_revision) { + /* CG2900 used */ + skb = alloc_skb(HCI_BT_LEN_VS_POWER_SWITCH_OFF + H4_HEADER_LENGTH, GFP_KERNEL); + if (skb) { + skb_reserve(skb, H4_HEADER_LENGTH); + data = skb_put(skb, HCI_BT_LEN_VS_POWER_SWITCH_OFF); + data[0] = MAKE_FIRST_BYTE_IN_CMD(HCI_BT_OCF_VS_POWER_SWITCH_OFF); + data[1] = MAKE_SECOND_BYTE_IN_CMD(HCI_BT_OGF_VS, HCI_BT_OCF_VS_POWER_SWITCH_OFF); + data[2] = 0x06; + /* Enter system specific GPIO settings here: + * Section data[3-5] is GPIO pull-up selection + * Section data[6-8] is GPIO pull-down selection + * Each section is a bitfield where + * - byte 0 bit 0 is GPIO 0 + * - byte 0 bit 1 is GPIO 1 + * - up to + * - byte 2 bit 4 which is GPIO 20 + * where each bit means: + * - 0: No pull-up / no pull-down + * - 1: Pull-up / pull-down + * All GPIOs are set as input. + */ + data[3] = 0x00; /* GPIO 0-7 pull-up */ + data[4] = 0x00; /* GPIO 8-15 pull-up */ + data[5] = 0x00; /* GPIO 16-20 pull-up */ + data[6] = 0x00; /* GPIO 0-7 pull-down */ + data[7] = 0x00; /* GPIO 8-15 pull-down */ + data[8] = 0x00; /* GPIO 16-20 pull-down */ + } else { + STE_CONN_ERR("Could not allocate skb"); + } + } else { + /* No command to send. Leave as NULL */ + } + + if (skb) { + if (op_lsb) { + *op_lsb = data[0]; + } + if (op_msb) { + *op_msb = data[1]; + } + } + + return skb; +} + +struct sk_buff *ste_conn_devices_get_bt_enable_cmd(uint8_t *op_lsb, uint8_t *op_msb, bool bt_enable) +{ + struct sk_buff *skb = NULL; + uint8_t *data = NULL; + + if (LOWEST_CG2900_HCI_REV <= ste_conn_hci_revision) { + /* CG2900 used */ + skb = alloc_skb(HCI_BT_LEN_VS_BT_ENABLE + H4_HEADER_LENGTH, GFP_KERNEL); + if (skb) { + skb_reserve(skb, H4_HEADER_LENGTH); + data = skb_put(skb, HCI_BT_LEN_VS_BT_ENABLE); + data[0] = MAKE_FIRST_BYTE_IN_CMD(HCI_BT_OCF_VS_BT_ENABLE); + data[1] = MAKE_SECOND_BYTE_IN_CMD(HCI_BT_OGF_VS, HCI_BT_OCF_VS_BT_ENABLE); + data[2] = 0x01; + if (bt_enable) { + data[3] = 0x01; + } else { + data[3] = 0x00; + } + } else { + STE_CONN_ERR("Could not allocate skb"); + } + } else { + /* No command to send. Leave as NULL */ + } + + if (skb) { + if (op_lsb) { + *op_lsb = data[0]; + } + if (op_msb) { + *op_msb = data[1]; + } + } + + return skb; +} + +int ste_conn_devices_init(void) +{ + int err = 0; + + err = gpio_request(GBF_ENA_RESET_GPIO, GBF_ENA_RESET_NAME); + if (err < 0) { + STE_CONN_ERR("gpio_request failed with err: %d", err); + goto finished; + } + + err = gpio_direction_output(GBF_ENA_RESET_GPIO, GPIO_HIGH); + if (err < 0) { + STE_CONN_ERR("gpio_direction_output failed with err: %d", err); + goto error_handling; + } + + err = gpio_request(BT_ENABLE_GPIO, BT_ENABLE_NAME); + if (err < 0) { + STE_CONN_ERR("gpio_request failed with err: %d", err); + goto finished; + } + + err = gpio_direction_output(BT_ENABLE_GPIO, GPIO_HIGH); + if (err < 0) { + STE_CONN_ERR("gpio_direction_output failed with err: %d", err); + goto error_handling; + } + + goto finished; + +error_handling: + gpio_free(GBF_ENA_RESET_GPIO); + +finished: + ste_conn_devices_disable_chip(); + return err; +} + +void ste_conn_devices_exit(void) +{ + ste_conn_devices_disable_chip(); + + gpio_free(GBF_ENA_RESET_GPIO); +} + +EXPORT_SYMBOL(ste_conn_devices_get_h4_channel); +EXPORT_SYMBOL(ste_conn_devices_enable_chip); +EXPORT_SYMBOL(ste_conn_devices_disable_chip); +EXPORT_SYMBOL(ste_conn_devices_set_hci_revision); +EXPORT_SYMBOL(ste_conn_devices_get_reset_cmd); +EXPORT_SYMBOL(ste_conn_devices_get_power_switch_off_cmd); +EXPORT_SYMBOL(ste_conn_devices_get_bt_enable_cmd); +EXPORT_SYMBOL(ste_conn_devices_init); +EXPORT_SYMBOL(ste_conn_devices_exit); diff --git a/arch/arm/mach-ux500/timer-rtt.c b/arch/arm/mach-ux500/timer-rtt.c new file mode 100644 index 00000000000..1b7f15a381c --- /dev/null +++ b/arch/arm/mach-ux500/timer-rtt.c @@ -0,0 +1,171 @@ +/* + * linux/arch/arm/mach-u8500/timer-rtt.c + * + * Copyright (C) 2009 ST-Ericsson + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + */ +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/io.h> +#include <linux/clockchips.h> +#include <asm/mach/time.h> + +#define RATE_32K 32768 +#define LATCH_32K ((RATE_32K + HZ/2) / HZ) + +#define RTT_IMSC 0x04 +#define RTT_ICR 0x10 +#define RTT_DR 0x14 +#define RTT_LR 0x18 +#define RTT_CR 0x1C + +#define RTT_CR_RTTEN (1 << 1) +#define RTT_CR_RTTOS (1 << 0) + +#define RTC_IMSC 0x10 +#define RTC_RIS 0x14 +#define RTC_MIS 0x18 +#define RTC_ICR 0x1C +#define RTC_TDR 0x20 +#define RTC_TLR1 0x24 +#define RTC_TCR 0x28 + +#define RTC_TCR_RTTOS (1 << 0) +#define RTC_TCR_RTTEN (1 << 1) +#define RTC_TCR_RTTSS (1 << 2) + +#define RTC_IMSC_TIMSC (1 << 1) +#define RTC_ICR_TIC (1 << 1) + +static void rtc_writel(unsigned long val, unsigned long addr) +{ + writel(val, IO_ADDRESS(U8500_RTC_BASE) + addr); +} + +static unsigned long rtc_readl(unsigned long addr) +{ + return readl(IO_ADDRESS(U8500_RTC_BASE) + addr); +} + +static void u8500_rtc_set_mode(enum clock_event_mode mode, + struct clock_event_device *evt) +{ + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + rtc_writel(RTC_TCR_RTTSS, RTC_TCR); + rtc_writel(LATCH_32K, RTC_TLR1); + break; + + case CLOCK_EVT_MODE_ONESHOT: + rtc_writel(0, RTC_TCR); + break; + + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_SHUTDOWN: + rtc_writel(0, RTC_TCR); + break; + + case CLOCK_EVT_MODE_RESUME: + break; + + } +} + +#include <linux/delay.h> +static int u8500_rtc_set_event(unsigned long delta, + struct clock_event_device *dev) +{ + /* succesive writes to TCR require a delay of + * 1 32KHz cycle. so safely delaying 50 + */ + rtc_writel(RTC_TCR_RTTOS, RTC_TCR); + udelay(50); + rtc_writel(delta, RTC_TLR1); + udelay(50); + rtc_writel(RTC_TCR_RTTOS | RTC_TCR_RTTEN, RTC_TCR); + udelay(50); + + return 0; +} + +static int u8500_rtc_interrupt(int irq, void *dev) +{ + struct clock_event_device *clkevt = dev; + + /* we make sure if this is our rtt isr */ + if (rtc_readl(RTC_MIS) & 0x2) { + rtc_writel(RTC_ICR_TIC, RTC_ICR); + clkevt->event_handler(clkevt); + return IRQ_HANDLED; + } + return IRQ_NONE; +} + +static struct clock_event_device u8500_rtc = { + .name = "rtc", + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, + .shift = 32, + .rating = 500, + .set_next_event = u8500_rtc_set_event, + .set_mode = u8500_rtc_set_mode, + .broadcast = smp_timer_broadcast, + .irq = IRQ_RTC_RTT, + .cpumask = cpu_all_mask, +}; + +static struct irqaction u8500_rtc_irq = { + .name = "rtc", + .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_SHARED, + .handler = u8500_rtc_interrupt, + .dev_id = &u8500_rtc, +}; + +void u8500_rtc_init(unsigned int cpu) +{ + rtc_writel(0, RTC_TCR); + rtc_writel(1, RTC_ICR); + rtc_writel(RTC_IMSC_TIMSC, RTC_IMSC); + + u8500_rtc.mult = div_sc(RATE_32K, NSEC_PER_SEC, u8500_rtc.shift); + u8500_rtc.max_delta_ns = clockevent_delta2ns(0xffffffff, &u8500_rtc); + u8500_rtc.min_delta_ns = clockevent_delta2ns(0xff, &u8500_rtc); + + setup_irq(IRQ_RTC_RTT, &u8500_rtc_irq); + clockevents_register_device(&u8500_rtc); +} + +static void rtt0_writel(unsigned long val, unsigned long addr) +{ + writel(val, IO_ADDRESS(U8500_RTT0_BASE) + addr); +} + +static unsigned long rtt0_readl(unsigned long addr) +{ + return readl(IO_ADDRESS(U8500_RTT0_BASE) + addr); +} + +static void u8500_rtt_set_mode(enum clock_event_mode mode, + struct clock_event_device *evt) +{ + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + rtt0_writel(0, RTT_CR); + rtt0_writel(LATCH_32K, RTT_LR); + break; + + case CLOCK_EVT_MODE_ONESHOT: + rtt0_writel(0, RTT_CR); + break; + + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_SHUTDOWN: + rtt0_writel(0, RTT_CR); + break; + + case CLOCK_EVT_MODE_RESUME: + break; + } +} diff --git a/arch/arm/mach-ux500/timer.c b/arch/arm/mach-ux500/timer.c new file mode 100755 index 00000000000..bfe5545bfac --- /dev/null +++ b/arch/arm/mach-ux500/timer.c @@ -0,0 +1,205 @@ +/* + * linux/arch/arm/mach-u8500/timer.c + * + * Copyright (C) 2008 STMicroelectronics + * Copyright (C) 2009 Alessandro Rubini, somewhat based on at91sam926x + * Copyright (C) 2009 ST Ericsson. + * added support to u8500 platform, heavily based on 8815 + * Author: Srinidhi KASAGAR <srinidhi.kasagar@stericsson.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + */ +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/io.h> +#include <linux/clockchips.h> +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/jiffies.h> +#include <asm/mach/time.h> +#include <mach/mtu.h> +#include <mach/setup.h> + +#define TIMER_CTRL 0x80 /* No divisor */ +#define TIMER_PERIODIC 0x40 +#define TIMER_SZ32BIT 0x02 + +static u32 u8500_count; /* accumulated count */ +static u32 u8500_cycle; /* write-once */ +static __iomem void *mtu0_base; +static __iomem void *mtu1_base; + +/* + * clocksource: the MTU device is a decrementing counters, so we negate + * the value being read. + */ +static cycle_t u8500_read_timer(void) +{ + u32 count = readl(mtu1_base + MTU_VAL(0)); + return ~count; +} + +static void u8500_timer_reset(void); + +static void u8500_clocksource_resume(void) +{ + u8500_timer_reset(); +} + +static struct clocksource u8500_clksrc = { + .name = "mtu_1", + .rating = 400, + .read = u8500_read_timer, + .shift = 20, + .mask = CLOCKSOURCE_MASK(32), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, + .resume = u8500_clocksource_resume, +}; + +/* + * Clockevent device: currently only periodic mode is supported + */ +static void u8500_clkevt_mode(enum clock_event_mode mode, + struct clock_event_device *dev) +{ + unsigned long flags; + + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + /* enable interrupts -- and count current value? */ + raw_local_irq_save(flags); + writel(readl(mtu0_base + MTU_IMSC) | 1, mtu0_base + MTU_IMSC); + raw_local_irq_restore(flags); + break; + case CLOCK_EVT_MODE_ONESHOT: + BUG(); /* Not yet supported */ + /* FALLTHROUGH */ + case CLOCK_EVT_MODE_SHUTDOWN: + case CLOCK_EVT_MODE_UNUSED: + /* disable irq */ + raw_local_irq_save(flags); + writel(readl(mtu0_base + MTU_IMSC) & ~1, mtu0_base + MTU_IMSC); + raw_local_irq_restore(flags); + break; + case CLOCK_EVT_MODE_RESUME: + break; + } +} + +static struct clock_event_device u8500_clkevt = { + .name = "mtu_0", + .features = CLOCK_EVT_FEAT_PERIODIC, + .shift = 32, + .rating = 400, + .set_mode = u8500_clkevt_mode, + .irq = IRQ_MTU0, +}; + +/* + * IRQ Handler for the timer 0 of the MTU block. The irq is not shared + * as we are the only users of mtu0 by now. + */ +static irqreturn_t u8500_timer_interrupt(int irq, void *dev_id) +{ + /* ack: "interrupt clear register" */ + writel(1 << 0, mtu0_base + MTU_ICR); + + u8500_clkevt.event_handler(&u8500_clkevt); + + return IRQ_HANDLED; +} + +/* + * Set up timer interrupt, and return the current time in seconds. + */ +static struct irqaction u8500_timer_irq = { + .name = "U8500 Timer Tick", + .flags = IRQF_DISABLED | IRQF_TIMER, + .handler = u8500_timer_interrupt, +}; + +static void u8500_timer_reset(void) +{ + u32 cr; + + writel(0, mtu0_base + MTU_CR(0)); /* off */ + writel(0, mtu1_base + MTU_CR(0)); /* off */ + + /* Timer: configure load and background-load, and fire it up */ + writel(u8500_cycle, mtu0_base + MTU_LR(0)); + writel(u8500_cycle, mtu0_base + MTU_BGLR(0)); + cr = MTU_CRn_PERIODIC | (MTU_CRn_PRESCALE_1 << 2) | MTU_CRn_32BITS; + writel(cr, mtu0_base + MTU_CR(0)); + writel(cr | MTU_CRn_ENA, mtu0_base + MTU_CR(0)); + + /* CS: configure load and background-load, and fire it up */ + writel(u8500_cycle, mtu1_base + MTU_LR(0)); + writel(u8500_cycle, mtu1_base + MTU_BGLR(0)); + cr = (MTU_CRn_PRESCALE_1 << 2) | MTU_CRn_32BITS; + writel(cr, mtu1_base + MTU_CR(0)); + writel(cr | MTU_CRn_ENA, mtu1_base + MTU_CR(0)); +} + +static void __init u8500_timer_init(void) +{ + unsigned long rate; + struct clk *clk0; + struct clk *clk1; + int bits; + +#ifdef CONFIG_LOCAL_TIMERS + twd_base = (void *)IO_ADDRESS(UX500_TWD_BASE); +#endif + clk0 = clk_get_sys("mtu0", NULL); + BUG_ON(IS_ERR(clk0)); + + clk1 = clk_get_sys("mtu1", NULL); + BUG_ON(IS_ERR(clk1)); + + clk_enable(clk0); + clk_enable(clk1); + + rate = clk_get_rate(clk0); + u8500_cycle = (rate + HZ/2) / HZ; + + /* Save global pointer to mtu, used by functions above */ + if (cpu_is_u8500ed()) { + mtu0_base = (void *)IO_ADDRESS(U8500_MTU0_BASE_ED); + mtu1_base = (void *)IO_ADDRESS(U8500_MTU1_BASE_ED); + } else { + mtu0_base = (void *)IO_ADDRESS(UX500_MTU0_BASE); + mtu1_base = (void *)IO_ADDRESS(UX500_MTU1_BASE); + } + + /* Init the timer and register clocksource */ + u8500_timer_reset(); + + u8500_clksrc.mult = clocksource_hz2mult(rate, u8500_clksrc.shift); + bits = 8*sizeof(u8500_count); + + clocksource_register(&u8500_clksrc); + + /* Register irq and clockevents */ + setup_irq(IRQ_MTU0, &u8500_timer_irq); + u8500_clkevt.mult = div_sc(rate, NSEC_PER_SEC, u8500_clkevt.shift); + u8500_clkevt.cpumask = cpumask_of(0); + clockevents_register_device(&u8500_clkevt); + { + extern void u8500_rtc_init(unsigned int cpu); + u8500_rtc_init(0); + } +} + +static void u8500_timer_suspend(void) +{ + /* not supported yet */ +} + +struct sys_timer u8500_timer = { + .init = u8500_timer_init, + .suspend = u8500_timer_suspend, + .resume = u8500_timer_reset, +}; |