diff options
Diffstat (limited to 'arch/arm/mach-omap2')
75 files changed, 4972 insertions, 1219 deletions
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index b31b6f12312..b48bacf0a7a 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -1,22 +1,77 @@ +if ARCH_OMAP2PLUS + +menu "TI OMAP2/3/4 Specific Features" + +config ARCH_OMAP2PLUS_TYPICAL + bool "Typical OMAP configuration" + default y + select AEABI + select REGULATOR + select PM + select PM_RUNTIME + select VFP + select NEON if ARCH_OMAP3 || ARCH_OMAP4 + select SERIAL_8250 + select SERIAL_CORE_CONSOLE + select SERIAL_8250_CONSOLE + select I2C + select I2C_OMAP + select MFD + select MENELAUS if ARCH_OMAP2 + select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4 + select TWL4030_POWER if ARCH_OMAP3 || ARCH_OMAP4 + help + Compile a kernel suitable for booting most boards + +config ARCH_OMAP2 + bool "TI OMAP2" + depends on ARCH_OMAP2PLUS + default y + select CPU_V6 + +config ARCH_OMAP3 + bool "TI OMAP3" + depends on ARCH_OMAP2PLUS + default y + select CPU_V7 + select USB_ARCH_HAS_EHCI + select ARM_L1_CACHE_SHIFT_6 + +config ARCH_OMAP4 + bool "TI OMAP4" + default y + depends on ARCH_OMAP2PLUS + select CPU_V7 + select ARM_GIC + comment "OMAP Core Type" depends on ARCH_OMAP2 config ARCH_OMAP2420 bool "OMAP2420 support" depends on ARCH_OMAP2 + default y select OMAP_DM_TIMER select ARCH_OMAP_OTG config ARCH_OMAP2430 bool "OMAP2430 support" depends on ARCH_OMAP2 + default y select ARCH_OMAP_OTG config ARCH_OMAP3430 bool "OMAP3430 support" depends on ARCH_OMAP3 + default y select ARCH_OMAP_OTG +config OMAP_PACKAGE_ZAF + bool + +config OMAP_PACKAGE_ZAC + bool + config OMAP_PACKAGE_CBC bool @@ -35,6 +90,7 @@ comment "OMAP Board Type" config MACH_OMAP_GENERIC bool "Generic OMAP board" depends on ARCH_OMAP2 + default y config MACH_OMAP2_TUSB6010 bool @@ -44,60 +100,75 @@ config MACH_OMAP2_TUSB6010 config MACH_OMAP_H4 bool "OMAP 2420 H4 board" depends on ARCH_OMAP2 + default y + select OMAP_PACKAGE_ZAF select OMAP_DEBUG_DEVICES config MACH_OMAP_APOLLON bool "OMAP 2420 Apollon board" depends on ARCH_OMAP2 + default y + select OMAP_PACKAGE_ZAC config MACH_OMAP_2430SDP bool "OMAP 2430 SDP board" depends on ARCH_OMAP2 + default y + select OMAP_PACKAGE_ZAC config MACH_OMAP3_BEAGLE bool "OMAP3 BEAGLE board" depends on ARCH_OMAP3 + default y select OMAP_PACKAGE_CBB config MACH_DEVKIT8000 bool "DEVKIT8000 board" depends on ARCH_OMAP3 + default y select OMAP_PACKAGE_CUS select OMAP_MUX config MACH_OMAP_LDP bool "OMAP3 LDP board" depends on ARCH_OMAP3 + default y select OMAP_PACKAGE_CBB config MACH_OVERO bool "Gumstix Overo board" depends on ARCH_OMAP3 + default y select OMAP_PACKAGE_CBB config MACH_OMAP3EVM bool "OMAP 3530 EVM board" depends on ARCH_OMAP3 + default y select OMAP_PACKAGE_CBB config MACH_OMAP3517EVM bool "OMAP3517/ AM3517 EVM board" depends on ARCH_OMAP3 + default y select OMAP_PACKAGE_CBB config MACH_OMAP3_PANDORA bool "OMAP3 Pandora" depends on ARCH_OMAP3 + default y select OMAP_PACKAGE_CBB config MACH_OMAP3_TOUCHBOOK bool "OMAP3 Touch Book" depends on ARCH_OMAP3 + default y select BACKLIGHT_CLASS_DEVICE config MACH_OMAP_3430SDP bool "OMAP 3430 SDP board" depends on ARCH_OMAP3 + default y select OMAP_PACKAGE_CBB config MACH_NOKIA_N800 @@ -112,6 +183,8 @@ config MACH_NOKIA_N810_WIMAX config MACH_NOKIA_N8X0 bool "Nokia N800/N810" depends on ARCH_OMAP2420 + default y + select OMAP_PACKAGE_ZAC select MACH_NOKIA_N800 select MACH_NOKIA_N810 select MACH_NOKIA_N810_WIMAX @@ -119,42 +192,55 @@ config MACH_NOKIA_N8X0 config MACH_NOKIA_RX51 bool "Nokia RX-51 board" depends on ARCH_OMAP3 + default y select OMAP_PACKAGE_CBB config MACH_OMAP_ZOOM2 bool "OMAP3 Zoom2 board" depends on ARCH_OMAP3 + default y select OMAP_PACKAGE_CBB config MACH_OMAP_ZOOM3 bool "OMAP3630 Zoom3 board" depends on ARCH_OMAP3 + default y select OMAP_PACKAGE_CBP config MACH_CM_T35 bool "CompuLab CM-T35 module" depends on ARCH_OMAP3 + default y select OMAP_PACKAGE_CUS select OMAP_MUX config MACH_IGEP0020 bool "IGEP v2 board" depends on ARCH_OMAP3 + default y select OMAP_PACKAGE_CBB config MACH_SBC3530 bool "OMAP3 SBC STALKER board" depends on ARCH_OMAP3 + default y select OMAP_PACKAGE_CUS select OMAP_MUX config MACH_OMAP_3630SDP bool "OMAP3630 SDP board" depends on ARCH_OMAP3 + default y select OMAP_PACKAGE_CBP config MACH_OMAP_4430SDP bool "OMAP 4430 SDP board" + default y + depends on ARCH_OMAP4 + +config MACH_OMAP4_PANDA + bool "OMAP4 Panda Board" + default y depends on ARCH_OMAP4 config OMAP3_EMU @@ -176,3 +262,6 @@ config OMAP3_SDRC_AC_TIMING wish to say no. Selecting yes without understanding what is going on could result in system crashes; +endmenu + +endif diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index ea52b034e96..63b2d8859c3 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -3,7 +3,7 @@ # # Common support -obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o +obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o pm.o omap-2-3-common = irq.o sdrc.o hwmod-common = omap_hwmod.o \ @@ -15,13 +15,14 @@ clock-common = clock.o clock_common_data.o \ obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(prcm-common) $(hwmod-common) obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(prcm-common) $(hwmod-common) -obj-$(CONFIG_ARCH_OMAP4) += $(prcm-common) +obj-$(CONFIG_ARCH_OMAP4) += $(prcm-common) $(hwmod-common) obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o # SMP support ONLY available for OMAP4 obj-$(CONFIG_SMP) += omap-smp.o omap-headsmp.o obj-$(CONFIG_LOCAL_TIMERS) += timer-mpu.o +obj-$(CONFIG_HOTPLUG_CPU) += omap-hotplug.o obj-$(CONFIG_ARCH_OMAP4) += omap44xx-smc.o omap4-common.o AFLAGS_omap44xx-smc.o :=-Wa,-march=armv7-a @@ -36,6 +37,8 @@ AFLAGS_sram243x.o :=-Wa,-march=armv6 AFLAGS_sram34xx.o :=-Wa,-march=armv7-a # Pin multiplexing +obj-$(CONFIG_ARCH_OMAP2420) += mux2420.o +obj-$(CONFIG_ARCH_OMAP2430) += mux2430.o obj-$(CONFIG_ARCH_OMAP3) += mux34xx.o # SMS/SDRC @@ -47,6 +50,7 @@ ifeq ($(CONFIG_PM),y) obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o cpuidle34xx.o +obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o obj-$(CONFIG_PM_DEBUG) += pm-debug.o AFLAGS_sleep24xx.o :=-Wa,-march=armv6 @@ -89,7 +93,10 @@ obj-$(CONFIG_OMAP3_EMU) += emu.o obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o mailbox_mach-objs := mailbox.o -obj-$(CONFIG_OMAP_IOMMU) := iommu2.o omap-iommu.o +obj-$(CONFIG_OMAP_IOMMU) += iommu2.o + +iommu-$(CONFIG_OMAP_IOMMU) := omap-iommu.o +obj-y += $(iommu-m) $(iommu-y) i2c-omap-$(CONFIG_I2C_OMAP) := i2c.o obj-y += $(i2c-omap-m) $(i2c-omap-y) @@ -105,6 +112,7 @@ obj-$(CONFIG_MACH_OMAP3_BEAGLE) += board-omap3beagle.o \ obj-$(CONFIG_MACH_DEVKIT8000) += board-devkit8000.o \ hsmmc.o obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o \ + board-flash.o \ hsmmc.o obj-$(CONFIG_MACH_OVERO) += board-overo.o \ hsmmc.o @@ -114,7 +122,7 @@ obj-$(CONFIG_MACH_OMAP3_PANDORA) += board-omap3pandora.o \ hsmmc.o obj-$(CONFIG_MACH_OMAP_3430SDP) += board-3430sdp.o \ hsmmc.o \ - board-sdp-flash.o + board-flash.o obj-$(CONFIG_MACH_NOKIA_N8X0) += board-n8x0.o obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51.o \ board-rx51-sdram.o \ @@ -123,14 +131,17 @@ obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51.o \ hsmmc.o obj-$(CONFIG_MACH_OMAP_ZOOM2) += board-zoom2.o \ board-zoom-peripherals.o \ + board-flash.o \ hsmmc.o \ board-zoom-debugboard.o obj-$(CONFIG_MACH_OMAP_ZOOM3) += board-zoom3.o \ board-zoom-peripherals.o \ + board-flash.o \ hsmmc.o \ board-zoom-debugboard.o obj-$(CONFIG_MACH_OMAP_3630SDP) += board-3630sdp.o \ board-zoom-peripherals.o \ + board-flash.o \ hsmmc.o obj-$(CONFIG_MACH_CM_T35) += board-cm-t35.o \ hsmmc.o @@ -140,12 +151,16 @@ obj-$(CONFIG_MACH_OMAP3_TOUCHBOOK) += board-omap3touchbook.o \ hsmmc.o obj-$(CONFIG_MACH_OMAP_4430SDP) += board-4430sdp.o \ hsmmc.o +obj-$(CONFIG_MACH_OMAP4_PANDA) += board-omap4panda.o \ + hsmmc.o obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o obj-$(CONFIG_MACH_SBC3530) += board-omap3stalker.o \ hsmmc.o # Platform specific device init code +usbfs-$(CONFIG_ARCH_OMAP_OTG) := usb-fs.o +obj-y += $(usbfs-m) $(usbfs-y) obj-y += usb-musb.o obj-$(CONFIG_MACH_OMAP2_TUSB6010) += usb-tusb6010.o obj-y += usb-ehci.o diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c index 42f49f785c9..8538e4131d2 100644 --- a/arch/arm/mach-omap2/board-2430sdp.c +++ b/arch/arm/mach-omap2/board-2430sdp.c @@ -31,13 +31,13 @@ #include <asm/mach/map.h> #include <mach/gpio.h> -#include <plat/mux.h> #include <plat/board.h> #include <plat/common.h> #include <plat/gpmc.h> #include <plat/usb.h> #include <plat/gpmc-smc91x.h> +#include "mux.h" #include "hsmmc.h" #define SDP2430_CS0_BASE 0x04000000 @@ -122,11 +122,7 @@ static struct omap_smc91x_platform_data board_smc91x_data = { static void __init board_smc91x_init(void) { - if (omap_rev() > OMAP3430_REV_ES1_0) - board_smc91x_data.gpio_irq = 6; - else - board_smc91x_data.gpio_irq = 29; - + omap_mux_init_gpio(149, OMAP_PIN_INPUT); gpmc_smc91x_init(&board_smc91x_data); } @@ -217,17 +213,30 @@ static struct omap_usb_config sdp2430_usb_config __initdata = { .pins[0] = 3, }; +#ifdef CONFIG_OMAP_MUX +static struct omap_board_mux board_mux[] __initdata = { + { .reg_offset = OMAP_MUX_TERMINATOR }, +}; +#else +#define board_mux NULL +#endif + static void __init omap_2430sdp_init(void) { int ret; + omap2430_mux_init(board_mux, OMAP_PACKAGE_ZAC); + omap2430_i2c_init(); platform_add_devices(sdp2430_devices, ARRAY_SIZE(sdp2430_devices)); omap_serial_init(); omap2_hsmmc_init(mmc); - omap_usb_init(&sdp2430_usb_config); + omap2_usbfs_init(&sdp2430_usb_config); + + omap_mux_init_signal("usb0hs_stp", OMAP_PULL_ENA | OMAP_PULL_UP); usb_musb_init(&musb_board_data); + board_smc91x_init(); /* Turn off secondary LCD backlight */ diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c index dd9c03171a1..67b95b5f1a2 100644 --- a/arch/arm/mach-omap2/board-3430sdp.c +++ b/arch/arm/mach-omap2/board-3430sdp.c @@ -41,7 +41,7 @@ #include <plat/control.h> #include <plat/gpmc-smc91x.h> -#include <mach/board-sdp.h> +#include <mach/board-flash.h> #include "mux.h" #include "sdram-qimonda-hyb18m512160af-6.h" @@ -667,6 +667,18 @@ static struct omap_board_mux board_mux[] __initdata = { #define board_mux NULL #endif +/* + * SDP3430 V2 Board CS organization + * Different from SDP3430 V1. Now 4 switches used to specify CS + * + * See also the Switch S8 settings in the comments. + */ +static char chip_sel_3430[][GPMC_CS_NUM] = { + {PDC_NOR, PDC_NAND, PDC_ONENAND, DBG_MPDB, 0, 0, 0, 0}, /* S8:1111 */ + {PDC_ONENAND, PDC_NAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1110 */ + {PDC_NAND, PDC_ONENAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1101 */ +}; + static struct mtd_partition sdp_nor_partitions[] = { /* bootloader (U-Boot, etc) in first sector */ { @@ -797,24 +809,18 @@ static void __init omap_3430sdp_init(void) omap_serial_init(); usb_musb_init(&musb_board_data); board_smc91x_init(); - sdp_flash_init(sdp_flash_partitions); + board_flash_init(sdp_flash_partitions, chip_sel_3430); sdp3430_display_init(); enable_board_wakeup_source(); usb_ehci_init(&ehci_pdata); } -static void __init omap_3430sdp_map_io(void) -{ - omap2_set_globals_343x(); - omap34xx_map_common_io(); -} - MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board") /* Maintainer: Syed Khasim - Texas Instruments Inc */ .phys_io = 0x48000000, .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, .boot_params = 0x80000100, - .map_io = omap_3430sdp_map_io, + .map_io = omap3_map_io, .reserve = omap_reserve, .init_irq = omap_3430sdp_init_irq, .init_machine = omap_3430sdp_init, diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c index 57290fb3fcd..b359c3f7bb3 100644 --- a/arch/arm/mach-omap2/board-3630sdp.c +++ b/arch/arm/mach-omap2/board-3630sdp.c @@ -18,10 +18,10 @@ #include <plat/common.h> #include <plat/board.h> #include <plat/gpmc-smc91x.h> -#include <plat/mux.h> #include <plat/usb.h> #include <mach/board-zoom.h> +#include <mach/board-flash.h> #include "mux.h" #include "sdram-hynix-h8mbx00u0mer-0em.h" @@ -66,12 +66,6 @@ static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { .reset_gpio_port[2] = -EINVAL }; -static void __init omap_sdp_map_io(void) -{ - omap2_set_globals_36xx(); - omap34xx_map_common_io(); -} - static struct omap_board_config_kernel sdp_config[] __initdata = { }; @@ -93,12 +87,131 @@ static struct omap_board_mux board_mux[] __initdata = { #define board_mux NULL #endif +/* + * SDP3630 CS organization + * See also the Switch S8 settings in the comments. + */ +static char chip_sel_sdp[][GPMC_CS_NUM] = { + {PDC_NOR, PDC_NAND, PDC_ONENAND, DBG_MPDB, 0, 0, 0, 0}, /* S8:1111 */ + {PDC_ONENAND, PDC_NAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1110 */ + {PDC_NAND, PDC_ONENAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1101 */ +}; + +static struct mtd_partition sdp_nor_partitions[] = { + /* bootloader (U-Boot, etc) in first sector */ + { + .name = "Bootloader-NOR", + .offset = 0, + .size = SZ_256K, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, + /* bootloader params in the next sector */ + { + .name = "Params-NOR", + .offset = MTDPART_OFS_APPEND, + .size = SZ_256K, + .mask_flags = 0, + }, + /* kernel */ + { + .name = "Kernel-NOR", + .offset = MTDPART_OFS_APPEND, + .size = SZ_2M, + .mask_flags = 0 + }, + /* file system */ + { + .name = "Filesystem-NOR", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + .mask_flags = 0 + } +}; + +static struct mtd_partition sdp_onenand_partitions[] = { + { + .name = "X-Loader-OneNAND", + .offset = 0, + .size = 4 * (64 * 2048), + .mask_flags = MTD_WRITEABLE /* force read-only */ + }, + { + .name = "U-Boot-OneNAND", + .offset = MTDPART_OFS_APPEND, + .size = 2 * (64 * 2048), + .mask_flags = MTD_WRITEABLE /* force read-only */ + }, + { + .name = "U-Boot Environment-OneNAND", + .offset = MTDPART_OFS_APPEND, + .size = 1 * (64 * 2048), + }, + { + .name = "Kernel-OneNAND", + .offset = MTDPART_OFS_APPEND, + .size = 16 * (64 * 2048), + }, + { + .name = "File System-OneNAND", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct mtd_partition sdp_nand_partitions[] = { + /* All the partition sizes are listed in terms of NAND block size */ + { + .name = "X-Loader-NAND", + .offset = 0, + .size = 4 * (64 * 2048), + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, + { + .name = "U-Boot-NAND", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */ + .size = 10 * (64 * 2048), + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, + { + .name = "Boot Env-NAND", + + .offset = MTDPART_OFS_APPEND, /* Offset = 0x1c0000 */ + .size = 6 * (64 * 2048), + }, + { + .name = "Kernel-NAND", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */ + .size = 40 * (64 * 2048), + }, + { + .name = "File System - NAND", + .size = MTDPART_SIZ_FULL, + .offset = MTDPART_OFS_APPEND, /* Offset = 0x780000 */ + }, +}; + +static struct flash_partitions sdp_flash_partitions[] = { + { + .parts = sdp_nor_partitions, + .nr_parts = ARRAY_SIZE(sdp_nor_partitions), + }, + { + .parts = sdp_onenand_partitions, + .nr_parts = ARRAY_SIZE(sdp_onenand_partitions), + }, + { + .parts = sdp_nand_partitions, + .nr_parts = ARRAY_SIZE(sdp_nand_partitions), + }, +}; + static void __init omap_sdp_init(void) { omap3_mux_init(board_mux, OMAP_PACKAGE_CBP); omap_serial_init(); zoom_peripherals_init(); board_smc91x_init(); + board_flash_init(sdp_flash_partitions, chip_sel_sdp); enable_board_wakeup_source(); usb_ehci_init(&ehci_pdata); } @@ -107,7 +220,7 @@ MACHINE_START(OMAP_3630SDP, "OMAP 3630SDP board") .phys_io = 0x48000000, .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, .boot_params = 0x80000100, - .map_io = omap_sdp_map_io, + .map_io = omap3_map_io, .reserve = omap_reserve, .init_irq = omap_sdp_init_irq, .init_machine = omap_sdp_init, diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index 4bb2c5d151e..9447644774c 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c @@ -21,6 +21,7 @@ #include <linux/spi/spi.h> #include <linux/i2c/twl.h> #include <linux/regulator/machine.h> +#include <linux/leds.h> #include <mach/hardware.h> #include <mach/omap4-common.h> @@ -40,6 +41,54 @@ #define ETH_KS8851_POWER_ON 48 #define ETH_KS8851_QUART 138 +static struct gpio_led sdp4430_gpio_leds[] = { + { + .name = "omap4:green:debug0", + .gpio = 61, + }, + { + .name = "omap4:green:debug1", + .gpio = 30, + }, + { + .name = "omap4:green:debug2", + .gpio = 7, + }, + { + .name = "omap4:green:debug3", + .gpio = 8, + }, + { + .name = "omap4:green:debug4", + .gpio = 50, + }, + { + .name = "omap4:blue:user", + .gpio = 169, + }, + { + .name = "omap4:red:user", + .gpio = 170, + }, + { + .name = "omap4:green:user", + .gpio = 139, + }, + +}; + +static struct gpio_led_platform_data sdp4430_led_data = { + .leds = sdp4430_gpio_leds, + .num_leds = ARRAY_SIZE(sdp4430_gpio_leds), +}; + +static struct platform_device sdp4430_leds_gpio = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &sdp4430_led_data, + }, +}; static struct spi_board_info sdp4430_spi_board_info[] __initdata = { { .modalias = "ks8851", @@ -112,6 +161,7 @@ static struct platform_device sdp4430_lcd_device = { static struct platform_device *sdp4430_devices[] __initdata = { &sdp4430_lcd_device, + &sdp4430_leds_gpio, }; static struct omap_lcd_config sdp4430_lcd_config __initdata = { @@ -156,14 +206,16 @@ static struct omap2_hsmmc_info mmc[] = { {} /* Terminator */ }; -static struct regulator_consumer_supply sdp4430_vmmc_supply[] = { +static struct regulator_consumer_supply sdp4430_vaux_supply[] = { { .supply = "vmmc", - .dev_name = "mmci-omap-hs.0", + .dev_name = "mmci-omap-hs.1", }, +}; +static struct regulator_consumer_supply sdp4430_vmmc_supply[] = { { .supply = "vmmc", - .dev_name = "mmci-omap-hs.1", + .dev_name = "mmci-omap-hs.0", }, }; @@ -210,6 +262,8 @@ static struct regulator_init_data sdp4430_vaux1 = { | REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, }, + .num_consumer_supplies = 1, + .consumer_supplies = sdp4430_vaux_supply, }; static struct regulator_init_data sdp4430_vaux2 = { @@ -250,7 +304,7 @@ static struct regulator_init_data sdp4430_vmmc = { | REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, }, - .num_consumer_supplies = 2, + .num_consumer_supplies = 1, .consumer_supplies = sdp4430_vmmc_supply, }; @@ -353,6 +407,11 @@ static struct i2c_board_info __initdata sdp4430_i2c_boardinfo[] = { .platform_data = &sdp4430_twldata, }, }; +static struct i2c_board_info __initdata sdp4430_i2c_3_boardinfo[] = { + { + I2C_BOARD_INFO("tmp105", 0x48), + }, +}; static int __init omap4_i2c_init(void) { /* @@ -362,7 +421,8 @@ static int __init omap4_i2c_init(void) omap_register_i2c_bus(1, 400, sdp4430_i2c_boardinfo, ARRAY_SIZE(sdp4430_i2c_boardinfo)); omap_register_i2c_bus(2, 400, NULL, 0); - omap_register_i2c_bus(3, 400, NULL, 0); + omap_register_i2c_bus(3, 400, sdp4430_i2c_3_boardinfo, + ARRAY_SIZE(sdp4430_i2c_3_boardinfo)); omap_register_i2c_bus(4, 400, NULL, 0); return 0; } diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c index 7da92defcde..4d0f5859286 100644 --- a/arch/arm/mach-omap2/board-am3517evm.c +++ b/arch/arm/mach-omap2/board-am3517evm.c @@ -461,17 +461,11 @@ static void __init am3517_evm_init(void) am3517_evm_ethernet_init(&am3517_evm_emac_pdata); } -static void __init am3517_evm_map_io(void) -{ - omap2_set_globals_343x(); - omap34xx_map_common_io(); -} - MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM") .phys_io = 0x48000000, .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, .boot_params = 0x80000100, - .map_io = am3517_evm_map_io, + .map_io = omap3_map_io, .reserve = omap_reserve, .init_irq = am3517_evm_init_irq, .init_machine = am3517_evm_init, diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c index bd75642aee6..c6421a72514 100644 --- a/arch/arm/mach-omap2/board-apollon.c +++ b/arch/arm/mach-omap2/board-apollon.c @@ -35,13 +35,14 @@ #include <mach/gpio.h> #include <plat/led.h> -#include <plat/mux.h> #include <plat/usb.h> #include <plat/board.h> #include <plat/common.h> #include <plat/gpmc.h> #include <plat/control.h> +#include "mux.h" + /* LED & Switch macros */ #define LED0_GPIO13 13 #define LED1_GPIO14 14 @@ -244,7 +245,7 @@ static inline void __init apollon_init_smc91x(void) apollon_smc91x_resources[0].end = base + 0x30f; udelay(100); - omap_cfg_reg(W4__24XX_GPIO74); + omap_mux_init_gpio(74, 0); if (gpio_request(APOLLON_ETHR_GPIO_IRQ, "SMC91x irq") < 0) { printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n", APOLLON_ETHR_GPIO_IRQ); @@ -286,15 +287,15 @@ static void __init omap_apollon_init_irq(void) static void __init apollon_led_init(void) { /* LED0 - AA10 */ - omap_cfg_reg(AA10_242X_GPIO13); + omap_mux_init_signal("vlynq_clk.gpio_13", 0); gpio_request(LED0_GPIO13, "LED0"); gpio_direction_output(LED0_GPIO13, 0); /* LED1 - AA6 */ - omap_cfg_reg(AA6_242X_GPIO14); + omap_mux_init_signal("vlynq_rx1.gpio_14", 0); gpio_request(LED1_GPIO14, "LED1"); gpio_direction_output(LED1_GPIO14, 0); /* LED2 - AA4 */ - omap_cfg_reg(AA4_242X_GPIO15); + omap_mux_init_signal("vlynq_rx0.gpio_15", 0); gpio_request(LED2_GPIO15, "LED2"); gpio_direction_output(LED2_GPIO15, 0); } @@ -303,22 +304,35 @@ static void __init apollon_usb_init(void) { /* USB device */ /* DEVICE_SUSPEND */ - omap_cfg_reg(P21_242X_GPIO12); + omap_mux_init_signal("mcbsp2_clkx.gpio_12", 0); gpio_request(12, "USB suspend"); gpio_direction_output(12, 0); - omap_usb_init(&apollon_usb_config); + omap2_usbfs_init(&apollon_usb_config); } +#ifdef CONFIG_OMAP_MUX +static struct omap_board_mux board_mux[] __initdata = { + { .reg_offset = OMAP_MUX_TERMINATOR }, +}; +#else +#define board_mux NULL +#endif + static void __init omap_apollon_init(void) { u32 v; + omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAC); + apollon_led_init(); apollon_flash_init(); apollon_usb_init(); /* REVISIT: where's the correct place */ - omap_cfg_reg(W19_24XX_SYS_NIRQ); + omap_mux_init_signal("sys_nirq", OMAP_PULL_ENA | OMAP_PULL_UP); + + /* LCD PWR_EN */ + omap_mux_init_signal("mcbsp2_dr.gpio_11", OMAP_PULL_ENA | OMAP_PULL_UP); /* Use Interal loop-back in MMC/SDIO Module Input Clock selection */ v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c index bc4c3f80706..e10bc109415 100644 --- a/arch/arm/mach-omap2/board-cm-t35.c +++ b/arch/arm/mach-omap2/board-cm-t35.c @@ -61,8 +61,6 @@ #define SB_T35_SMSC911X_GPIO 65 #define NAND_BLOCK_SIZE SZ_128K -#define GPMC_CS0_BASE 0x60 -#define GPMC_CS0_BASE_ADDR (OMAP34XX_GPMC_VIRT + GPMC_CS0_BASE) #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) #include <linux/smsc911x.h> @@ -223,28 +221,12 @@ static struct omap_nand_platform_data cm_t35_nand_data = { .nr_parts = ARRAY_SIZE(cm_t35_nand_partitions), .dma_channel = -1, /* disable DMA in OMAP NAND driver */ .cs = 0, - .gpmc_cs_baseaddr = (void __iomem *)GPMC_CS0_BASE_ADDR, - .gpmc_baseaddr = (void __iomem *)OMAP34XX_GPMC_VIRT, }; -static struct resource cm_t35_nand_resource = { - .flags = IORESOURCE_MEM, -}; - -static struct platform_device cm_t35_nand_device = { - .name = "omap2-nand", - .id = -1, - .num_resources = 1, - .resource = &cm_t35_nand_resource, - .dev = { - .platform_data = &cm_t35_nand_data, - }, -}; - static void __init cm_t35_init_nand(void) { - if (platform_device_register(&cm_t35_nand_device) < 0) + if (gpmc_nand_init(&cm_t35_nand_data) < 0) pr_err("CM-T35: Unable to register NAND device\n"); } #else @@ -708,12 +690,6 @@ static void __init cm_t35_init_irq(void) omap_gpio_init(); } -static void __init cm_t35_map_io(void) -{ - omap2_set_globals_343x(); - omap34xx_map_common_io(); -} - static struct omap_board_mux board_mux[] __initdata = { /* nCS and IRQ for CM-T35 ethernet */ OMAP3_MUX(GPMC_NCS5, OMAP_MUX_MODE0), @@ -836,7 +812,7 @@ MACHINE_START(CM_T35, "Compulab CM-T35") .phys_io = 0x48000000, .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, .boot_params = 0x80000100, - .map_io = cm_t35_map_io, + .map_io = omap3_map_io, .reserve = omap_reserve, .init_irq = cm_t35_init_irq, .init_machine = cm_t35_init, diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c index 922b7464807..a07086d6a0b 100644 --- a/arch/arm/mach-omap2/board-devkit8000.c +++ b/arch/arm/mach-omap2/board-devkit8000.c @@ -33,6 +33,7 @@ #include <linux/i2c/twl.h> #include <mach/hardware.h> +#include <mach/id.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -58,9 +59,6 @@ #include "mux.h" #include "hsmmc.h" -#define GPMC_CS0_BASE 0x60 -#define GPMC_CS_SIZE 0x30 - #define NAND_BLOCK_SIZE SZ_128K #define OMAP_DM9000_GPIO_IRQ 25 @@ -104,20 +102,6 @@ static struct omap_nand_platform_data devkit8000_nand_data = { .dma_channel = -1, /* disable DMA in OMAP NAND driver */ }; -static struct resource devkit8000_nand_resource = { - .flags = IORESOURCE_MEM, -}; - -static struct platform_device devkit8000_nand_device = { - .name = "omap2-nand", - .id = -1, - .dev = { - .platform_data = &devkit8000_nand_data, - }, - .num_resources = 1, - .resource = &devkit8000_nand_resource, -}; - static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, @@ -126,54 +110,50 @@ static struct omap2_hsmmc_info mmc[] = { }, {} /* Terminator */ }; -static struct omap_board_config_kernel devkit8000_config[] __initdata = { -}; static int devkit8000_panel_enable_lcd(struct omap_dss_device *dssdev) { twl_i2c_write_u8(TWL4030_MODULE_GPIO, 0x80, REG_GPIODATADIR1); twl_i2c_write_u8(TWL4030_MODULE_LED, 0x0, 0x0); + if (gpio_is_valid(dssdev->reset_gpio)) + gpio_set_value(dssdev->reset_gpio, 1); return 0; } static void devkit8000_panel_disable_lcd(struct omap_dss_device *dssdev) { + if (gpio_is_valid(dssdev->reset_gpio)) + gpio_set_value(dssdev->reset_gpio, 0); } + static int devkit8000_panel_enable_dvi(struct omap_dss_device *dssdev) { + if (gpio_is_valid(dssdev->reset_gpio)) + gpio_set_value(dssdev->reset_gpio, 1); return 0; } static void devkit8000_panel_disable_dvi(struct omap_dss_device *dssdev) { + if (gpio_is_valid(dssdev->reset_gpio)) + gpio_set_value(dssdev->reset_gpio, 0); } -static int devkit8000_panel_enable_tv(struct omap_dss_device *dssdev) -{ +static struct regulator_consumer_supply devkit8000_vmmc1_supply = + REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0"); - return 0; -} - -static void devkit8000_panel_disable_tv(struct omap_dss_device *dssdev) -{ -} - - -static struct regulator_consumer_supply devkit8000_vmmc1_supply = { - .supply = "vmmc", -}; - -static struct regulator_consumer_supply devkit8000_vsim_supply = { - .supply = "vmmc_aux", -}; +/* ads7846 on SPI */ +static struct regulator_consumer_supply devkit8000_vio_supply = + REGULATOR_SUPPLY("vcc", "spi2.0"); static struct omap_dss_device devkit8000_lcd_device = { .name = "lcd", - .driver_name = "innolux_at_panel", + .driver_name = "generic_panel", .type = OMAP_DISPLAY_TYPE_DPI, .phy.dpi.data_lines = 24, + .reset_gpio = -EINVAL, /* will be replaced */ .platform_enable = devkit8000_panel_enable_lcd, .platform_disable = devkit8000_panel_disable_lcd, }; @@ -182,6 +162,7 @@ static struct omap_dss_device devkit8000_dvi_device = { .driver_name = "generic_panel", .type = OMAP_DISPLAY_TYPE_DPI, .phy.dpi.data_lines = 24, + .reset_gpio = -EINVAL, /* will be replaced */ .platform_enable = devkit8000_panel_enable_dvi, .platform_disable = devkit8000_panel_disable_dvi, }; @@ -191,8 +172,6 @@ static struct omap_dss_device devkit8000_tv_device = { .driver_name = "venc", .type = OMAP_DISPLAY_TYPE_VENC, .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, - .platform_enable = devkit8000_panel_enable_tv, - .platform_disable = devkit8000_panel_disable_tv, }; @@ -216,10 +195,8 @@ static struct platform_device devkit8000_dss_device = { }, }; -static struct regulator_consumer_supply devkit8000_vdda_dac_supply = { - .supply = "vdda_dac", - .dev = &devkit8000_dss_device.dev, -}; +static struct regulator_consumer_supply devkit8000_vdda_dac_supply = + REGULATOR_SUPPLY("vdda_dac", "omapdss"); static int board_keymap[] = { KEY(0, 0, KEY_1), @@ -266,7 +243,21 @@ static int devkit8000_twl_gpio_setup(struct device *dev, /* link regulators to MMC adapters */ devkit8000_vmmc1_supply.dev = mmc[0].dev; - devkit8000_vsim_supply.dev = mmc[0].dev; + + /* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */ + gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1; + + /* gpio + 1 is "LCD_PWREN" (out, active high) */ + devkit8000_lcd_device.reset_gpio = gpio + 1; + gpio_request(devkit8000_lcd_device.reset_gpio, "LCD_PWREN"); + /* Disable until needed */ + gpio_direction_output(devkit8000_lcd_device.reset_gpio, 0); + + /* gpio + 7 is "DVI_PD" (out, active low) */ + devkit8000_dvi_device.reset_gpio = gpio + 7; + gpio_request(devkit8000_dvi_device.reset_gpio, "DVI PowerDown"); + /* Disable until needed */ + gpio_direction_output(devkit8000_dvi_device.reset_gpio, 0); return 0; } @@ -282,16 +273,8 @@ static struct twl4030_gpio_platform_data devkit8000_gpio_data = { .setup = devkit8000_twl_gpio_setup, }; -static struct regulator_consumer_supply devkit8000_vpll2_supplies[] = { - { - .supply = "vdvi", - .dev = &devkit8000_lcd_device.dev, - }, - { - .supply = "vdds_dsi", - .dev = &devkit8000_dss_device.dev, - } -}; +static struct regulator_consumer_supply devkit8000_vpll1_supply = + REGULATOR_SUPPLY("vdds_dsi", "omapdss"); /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ static struct regulator_init_data devkit8000_vmmc1 = { @@ -308,21 +291,6 @@ static struct regulator_init_data devkit8000_vmmc1 = { .consumer_supplies = &devkit8000_vmmc1_supply, }; -/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */ -static struct regulator_init_data devkit8000_vsim = { - .constraints = { - .min_uV = 1800000, - .max_uV = 3000000, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE - | REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &devkit8000_vsim_supply, -}; - /* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */ static struct regulator_init_data devkit8000_vdac = { .constraints = { @@ -337,10 +305,9 @@ static struct regulator_init_data devkit8000_vdac = { .consumer_supplies = &devkit8000_vdda_dac_supply, }; -/* VPLL2 for digital video outputs */ -static struct regulator_init_data devkit8000_vpll2 = { +/* VPLL1 for digital video outputs */ +static struct regulator_init_data devkit8000_vpll1 = { .constraints = { - .name = "VDVI", .min_uV = 1800000, .max_uV = 1800000, .valid_modes_mask = REGULATOR_MODE_NORMAL @@ -348,8 +315,23 @@ static struct regulator_init_data devkit8000_vpll2 = { .valid_ops_mask = REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, }, - .num_consumer_supplies = ARRAY_SIZE(devkit8000_vpll2_supplies), - .consumer_supplies = devkit8000_vpll2_supplies, + .num_consumer_supplies = 1, + .consumer_supplies = &devkit8000_vpll1_supply, +}; + +/* VAUX4 for ads7846 and nubs */ +static struct regulator_init_data devkit8000_vio = { + .constraints = { + .min_uV = 1800000, + .max_uV = 1800000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &devkit8000_vio_supply, }; static struct twl4030_usb_data devkit8000_usb_data = { @@ -374,15 +356,15 @@ static struct twl4030_platform_data devkit8000_twldata = { .gpio = &devkit8000_gpio_data, .codec = &devkit8000_codec_data, .vmmc1 = &devkit8000_vmmc1, - .vsim = &devkit8000_vsim, .vdac = &devkit8000_vdac, - .vpll2 = &devkit8000_vpll2, + .vpll1 = &devkit8000_vpll1, + .vio = &devkit8000_vio, .keypad = &devkit8000_kp_data, }; static struct i2c_board_info __initdata devkit8000_i2c_boardinfo[] = { { - I2C_BOARD_INFO("twl4030", 0x48), + I2C_BOARD_INFO("tps65930", 0x48), .flags = I2C_CLIENT_WAKE, .irq = INT_34XX_SYS_NIRQ, .platform_data = &devkit8000_twldata, @@ -464,8 +446,6 @@ static struct platform_device keys_gpio = { static void __init devkit8000_init_irq(void) { - omap_board_config = devkit8000_config; - omap_board_config_size = ARRAY_SIZE(devkit8000_config); omap2_init_common_hw(mt46h32m32lf6_sdrc_params, mt46h32m32lf6_sdrc_params); omap_init_irq(); @@ -560,6 +540,9 @@ static struct platform_device omap_dm9000_dev = { static void __init omap_dm9000_init(void) { + unsigned char *eth_addr = omap_dm9000_platdata.dev_addr; + struct omap_die_id odi; + if (gpio_request(OMAP_DM9000_GPIO_IRQ, "dm9000 irq") < 0) { printk(KERN_ERR "Failed to request GPIO%d for dm9000 IRQ\n", OMAP_DM9000_GPIO_IRQ); @@ -567,6 +550,16 @@ static void __init omap_dm9000_init(void) } gpio_direction_input(OMAP_DM9000_GPIO_IRQ); + + /* init the mac address using DIE id */ + omap_get_die_id(&odi); + + eth_addr[0] = 0x02; /* locally administered */ + eth_addr[1] = odi.id_1 & 0xff; + eth_addr[2] = (odi.id_0 & 0xff000000) >> 24; + eth_addr[3] = (odi.id_0 & 0x00ff0000) >> 16; + eth_addr[4] = (odi.id_0 & 0x0000ff00) >> 8; + eth_addr[5] = (odi.id_0 & 0x000000ff); } static struct platform_device *devkit8000_devices[] __initdata = { @@ -581,8 +574,6 @@ static void __init devkit8000_flash_init(void) u8 cs = 0; u8 nandcs = GPMC_CS_NUM + 1; - u32 gpmc_base_add = OMAP34XX_GPMC_VIRT; - /* find out the chip-select on which NAND exists */ while (cs < GPMC_CS_NUM) { u32 ret = 0; @@ -604,13 +595,9 @@ static void __init devkit8000_flash_init(void) if (nandcs < GPMC_CS_NUM) { devkit8000_nand_data.cs = nandcs; - devkit8000_nand_data.gpmc_cs_baseaddr = (void *) - (gpmc_base_add + GPMC_CS0_BASE + nandcs * GPMC_CS_SIZE); - devkit8000_nand_data.gpmc_baseaddr = (void *) - (gpmc_base_add); printk(KERN_INFO "Registering NAND on CS%d\n", nandcs); - if (platform_device_register(&devkit8000_nand_device) < 0) + if (gpmc_nand_init(&devkit8000_nand_data) < 0) printk(KERN_ERR "Unable to register NAND device\n"); } } @@ -797,8 +784,6 @@ static void __init devkit8000_init(void) devkit8000_i2c_init(); platform_add_devices(devkit8000_devices, ARRAY_SIZE(devkit8000_devices)); - omap_board_config = devkit8000_config; - omap_board_config_size = ARRAY_SIZE(devkit8000_config); spi_register_board_info(devkit8000_spi_board_info, ARRAY_SIZE(devkit8000_spi_board_info)); @@ -814,17 +799,11 @@ static void __init devkit8000_init(void) omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT); } -static void __init devkit8000_map_io(void) -{ - omap2_set_globals_343x(); - omap34xx_map_common_io(); -} - MACHINE_START(DEVKIT8000, "OMAP3 Devkit8000") .phys_io = 0x48000000, .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, .boot_params = 0x80000100, - .map_io = devkit8000_map_io, + .map_io = omap3_map_io, .reserve = omap_reserve, .init_irq = devkit8000_init_irq, .init_machine = devkit8000_init, diff --git a/arch/arm/mach-omap2/board-sdp-flash.c b/arch/arm/mach-omap2/board-flash.c index 2d026328e38..ac834aa7abf 100644 --- a/arch/arm/mach-omap2/board-sdp-flash.c +++ b/arch/arm/mach-omap2/board-flash.c @@ -21,7 +21,7 @@ #include <plat/nand.h> #include <plat/onenand.h> #include <plat/tc.h> -#include <mach/board-sdp.h> +#include <mach/board-flash.h> #define REG_FPGA_REV 0x10 #define REG_FPGA_DIP_SWITCH_INPUT2 0x60 @@ -29,72 +29,53 @@ #define DEBUG_BASE 0x08000000 /* debug board */ -#define PDC_NOR 1 -#define PDC_NAND 2 -#define PDC_ONENAND 3 -#define DBG_MPDB 4 - /* various memory sizes */ #define FLASH_SIZE_SDPV1 SZ_64M /* NOR flash (64 Meg aligned) */ #define FLASH_SIZE_SDPV2 SZ_128M /* NOR flash (256 Meg aligned) */ -/* - * SDP3430 V2 Board CS organization - * Different from SDP3430 V1. Now 4 switches used to specify CS - * - * See also the Switch S8 settings in the comments. - * - * REVISIT: Add support for 2430 SDP - */ -static const unsigned char chip_sel_sdp[][GPMC_CS_NUM] = { - {PDC_NOR, PDC_NAND, PDC_ONENAND, DBG_MPDB, 0, 0, 0, 0}, /* S8:1111 */ - {PDC_ONENAND, PDC_NAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1110 */ - {PDC_NAND, PDC_ONENAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1101 */ -}; - -static struct physmap_flash_data sdp_nor_data = { +static struct physmap_flash_data board_nor_data = { .width = 2, }; -static struct resource sdp_nor_resource = { +static struct resource board_nor_resource = { .flags = IORESOURCE_MEM, }; -static struct platform_device sdp_nor_device = { +static struct platform_device board_nor_device = { .name = "physmap-flash", .id = 0, .dev = { - .platform_data = &sdp_nor_data, + .platform_data = &board_nor_data, }, .num_resources = 1, - .resource = &sdp_nor_resource, + .resource = &board_nor_resource, }; static void -__init board_nor_init(struct flash_partitions sdp_nor_parts, u8 cs) +__init board_nor_init(struct mtd_partition *nor_parts, u8 nr_parts, u8 cs) { int err; - sdp_nor_data.parts = sdp_nor_parts.parts; - sdp_nor_data.nr_parts = sdp_nor_parts.nr_parts; + board_nor_data.parts = nor_parts; + board_nor_data.nr_parts = nr_parts; /* Configure start address and size of NOR device */ if (omap_rev() >= OMAP3430_REV_ES1_0) { err = gpmc_cs_request(cs, FLASH_SIZE_SDPV2 - 1, - (unsigned long *)&sdp_nor_resource.start); - sdp_nor_resource.end = sdp_nor_resource.start + (unsigned long *)&board_nor_resource.start); + board_nor_resource.end = board_nor_resource.start + FLASH_SIZE_SDPV2 - 1; } else { err = gpmc_cs_request(cs, FLASH_SIZE_SDPV1 - 1, - (unsigned long *)&sdp_nor_resource.start); - sdp_nor_resource.end = sdp_nor_resource.start + (unsigned long *)&board_nor_resource.start); + board_nor_resource.end = board_nor_resource.start + FLASH_SIZE_SDPV1 - 1; } if (err < 0) { printk(KERN_ERR "NOR: Can't request GPMC CS\n"); return; } - if (platform_device_register(&sdp_nor_device) < 0) + if (platform_device_register(&board_nor_device) < 0) printk(KERN_ERR "Unable to register NOR device\n"); } @@ -105,17 +86,18 @@ static struct omap_onenand_platform_data board_onenand_data = { }; static void -__init board_onenand_init(struct flash_partitions sdp_onenand_parts, u8 cs) +__init board_onenand_init(struct mtd_partition *onenand_parts, + u8 nr_parts, u8 cs) { board_onenand_data.cs = cs; - board_onenand_data.parts = sdp_onenand_parts.parts; - board_onenand_data.nr_parts = sdp_onenand_parts.nr_parts; + board_onenand_data.parts = onenand_parts; + board_onenand_data.nr_parts = nr_parts; gpmc_onenand_init(&board_onenand_data); } #else static void -__init board_onenand_init(struct flash_partitions sdp_onenand_parts, u8 cs) +__init board_onenand_init(struct mtd_partition *nor_parts, u8 nr_parts, u8 cs) { } #endif /* CONFIG_MTD_ONENAND_OMAP2 || CONFIG_MTD_ONENAND_OMAP2_MODULE */ @@ -147,7 +129,7 @@ static struct gpmc_timings nand_timings = { .wr_data_mux_bus = 0, }; -static struct omap_nand_platform_data sdp_nand_data = { +static struct omap_nand_platform_data board_nand_data = { .nand_setup = NULL, .gpmc_t = &nand_timings, .dma_channel = -1, /* disable DMA in OMAP NAND driver */ @@ -155,23 +137,18 @@ static struct omap_nand_platform_data sdp_nand_data = { .devsize = 0, /* '0' for 8-bit, '1' for 16-bit device */ }; -static void -__init board_nand_init(struct flash_partitions sdp_nand_parts, u8 cs) +void +__init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs) { - sdp_nand_data.cs = cs; - sdp_nand_data.parts = sdp_nand_parts.parts; - sdp_nand_data.nr_parts = sdp_nand_parts.nr_parts; + board_nand_data.cs = cs; + board_nand_data.parts = nand_parts; + board_nand_data.nr_parts = nr_parts; - sdp_nand_data.gpmc_cs_baseaddr = (void *)(OMAP34XX_GPMC_VIRT + - GPMC_CS0_BASE + - cs * GPMC_CS_SIZE); - sdp_nand_data.gpmc_baseaddr = (void *) (OMAP34XX_GPMC_VIRT); - - gpmc_nand_init(&sdp_nand_data); + gpmc_nand_init(&board_nand_data); } #else -static void -__init board_nand_init(struct flash_partitions sdp_nand_parts, u8 cs) +void +__init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs) { } #endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */ @@ -215,7 +192,8 @@ unmap: * * @return - void. */ -void __init sdp_flash_init(struct flash_partitions sdp_partition_info[]) +void board_flash_init(struct flash_partitions partition_info[], + char chip_sel_board[][GPMC_CS_NUM]) { u8 cs = 0; u8 norcs = GPMC_CS_NUM + 1; @@ -232,7 +210,7 @@ void __init sdp_flash_init(struct flash_partitions sdp_partition_info[]) printk(KERN_ERR "%s: Invalid chip select: %d\n", __func__, cs); return; } - config_sel = (unsigned char *)(chip_sel_sdp[idx]); + config_sel = (unsigned char *)(chip_sel_board[idx]); while (cs < GPMC_CS_NUM) { switch (config_sel[cs]) { @@ -256,17 +234,20 @@ void __init sdp_flash_init(struct flash_partitions sdp_partition_info[]) printk(KERN_INFO "NOR: Unable to find configuration " "in GPMC\n"); else - board_nor_init(sdp_partition_info[0], norcs); + board_nor_init(partition_info[0].parts, + partition_info[0].nr_parts, norcs); if (onenandcs > GPMC_CS_NUM) printk(KERN_INFO "OneNAND: Unable to find configuration " "in GPMC\n"); else - board_onenand_init(sdp_partition_info[1], onenandcs); + board_onenand_init(partition_info[1].parts, + partition_info[1].nr_parts, onenandcs); if (nandcs > GPMC_CS_NUM) printk(KERN_INFO "NAND: Unable to find configuration " "in GPMC\n"); else - board_nand_init(sdp_partition_info[2], nandcs); + board_nand_init(partition_info[2].parts, + partition_info[2].nr_parts, nandcs); } diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index 9242902d3a4..3482b99e8c8 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c @@ -26,7 +26,6 @@ #include <asm/mach/map.h> #include <mach/gpio.h> -#include <plat/mux.h> #include <plat/usb.h> #include <plat/board.h> #include <plat/common.h> diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c index 16703fdb351..e09bd686389 100644 --- a/arch/arm/mach-omap2/board-h4.c +++ b/arch/arm/mach-omap2/board-h4.c @@ -33,7 +33,6 @@ #include <plat/control.h> #include <mach/gpio.h> -#include <plat/mux.h> #include <plat/usb.h> #include <plat/board.h> #include <plat/common.h> @@ -42,6 +41,8 @@ #include <plat/dma.h> #include <plat/gpmc.h> +#include "mux.h" + #define H4_FLASH_CS 0 #define H4_SMC91X_CS 1 @@ -246,7 +247,7 @@ static inline void __init h4_init_debug(void) udelay(100); - omap_cfg_reg(M15_24XX_GPIO92); + omap_mux_init_gpio(92, 0); if (debug_card_init(cs_mem_base, H4_ETHR_GPIO_IRQ) < 0) gpmc_cs_free(eth_cs); @@ -272,27 +273,6 @@ static struct omap_lcd_config h4_lcd_config __initdata = { }; static struct omap_usb_config h4_usb_config __initdata = { -#ifdef CONFIG_MACH_OMAP2_H4_USB1 - /* NOTE: usb1 could also be used with 3 wire signaling */ - .pins[1] = 4, -#endif - -#ifdef CONFIG_MACH_OMAP_H4_OTG - /* S1.10 ON -- USB OTG port - * usb0 switched to Mini-AB port and isp1301 transceiver; - * S2.POS3 = OFF, S2.POS4 = ON ... to allow battery charging - */ - .otg = 1, - .pins[0] = 4, -#ifdef CONFIG_USB_GADGET_OMAP - /* use OTG cable, or standard A-to-MiniB */ - .hmc_mode = 0x14, /* 0:dev/otg 1:host 2:disable */ -#elif defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) - /* use OTG cable, or NONSTANDARD (B-to-MiniB) */ - .hmc_mode = 0x11, /* 0:host 1:host 2:disable */ -#endif /* XX */ - -#else /* S1.10 OFF -- usb "download port" * usb0 switched to Mini-B port and isp1105 transceiver; * S2.POS3 = ON, S2.POS4 = OFF ... to enable battery charging @@ -301,7 +281,6 @@ static struct omap_usb_config h4_usb_config __initdata = { .pins[0] = 3, /* .hmc_mode = 0x14,*/ /* 0:dev 1:host 2:disable */ .hmc_mode = 0x00, /* 0:dev|otg 1:disable 2:disable */ -#endif }; static struct omap_board_config_kernel h4_config[] = { @@ -338,31 +317,54 @@ static struct i2c_board_info __initdata h4_i2c_board_info[] = { }, }; +#ifdef CONFIG_OMAP_MUX +static struct omap_board_mux board_mux[] __initdata = { + { .reg_offset = OMAP_MUX_TERMINATOR }, +}; +#else +#define board_mux NULL +#endif + static void __init omap_h4_init(void) { + omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAF); + /* * Make sure the serial ports are muxed on at this point. * You have to mux them off in device drivers later on * if not needed. */ -#if defined(CONFIG_OMAP_IR) || defined(CONFIG_OMAP_IR_MODULE) - omap_cfg_reg(K15_24XX_UART3_TX); - omap_cfg_reg(K14_24XX_UART3_RX); -#endif #if defined(CONFIG_KEYBOARD_OMAP) || defined(CONFIG_KEYBOARD_OMAP_MODULE) + omap_mux_init_gpio(88, OMAP_PULL_ENA | OMAP_PULL_UP); + omap_mux_init_gpio(89, OMAP_PULL_ENA | OMAP_PULL_UP); + omap_mux_init_gpio(124, OMAP_PULL_ENA | OMAP_PULL_UP); + omap_mux_init_signal("mcbsp2_dr.gpio_11", OMAP_PULL_ENA | OMAP_PULL_UP); if (omap_has_menelaus()) { + omap_mux_init_signal("sdrc_a14.gpio0", + OMAP_PULL_ENA | OMAP_PULL_UP); + omap_mux_init_signal("vlynq_rx0.gpio_15", 0); + omap_mux_init_signal("gpio_98", 0); row_gpios[5] = 0; col_gpios[2] = 15; col_gpios[6] = 18; + } else { + omap_mux_init_signal("gpio_96", OMAP_PULL_ENA | OMAP_PULL_UP); + omap_mux_init_signal("gpio_100", 0); + omap_mux_init_signal("gpio_98", 0); } + omap_mux_init_signal("gpio_90", 0); + omap_mux_init_signal("gpio_91", 0); + omap_mux_init_signal("gpio_36", 0); + omap_mux_init_signal("mcbsp2_clkx.gpio_12", 0); + omap_mux_init_signal("gpio_97", 0); #endif i2c_register_board_info(1, h4_i2c_board_info, ARRAY_SIZE(h4_i2c_board_info)); platform_add_devices(h4_devices, ARRAY_SIZE(h4_devices)); - omap_usb_init(&h4_usb_config); + omap2_usbfs_init(&h4_usb_config); omap_serial_init(); } diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c index 759e39d1a70..175f0433976 100644 --- a/arch/arm/mach-omap2/board-igep0020.c +++ b/arch/arm/mach-omap2/board-igep0020.c @@ -532,17 +532,11 @@ static void __init igep2_init(void) pr_warning("IGEP v2: Could not obtain gpio GPIO_WIFI_NRESET\n"); } -static void __init igep2_map_io(void) -{ - omap2_set_globals_343x(); - omap34xx_map_common_io(); -} - MACHINE_START(IGEP0020, "IGEP v2 board") .phys_io = 0x48000000, .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, .boot_params = 0x80000100, - .map_io = igep2_map_io, + .map_io = omap3_map_io, .reserve = omap_reserve, .init_irq = igep2_init_irq, .init_machine = igep2_init, diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c index 9cd2669113e..00d9b13b01c 100644 --- a/arch/arm/mach-omap2/board-ldp.c +++ b/arch/arm/mach-omap2/board-ldp.c @@ -38,6 +38,7 @@ #include <plat/board.h> #include <plat/common.h> #include <plat/gpmc.h> +#include <mach/board-zoom.h> #include <asm/delay.h> #include <plat/control.h> @@ -388,6 +389,38 @@ static struct omap_musb_board_data musb_board_data = { .power = 100, }; +static struct mtd_partition ldp_nand_partitions[] = { + /* All the partition sizes are listed in terms of NAND block size */ + { + .name = "X-Loader-NAND", + .offset = 0, + .size = 4 * (64 * 2048), /* 512KB, 0x80000 */ + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, + { + .name = "U-Boot-NAND", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */ + .size = 10 * (64 * 2048), /* 1.25MB, 0x140000 */ + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, + { + .name = "Boot Env-NAND", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x1c0000 */ + .size = 2 * (64 * 2048), /* 256KB, 0x40000 */ + }, + { + .name = "Kernel-NAND", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x0200000*/ + .size = 240 * (64 * 2048), /* 30M, 0x1E00000 */ + }, + { + .name = "File System - NAND", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x2000000 */ + .size = MTDPART_SIZ_FULL, /* 96MB, 0x6000000 */ + }, + +}; + static void __init omap_ldp_init(void) { omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); @@ -400,23 +433,19 @@ static void __init omap_ldp_init(void) ads7846_dev_init(); omap_serial_init(); usb_musb_init(&musb_board_data); + board_nand_init(ldp_nand_partitions, + ARRAY_SIZE(ldp_nand_partitions), ZOOM_NAND_CS); omap2_hsmmc_init(mmc); /* link regulators to MMC adapters */ ldp_vmmc1_supply.dev = mmc[0].dev; } -static void __init omap_ldp_map_io(void) -{ - omap2_set_globals_343x(); - omap34xx_map_common_io(); -} - MACHINE_START(OMAP_LDP, "OMAP LDP board") .phys_io = 0x48000000, .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, .boot_params = 0x80000100, - .map_io = omap_ldp_map_io, + .map_io = omap3_map_io, .reserve = omap_reserve, .init_irq = omap_ldp_init_irq, .init_machine = omap_ldp_init, diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c index 2565ff08a22..a3e2b49aa39 100644 --- a/arch/arm/mach-omap2/board-n8x0.c +++ b/arch/arm/mach-omap2/board-n8x0.c @@ -33,6 +33,8 @@ #include <plat/mmc.h> #include <plat/serial.h> +#include "mux.h" + static int slot1_cover_open; static int slot2_cover_open; static struct device *mmc_device; @@ -649,8 +651,17 @@ static void __init n8x0_init_irq(void) omap_gpio_init(); } +#ifdef CONFIG_OMAP_MUX +static struct omap_board_mux board_mux[] __initdata = { + { .reg_offset = OMAP_MUX_TERMINATOR }, +}; +#else +#define board_mux NULL +#endif + static void __init n8x0_init_machine(void) { + omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAC); /* FIXME: add n810 spi devices */ spi_register_board_info(n800_spi_board_info, ARRAY_SIZE(n800_spi_board_info)); diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index 0ab0c26db4d..87969c7df65 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c @@ -48,9 +48,6 @@ #include "mux.h" #include "hsmmc.h" -#define GPMC_CS0_BASE 0x60 -#define GPMC_CS_SIZE 0x30 - #define NAND_BLOCK_SIZE SZ_128K static struct mtd_partition omap3beagle_nand_partitions[] = { @@ -93,20 +90,6 @@ static struct omap_nand_platform_data omap3beagle_nand_data = { .dev_ready = NULL, }; -static struct resource omap3beagle_nand_resource = { - .flags = IORESOURCE_MEM, -}; - -static struct platform_device omap3beagle_nand_device = { - .name = "omap2-nand", - .id = -1, - .dev = { - .platform_data = &omap3beagle_nand_data, - }, - .num_resources = 1, - .resource = &omap3beagle_nand_resource, -}; - /* DSS */ static int beagle_enable_dvi(struct omap_dss_device *dssdev) @@ -424,8 +407,6 @@ static void __init omap3beagle_flash_init(void) u8 cs = 0; u8 nandcs = GPMC_CS_NUM + 1; - u32 gpmc_base_add = OMAP34XX_GPMC_VIRT; - /* find out the chip-select on which NAND exists */ while (cs < GPMC_CS_NUM) { u32 ret = 0; @@ -447,12 +428,9 @@ static void __init omap3beagle_flash_init(void) if (nandcs < GPMC_CS_NUM) { omap3beagle_nand_data.cs = nandcs; - omap3beagle_nand_data.gpmc_cs_baseaddr = (void *) - (gpmc_base_add + GPMC_CS0_BASE + nandcs * GPMC_CS_SIZE); - omap3beagle_nand_data.gpmc_baseaddr = (void *) (gpmc_base_add); printk(KERN_INFO "Registering NAND on CS%d\n", nandcs); - if (platform_device_register(&omap3beagle_nand_device) < 0) + if (gpmc_nand_init(&omap3beagle_nand_data) < 0) printk(KERN_ERR "Unable to register NAND device\n"); } } @@ -507,18 +485,12 @@ static void __init omap3_beagle_init(void) beagle_display_init(); } -static void __init omap3_beagle_map_io(void) -{ - omap2_set_globals_343x(); - omap34xx_map_common_io(); -} - MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board") /* Maintainer: Syed Mohammed Khasim - http://beagleboard.org */ .phys_io = 0x48000000, .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, .boot_params = 0x80000100, - .map_io = omap3_beagle_map_io, + .map_io = omap3_map_io, .reserve = omap_reserve, .init_irq = omap3_beagle_init_irq, .init_machine = omap3_beagle_init, diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index a3d2e285e11..f76d9c0a47a 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c @@ -514,14 +514,11 @@ static struct regulator_init_data omap3_evm_vdac = { }; /* VPLL2 for digital video outputs */ -static struct regulator_consumer_supply omap3_evm_vpll2_supply = { - .supply = "vdvi", - .dev = &omap3_evm_lcd_device.dev, -}; +static struct regulator_consumer_supply omap3_evm_vpll2_supply = + REGULATOR_SUPPLY("vdds_dsi", "omapdss"); static struct regulator_init_data omap3_evm_vpll2 = { .constraints = { - .name = "VDVI", .min_uV = 1800000, .max_uV = 1800000, .apply_uV = true, @@ -715,18 +712,12 @@ static void __init omap3_evm_init(void) omap3_evm_display_init(); } -static void __init omap3_evm_map_io(void) -{ - omap2_set_globals_343x(); - omap34xx_map_common_io(); -} - MACHINE_START(OMAP3EVM, "OMAP3 EVM") /* Maintainer: Syed Mohammed Khasim - Texas Instruments */ .phys_io = 0x48000000, .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, .boot_params = 0x80000100, - .map_io = omap3_evm_map_io, + .map_io = omap3_map_io, .reserve = omap_reserve, .init_irq = omap3_evm_init_irq, .init_machine = omap3_evm_init, diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c index c0f4f12eba5..dd3af2be13b 100644 --- a/arch/arm/mach-omap2/board-omap3pandora.c +++ b/arch/arm/mach-omap2/board-omap3pandora.c @@ -25,10 +25,14 @@ #include <linux/spi/ads7846.h> #include <linux/regulator/machine.h> #include <linux/i2c/twl.h> +#include <linux/spi/wl12xx.h> +#include <linux/mtd/partitions.h> +#include <linux/mtd/nand.h> #include <linux/leds.h> #include <linux/input.h> #include <linux/input/matrix_keypad.h> #include <linux/gpio_keys.h> +#include <linux/mmc/card.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -41,15 +45,49 @@ #include <plat/mcspi.h> #include <plat/usb.h> #include <plat/display.h> +#include <plat/nand.h> #include "mux.h" #include "sdram-micron-mt46h32m32lf-6.h" #include "hsmmc.h" +#define PANDORA_WIFI_IRQ_GPIO 21 +#define PANDORA_WIFI_NRESET_GPIO 23 #define OMAP3_PANDORA_TS_GPIO 94 -/* hardware debounce: (value + 1) * 31us */ -#define GPIO_DEBOUNCE_TIME 127 +#define NAND_BLOCK_SIZE SZ_128K + +static struct mtd_partition omap3pandora_nand_partitions[] = { + { + .name = "xloader", + .offset = 0, + .size = 4 * NAND_BLOCK_SIZE, + .mask_flags = MTD_WRITEABLE + }, { + .name = "uboot", + .offset = MTDPART_OFS_APPEND, + .size = 15 * NAND_BLOCK_SIZE, + }, { + .name = "uboot-env", + .offset = MTDPART_OFS_APPEND, + .size = 1 * NAND_BLOCK_SIZE, + }, { + .name = "boot", + .offset = MTDPART_OFS_APPEND, + .size = 80 * NAND_BLOCK_SIZE, + }, { + .name = "rootfs", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct omap_nand_platform_data pandora_nand_data = { + .cs = 0, + .devsize = 1, /* '0' for 8-bit, '1' for 16-bit device */ + .parts = omap3pandora_nand_partitions, + .nr_parts = ARRAY_SIZE(omap3pandora_nand_partitions), +}; static struct gpio_led pandora_gpio_leds[] = { { @@ -88,6 +126,7 @@ static struct platform_device pandora_leds_gpio = { .type = ev_type, \ .code = ev_code, \ .active_low = act_low, \ + .debounce_interval = 4, \ .desc = "btn " descr, \ } @@ -99,14 +138,14 @@ static struct gpio_keys_button pandora_gpio_keys[] = { GPIO_BUTTON_LOW(103, KEY_DOWN, "down"), GPIO_BUTTON_LOW(96, KEY_LEFT, "left"), GPIO_BUTTON_LOW(98, KEY_RIGHT, "right"), - GPIO_BUTTON_LOW(109, KEY_KP1, "game 1"), - GPIO_BUTTON_LOW(111, KEY_KP2, "game 2"), - GPIO_BUTTON_LOW(106, KEY_KP3, "game 3"), - GPIO_BUTTON_LOW(101, KEY_KP4, "game 4"), - GPIO_BUTTON_LOW(102, BTN_TL, "l"), - GPIO_BUTTON_LOW(97, BTN_TL2, "l2"), - GPIO_BUTTON_LOW(105, BTN_TR, "r"), - GPIO_BUTTON_LOW(107, BTN_TR2, "r2"), + GPIO_BUTTON_LOW(109, KEY_PAGEUP, "game 1"), + GPIO_BUTTON_LOW(111, KEY_END, "game 2"), + GPIO_BUTTON_LOW(106, KEY_PAGEDOWN, "game 3"), + GPIO_BUTTON_LOW(101, KEY_HOME, "game 4"), + GPIO_BUTTON_LOW(102, KEY_RIGHTSHIFT, "l"), + GPIO_BUTTON_LOW(97, KEY_KPPLUS, "l2"), + GPIO_BUTTON_LOW(105, KEY_RIGHTCTRL, "r"), + GPIO_BUTTON_LOW(107, KEY_KPMINUS, "r2"), GPIO_BUTTON_LOW(104, KEY_LEFTCTRL, "ctrl"), GPIO_BUTTON_LOW(99, KEY_MENU, "menu"), GPIO_BUTTON_LOW(176, KEY_COFFEE, "hold"), @@ -127,14 +166,7 @@ static struct platform_device pandora_keys_gpio = { }, }; -static void __init pandora_keys_gpio_init(void) -{ - /* set debounce time for GPIO banks 4 and 6 */ - gpio_set_debounce(32 * 3, GPIO_DEBOUNCE_TIME); - gpio_set_debounce(32 * 5, GPIO_DEBOUNCE_TIME); -} - -static int board_keymap[] = { +static const uint32_t board_keymap[] = { /* row, col, code */ KEY(0, 0, KEY_9), KEY(0, 1, KEY_8), @@ -227,6 +259,20 @@ static struct platform_device pandora_dss_device = { }, }; +static void pandora_wl1251_init_card(struct mmc_card *card) +{ + /* + * We have TI wl1251 attached to MMC3. Pass this information to + * SDIO core because it can't be probed by normal methods. + */ + card->quirks |= MMC_QUIRK_NONSTD_SDIO; + card->cccr.wide_bus = 1; + card->cis.vendor = 0x104c; + card->cis.device = 0x9066; + card->cis.blksize = 512; + card->cis.max_dtr = 20000000; +} + static struct omap2_hsmmc_info omap3pandora_mmc[] = { { .mmc = 1, @@ -248,6 +294,7 @@ static struct omap2_hsmmc_info omap3pandora_mmc[] = { .wires = 4, .gpio_cd = -EINVAL, .gpio_wp = -EINVAL, + .init_card = pandora_wl1251_init_card, }, {} /* Terminator */ }; @@ -255,12 +302,33 @@ static struct omap2_hsmmc_info omap3pandora_mmc[] = { static int omap3pandora_twl_gpio_setup(struct device *dev, unsigned gpio, unsigned ngpio) { + int ret, gpio_32khz; + /* gpio + {0,1} is "mmc{0,1}_cd" (input/IRQ) */ omap3pandora_mmc[0].gpio_cd = gpio + 0; omap3pandora_mmc[1].gpio_cd = gpio + 1; omap2_hsmmc_init(omap3pandora_mmc); + /* gpio + 13 drives 32kHz buffer for wifi module */ + gpio_32khz = gpio + 13; + ret = gpio_request(gpio_32khz, "wifi 32kHz"); + if (ret < 0) { + pr_err("Cannot get GPIO line %d, ret=%d\n", gpio_32khz, ret); + goto fail; + } + + ret = gpio_direction_output(gpio_32khz, 1); + if (ret < 0) { + pr_err("Cannot set GPIO line %d, ret=%d\n", gpio_32khz, ret); + goto fail_direction; + } + return 0; + +fail_direction: + gpio_free(gpio_32khz); +fail: + return -ENODEV; } static struct twl4030_gpio_platform_data omap3pandora_gpio_data = { @@ -539,10 +607,67 @@ static void __init omap3pandora_init_irq(void) omap_gpio_init(); } +static void pandora_wl1251_set_power(bool enable) +{ + /* + * Keep power always on until wl1251_sdio driver learns to re-init + * the chip after powering it down and back up. + */ +} + +static struct wl12xx_platform_data pandora_wl1251_pdata = { + .set_power = pandora_wl1251_set_power, + .use_eeprom = true, +}; + +static struct platform_device pandora_wl1251_data = { + .name = "wl1251_data", + .id = -1, + .dev = { + .platform_data = &pandora_wl1251_pdata, + }, +}; + +static void pandora_wl1251_init(void) +{ + int ret; + + ret = gpio_request(PANDORA_WIFI_IRQ_GPIO, "wl1251 irq"); + if (ret < 0) + goto fail; + + ret = gpio_direction_input(PANDORA_WIFI_IRQ_GPIO); + if (ret < 0) + goto fail_irq; + + pandora_wl1251_pdata.irq = gpio_to_irq(PANDORA_WIFI_IRQ_GPIO); + if (pandora_wl1251_pdata.irq < 0) + goto fail_irq; + + ret = gpio_request(PANDORA_WIFI_NRESET_GPIO, "wl1251 nreset"); + if (ret < 0) + goto fail_irq; + + /* start powered so that it probes with MMC subsystem */ + ret = gpio_direction_output(PANDORA_WIFI_NRESET_GPIO, 1); + if (ret < 0) + goto fail_nreset; + + return; + +fail_nreset: + gpio_free(PANDORA_WIFI_NRESET_GPIO); +fail_irq: + gpio_free(PANDORA_WIFI_IRQ_GPIO); +fail: + printk(KERN_ERR "wl1251 board initialisation failed\n"); +} + static struct platform_device *omap3pandora_devices[] __initdata = { &pandora_leds_gpio, &pandora_keys_gpio, &pandora_dss_device, + &pandora_wl1251_data, }; static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { @@ -575,6 +700,7 @@ static void __init omap3pandora_init(void) { omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); omap3pandora_i2c_init(); + pandora_wl1251_init(); platform_add_devices(omap3pandora_devices, ARRAY_SIZE(omap3pandora_devices)); omap_serial_init(); @@ -582,25 +708,19 @@ static void __init omap3pandora_init(void) ARRAY_SIZE(omap3pandora_spi_board_info)); omap3pandora_ads7846_init(); usb_ehci_init(&ehci_pdata); - pandora_keys_gpio_init(); usb_musb_init(&musb_board_data); + gpmc_nand_init(&pandora_nand_data); /* Ensure SDRC pins are mux'd for self-refresh */ omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT); omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT); } -static void __init omap3pandora_map_io(void) -{ - omap2_set_globals_343x(); - omap34xx_map_common_io(); -} - MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console") .phys_io = 0x48000000, .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, .boot_params = 0x80000100, - .map_io = omap3pandora_map_io, + .map_io = omap3_map_io, .reserve = omap_reserve, .init_irq = omap3pandora_init_irq, .init_machine = omap3pandora_init, diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c index a04cffd691c..bcd01d278c6 100644 --- a/arch/arm/mach-omap2/board-omap3stalker.c +++ b/arch/arm/mach-omap2/board-omap3stalker.c @@ -652,18 +652,12 @@ static void __init omap3_stalker_init(void) omap_mux_init_signal("sdr_cke1", OMAP_PIN_OUTPUT); } -static void __init omap3_stalker_map_io(void) -{ - omap2_set_globals_343x(); - omap34xx_map_common_io(); -} - MACHINE_START(SBC3530, "OMAP3 STALKER") /* Maintainer: Jason Lam -lzg@ema-tech.com */ .phys_io = 0x48000000, .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, .boot_params = 0x80000100, - .map_io = omap3_stalker_map_io, + .map_io = omap3_map_io, .init_irq = omap3_stalker_init_irq, .init_machine = omap3_stalker_init, .timer = &omap_timer, diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c index f05b867c585..663c62d271e 100644 --- a/arch/arm/mach-omap2/board-omap3touchbook.c +++ b/arch/arm/mach-omap2/board-omap3touchbook.c @@ -54,9 +54,6 @@ #include <asm/setup.h> -#define GPMC_CS0_BASE 0x60 -#define GPMC_CS_SIZE 0x30 - #define NAND_BLOCK_SIZE SZ_128K #define OMAP3_AC_GPIO 136 @@ -106,20 +103,6 @@ static struct omap_nand_platform_data omap3touchbook_nand_data = { .dev_ready = NULL, }; -static struct resource omap3touchbook_nand_resource = { - .flags = IORESOURCE_MEM, -}; - -static struct platform_device omap3touchbook_nand_device = { - .name = "omap2-nand", - .id = -1, - .dev = { - .platform_data = &omap3touchbook_nand_data, - }, - .num_resources = 1, - .resource = &omap3touchbook_nand_resource, -}; - #include "sdram-micron-mt46h32m32lf-6.h" static struct omap2_hsmmc_info mmc[] = { @@ -458,8 +441,6 @@ static void __init omap3touchbook_flash_init(void) u8 cs = 0; u8 nandcs = GPMC_CS_NUM + 1; - u32 gpmc_base_add = OMAP34XX_GPMC_VIRT; - /* find out the chip-select on which NAND exists */ while (cs < GPMC_CS_NUM) { u32 ret = 0; @@ -481,13 +462,9 @@ static void __init omap3touchbook_flash_init(void) if (nandcs < GPMC_CS_NUM) { omap3touchbook_nand_data.cs = nandcs; - omap3touchbook_nand_data.gpmc_cs_baseaddr = (void *) - (gpmc_base_add + GPMC_CS0_BASE + nandcs * GPMC_CS_SIZE); - omap3touchbook_nand_data.gpmc_baseaddr = - (void *) (gpmc_base_add); printk(KERN_INFO "Registering NAND on CS%d\n", nandcs); - if (platform_device_register(&omap3touchbook_nand_device) < 0) + if (gpmc_nand_init(&omap3touchbook_nand_data) < 0) printk(KERN_ERR "Unable to register NAND device\n"); } } @@ -559,18 +536,12 @@ static void __init omap3_touchbook_init(void) omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT); } -static void __init omap3_touchbook_map_io(void) -{ - omap2_set_globals_343x(); - omap34xx_map_common_io(); -} - MACHINE_START(TOUCHBOOK, "OMAP3 touchbook Board") /* Maintainer: Gregoire Gentil - http://www.alwaysinnovating.com */ .phys_io = 0x48000000, .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, .boot_params = 0x80000100, - .map_io = omap3_touchbook_map_io, + .map_io = omap3_map_io, .reserve = omap_reserve, .init_irq = omap3_touchbook_init_irq, .init_machine = omap3_touchbook_init, diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c new file mode 100644 index 00000000000..c03d1d56db5 --- /dev/null +++ b/arch/arm/mach-omap2/board-omap4panda.c @@ -0,0 +1,304 @@ +/* + * Board support file for OMAP4430 based PandaBoard. + * + * Copyright (C) 2010 Texas Instruments + * + * Author: David Anders <x0132446@ti.com> + * + * Based on mach-omap2/board-4430sdp.c + * + * Author: Santosh Shilimkar <santosh.shilimkar@ti.com> + * + * Based on mach-omap2/board-3430sdp.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/io.h> +#include <linux/gpio.h> +#include <linux/usb/otg.h> +#include <linux/i2c/twl.h> +#include <linux/regulator/machine.h> + +#include <mach/hardware.h> +#include <mach/omap4-common.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> + +#include <plat/board.h> +#include <plat/common.h> +#include <plat/control.h> +#include <plat/timer-gp.h> +#include <plat/usb.h> +#include <plat/mmc.h> +#include "hsmmc.h" + + +static void __init omap4_panda_init_irq(void) +{ + omap2_init_common_hw(NULL, NULL); + gic_init_irq(); + omap_gpio_init(); +} + +static struct omap_musb_board_data musb_board_data = { + .interface_type = MUSB_INTERFACE_UTMI, + .mode = MUSB_PERIPHERAL, + .power = 100, +}; + +static struct omap2_hsmmc_info mmc[] = { + { + .mmc = 1, + .wires = 8, + .gpio_wp = -EINVAL, + }, + {} /* Terminator */ +}; + +static struct regulator_consumer_supply omap4_panda_vmmc_supply[] = { + { + .supply = "vmmc", + .dev_name = "mmci-omap-hs.0", + }, + { + .supply = "vmmc", + .dev_name = "mmci-omap-hs.1", + }, +}; + +static int omap4_twl6030_hsmmc_late_init(struct device *dev) +{ + int ret = 0; + struct platform_device *pdev = container_of(dev, + struct platform_device, dev); + struct omap_mmc_platform_data *pdata = dev->platform_data; + + /* Setting MMC1 Card detect Irq */ + if (pdev->id == 0) + pdata->slots[0].card_detect_irq = TWL6030_IRQ_BASE + + MMCDETECT_INTR_OFFSET; + return ret; +} + +static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev) +{ + struct omap_mmc_platform_data *pdata = dev->platform_data; + + pdata->init = omap4_twl6030_hsmmc_late_init; +} + +static int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers) +{ + struct omap2_hsmmc_info *c; + + omap2_hsmmc_init(controllers); + for (c = controllers; c->mmc; c++) + omap4_twl6030_hsmmc_set_late_init(c->dev); + + return 0; +} + +static struct regulator_init_data omap4_panda_vaux1 = { + .constraints = { + .min_uV = 1000000, + .max_uV = 3000000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE + | REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, +}; + +static struct regulator_init_data omap4_panda_vaux2 = { + .constraints = { + .min_uV = 1200000, + .max_uV = 2800000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE + | REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, +}; + +static struct regulator_init_data omap4_panda_vaux3 = { + .constraints = { + .min_uV = 1000000, + .max_uV = 3000000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE + | REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, +}; + +/* VMMC1 for MMC1 card */ +static struct regulator_init_data omap4_panda_vmmc = { + .constraints = { + .min_uV = 1200000, + .max_uV = 3000000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE + | REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = 2, + .consumer_supplies = omap4_panda_vmmc_supply, +}; + +static struct regulator_init_data omap4_panda_vpp = { + .constraints = { + .min_uV = 1800000, + .max_uV = 2500000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE + | REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, +}; + +static struct regulator_init_data omap4_panda_vusim = { + .constraints = { + .min_uV = 1200000, + .max_uV = 2900000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE + | REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, +}; + +static struct regulator_init_data omap4_panda_vana = { + .constraints = { + .min_uV = 2100000, + .max_uV = 2100000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, +}; + +static struct regulator_init_data omap4_panda_vcxio = { + .constraints = { + .min_uV = 1800000, + .max_uV = 1800000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, +}; + +static struct regulator_init_data omap4_panda_vdac = { + .constraints = { + .min_uV = 1800000, + .max_uV = 1800000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, +}; + +static struct regulator_init_data omap4_panda_vusb = { + .constraints = { + .min_uV = 3300000, + .max_uV = 3300000, + .apply_uV = true, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, +}; + +static struct twl4030_platform_data omap4_panda_twldata = { + .irq_base = TWL6030_IRQ_BASE, + .irq_end = TWL6030_IRQ_END, + + /* Regulators */ + .vmmc = &omap4_panda_vmmc, + .vpp = &omap4_panda_vpp, + .vusim = &omap4_panda_vusim, + .vana = &omap4_panda_vana, + .vcxio = &omap4_panda_vcxio, + .vdac = &omap4_panda_vdac, + .vusb = &omap4_panda_vusb, + .vaux1 = &omap4_panda_vaux1, + .vaux2 = &omap4_panda_vaux2, + .vaux3 = &omap4_panda_vaux3, +}; + +static struct i2c_board_info __initdata omap4_panda_i2c_boardinfo[] = { + { + I2C_BOARD_INFO("twl6030", 0x48), + .flags = I2C_CLIENT_WAKE, + .irq = OMAP44XX_IRQ_SYS_1N, + .platform_data = &omap4_panda_twldata, + }, +}; +static int __init omap4_panda_i2c_init(void) +{ + /* + * Phoenix Audio IC needs I2C1 to + * start with 400 KHz or less + */ + omap_register_i2c_bus(1, 400, omap4_panda_i2c_boardinfo, + ARRAY_SIZE(omap4_panda_i2c_boardinfo)); + omap_register_i2c_bus(2, 400, NULL, 0); + omap_register_i2c_bus(3, 400, NULL, 0); + omap_register_i2c_bus(4, 400, NULL, 0); + return 0; +} +static void __init omap4_panda_init(void) +{ + int status; + + omap4_panda_i2c_init(); + omap_serial_init(); + omap4_twl6030_hsmmc_init(mmc); + /* OMAP4 Panda uses internal transceiver so register nop transceiver */ + usb_nop_xceiv_register(); + /* FIXME: allow multi-omap to boot until musb is updated for omap4 */ + if (!cpu_is_omap44xx()) + usb_musb_init(&musb_board_data); +} + +static void __init omap4_panda_map_io(void) +{ + omap2_set_globals_443x(); + omap44xx_map_common_io(); +} + +MACHINE_START(OMAP4_PANDA, "OMAP4 Panda board") + /* Maintainer: David Anders - Texas Instruments Inc */ + .phys_io = 0x48000000, + .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, + .boot_params = 0x80000100, + .map_io = omap4_panda_map_io, + .init_irq = omap4_panda_init_irq, + .init_machine = omap4_panda_init, + .timer = &omap_timer, +MACHINE_END diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c index 87acb2f198e..4c484361835 100644 --- a/arch/arm/mach-omap2/board-overo.c +++ b/arch/arm/mach-omap2/board-overo.c @@ -58,8 +58,6 @@ #define OVERO_GPIO_USBH_NRESET 183 #define NAND_BLOCK_SIZE SZ_128K -#define GPMC_CS0_BASE 0x60 -#define GPMC_CS_SIZE 0x30 #define OVERO_SMSC911X_CS 5 #define OVERO_SMSC911X_GPIO 176 @@ -166,9 +164,26 @@ static struct platform_device overo_smsc911x_device = { }, }; +static struct platform_device overo_smsc911x2_device = { + .name = "smsc911x", + .id = 1, + .num_resources = ARRAY_SIZE(overo_smsc911x2_resources), + .resource = overo_smsc911x2_resources, + .dev = { + .platform_data = &overo_smsc911x_config, + }, +}; + +static struct platform_device *smsc911x_devices[] = { + &overo_smsc911x_device, + &overo_smsc911x2_device, +}; + static inline void __init overo_init_smsc911x(void) { - unsigned long cs_mem_base; + unsigned long cs_mem_base, cs_mem_base2; + + /* set up first smsc911x chip */ if (gpmc_cs_request(OVERO_SMSC911X_CS, SZ_16M, &cs_mem_base) < 0) { printk(KERN_ERR "Failed request for GPMC mem for smsc911x\n"); @@ -189,7 +204,28 @@ static inline void __init overo_init_smsc911x(void) overo_smsc911x_resources[1].start = OMAP_GPIO_IRQ(OVERO_SMSC911X_GPIO); overo_smsc911x_resources[1].end = 0; - platform_device_register(&overo_smsc911x_device); + /* set up second smsc911x chip */ + + if (gpmc_cs_request(OVERO_SMSC911X2_CS, SZ_16M, &cs_mem_base2) < 0) { + printk(KERN_ERR "Failed request for GPMC mem for smsc911x2\n"); + return; + } + + overo_smsc911x2_resources[0].start = cs_mem_base2 + 0x0; + overo_smsc911x2_resources[0].end = cs_mem_base2 + 0xff; + + if ((gpio_request(OVERO_SMSC911X2_GPIO, "SMSC911X2 IRQ") == 0) && + (gpio_direction_input(OVERO_SMSC911X2_GPIO) == 0)) { + gpio_export(OVERO_SMSC911X2_GPIO, 0); + } else { + printk(KERN_ERR "could not obtain gpio for SMSC911X2 IRQ\n"); + return; + } + + overo_smsc911x2_resources[1].start = OMAP_GPIO_IRQ(OVERO_SMSC911X2_GPIO); + overo_smsc911x2_resources[1].end = 0; + + platform_add_devices(smsc911x_devices, ARRAY_SIZE(smsc911x_devices)); } #else @@ -231,28 +267,11 @@ static struct omap_nand_platform_data overo_nand_data = { .dma_channel = -1, /* disable DMA in OMAP NAND driver */ }; -static struct resource overo_nand_resource = { - .flags = IORESOURCE_MEM, -}; - -static struct platform_device overo_nand_device = { - .name = "omap2-nand", - .id = -1, - .dev = { - .platform_data = &overo_nand_data, - }, - .num_resources = 1, - .resource = &overo_nand_resource, -}; - - static void __init overo_flash_init(void) { u8 cs = 0; u8 nandcs = GPMC_CS_NUM + 1; - u32 gpmc_base_add = OMAP34XX_GPMC_VIRT; - /* find out the chip-select on which NAND exists */ while (cs < GPMC_CS_NUM) { u32 ret = 0; @@ -274,12 +293,9 @@ static void __init overo_flash_init(void) if (nandcs < GPMC_CS_NUM) { overo_nand_data.cs = nandcs; - overo_nand_data.gpmc_cs_baseaddr = (void *) - (gpmc_base_add + GPMC_CS0_BASE + nandcs * GPMC_CS_SIZE); - overo_nand_data.gpmc_baseaddr = (void *) (gpmc_base_add); printk(KERN_INFO "Registering NAND on CS%d\n", nandcs); - if (platform_device_register(&overo_nand_device) < 0) + if (gpmc_nand_init(&overo_nand_data) < 0) printk(KERN_ERR "Unable to register NAND device\n"); } } @@ -484,17 +500,11 @@ static void __init overo_init(void) "OVERO_GPIO_USBH_CPEN\n"); } -static void __init overo_map_io(void) -{ - omap2_set_globals_343x(); - omap34xx_map_common_io(); -} - MACHINE_START(OVERO, "Gumstix Overo") .phys_io = 0x48000000, .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, .boot_params = 0x80000100, - .map_io = overo_map_io, + .map_io = omap3_map_io, .reserve = omap_reserve, .init_irq = overo_init_irq, .init_machine = overo_init, diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c index 03483920ed6..9a5eb87425f 100644 --- a/arch/arm/mach-omap2/board-rx51-peripherals.c +++ b/arch/arm/mach-omap2/board-rx51-peripherals.c @@ -25,7 +25,6 @@ #include <linux/mmc/host.h> #include <plat/mcspi.h> -#include <plat/mux.h> #include <plat/board.h> #include <plat/common.h> #include <plat/dma.h> @@ -33,6 +32,11 @@ #include <plat/onenand.h> #include <plat/gpmc-smc91x.h> +#include <sound/tlv320aic3x.h> +#include <sound/tpa6130a2-plat.h> + +#include <../drivers/staging/iio/light/tsl2563.h> + #include "mux.h" #include "hsmmc.h" @@ -51,6 +55,12 @@ enum { static struct wl12xx_platform_data wl1251_pdata; +#if defined(CONFIG_SENSORS_TSL2563) || defined(CONFIG_SENSORS_TSL2563_MODULE) +static struct tsl2563_platform_data rx51_tsl2563_platform_data = { + .cover_comp_gain = 16, +}; +#endif + static struct omap2_mcspi_device_config wl1251_mcspi_config = { .turbo_mode = 0, .single_channel = 1, @@ -311,48 +321,29 @@ static struct omap2_hsmmc_info mmc[] __initdata = { {} /* Terminator */ }; -static struct regulator_consumer_supply rx51_vmmc1_supply = { - .supply = "vmmc", - .dev_name = "mmci-omap-hs.0", -}; +static struct regulator_consumer_supply rx51_vmmc1_supply = + REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0"); -static struct regulator_consumer_supply rx51_vaux3_supply = { - .supply = "vmmc", - .dev_name = "mmci-omap-hs.1", -}; +static struct regulator_consumer_supply rx51_vaux3_supply = + REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"); -static struct regulator_consumer_supply rx51_vsim_supply = { - .supply = "vmmc_aux", - .dev_name = "mmci-omap-hs.1", -}; +static struct regulator_consumer_supply rx51_vsim_supply = + REGULATOR_SUPPLY("vmmc_aux", "mmci-omap-hs.1"); static struct regulator_consumer_supply rx51_vmmc2_supplies[] = { /* tlv320aic3x analog supplies */ - { - .supply = "AVDD", - .dev_name = "2-0018", - }, - { - .supply = "DRVDD", - .dev_name = "2-0018", - }, + REGULATOR_SUPPLY("AVDD", "2-0018"), + REGULATOR_SUPPLY("DRVDD", "2-0018"), + /* tpa6130a2 */ + REGULATOR_SUPPLY("Vdd", "2-0060"), /* Keep vmmc as last item. It is not iterated for newer boards */ - { - .supply = "vmmc", - .dev_name = "mmci-omap-hs.1", - }, + REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"), }; static struct regulator_consumer_supply rx51_vio_supplies[] = { /* tlv320aic3x digital supplies */ - { - .supply = "IOVDD", - .dev_name = "2-0018" - }, - { - .supply = "DVDD", - .dev_name = "2-0018" - }, + REGULATOR_SUPPLY("IOVDD", "2-0018"), + REGULATOR_SUPPLY("DVDD", "2-0018"), }; #if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE) @@ -373,6 +364,7 @@ static struct regulator_init_data rx51_vaux1 = { .name = "V28", .min_uV = 2800000, .max_uV = 2800000, + .always_on = true, /* due battery cover sensor */ .valid_modes_mask = REGULATOR_MODE_NORMAL | REGULATOR_MODE_STANDBY, .valid_ops_mask = REGULATOR_CHANGE_MODE @@ -718,6 +710,15 @@ static struct twl4030_platform_data rx51_twldata __initdata = { .vio = &rx51_vio, }; +static struct aic3x_pdata rx51_aic3x_data __initdata = { + .gpio_reset = 60, +}; + +static struct tpa6130a2_platform_data rx51_tpa6130a2_data __initdata = { + .id = TPA6130A2, + .power_gpio = 98, +}; + static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_1[] = { { I2C_BOARD_INFO("twl5030", 0x48), @@ -730,7 +731,18 @@ static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_1[] = { static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_2[] = { { I2C_BOARD_INFO("tlv320aic3x", 0x18), + .platform_data = &rx51_aic3x_data, + }, +#if defined(CONFIG_SENSORS_TSL2563) || defined(CONFIG_SENSORS_TSL2563_MODULE) + { + I2C_BOARD_INFO("tsl2563", 0x29), + .platform_data = &rx51_tsl2563_platform_data, }, +#endif + { + I2C_BOARD_INFO("tpa6130a2", 0x60), + .platform_data = &rx51_tpa6130a2_data, + } }; static int __init rx51_i2c_init(void) diff --git a/arch/arm/mach-omap2/board-rx51-video.c b/arch/arm/mach-omap2/board-rx51-video.c index b743a4f4264..5a1005ba981 100644 --- a/arch/arm/mach-omap2/board-rx51-video.c +++ b/arch/arm/mach-omap2/board-rx51-video.c @@ -16,7 +16,6 @@ #include <linux/mm.h> #include <asm/mach-types.h> -#include <plat/mux.h> #include <plat/display.h> #include <plat/vram.h> #include <plat/mcspi.h> diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c index 3bd956f9e19..a58e8cb1a7f 100644 --- a/arch/arm/mach-omap2/board-rx51.c +++ b/arch/arm/mach-omap2/board-rx51.c @@ -143,7 +143,7 @@ static void __init rx51_init(void) static void __init rx51_map_io(void) { - omap2_set_globals_343x(); + omap2_set_globals_3xxx(); rx51_video_mem_init(); omap34xx_map_common_io(); } diff --git a/arch/arm/mach-omap2/board-zoom2.c b/arch/arm/mach-omap2/board-zoom2.c index ffe188cb18e..3ad9ecf7f5e 100644 --- a/arch/arm/mach-omap2/board-zoom2.c +++ b/arch/arm/mach-omap2/board-zoom2.c @@ -71,30 +71,80 @@ static struct twl4030_platform_data zoom2_twldata = { #ifdef CONFIG_OMAP_MUX static struct omap_board_mux board_mux[] __initdata = { + /* WLAN IRQ - GPIO 162 */ + OMAP3_MUX(MCBSP1_CLKX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP), + /* WLAN POWER ENABLE - GPIO 101 */ + OMAP3_MUX(CAM_D2, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), + /* WLAN SDIO: MMC3 CMD */ + OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE3 | OMAP_PIN_INPUT_PULLUP), + /* WLAN SDIO: MMC3 CLK */ + OMAP3_MUX(ETK_CLK, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), + /* WLAN SDIO: MMC3 DAT[0-3] */ + OMAP3_MUX(ETK_D3, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), + OMAP3_MUX(ETK_D4, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), + OMAP3_MUX(ETK_D5, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), + OMAP3_MUX(ETK_D6, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), { .reg_offset = OMAP_MUX_TERMINATOR }, }; #else #define board_mux NULL #endif +static struct mtd_partition zoom_nand_partitions[] = { + /* All the partition sizes are listed in terms of NAND block size */ + { + .name = "X-Loader-NAND", + .offset = 0, + .size = 4 * (64 * 2048), /* 512KB, 0x80000 */ + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, + { + .name = "U-Boot-NAND", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */ + .size = 10 * (64 * 2048), /* 1.25MB, 0x140000 */ + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, + { + .name = "Boot Env-NAND", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x1c0000 */ + .size = 2 * (64 * 2048), /* 256KB, 0x40000 */ + }, + { + .name = "Kernel-NAND", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x0200000*/ + .size = 240 * (64 * 2048), /* 30M, 0x1E00000 */ + }, + { + .name = "system", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x2000000 */ + .size = 3328 * (64 * 2048), /* 416M, 0x1A000000 */ + }, + { + .name = "userdata", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x1C000000*/ + .size = 256 * (64 * 2048), /* 32M, 0x2000000 */ + }, + { + .name = "cache", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x1E000000*/ + .size = 256 * (64 * 2048), /* 32M, 0x2000000 */ + }, +}; + static void __init omap_zoom2_init(void) { omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); zoom_peripherals_init(); + board_nand_init(zoom_nand_partitions, + ARRAY_SIZE(zoom_nand_partitions), ZOOM_NAND_CS); zoom_debugboard_init(); } -static void __init omap_zoom2_map_io(void) -{ - omap2_set_globals_343x(); - omap34xx_map_common_io(); -} - MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board") .phys_io = ZOOM_UART_BASE, .io_pg_offst = (ZOOM_UART_VIRT >> 18) & 0xfffc, .boot_params = 0x80000100, - .map_io = omap_zoom2_map_io, + .map_io = omap3_map_io, .reserve = omap_reserve, .init_irq = omap_zoom2_init_irq, .init_machine = omap_zoom2_init, diff --git a/arch/arm/mach-omap2/board-zoom3.c b/arch/arm/mach-omap2/board-zoom3.c index 5b605eba3e7..6ca0b834161 100644 --- a/arch/arm/mach-omap2/board-zoom3.c +++ b/arch/arm/mach-omap2/board-zoom3.c @@ -25,15 +25,50 @@ #include "mux.h" #include "sdram-hynix-h8mbx00u0mer-0em.h" -static void __init omap_zoom_map_io(void) -{ - omap2_set_globals_36xx(); - omap34xx_map_common_io(); -} - static struct omap_board_config_kernel zoom_config[] __initdata = { }; +static struct mtd_partition zoom_nand_partitions[] = { + /* All the partition sizes are listed in terms of NAND block size */ + { + .name = "X-Loader-NAND", + .offset = 0, + .size = 4 * (64 * 2048), /* 512KB, 0x80000 */ + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, + { + .name = "U-Boot-NAND", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */ + .size = 10 * (64 * 2048), /* 1.25MB, 0x140000 */ + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, + { + .name = "Boot Env-NAND", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x1c0000 */ + .size = 2 * (64 * 2048), /* 256KB, 0x40000 */ + }, + { + .name = "Kernel-NAND", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x0200000*/ + .size = 240 * (64 * 2048), /* 30M, 0x1E00000 */ + }, + { + .name = "system", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x2000000 */ + .size = 3328 * (64 * 2048), /* 416M, 0x1A000000 */ + }, + { + .name = "userdata", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x1C000000*/ + .size = 256 * (64 * 2048), /* 32M, 0x2000000 */ + }, + { + .name = "cache", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x1E000000*/ + .size = 256 * (64 * 2048), /* 32M, 0x2000000 */ + }, +}; + static void __init omap_zoom_init_irq(void) { omap_board_config = zoom_config; @@ -46,6 +81,19 @@ static void __init omap_zoom_init_irq(void) #ifdef CONFIG_OMAP_MUX static struct omap_board_mux board_mux[] __initdata = { + /* WLAN IRQ - GPIO 162 */ + OMAP3_MUX(MCBSP1_CLKX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP), + /* WLAN POWER ENABLE - GPIO 101 */ + OMAP3_MUX(CAM_D2, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), + /* WLAN SDIO: MMC3 CMD */ + OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE3 | OMAP_PIN_INPUT_PULLUP), + /* WLAN SDIO: MMC3 CLK */ + OMAP3_MUX(ETK_CLK, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), + /* WLAN SDIO: MMC3 DAT[0-3] */ + OMAP3_MUX(ETK_D3, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), + OMAP3_MUX(ETK_D4, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), + OMAP3_MUX(ETK_D5, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), + OMAP3_MUX(ETK_D6, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), { .reg_offset = OMAP_MUX_TERMINATOR }, }; #else @@ -66,6 +114,8 @@ static void __init omap_zoom_init(void) { omap3_mux_init(board_mux, OMAP_PACKAGE_CBP); zoom_peripherals_init(); + board_nand_init(zoom_nand_partitions, + ARRAY_SIZE(zoom_nand_partitions), ZOOM_NAND_CS); zoom_debugboard_init(); omap_mux_init_gpio(64, OMAP_PIN_OUTPUT); @@ -76,7 +126,7 @@ MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board") .phys_io = ZOOM_UART_BASE, .io_pg_offst = (ZOOM_UART_VIRT >> 18) & 0xfffc, .boot_params = 0x80000100, - .map_io = omap_zoom_map_io, + .map_io = omap3_map_io, .reserve = omap_reserve, .init_irq = omap_zoom_init_irq, .init_machine = omap_zoom_init, diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index d33744117ce..138646deac8 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c @@ -1408,7 +1408,7 @@ static struct clk ts_fck = { static struct clk usbtll_fck = { .name = "usbtll_fck", - .ops = &clkops_omap2_dflt, + .ops = &clkops_omap2_dflt_wait, .parent = &dpll5_m2_ck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, diff --git a/arch/arm/mach-omap2/cm.c b/arch/arm/mach-omap2/cm.c index 2d83565d2be..721c3b66740 100644 --- a/arch/arm/mach-omap2/cm.c +++ b/arch/arm/mach-omap2/cm.c @@ -50,15 +50,15 @@ int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift) cm_idlest_reg = cm_idlest_offs[idlest_id - 1]; + mask = 1 << idlest_shift; + if (cpu_is_omap24xx()) - ena = idlest_shift; + ena = mask; else if (cpu_is_omap34xx()) ena = 0; else BUG(); - mask = 1 << idlest_shift; - /* XXX should be OMAP2 CM */ omap_test_timeout(((cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) == ena), MAX_MODULE_READY_TIME, i); diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 03e6c9ed82a..2dbb265bedd 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -25,7 +25,6 @@ #include <plat/control.h> #include <plat/tc.h> #include <plat/board.h> -#include <plat/mux.h> #include <mach/gpio.h> #include <plat/mmc.h> #include <plat/dma.h> @@ -153,10 +152,12 @@ static struct resource omap2_mbox_resources[] = { { .start = INT_24XX_MAIL_U0_MPU, .flags = IORESOURCE_IRQ, + .name = "dsp", }, { .start = INT_24XX_MAIL_U3_MPU, .flags = IORESOURCE_IRQ, + .name = "iva", }, }; static int omap2_mbox_resources_sz = ARRAY_SIZE(omap2_mbox_resources); @@ -175,6 +176,7 @@ static struct resource omap3_mbox_resources[] = { { .start = INT_24XX_MAIL_U0_MPU, .flags = IORESOURCE_IRQ, + .name = "dsp", }, }; static int omap3_mbox_resources_sz = ARRAY_SIZE(omap3_mbox_resources); @@ -196,6 +198,7 @@ static struct resource omap4_mbox_resources[] = { { .start = OMAP44XX_IRQ_MAIL_U0, .flags = IORESOURCE_IRQ, + .name = "mbox", }, }; static int omap4_mbox_resources_sz = ARRAY_SIZE(omap4_mbox_resources); @@ -205,7 +208,7 @@ static int omap4_mbox_resources_sz = ARRAY_SIZE(omap4_mbox_resources); #endif static struct platform_device mbox_device = { - .name = "omap2-mailbox", + .name = "omap-mailbox", .id = -1, }; @@ -230,64 +233,7 @@ static inline void omap_init_mbox(void) static inline void omap_init_mbox(void) { } #endif /* CONFIG_OMAP_MBOX_FWK */ -#if defined(CONFIG_OMAP_STI) - -#if defined(CONFIG_ARCH_OMAP2) - -#define OMAP2_STI_BASE 0x48068000 -#define OMAP2_STI_CHANNEL_BASE 0x54000000 -#define OMAP2_STI_IRQ 4 - -static struct resource sti_resources[] = { - { - .start = OMAP2_STI_BASE, - .end = OMAP2_STI_BASE + 0x7ff, - .flags = IORESOURCE_MEM, - }, - { - .start = OMAP2_STI_CHANNEL_BASE, - .end = OMAP2_STI_CHANNEL_BASE + SZ_64K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = OMAP2_STI_IRQ, - .flags = IORESOURCE_IRQ, - } -}; -#elif defined(CONFIG_ARCH_OMAP3) - -#define OMAP3_SDTI_BASE 0x54500000 -#define OMAP3_SDTI_CHANNEL_BASE 0x54600000 - -static struct resource sti_resources[] = { - { - .start = OMAP3_SDTI_BASE, - .end = OMAP3_SDTI_BASE + 0xFFF, - .flags = IORESOURCE_MEM, - }, - { - .start = OMAP3_SDTI_CHANNEL_BASE, - .end = OMAP3_SDTI_CHANNEL_BASE + SZ_1M - 1, - .flags = IORESOURCE_MEM, - } -}; - -#endif - -static struct platform_device sti_device = { - .name = "sti", - .id = -1, - .num_resources = ARRAY_SIZE(sti_resources), - .resource = sti_resources, -}; - -static inline void omap_init_sti(void) -{ - platform_device_register(&sti_device); -} -#else static inline void omap_init_sti(void) {} -#endif #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE) @@ -672,19 +618,19 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller, OMAP_PIN_INPUT_PULLUP); if (cpu_is_omap2420() && controller_nr == 0) { - omap_cfg_reg(H18_24XX_MMC_CMD); - omap_cfg_reg(H15_24XX_MMC_CLKI); - omap_cfg_reg(G19_24XX_MMC_CLKO); - omap_cfg_reg(F20_24XX_MMC_DAT0); - omap_cfg_reg(F19_24XX_MMC_DAT_DIR0); - omap_cfg_reg(G18_24XX_MMC_CMD_DIR); + omap_mux_init_signal("sdmmc_cmd", 0); + omap_mux_init_signal("sdmmc_clki", 0); + omap_mux_init_signal("sdmmc_clko", 0); + omap_mux_init_signal("sdmmc_dat0", 0); + omap_mux_init_signal("sdmmc_dat_dir0", 0); + omap_mux_init_signal("sdmmc_cmd_dir", 0); if (mmc_controller->slots[0].wires == 4) { - omap_cfg_reg(H14_24XX_MMC_DAT1); - omap_cfg_reg(E19_24XX_MMC_DAT2); - omap_cfg_reg(D19_24XX_MMC_DAT3); - omap_cfg_reg(E20_24XX_MMC_DAT_DIR1); - omap_cfg_reg(F18_24XX_MMC_DAT_DIR2); - omap_cfg_reg(E18_24XX_MMC_DAT_DIR3); + omap_mux_init_signal("sdmmc_dat1", 0); + omap_mux_init_signal("sdmmc_dat2", 0); + omap_mux_init_signal("sdmmc_dat3", 0); + omap_mux_init_signal("sdmmc_dat_dir1", 0); + omap_mux_init_signal("sdmmc_dat_dir2", 0); + omap_mux_init_signal("sdmmc_dat_dir3", 0); } /* diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c index e57fb29ff85..72220960192 100644 --- a/arch/arm/mach-omap2/gpmc-nand.c +++ b/arch/arm/mach-omap2/gpmc-nand.c @@ -19,8 +19,6 @@ #include <plat/board.h> #include <plat/gpmc.h> -#define WR_RD_PIN_MONITORING 0x00600000 - static struct omap_nand_platform_data *gpmc_nand_data; static struct resource gpmc_nand_resource = { @@ -71,10 +69,10 @@ static int omap2_nand_gpmc_retime(void) t.wr_cycle = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->wr_cycle); /* Configure GPMC */ - gpmc_cs_write_reg(gpmc_nand_data->cs, GPMC_CS_CONFIG1, - GPMC_CONFIG1_DEVICESIZE(gpmc_nand_data->devsize) | - GPMC_CONFIG1_DEVICETYPE_NAND); - + gpmc_cs_configure(gpmc_nand_data->cs, + GPMC_CONFIG_DEV_SIZE, gpmc_nand_data->devsize); + gpmc_cs_configure(gpmc_nand_data->cs, + GPMC_CONFIG_DEV_TYPE, GPMC_DEVICETYPE_NAND); err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t); if (err) return err; @@ -82,27 +80,13 @@ static int omap2_nand_gpmc_retime(void) return 0; } -static int gpmc_nand_setup(void) -{ - struct device *dev = &gpmc_nand_device.dev; - - /* Set timings in GPMC */ - if (omap2_nand_gpmc_retime() < 0) { - dev_err(dev, "Unable to set gpmc timings\n"); - return -EINVAL; - } - - return 0; -} - int __init gpmc_nand_init(struct omap_nand_platform_data *_nand_data) { - unsigned int val; int err = 0; struct device *dev = &gpmc_nand_device.dev; gpmc_nand_data = _nand_data; - gpmc_nand_data->nand_setup = gpmc_nand_setup; + gpmc_nand_data->nand_setup = omap2_nand_gpmc_retime; gpmc_nand_device.dev.platform_data = gpmc_nand_data; err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE, @@ -112,19 +96,16 @@ int __init gpmc_nand_init(struct omap_nand_platform_data *_nand_data) return err; } - err = gpmc_nand_setup(); + /* Set timings in GPMC */ + err = omap2_nand_gpmc_retime(); if (err < 0) { - dev_err(dev, "NAND platform setup failed: %d\n", err); + dev_err(dev, "Unable to set gpmc timings: %d\n", err); return err; } /* Enable RD PIN Monitoring Reg */ if (gpmc_nand_data->dev_ready) { - val = gpmc_cs_read_reg(gpmc_nand_data->cs, - GPMC_CS_CONFIG1); - val |= WR_RD_PIN_MONITORING; - gpmc_cs_write_reg(gpmc_nand_data->cs, - GPMC_CS_CONFIG1, val); + gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_RDY_BSY, 1); } err = platform_device_register(&gpmc_nand_device); diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index 5bc3ca03551..f46933bc937 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@ -46,8 +46,9 @@ #define GPMC_ECC_CONFIG 0x1f4 #define GPMC_ECC_CONTROL 0x1f8 #define GPMC_ECC_SIZE_CONFIG 0x1fc +#define GPMC_ECC1_RESULT 0x200 -#define GPMC_CS0 0x60 +#define GPMC_CS0_OFFSET 0x60 #define GPMC_CS_SIZE 0x30 #define GPMC_MEM_START 0x00000000 @@ -92,7 +93,8 @@ struct omap3_gpmc_regs { static struct resource gpmc_mem_root; static struct resource gpmc_cs_mem[GPMC_CS_NUM]; static DEFINE_SPINLOCK(gpmc_mem_lock); -static unsigned gpmc_cs_map; +static unsigned int gpmc_cs_map; /* flag for cs which are initialized */ +static int gpmc_ecc_used = -EINVAL; /* cs using ecc engine */ static void __iomem *gpmc_base; @@ -108,11 +110,27 @@ static u32 gpmc_read_reg(int idx) return __raw_readl(gpmc_base + idx); } +static void gpmc_cs_write_byte(int cs, int idx, u8 val) +{ + void __iomem *reg_addr; + + reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; + __raw_writeb(val, reg_addr); +} + +static u8 gpmc_cs_read_byte(int cs, int idx) +{ + void __iomem *reg_addr; + + reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; + return __raw_readb(reg_addr); +} + void gpmc_cs_write_reg(int cs, int idx, u32 val) { void __iomem *reg_addr; - reg_addr = gpmc_base + GPMC_CS0 + (cs * GPMC_CS_SIZE) + idx; + reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; __raw_writel(val, reg_addr); } @@ -120,7 +138,7 @@ u32 gpmc_cs_read_reg(int cs, int idx) { void __iomem *reg_addr; - reg_addr = gpmc_base + GPMC_CS0 + (cs * GPMC_CS_SIZE) + idx; + reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; return __raw_readl(reg_addr); } @@ -419,8 +437,157 @@ void gpmc_cs_free(int cs) EXPORT_SYMBOL(gpmc_cs_free); /** + * gpmc_read_status - read access request to get the different gpmc status + * @cmd: command type + * @return status + */ +int gpmc_read_status(int cmd) +{ + int status = -EINVAL; + u32 regval = 0; + + switch (cmd) { + case GPMC_GET_IRQ_STATUS: + status = gpmc_read_reg(GPMC_IRQSTATUS); + break; + + case GPMC_PREFETCH_FIFO_CNT: + regval = gpmc_read_reg(GPMC_PREFETCH_STATUS); + status = GPMC_PREFETCH_STATUS_FIFO_CNT(regval); + break; + + case GPMC_PREFETCH_COUNT: + regval = gpmc_read_reg(GPMC_PREFETCH_STATUS); + status = GPMC_PREFETCH_STATUS_COUNT(regval); + break; + + case GPMC_STATUS_BUFFER: + regval = gpmc_read_reg(GPMC_STATUS); + /* 1 : buffer is available to write */ + status = regval & GPMC_STATUS_BUFF_EMPTY; + break; + + default: + printk(KERN_ERR "gpmc_read_status: Not supported\n"); + } + return status; +} +EXPORT_SYMBOL(gpmc_read_status); + +/** + * gpmc_cs_configure - write request to configure gpmc + * @cs: chip select number + * @cmd: command type + * @wval: value to write + * @return status of the operation + */ +int gpmc_cs_configure(int cs, int cmd, int wval) +{ + int err = 0; + u32 regval = 0; + + switch (cmd) { + case GPMC_SET_IRQ_STATUS: + gpmc_write_reg(GPMC_IRQSTATUS, wval); + break; + + case GPMC_CONFIG_WP: + regval = gpmc_read_reg(GPMC_CONFIG); + if (wval) + regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */ + else + regval |= GPMC_CONFIG_WRITEPROTECT; /* WP is OFF */ + gpmc_write_reg(GPMC_CONFIG, regval); + break; + + case GPMC_CONFIG_RDY_BSY: + regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); + if (wval) + regval |= WR_RD_PIN_MONITORING; + else + regval &= ~WR_RD_PIN_MONITORING; + gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval); + break; + + case GPMC_CONFIG_DEV_SIZE: + regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); + regval |= GPMC_CONFIG1_DEVICESIZE(wval); + gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval); + break; + + case GPMC_CONFIG_DEV_TYPE: + regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); + regval |= GPMC_CONFIG1_DEVICETYPE(wval); + if (wval == GPMC_DEVICETYPE_NOR) + regval |= GPMC_CONFIG1_MUXADDDATA; + gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval); + break; + + default: + printk(KERN_ERR "gpmc_configure_cs: Not supported\n"); + err = -EINVAL; + } + + return err; +} +EXPORT_SYMBOL(gpmc_cs_configure); + +/** + * gpmc_nand_read - nand specific read access request + * @cs: chip select number + * @cmd: command type + */ +int gpmc_nand_read(int cs, int cmd) +{ + int rval = -EINVAL; + + switch (cmd) { + case GPMC_NAND_DATA: + rval = gpmc_cs_read_byte(cs, GPMC_CS_NAND_DATA); + break; + + default: + printk(KERN_ERR "gpmc_read_nand_ctrl: Not supported\n"); + } + return rval; +} +EXPORT_SYMBOL(gpmc_nand_read); + +/** + * gpmc_nand_write - nand specific write request + * @cs: chip select number + * @cmd: command type + * @wval: value to write + */ +int gpmc_nand_write(int cs, int cmd, int wval) +{ + int err = 0; + + switch (cmd) { + case GPMC_NAND_COMMAND: + gpmc_cs_write_byte(cs, GPMC_CS_NAND_COMMAND, wval); + break; + + case GPMC_NAND_ADDRESS: + gpmc_cs_write_byte(cs, GPMC_CS_NAND_ADDRESS, wval); + break; + + case GPMC_NAND_DATA: + gpmc_cs_write_byte(cs, GPMC_CS_NAND_DATA, wval); + + default: + printk(KERN_ERR "gpmc_write_nand_ctrl: Not supported\n"); + err = -EINVAL; + } + return err; +} +EXPORT_SYMBOL(gpmc_nand_write); + + + +/** * gpmc_prefetch_enable - configures and starts prefetch transfer - * @cs: nand cs (chip select) number + * @cs: cs (chip select) number * @dma_mode: dma mode enable (1) or disable (0) * @u32_count: number of bytes to be transferred * @is_write: prefetch read(0) or write post(1) mode @@ -428,7 +595,6 @@ EXPORT_SYMBOL(gpmc_cs_free); int gpmc_prefetch_enable(int cs, int dma_mode, unsigned int u32_count, int is_write) { - uint32_t prefetch_config1; if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) { /* Set the amount of bytes to be prefetched */ @@ -437,17 +603,17 @@ int gpmc_prefetch_enable(int cs, int dma_mode, /* Set dma/mpu mode, the prefetch read / post write and * enable the engine. Set which cs is has requested for. */ - prefetch_config1 = ((cs << CS_NUM_SHIFT) | + gpmc_write_reg(GPMC_PREFETCH_CONFIG1, ((cs << CS_NUM_SHIFT) | PREFETCH_FIFOTHRESHOLD | ENABLE_PREFETCH | (dma_mode << DMA_MPU_MODE) | - (0x1 & is_write)); - gpmc_write_reg(GPMC_PREFETCH_CONFIG1, prefetch_config1); + (0x1 & is_write))); + + /* Start the prefetch engine */ + gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x1); } else { return -EBUSY; } - /* Start the prefetch engine */ - gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x1); return 0; } @@ -456,24 +622,24 @@ EXPORT_SYMBOL(gpmc_prefetch_enable); /** * gpmc_prefetch_reset - disables and stops the prefetch engine */ -void gpmc_prefetch_reset(void) +int gpmc_prefetch_reset(int cs) { + u32 config1; + + /* check if the same module/cs is trying to reset */ + config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1); + if (((config1 >> CS_NUM_SHIFT) & 0x7) != cs) + return -EINVAL; + /* Stop the PFPW engine */ gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x0); /* Reset/disable the PFPW engine */ gpmc_write_reg(GPMC_PREFETCH_CONFIG1, 0x0); -} -EXPORT_SYMBOL(gpmc_prefetch_reset); -/** - * gpmc_prefetch_status - reads prefetch status of engine - */ -int gpmc_prefetch_status(void) -{ - return gpmc_read_reg(GPMC_PREFETCH_STATUS); + return 0; } -EXPORT_SYMBOL(gpmc_prefetch_status); +EXPORT_SYMBOL(gpmc_prefetch_reset); static void __init gpmc_mem_init(void) { @@ -615,3 +781,79 @@ void omap3_gpmc_restore_context(void) } } #endif /* CONFIG_ARCH_OMAP3 */ + +/** + * gpmc_enable_hwecc - enable hardware ecc functionality + * @cs: chip select number + * @mode: read/write mode + * @dev_width: device bus width(1 for x16, 0 for x8) + * @ecc_size: bytes for which ECC will be generated + */ +int gpmc_enable_hwecc(int cs, int mode, int dev_width, int ecc_size) +{ + unsigned int val; + + /* check if ecc module is in used */ + if (gpmc_ecc_used != -EINVAL) + return -EINVAL; + + gpmc_ecc_used = cs; + + /* clear ecc and enable bits */ + val = ((0x00000001<<8) | 0x00000001); + gpmc_write_reg(GPMC_ECC_CONTROL, val); + + /* program ecc and result sizes */ + val = ((((ecc_size >> 1) - 1) << 22) | (0x0000000F)); + gpmc_write_reg(GPMC_ECC_SIZE_CONFIG, val); + + switch (mode) { + case GPMC_ECC_READ: + gpmc_write_reg(GPMC_ECC_CONTROL, 0x101); + break; + case GPMC_ECC_READSYN: + gpmc_write_reg(GPMC_ECC_CONTROL, 0x100); + break; + case GPMC_ECC_WRITE: + gpmc_write_reg(GPMC_ECC_CONTROL, 0x101); + break; + default: + printk(KERN_INFO "Error: Unrecognized Mode[%d]!\n", mode); + break; + } + + /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */ + val = (dev_width << 7) | (cs << 1) | (0x1); + gpmc_write_reg(GPMC_ECC_CONFIG, val); + return 0; +} + +/** + * gpmc_calculate_ecc - generate non-inverted ecc bytes + * @cs: chip select number + * @dat: data pointer over which ecc is computed + * @ecc_code: ecc code buffer + * + * Using non-inverted ECC is considered ugly since writing a blank + * page (padding) will clear the ECC bytes. This is not a problem as long + * no one is trying to write data on the seemingly unused page. Reading + * an erased page will produce an ECC mismatch between generated and read + * ECC bytes that has to be dealt with separately. + */ +int gpmc_calculate_ecc(int cs, const u_char *dat, u_char *ecc_code) +{ + unsigned int val = 0x0; + + if (gpmc_ecc_used != cs) + return -EINVAL; + + /* read ecc result */ + val = gpmc_read_reg(GPMC_ECC1_RESULT); + *ecc_code++ = val; /* P128e, ..., P1e */ + *ecc_code++ = val >> 16; /* P128o, ..., P1o */ + /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */ + *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0); + + gpmc_ecc_used = -EINVAL; + return 0; +} diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c index 1ef54b03610..c8f647b6205 100644 --- a/arch/arm/mach-omap2/hsmmc.c +++ b/arch/arm/mach-omap2/hsmmc.c @@ -268,6 +268,7 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) mmc->slots[0].gpio_wp = c->gpio_wp; mmc->slots[0].remux = c->remux; + mmc->slots[0].init_card = c->init_card; if (c->cover_only) mmc->slots[0].cover = 1; diff --git a/arch/arm/mach-omap2/hsmmc.h b/arch/arm/mach-omap2/hsmmc.h index 36f0ba8d89e..1fe6f018717 100644 --- a/arch/arm/mach-omap2/hsmmc.h +++ b/arch/arm/mach-omap2/hsmmc.h @@ -6,6 +6,8 @@ * published by the Free Software Foundation. */ +struct mmc_card; + struct omap2_hsmmc_info { u8 mmc; /* controller 1/2/3 */ u8 wires; /* 1/4/8 wires */ @@ -23,6 +25,8 @@ struct omap2_hsmmc_info { int ocr_mask; /* temporary HACK */ /* Remux (pad configuation) when powering on/off */ void (*remux)(struct device *dev, int slot, int power_on); + /* init some special card */ + void (*init_card)(struct mmc_card *card); }; #if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) diff --git a/arch/arm/mach-omap2/i2c.c b/arch/arm/mach-omap2/i2c.c index 7951ae1447e..79c478c4cb1 100644 --- a/arch/arm/mach-omap2/i2c.c +++ b/arch/arm/mach-omap2/i2c.c @@ -21,32 +21,19 @@ #include <plat/cpu.h> #include <plat/i2c.h> -#include <plat/mux.h> #include "mux.h" void __init omap2_i2c_mux_pins(int bus_id) { - if (cpu_is_omap24xx()) { - const int omap24xx_pins[][2] = { - { M19_24XX_I2C1_SCL, L15_24XX_I2C1_SDA }, - { J15_24XX_I2C2_SCL, H19_24XX_I2C2_SDA }, - }; - int scl, sda; - - scl = omap24xx_pins[bus_id - 1][0]; - sda = omap24xx_pins[bus_id - 1][1]; - omap_cfg_reg(sda); - omap_cfg_reg(scl); - } + char mux_name[sizeof("i2c2_scl.i2c2_scl")]; /* First I2C bus is not muxable */ - if (cpu_is_omap34xx() && bus_id > 1) { - char mux_name[sizeof("i2c2_scl.i2c2_scl")]; + if (bus_id == 1) + return; - sprintf(mux_name, "i2c%i_scl.i2c%i_scl", bus_id, bus_id); - omap_mux_init_signal(mux_name, OMAP_PIN_INPUT); - sprintf(mux_name, "i2c%i_sda.i2c%i_sda", bus_id, bus_id); - omap_mux_init_signal(mux_name, OMAP_PIN_INPUT); - } + sprintf(mux_name, "i2c%i_scl.i2c%i_scl", bus_id, bus_id); + omap_mux_init_signal(mux_name, OMAP_PIN_INPUT); + sprintf(mux_name, "i2c%i_sda.i2c%i_sda", bus_id, bus_id); + omap_mux_init_signal(mux_name, OMAP_PIN_INPUT); } diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index 37b8a1a4adf..e8256a2ed8e 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -25,6 +25,8 @@ #include <plat/control.h> #include <plat/cpu.h> +#include <mach/id.h> + static struct omap_chip_id omap_chip; static unsigned int omap_revision; @@ -102,30 +104,36 @@ static struct omap_id omap_ids[] __initdata = { static void __iomem *tap_base; static u16 tap_prod_id; -void __init omap24xx_check_revision(void) +void omap_get_die_id(struct omap_die_id *odi) +{ + odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_0); + odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_1); + odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_2); + odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3); +} + +static void __init omap24xx_check_revision(void) { int i, j; u32 idcode, prod_id; u16 hawkeye; u8 dev_type, rev; + struct omap_die_id odi; idcode = read_tap_reg(OMAP_TAP_IDCODE); prod_id = read_tap_reg(tap_prod_id); hawkeye = (idcode >> 12) & 0xffff; rev = (idcode >> 28) & 0x0f; dev_type = (prod_id >> 16) & 0x0f; + omap_get_die_id(&odi); pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n", idcode, rev, hawkeye, (idcode >> 1) & 0x7ff); - pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", - read_tap_reg(OMAP_TAP_DIE_ID_0)); + pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", odi.id_0); pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n", - read_tap_reg(OMAP_TAP_DIE_ID_1), - (read_tap_reg(OMAP_TAP_DIE_ID_1) >> 28) & 0xf); - pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", - read_tap_reg(OMAP_TAP_DIE_ID_2)); - pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", - read_tap_reg(OMAP_TAP_DIE_ID_3)); + odi.id_1, (odi.id_1 >> 28) & 0xf); + pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", odi.id_2); + pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", odi.id_3); pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n", prod_id, dev_type); @@ -164,7 +172,7 @@ void __init omap24xx_check_revision(void) omap3_features |= OMAP3_HAS_ ##feat; \ } -void __init omap3_check_features(void) +static void __init omap3_check_features(void) { u32 status; @@ -179,6 +187,8 @@ void __init omap3_check_features(void) OMAP3_CHECK_FEATURE(status, ISP); if (cpu_is_omap3630()) omap3_features |= OMAP3_HAS_192MHZ_CLK; + if (!cpu_is_omap3505() && !cpu_is_omap3517()) + omap3_features |= OMAP3_HAS_IO_WAKEUP; /* * TODO: Get additional info (where applicable) @@ -186,7 +196,7 @@ void __init omap3_check_features(void) */ } -void __init omap3_check_revision(void) +static void __init omap3_check_revision(void) { u32 cpuid, idcode; u16 hawkeye; @@ -259,15 +269,31 @@ void __init omap3_check_revision(void) omap_chip.oc |= CHIP_IS_OMAP3430ES3_1; break; case 0xb891: - /* FALLTHROUGH */ + /* Handle 36xx devices */ + omap_chip.oc |= CHIP_IS_OMAP3630ES1; + + switch(rev) { + case 0: /* Take care of early samples */ + omap_revision = OMAP3630_REV_ES1_0; + break; + case 1: + omap_revision = OMAP3630_REV_ES1_1; + omap_chip.oc |= CHIP_IS_OMAP3630ES1_1; + break; + case 2: + default: + omap_revision = OMAP3630_REV_ES1_2; + omap_chip.oc |= CHIP_IS_OMAP3630ES1_2; + break; + } default: /* Unknown default to latest silicon rev as default*/ - omap_revision = OMAP3630_REV_ES1_0; - omap_chip.oc |= CHIP_IS_OMAP3630ES1; + omap_revision = OMAP3630_REV_ES1_2; + omap_chip.oc |= CHIP_IS_OMAP3630ES1_2; } } -void __init omap4_check_revision(void) +static void __init omap4_check_revision(void) { u32 idcode; u16 hawkeye; @@ -297,7 +323,7 @@ void __init omap4_check_revision(void) if (omap3_has_ ##feat()) \ printk(#feat" "); -void __init omap3_cpuinfo(void) +static void __init omap3_cpuinfo(void) { u8 rev = GET_OMAP_REVISION(); char cpu_name[16], cpu_rev[16]; @@ -339,6 +365,12 @@ void __init omap3_cpuinfo(void) case OMAP_REVBITS_00: strcpy(cpu_rev, "1.0"); break; + case OMAP_REVBITS_01: + strcpy(cpu_rev, "1.1"); + break; + case OMAP_REVBITS_02: + strcpy(cpu_rev, "1.2"); + break; case OMAP_REVBITS_10: strcpy(cpu_rev, "2.0"); break; diff --git a/arch/arm/mach-omap2/include/mach/board-sdp.h b/arch/arm/mach-omap2/include/mach/board-flash.h index 465169c0908..b2242ae2bb6 100644 --- a/arch/arm/mach-omap2/include/mach/board-sdp.h +++ b/arch/arm/mach-omap2/include/mach/board-flash.h @@ -12,10 +12,17 @@ */ #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> +#include <plat/gpmc.h> + +#define PDC_NOR 1 +#define PDC_NAND 2 +#define PDC_ONENAND 3 +#define DBG_MPDB 4 struct flash_partitions { struct mtd_partition *parts; int nr_parts; }; -extern void sdp_flash_init(struct flash_partitions []); +extern void board_flash_init(struct flash_partitions [], + char chip_sel[][GPMC_CS_NUM]); diff --git a/arch/arm/mach-omap2/include/mach/board-zoom.h b/arch/arm/mach-omap2/include/mach/board-zoom.h index c93b29e21b7..3af69d2c3dc 100644 --- a/arch/arm/mach-omap2/include/mach/board-zoom.h +++ b/arch/arm/mach-omap2/include/mach/board-zoom.h @@ -1,5 +1,11 @@ /* * Defines for zoom boards */ +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> + +#define ZOOM_NAND_CS 0 + +extern void __init board_nand_init(struct mtd_partition *, u8 nr_parts, u8 cs); extern int __init zoom_debugboard_init(void); extern void __init zoom_peripherals_init(void); diff --git a/arch/arm/mach-omap2/include/mach/debug-macro.S b/arch/arm/mach-omap2/include/mach/debug-macro.S index 35b24409a0c..09331bbbda5 100644 --- a/arch/arm/mach-omap2/include/mach/debug-macro.S +++ b/arch/arm/mach-omap2/include/mach/debug-macro.S @@ -36,7 +36,7 @@ omap_uart_lsr: .word 0 /* Use omap_uart_phys/virt if already configured */ 10: mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? - ldreq \rx, =omap_uart_phys @ physical base address + ldreq \rx, =__virt_to_phys(omap_uart_phys) @ physical base address ldrne \rx, =omap_uart_virt @ virtual base address ldr \rx, [\rx, #0] cmp \rx, #0 @ is port configured? @@ -89,26 +89,36 @@ omap_uart_lsr: .word 0 44: mov \rx, #UART_OFFSET(OMAP4_UART4_BASE) b 98f 95: ldr \rx, =ZOOM_UART_BASE - ldr \tmp, =omap_uart_phys + mrc p15, 0, \tmp, c1, c0 + tst \tmp, #1 @ MMU enabled? + ldreq \tmp, =__virt_to_phys(omap_uart_phys) + ldrne \tmp, =omap_uart_phys str \rx, [\tmp, #0] ldr \rx, =ZOOM_UART_VIRT - ldr \tmp, =omap_uart_virt + ldreq \tmp, =__virt_to_phys(omap_uart_virt) + ldrne \tmp, =omap_uart_virt str \rx, [\tmp, #0] mov \rx, #(UART_LSR << ZOOM_PORT_SHIFT) - ldr \tmp, =omap_uart_lsr + ldreq \tmp, =__virt_to_phys(omap_uart_lsr) + ldrne \tmp, =omap_uart_lsr str \rx, [\tmp, #0] b 10b /* Store both phys and virt address for the uart */ 98: add \rx, \rx, #0x48000000 @ phys base - ldr \tmp, =omap_uart_phys + mrc p15, 0, \tmp, c1, c0 + tst \tmp, #1 @ MMU enabled? + ldreq \tmp, =__virt_to_phys(omap_uart_phys) + ldrne \tmp, =omap_uart_phys str \rx, [\tmp, #0] sub \rx, \rx, #0x48000000 @ phys base add \rx, \rx, #0xfa000000 @ virt base - ldr \tmp, =omap_uart_virt + ldreq \tmp, =__virt_to_phys(omap_uart_virt) + ldrne \tmp, =omap_uart_virt str \rx, [\tmp, #0] mov \rx, #(UART_LSR << OMAP_PORT_SHIFT) - ldr \tmp, =omap_uart_lsr + ldreq \tmp, =__virt_to_phys(omap_uart_lsr) + ldrne \tmp, =omap_uart_lsr str \rx, [\tmp, #0] b 10b @@ -120,7 +130,10 @@ omap_uart_lsr: .word 0 .endm .macro busyuart,rd,rx -1001: ldr \rd, =omap_uart_lsr +1001: mrc p15, 0, \rd, c1, c0 + tst \rd, #1 @ MMU enabled? + ldreq \rd, =__virt_to_phys(omap_uart_lsr) + ldrne \rd, =omap_uart_lsr ldr \rd, [\rd, #0] ldrb \rd, [\rx, \rd] and \rd, \rd, #(UART_LSR_TEMT | UART_LSR_THRE) diff --git a/arch/arm/mach-omap2/include/mach/id.h b/arch/arm/mach-omap2/include/mach/id.h new file mode 100644 index 00000000000..02ed3aa56f1 --- /dev/null +++ b/arch/arm/mach-omap2/include/mach/id.h @@ -0,0 +1,22 @@ +/* + * OMAP2 CPU identification code + * + * Copyright (C) 2010 Kan-Ru Chen <kanru@0xlab.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef OMAP2_ARCH_ID_H +#define OMAP2_ARCH_ID_H + +struct omap_die_id { + u32 id_0; + u32 id_1; + u32 id_2; + u32 id_3; +}; + +void omap_get_die_id(struct omap_die_id *odi); + +#endif diff --git a/arch/arm/mach-omap2/include/mach/omap4-common.h b/arch/arm/mach-omap2/include/mach/omap4-common.h index 423af3a6dd3..2744dfee1ff 100644 --- a/arch/arm/mach-omap2/include/mach/omap4-common.h +++ b/arch/arm/mach-omap2/include/mach/omap4-common.h @@ -13,6 +13,13 @@ #ifndef OMAP_ARCH_OMAP4_COMMON_H #define OMAP_ARCH_OMAP4_COMMON_H +/* + * wfi used in low power code. Directly opcode is used instead + * of instruction to avoid mulit-omap build break + */ +#define do_wfi() \ + __asm__ __volatile__ (".word 0xe320f003" : : : "memory") + #ifdef CONFIG_CACHE_L2X0 extern void __iomem *l2cache_base; #endif diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 4e1f53d0b88..b9ea70bce56 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -28,7 +28,6 @@ #include <asm/mach/map.h> -#include <plat/mux.h> #include <plat/sram.h> #include <plat/sdrc.h> #include <plat/gpmc.h> @@ -44,6 +43,7 @@ #include <plat/clockdomain.h> #include "clockdomains.h" + #include <plat/omap_hwmod.h> /* @@ -313,6 +313,8 @@ static int __init _omap2_init_reprogram_sdrc(void) void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0, struct omap_sdrc_params *sdrc_cs1) { + u8 skip_setup_idle = 0; + pwrdm_init(powerdomains_omap); clkdm_init(clockdomains_omap, clkdm_autodeps); if (cpu_is_omap242x()) @@ -321,7 +323,6 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0, omap2430_hwmod_init(); else if (cpu_is_omap34xx()) omap3xxx_hwmod_init(); - omap2_mux_init(); /* The OPP tables have to be registered before a clk init */ omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps); @@ -337,9 +338,13 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0, pr_err("Could not init clock framework - unknown CPU\n"); omap_serial_early_init(); + +#ifndef CONFIG_PM_RUNTIME + skip_setup_idle = 1; +#endif if (cpu_is_omap24xx() || cpu_is_omap34xx()) /* FIXME: OMAP4 */ - omap_hwmod_late_init(); - omap_pm_if_init(); + omap_hwmod_late_init(skip_setup_idle); + if (cpu_is_omap24xx() || cpu_is_omap34xx()) { omap2_sdrc_init(sdrc_cs0, sdrc_cs1); _omap2_init_reprogram_sdrc(); diff --git a/arch/arm/mach-omap2/iommu2.c b/arch/arm/mach-omap2/iommu2.c index e82da680d90..14ee686b649 100644 --- a/arch/arm/mach-omap2/iommu2.c +++ b/arch/arm/mach-omap2/iommu2.c @@ -44,9 +44,13 @@ #define MMU_IRQ_EMUMISS (1 << 2) #define MMU_IRQ_TRANSLATIONFAULT (1 << 1) #define MMU_IRQ_TLBMISS (1 << 0) -#define MMU_IRQ_MASK \ - (MMU_IRQ_MULTIHITFAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_EMUMISS | \ - MMU_IRQ_TRANSLATIONFAULT) + +#define __MMU_IRQ_FAULT \ + (MMU_IRQ_MULTIHITFAULT | MMU_IRQ_EMUMISS | MMU_IRQ_TRANSLATIONFAULT) +#define MMU_IRQ_MASK \ + (__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_TLBMISS) +#define MMU_IRQ_TWL_MASK (__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT) +#define MMU_IRQ_TLB_MISS_MASK (__MMU_IRQ_FAULT | MMU_IRQ_TLBMISS) /* MMU_CNTL */ #define MMU_CNTL_SHIFT 1 @@ -61,6 +65,26 @@ ((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 : \ ((pgsz) == MMU_CAM_PGSZ_4K) ? 0xfffff000 : 0) + +static void __iommu_set_twl(struct iommu *obj, bool on) +{ + u32 l = iommu_read_reg(obj, MMU_CNTL); + + if (on) + iommu_write_reg(obj, MMU_IRQ_TWL_MASK, MMU_IRQENABLE); + else + iommu_write_reg(obj, MMU_IRQ_TLB_MISS_MASK, MMU_IRQENABLE); + + l &= ~MMU_CNTL_MASK; + if (on) + l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN); + else + l |= (MMU_CNTL_MMU_EN); + + iommu_write_reg(obj, l, MMU_CNTL); +} + + static int omap2_iommu_enable(struct iommu *obj) { u32 l, pa; @@ -96,13 +120,9 @@ static int omap2_iommu_enable(struct iommu *obj) l |= (MMU_SYS_IDLE_SMART | MMU_SYS_AUTOIDLE); iommu_write_reg(obj, l, MMU_SYSCONFIG); - iommu_write_reg(obj, MMU_IRQ_MASK, MMU_IRQENABLE); iommu_write_reg(obj, pa, MMU_TTB); - l = iommu_read_reg(obj, MMU_CNTL); - l &= ~MMU_CNTL_MASK; - l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN); - iommu_write_reg(obj, l, MMU_CNTL); + __iommu_set_twl(obj, true); return 0; } @@ -118,6 +138,11 @@ static void omap2_iommu_disable(struct iommu *obj) dev_dbg(obj->dev, "%s is shutting down\n", obj->name); } +static void omap2_iommu_set_twl(struct iommu *obj, bool on) +{ + __iommu_set_twl(obj, false); +} + static u32 omap2_iommu_fault_isr(struct iommu *obj, u32 *ra) { int i; @@ -147,7 +172,7 @@ static u32 omap2_iommu_fault_isr(struct iommu *obj, u32 *ra) printk("\n"); iommu_write_reg(obj, stat, MMU_IRQSTATUS); - omap2_iommu_disable(obj); + return stat; } @@ -300,6 +325,7 @@ static const struct iommu_functions omap2_iommu_ops = { .enable = omap2_iommu_enable, .disable = omap2_iommu_disable, + .set_twl = omap2_iommu_set_twl, .fault_isr = omap2_iommu_fault_isr, .tlb_read_cr = omap2_tlb_read_cr, diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c index 318f3638653..42dbfa46e65 100644 --- a/arch/arm/mach-omap2/mailbox.c +++ b/arch/arm/mach-omap2/mailbox.c @@ -10,7 +10,6 @@ * for more details. */ -#include <linux/kernel.h> #include <linux/clk.h> #include <linux/err.h> #include <linux/platform_device.h> @@ -18,8 +17,6 @@ #include <plat/mailbox.h> #include <mach/irqs.h> -#define DRV_NAME "omap2-mailbox" - #define MAILBOX_REVISION 0x000 #define MAILBOX_SYSCONFIG 0x010 #define MAILBOX_SYSSTATUS 0x014 @@ -131,7 +128,7 @@ static int omap2_mbox_startup(struct omap_mbox *mbox) } l = mbox_read_reg(MAILBOX_REVISION); - pr_info("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f)); + pr_debug("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f)); if (cpu_is_omap44xx()) l = OMAP4_SMARTIDLE; @@ -283,6 +280,8 @@ static struct omap_mbox_ops omap2_mbox_ops = { */ /* FIXME: the following structs should be filled automatically by the user id */ + +#if defined(CONFIG_ARCH_OMAP3430) || defined(CONFIG_ARCH_OMAP2420) /* DSP */ static struct omap_mbox2_priv omap2_mbox_dsp_priv = { .tx_fifo = { @@ -300,10 +299,46 @@ static struct omap_mbox2_priv omap2_mbox_dsp_priv = { .irqdisable = MAILBOX_IRQENABLE(0), }; +struct omap_mbox mbox_dsp_info = { + .name = "dsp", + .ops = &omap2_mbox_ops, + .priv = &omap2_mbox_dsp_priv, +}; +#endif + +#if defined(CONFIG_ARCH_OMAP3430) +struct omap_mbox *omap3_mboxes[] = { &mbox_dsp_info, NULL }; +#endif + +#if defined(CONFIG_ARCH_OMAP2420) +/* IVA */ +static struct omap_mbox2_priv omap2_mbox_iva_priv = { + .tx_fifo = { + .msg = MAILBOX_MESSAGE(2), + .fifo_stat = MAILBOX_FIFOSTATUS(2), + }, + .rx_fifo = { + .msg = MAILBOX_MESSAGE(3), + .msg_stat = MAILBOX_MSGSTATUS(3), + }, + .irqenable = MAILBOX_IRQENABLE(3), + .irqstatus = MAILBOX_IRQSTATUS(3), + .notfull_bit = MAILBOX_IRQ_NOTFULL(2), + .newmsg_bit = MAILBOX_IRQ_NEWMSG(3), + .irqdisable = MAILBOX_IRQENABLE(3), +}; + +static struct omap_mbox mbox_iva_info = { + .name = "iva", + .ops = &omap2_mbox_ops, + .priv = &omap2_mbox_iva_priv, +}; +struct omap_mbox *omap2_mboxes[] = { &mbox_iva_info, &mbox_dsp_info, NULL }; +#endif -/* OMAP4 specific data structure. Use the cpu_is_omap4xxx() -to use this*/ +#if defined(CONFIG_ARCH_OMAP4) +/* OMAP4 */ static struct omap_mbox2_priv omap2_mbox_1_priv = { .tx_fifo = { .msg = MAILBOX_MESSAGE(0), @@ -325,14 +360,6 @@ struct omap_mbox mbox_1_info = { .ops = &omap2_mbox_ops, .priv = &omap2_mbox_1_priv, }; -EXPORT_SYMBOL(mbox_1_info); - -struct omap_mbox mbox_dsp_info = { - .name = "dsp", - .ops = &omap2_mbox_ops, - .priv = &omap2_mbox_dsp_priv, -}; -EXPORT_SYMBOL(mbox_dsp_info); static struct omap_mbox2_priv omap2_mbox_2_priv = { .tx_fifo = { @@ -355,110 +382,64 @@ struct omap_mbox mbox_2_info = { .ops = &omap2_mbox_ops, .priv = &omap2_mbox_2_priv, }; -EXPORT_SYMBOL(mbox_2_info); - - -#if defined(CONFIG_ARCH_OMAP2420) /* IVA */ -static struct omap_mbox2_priv omap2_mbox_iva_priv = { - .tx_fifo = { - .msg = MAILBOX_MESSAGE(2), - .fifo_stat = MAILBOX_FIFOSTATUS(2), - }, - .rx_fifo = { - .msg = MAILBOX_MESSAGE(3), - .msg_stat = MAILBOX_MSGSTATUS(3), - }, - .irqenable = MAILBOX_IRQENABLE(3), - .irqstatus = MAILBOX_IRQSTATUS(3), - .notfull_bit = MAILBOX_IRQ_NOTFULL(2), - .newmsg_bit = MAILBOX_IRQ_NEWMSG(3), - .irqdisable = MAILBOX_IRQENABLE(3), -}; -static struct omap_mbox mbox_iva_info = { - .name = "iva", - .ops = &omap2_mbox_ops, - .priv = &omap2_mbox_iva_priv, -}; +struct omap_mbox *omap4_mboxes[] = { &mbox_1_info, &mbox_2_info, NULL }; #endif static int __devinit omap2_mbox_probe(struct platform_device *pdev) { - struct resource *res; + struct resource *mem; int ret; + struct omap_mbox **list; - /* MBOX base */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (unlikely(!res)) { - dev_err(&pdev->dev, "invalid mem resource\n"); - return -ENODEV; + if (false) + ; +#if defined(CONFIG_ARCH_OMAP3430) + else if (cpu_is_omap3430()) { + list = omap3_mboxes; + + list[0]->irq = platform_get_irq_byname(pdev, "dsp"); } - mbox_base = ioremap(res->start, resource_size(res)); - if (!mbox_base) - return -ENOMEM; +#endif +#if defined(CONFIG_ARCH_OMAP2420) + else if (cpu_is_omap2420()) { + list = omap2_mboxes; - /* DSP or IVA2 IRQ */ - res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + list[0]->irq = platform_get_irq_byname(pdev, "dsp"); + list[1]->irq = platform_get_irq_byname(pdev, "iva"); + } +#endif +#if defined(CONFIG_ARCH_OMAP4) + else if (cpu_is_omap44xx()) { + list = omap4_mboxes; - if (unlikely(!res)) { - dev_err(&pdev->dev, "invalid irq resource\n"); - ret = -ENODEV; - goto err_dsp; + list[0]->irq = list[1]->irq = + platform_get_irq_byname(pdev, "mbox"); } - if (cpu_is_omap44xx()) { - mbox_1_info.irq = res->start; - ret = omap_mbox_register(&pdev->dev, &mbox_1_info); - } else { - mbox_dsp_info.irq = res->start; - ret = omap_mbox_register(&pdev->dev, &mbox_dsp_info); +#endif + else { + pr_err("%s: platform not supported\n", __func__); + return -ENODEV; } - if (ret) - goto err_dsp; - if (cpu_is_omap44xx()) { - mbox_2_info.irq = res->start; - ret = omap_mbox_register(&pdev->dev, &mbox_2_info); - if (ret) { - omap_mbox_unregister(&mbox_1_info); - goto err_dsp; - } - } -#if defined(CONFIG_ARCH_OMAP2420) /* IVA */ - if (cpu_is_omap2420()) { - /* IVA IRQ */ - res = platform_get_resource(pdev, IORESOURCE_IRQ, 1); - if (unlikely(!res)) { - dev_err(&pdev->dev, "invalid irq resource\n"); - ret = -ENODEV; - omap_mbox_unregister(&mbox_dsp_info); - goto err_dsp; - } - mbox_iva_info.irq = res->start; - ret = omap_mbox_register(&pdev->dev, &mbox_iva_info); - if (ret) { - omap_mbox_unregister(&mbox_dsp_info); - goto err_dsp; - } + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + mbox_base = ioremap(mem->start, resource_size(mem)); + if (!mbox_base) + return -ENOMEM; + + ret = omap_mbox_register(&pdev->dev, list); + if (ret) { + iounmap(mbox_base); + return ret; } -#endif return 0; -err_dsp: - iounmap(mbox_base); return ret; } static int __devexit omap2_mbox_remove(struct platform_device *pdev) { -#if defined(CONFIG_ARCH_OMAP2420) - omap_mbox_unregister(&mbox_iva_info); -#endif - - if (cpu_is_omap44xx()) { - omap_mbox_unregister(&mbox_2_info); - omap_mbox_unregister(&mbox_1_info); - } else - omap_mbox_unregister(&mbox_dsp_info); + omap_mbox_unregister(); iounmap(mbox_base); return 0; } @@ -467,7 +448,7 @@ static struct platform_driver omap2_mbox_driver = { .probe = omap2_mbox_probe, .remove = __devexit_p(omap2_mbox_remove), .driver = { - .name = DRV_NAME, + .name = "omap-mailbox", }, }; @@ -486,5 +467,6 @@ module_exit(omap2_mbox_exit); MODULE_LICENSE("GPL v2"); MODULE_DESCRIPTION("omap mailbox: omap2/3/4 architecture specific functions"); -MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>, Paul Mundt"); -MODULE_ALIAS("platform:"DRV_NAME); +MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>"); +MODULE_AUTHOR("Paul Mundt"); +MODULE_ALIAS("platform:omap2-mailbox"); diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c index c29337074ad..467aae24578 100644 --- a/arch/arm/mach-omap2/mcbsp.c +++ b/arch/arm/mach-omap2/mcbsp.c @@ -20,17 +20,18 @@ #include <mach/irqs.h> #include <plat/dma.h> -#include <plat/mux.h> #include <plat/cpu.h> #include <plat/mcbsp.h> +#include "mux.h" + static void omap2_mcbsp2_mux_setup(void) { - omap_cfg_reg(Y15_24XX_MCBSP2_CLKX); - omap_cfg_reg(R14_24XX_MCBSP2_FSX); - omap_cfg_reg(W15_24XX_MCBSP2_DR); - omap_cfg_reg(V15_24XX_MCBSP2_DX); - omap_cfg_reg(V14_24XX_GPIO117); + omap_mux_init_signal("eac_ac_sclk.mcbsp2_clkx", OMAP_PULL_ENA); + omap_mux_init_signal("eac_ac_fs.mcbsp2_fsx", OMAP_PULL_ENA); + omap_mux_init_signal("eac_ac_din.mcbsp2_dr", OMAP_PULL_ENA); + omap_mux_init_signal("eac_ac_dout.mcbsp2_dx", OMAP_PULL_ENA); + omap_mux_init_gpio(117, OMAP_PULL_ENA); /* * TODO: Need to add MUX settings for OMAP 2430 SDP */ @@ -133,7 +134,7 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { .rx_irq = INT_24XX_MCBSP1_IRQ_RX, .tx_irq = INT_24XX_MCBSP1_IRQ_TX, .ops = &omap2_mcbsp_ops, - .buffer_size = 0x6F, + .buffer_size = 0x80, /* The FIFO has 128 locations */ }, { .phys_base = OMAP34XX_MCBSP2_BASE, @@ -143,7 +144,7 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { .rx_irq = INT_24XX_MCBSP2_IRQ_RX, .tx_irq = INT_24XX_MCBSP2_IRQ_TX, .ops = &omap2_mcbsp_ops, - .buffer_size = 0x3FF, + .buffer_size = 0x500, /* The FIFO has 1024 + 256 locations */ }, { .phys_base = OMAP34XX_MCBSP3_BASE, @@ -153,7 +154,7 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { .rx_irq = INT_24XX_MCBSP3_IRQ_RX, .tx_irq = INT_24XX_MCBSP3_IRQ_TX, .ops = &omap2_mcbsp_ops, - .buffer_size = 0x6F, + .buffer_size = 0x80, /* The FIFO has 128 locations */ }, { .phys_base = OMAP34XX_MCBSP4_BASE, @@ -162,7 +163,7 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { .rx_irq = INT_24XX_MCBSP4_IRQ_RX, .tx_irq = INT_24XX_MCBSP4_IRQ_TX, .ops = &omap2_mcbsp_ops, - .buffer_size = 0x6F, + .buffer_size = 0x80, /* The FIFO has 128 locations */ }, { .phys_base = OMAP34XX_MCBSP5_BASE, @@ -171,7 +172,7 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { .rx_irq = INT_24XX_MCBSP5_IRQ_RX, .tx_irq = INT_24XX_MCBSP5_IRQ_TX, .ops = &omap2_mcbsp_ops, - .buffer_size = 0x6F, + .buffer_size = 0x80, /* The FIFO has 128 locations */ }, }; #define OMAP34XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap34xx_mcbsp_pdata) diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c index 8b3d26935a3..ab403b2ed26 100644 --- a/arch/arm/mach-omap2/mux.c +++ b/arch/arm/mach-omap2/mux.c @@ -37,12 +37,12 @@ #include <asm/system.h> #include <plat/control.h> -#include <plat/mux.h> #include "mux.h" #define OMAP_MUX_BASE_OFFSET 0x30 /* Offset from CTRL_BASE */ #define OMAP_MUX_BASE_SZ 0x5ca +#define MUXABLE_GPIO_MODE3 BIT(0) struct omap_mux_entry { struct omap_mux mux; @@ -51,6 +51,7 @@ struct omap_mux_entry { static unsigned long mux_phys; static void __iomem *mux_base; +static u8 omap_mux_flags; u16 omap_mux_read(u16 reg) { @@ -76,301 +77,6 @@ void omap_mux_write_array(struct omap_board_mux *board_mux) } } -#if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_OMAP_MUX) - -static struct omap_mux_cfg arch_mux_cfg; - -/* NOTE: See mux.h for the enumeration */ - -static struct pin_config __initdata_or_module omap24xx_pins[] = { -/* - * description mux mux pull pull debug - * offset mode ena type - */ - -/* 24xx I2C */ -MUX_CFG_24XX("M19_24XX_I2C1_SCL", 0x111, 0, 0, 0, 1) -MUX_CFG_24XX("L15_24XX_I2C1_SDA", 0x112, 0, 0, 0, 1) -MUX_CFG_24XX("J15_24XX_I2C2_SCL", 0x113, 0, 0, 1, 1) -MUX_CFG_24XX("H19_24XX_I2C2_SDA", 0x114, 0, 0, 0, 1) - -/* Menelaus interrupt */ -MUX_CFG_24XX("W19_24XX_SYS_NIRQ", 0x12c, 0, 1, 1, 1) - -/* 24xx clocks */ -MUX_CFG_24XX("W14_24XX_SYS_CLKOUT", 0x137, 0, 1, 1, 1) - -/* 24xx GPMC chipselects, wait pin monitoring */ -MUX_CFG_24XX("E2_GPMC_NCS2", 0x08e, 0, 1, 1, 1) -MUX_CFG_24XX("L2_GPMC_NCS7", 0x093, 0, 1, 1, 1) -MUX_CFG_24XX("L3_GPMC_WAIT0", 0x09a, 0, 1, 1, 1) -MUX_CFG_24XX("N7_GPMC_WAIT1", 0x09b, 0, 1, 1, 1) -MUX_CFG_24XX("M1_GPMC_WAIT2", 0x09c, 0, 1, 1, 1) -MUX_CFG_24XX("P1_GPMC_WAIT3", 0x09d, 0, 1, 1, 1) - -/* 24xx McBSP */ -MUX_CFG_24XX("Y15_24XX_MCBSP2_CLKX", 0x124, 1, 1, 0, 1) -MUX_CFG_24XX("R14_24XX_MCBSP2_FSX", 0x125, 1, 1, 0, 1) -MUX_CFG_24XX("W15_24XX_MCBSP2_DR", 0x126, 1, 1, 0, 1) -MUX_CFG_24XX("V15_24XX_MCBSP2_DX", 0x127, 1, 1, 0, 1) - -/* 24xx GPIO */ -MUX_CFG_24XX("M21_242X_GPIO11", 0x0c9, 3, 1, 1, 1) -MUX_CFG_24XX("P21_242X_GPIO12", 0x0ca, 3, 0, 0, 1) -MUX_CFG_24XX("AA10_242X_GPIO13", 0x0e5, 3, 0, 0, 1) -MUX_CFG_24XX("AA6_242X_GPIO14", 0x0e6, 3, 0, 0, 1) -MUX_CFG_24XX("AA4_242X_GPIO15", 0x0e7, 3, 0, 0, 1) -MUX_CFG_24XX("Y11_242X_GPIO16", 0x0e8, 3, 0, 0, 1) -MUX_CFG_24XX("AA12_242X_GPIO17", 0x0e9, 3, 0, 0, 1) -MUX_CFG_24XX("AA8_242X_GPIO58", 0x0ea, 3, 0, 0, 1) -MUX_CFG_24XX("Y20_24XX_GPIO60", 0x12c, 3, 0, 0, 1) -MUX_CFG_24XX("W4__24XX_GPIO74", 0x0f2, 3, 0, 0, 1) -MUX_CFG_24XX("N15_24XX_GPIO85", 0x103, 3, 0, 0, 1) -MUX_CFG_24XX("M15_24XX_GPIO92", 0x10a, 3, 0, 0, 1) -MUX_CFG_24XX("P20_24XX_GPIO93", 0x10b, 3, 0, 0, 1) -MUX_CFG_24XX("P18_24XX_GPIO95", 0x10d, 3, 0, 0, 1) -MUX_CFG_24XX("M18_24XX_GPIO96", 0x10e, 3, 0, 0, 1) -MUX_CFG_24XX("L14_24XX_GPIO97", 0x10f, 3, 0, 0, 1) -MUX_CFG_24XX("J15_24XX_GPIO99", 0x113, 3, 1, 1, 1) -MUX_CFG_24XX("V14_24XX_GPIO117", 0x128, 3, 1, 0, 1) -MUX_CFG_24XX("P14_24XX_GPIO125", 0x140, 3, 1, 1, 1) - -/* 242x DBG GPIO */ -MUX_CFG_24XX("V4_242X_GPIO49", 0xd3, 3, 0, 0, 1) -MUX_CFG_24XX("W2_242X_GPIO50", 0xd4, 3, 0, 0, 1) -MUX_CFG_24XX("U4_242X_GPIO51", 0xd5, 3, 0, 0, 1) -MUX_CFG_24XX("V3_242X_GPIO52", 0xd6, 3, 0, 0, 1) -MUX_CFG_24XX("V2_242X_GPIO53", 0xd7, 3, 0, 0, 1) -MUX_CFG_24XX("V6_242X_GPIO53", 0xcf, 3, 0, 0, 1) -MUX_CFG_24XX("T4_242X_GPIO54", 0xd8, 3, 0, 0, 1) -MUX_CFG_24XX("Y4_242X_GPIO54", 0xd0, 3, 0, 0, 1) -MUX_CFG_24XX("T3_242X_GPIO55", 0xd9, 3, 0, 0, 1) -MUX_CFG_24XX("U2_242X_GPIO56", 0xda, 3, 0, 0, 1) - -/* 24xx external DMA requests */ -MUX_CFG_24XX("AA10_242X_DMAREQ0", 0x0e5, 2, 0, 0, 1) -MUX_CFG_24XX("AA6_242X_DMAREQ1", 0x0e6, 2, 0, 0, 1) -MUX_CFG_24XX("E4_242X_DMAREQ2", 0x074, 2, 0, 0, 1) -MUX_CFG_24XX("G4_242X_DMAREQ3", 0x073, 2, 0, 0, 1) -MUX_CFG_24XX("D3_242X_DMAREQ4", 0x072, 2, 0, 0, 1) -MUX_CFG_24XX("E3_242X_DMAREQ5", 0x071, 2, 0, 0, 1) - -/* UART3 */ -MUX_CFG_24XX("K15_24XX_UART3_TX", 0x118, 0, 0, 0, 1) -MUX_CFG_24XX("K14_24XX_UART3_RX", 0x119, 0, 0, 0, 1) - -/* MMC/SDIO */ -MUX_CFG_24XX("G19_24XX_MMC_CLKO", 0x0f3, 0, 0, 0, 1) -MUX_CFG_24XX("H18_24XX_MMC_CMD", 0x0f4, 0, 0, 0, 1) -MUX_CFG_24XX("F20_24XX_MMC_DAT0", 0x0f5, 0, 0, 0, 1) -MUX_CFG_24XX("H14_24XX_MMC_DAT1", 0x0f6, 0, 0, 0, 1) -MUX_CFG_24XX("E19_24XX_MMC_DAT2", 0x0f7, 0, 0, 0, 1) -MUX_CFG_24XX("D19_24XX_MMC_DAT3", 0x0f8, 0, 0, 0, 1) -MUX_CFG_24XX("F19_24XX_MMC_DAT_DIR0", 0x0f9, 0, 0, 0, 1) -MUX_CFG_24XX("E20_24XX_MMC_DAT_DIR1", 0x0fa, 0, 0, 0, 1) -MUX_CFG_24XX("F18_24XX_MMC_DAT_DIR2", 0x0fb, 0, 0, 0, 1) -MUX_CFG_24XX("E18_24XX_MMC_DAT_DIR3", 0x0fc, 0, 0, 0, 1) -MUX_CFG_24XX("G18_24XX_MMC_CMD_DIR", 0x0fd, 0, 0, 0, 1) -MUX_CFG_24XX("H15_24XX_MMC_CLKI", 0x0fe, 0, 0, 0, 1) - -/* Full speed USB */ -MUX_CFG_24XX("J20_24XX_USB0_PUEN", 0x11d, 0, 0, 0, 1) -MUX_CFG_24XX("J19_24XX_USB0_VP", 0x11e, 0, 0, 0, 1) -MUX_CFG_24XX("K20_24XX_USB0_VM", 0x11f, 0, 0, 0, 1) -MUX_CFG_24XX("J18_24XX_USB0_RCV", 0x120, 0, 0, 0, 1) -MUX_CFG_24XX("K19_24XX_USB0_TXEN", 0x121, 0, 0, 0, 1) -MUX_CFG_24XX("J14_24XX_USB0_SE0", 0x122, 0, 0, 0, 1) -MUX_CFG_24XX("K18_24XX_USB0_DAT", 0x123, 0, 0, 0, 1) - -MUX_CFG_24XX("N14_24XX_USB1_SE0", 0x0ed, 2, 0, 0, 1) -MUX_CFG_24XX("W12_24XX_USB1_SE0", 0x0dd, 3, 0, 0, 1) -MUX_CFG_24XX("P15_24XX_USB1_DAT", 0x0ee, 2, 0, 0, 1) -MUX_CFG_24XX("R13_24XX_USB1_DAT", 0x0e0, 3, 0, 0, 1) -MUX_CFG_24XX("W20_24XX_USB1_TXEN", 0x0ec, 2, 0, 0, 1) -MUX_CFG_24XX("P13_24XX_USB1_TXEN", 0x0df, 3, 0, 0, 1) -MUX_CFG_24XX("V19_24XX_USB1_RCV", 0x0eb, 2, 0, 0, 1) -MUX_CFG_24XX("V12_24XX_USB1_RCV", 0x0de, 3, 0, 0, 1) - -MUX_CFG_24XX("AA10_24XX_USB2_SE0", 0x0e5, 2, 0, 0, 1) -MUX_CFG_24XX("Y11_24XX_USB2_DAT", 0x0e8, 2, 0, 0, 1) -MUX_CFG_24XX("AA12_24XX_USB2_TXEN", 0x0e9, 2, 0, 0, 1) -MUX_CFG_24XX("AA6_24XX_USB2_RCV", 0x0e6, 2, 0, 0, 1) -MUX_CFG_24XX("AA4_24XX_USB2_TLLSE0", 0x0e7, 2, 0, 0, 1) - -/* Keypad GPIO*/ -MUX_CFG_24XX("T19_24XX_KBR0", 0x106, 3, 1, 1, 1) -MUX_CFG_24XX("R19_24XX_KBR1", 0x107, 3, 1, 1, 1) -MUX_CFG_24XX("V18_24XX_KBR2", 0x139, 3, 1, 1, 1) -MUX_CFG_24XX("M21_24XX_KBR3", 0xc9, 3, 1, 1, 1) -MUX_CFG_24XX("E5__24XX_KBR4", 0x138, 3, 1, 1, 1) -MUX_CFG_24XX("M18_24XX_KBR5", 0x10e, 3, 1, 1, 1) -MUX_CFG_24XX("R20_24XX_KBC0", 0x108, 3, 0, 0, 1) -MUX_CFG_24XX("M14_24XX_KBC1", 0x109, 3, 0, 0, 1) -MUX_CFG_24XX("H19_24XX_KBC2", 0x114, 3, 0, 0, 1) -MUX_CFG_24XX("V17_24XX_KBC3", 0x135, 3, 0, 0, 1) -MUX_CFG_24XX("P21_24XX_KBC4", 0xca, 3, 0, 0, 1) -MUX_CFG_24XX("L14_24XX_KBC5", 0x10f, 3, 0, 0, 1) -MUX_CFG_24XX("N19_24XX_KBC6", 0x110, 3, 0, 0, 1) - -/* 24xx Menelaus Keypad GPIO */ -MUX_CFG_24XX("B3__24XX_KBR5", 0x30, 3, 1, 1, 1) -MUX_CFG_24XX("AA4_24XX_KBC2", 0xe7, 3, 0, 0, 1) -MUX_CFG_24XX("B13_24XX_KBC6", 0x110, 3, 0, 0, 1) - -/* 2430 USB */ -MUX_CFG_24XX("AD9_2430_USB0_PUEN", 0x133, 4, 0, 0, 1) -MUX_CFG_24XX("Y11_2430_USB0_VP", 0x134, 4, 0, 0, 1) -MUX_CFG_24XX("AD7_2430_USB0_VM", 0x135, 4, 0, 0, 1) -MUX_CFG_24XX("AE7_2430_USB0_RCV", 0x136, 4, 0, 0, 1) -MUX_CFG_24XX("AD4_2430_USB0_TXEN", 0x137, 4, 0, 0, 1) -MUX_CFG_24XX("AF9_2430_USB0_SE0", 0x138, 4, 0, 0, 1) -MUX_CFG_24XX("AE6_2430_USB0_DAT", 0x139, 4, 0, 0, 1) -MUX_CFG_24XX("AD24_2430_USB1_SE0", 0x107, 2, 0, 0, 1) -MUX_CFG_24XX("AB24_2430_USB1_RCV", 0x108, 2, 0, 0, 1) -MUX_CFG_24XX("Y25_2430_USB1_TXEN", 0x109, 2, 0, 0, 1) -MUX_CFG_24XX("AA26_2430_USB1_DAT", 0x10A, 2, 0, 0, 1) - -/* 2430 HS-USB */ -MUX_CFG_24XX("AD9_2430_USB0HS_DATA3", 0x133, 0, 0, 0, 1) -MUX_CFG_24XX("Y11_2430_USB0HS_DATA4", 0x134, 0, 0, 0, 1) -MUX_CFG_24XX("AD7_2430_USB0HS_DATA5", 0x135, 0, 0, 0, 1) -MUX_CFG_24XX("AE7_2430_USB0HS_DATA6", 0x136, 0, 0, 0, 1) -MUX_CFG_24XX("AD4_2430_USB0HS_DATA2", 0x137, 0, 0, 0, 1) -MUX_CFG_24XX("AF9_2430_USB0HS_DATA0", 0x138, 0, 0, 0, 1) -MUX_CFG_24XX("AE6_2430_USB0HS_DATA1", 0x139, 0, 0, 0, 1) -MUX_CFG_24XX("AE8_2430_USB0HS_CLK", 0x13A, 0, 0, 0, 1) -MUX_CFG_24XX("AD8_2430_USB0HS_DIR", 0x13B, 0, 0, 0, 1) -MUX_CFG_24XX("AE5_2430_USB0HS_STP", 0x13c, 0, 1, 1, 1) -MUX_CFG_24XX("AE9_2430_USB0HS_NXT", 0x13D, 0, 0, 0, 1) -MUX_CFG_24XX("AC7_2430_USB0HS_DATA7", 0x13E, 0, 0, 0, 1) - -/* 2430 McBSP */ -MUX_CFG_24XX("AD6_2430_MCBSP_CLKS", 0x011E, 0, 0, 0, 1) - -MUX_CFG_24XX("AB2_2430_MCBSP1_CLKR", 0x011A, 0, 0, 0, 1) -MUX_CFG_24XX("AD5_2430_MCBSP1_FSR", 0x011B, 0, 0, 0, 1) -MUX_CFG_24XX("AA1_2430_MCBSP1_DX", 0x011C, 0, 0, 0, 1) -MUX_CFG_24XX("AF3_2430_MCBSP1_DR", 0x011D, 0, 0, 0, 1) -MUX_CFG_24XX("AB3_2430_MCBSP1_FSX", 0x011F, 0, 0, 0, 1) -MUX_CFG_24XX("Y9_2430_MCBSP1_CLKX", 0x0120, 0, 0, 0, 1) - -MUX_CFG_24XX("AC10_2430_MCBSP2_FSX", 0x012E, 1, 0, 0, 1) -MUX_CFG_24XX("AD16_2430_MCBSP2_CLX", 0x012F, 1, 0, 0, 1) -MUX_CFG_24XX("AE13_2430_MCBSP2_DX", 0x0130, 1, 0, 0, 1) -MUX_CFG_24XX("AD13_2430_MCBSP2_DR", 0x0131, 1, 0, 0, 1) -MUX_CFG_24XX("AC10_2430_MCBSP2_FSX_OFF",0x012E, 0, 0, 0, 1) -MUX_CFG_24XX("AD16_2430_MCBSP2_CLX_OFF",0x012F, 0, 0, 0, 1) -MUX_CFG_24XX("AE13_2430_MCBSP2_DX_OFF", 0x0130, 0, 0, 0, 1) -MUX_CFG_24XX("AD13_2430_MCBSP2_DR_OFF", 0x0131, 0, 0, 0, 1) - -MUX_CFG_24XX("AC9_2430_MCBSP3_CLKX", 0x0103, 0, 0, 0, 1) -MUX_CFG_24XX("AE4_2430_MCBSP3_FSX", 0x0104, 0, 0, 0, 1) -MUX_CFG_24XX("AE2_2430_MCBSP3_DR", 0x0105, 0, 0, 0, 1) -MUX_CFG_24XX("AF4_2430_MCBSP3_DX", 0x0106, 0, 0, 0, 1) - -MUX_CFG_24XX("N3_2430_MCBSP4_CLKX", 0x010B, 1, 0, 0, 1) -MUX_CFG_24XX("AD23_2430_MCBSP4_DR", 0x010C, 1, 0, 0, 1) -MUX_CFG_24XX("AB25_2430_MCBSP4_DX", 0x010D, 1, 0, 0, 1) -MUX_CFG_24XX("AC25_2430_MCBSP4_FSX", 0x010E, 1, 0, 0, 1) - -MUX_CFG_24XX("AE16_2430_MCBSP5_CLKX", 0x00ED, 1, 0, 0, 1) -MUX_CFG_24XX("AF12_2430_MCBSP5_FSX", 0x00ED, 1, 0, 0, 1) -MUX_CFG_24XX("K7_2430_MCBSP5_DX", 0x00EF, 1, 0, 0, 1) -MUX_CFG_24XX("M1_2430_MCBSP5_DR", 0x00F0, 1, 0, 0, 1) - -/* 2430 MCSPI1 */ -MUX_CFG_24XX("Y18_2430_MCSPI1_CLK", 0x010F, 0, 0, 0, 1) -MUX_CFG_24XX("AD15_2430_MCSPI1_SIMO", 0x0110, 0, 0, 0, 1) -MUX_CFG_24XX("AE17_2430_MCSPI1_SOMI", 0x0111, 0, 0, 0, 1) -MUX_CFG_24XX("U1_2430_MCSPI1_CS0", 0x0112, 0, 0, 0, 1) - -/* Touchscreen GPIO */ -MUX_CFG_24XX("AF19_2430_GPIO_85", 0x0113, 3, 0, 0, 1) - -}; - -#define OMAP24XX_PINS_SZ ARRAY_SIZE(omap24xx_pins) - -#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS) - -static void __init_or_module omap2_cfg_debug(const struct pin_config *cfg, u16 reg) -{ - u16 orig; - u8 warn = 0, debug = 0; - - orig = omap_mux_read(cfg->mux_reg - OMAP_MUX_BASE_OFFSET); - -#ifdef CONFIG_OMAP_MUX_DEBUG - debug = cfg->debug; -#endif - warn = (orig != reg); - if (debug || warn) - printk(KERN_WARNING - "MUX: setup %s (0x%p): 0x%04x -> 0x%04x\n", - cfg->name, omap_ctrl_base_get() + cfg->mux_reg, - orig, reg); -} -#else -#define omap2_cfg_debug(x, y) do {} while (0) -#endif - -static int __init_or_module omap24xx_cfg_reg(const struct pin_config *cfg) -{ - static DEFINE_SPINLOCK(mux_spin_lock); - unsigned long flags; - u8 reg = 0; - - spin_lock_irqsave(&mux_spin_lock, flags); - reg |= cfg->mask & 0x7; - if (cfg->pull_val) - reg |= OMAP2_PULL_ENA; - if (cfg->pu_pd_val) - reg |= OMAP2_PULL_UP; - omap2_cfg_debug(cfg, reg); - omap_mux_write(reg, cfg->mux_reg - OMAP_MUX_BASE_OFFSET); - spin_unlock_irqrestore(&mux_spin_lock, flags); - - return 0; -} - -int __init omap2_mux_init(void) -{ - u32 mux_pbase; - - if (cpu_is_omap2420()) - mux_pbase = OMAP2420_CTRL_BASE + OMAP_MUX_BASE_OFFSET; - else if (cpu_is_omap2430()) - mux_pbase = OMAP243X_CTRL_BASE + OMAP_MUX_BASE_OFFSET; - else - return -ENODEV; - - mux_base = ioremap(mux_pbase, OMAP_MUX_BASE_SZ); - if (!mux_base) { - printk(KERN_ERR "mux: Could not ioremap\n"); - return -ENODEV; - } - - if (cpu_is_omap24xx()) { - arch_mux_cfg.pins = omap24xx_pins; - arch_mux_cfg.size = OMAP24XX_PINS_SZ; - arch_mux_cfg.cfg_reg = omap24xx_cfg_reg; - - return omap_mux_register(&arch_mux_cfg); - } - - return 0; -} - -#else -int __init omap2_mux_init(void) -{ - return 0; -} -#endif /* CONFIG_OMAP_MUX */ - -/*----------------------------------------------------------------------------*/ - -#ifdef CONFIG_ARCH_OMAP3 static LIST_HEAD(muxmodes); static DEFINE_MUTEX(muxmode_mutex); @@ -381,6 +87,9 @@ static char *omap_mux_options; int __init omap_mux_init_gpio(int gpio, int val) { struct omap_mux_entry *e; + struct omap_mux *gpio_mux; + u16 old_mode; + u16 mux_mode; int found = 0; if (!gpio) @@ -389,31 +98,33 @@ int __init omap_mux_init_gpio(int gpio, int val) list_for_each_entry(e, &muxmodes, node) { struct omap_mux *m = &e->mux; if (gpio == m->gpio) { - u16 old_mode; - u16 mux_mode; - - old_mode = omap_mux_read(m->reg_offset); - mux_mode = val & ~(OMAP_MUX_NR_MODES - 1); - mux_mode |= OMAP_MUX_MODE4; - printk(KERN_DEBUG "mux: Setting signal " - "%s.gpio%i 0x%04x -> 0x%04x\n", - m->muxnames[0], gpio, old_mode, mux_mode); - omap_mux_write(mux_mode, m->reg_offset); + gpio_mux = m; found++; } } - if (found == 1) - return 0; + if (found == 0) { + printk(KERN_ERR "mux: Could not set gpio%i\n", gpio); + return -ENODEV; + } if (found > 1) { - printk(KERN_ERR "mux: Multiple gpio paths for gpio%i\n", gpio); + printk(KERN_INFO "mux: Multiple gpio paths (%d) for gpio%i\n", + found, gpio); return -EINVAL; } - printk(KERN_ERR "mux: Could not set gpio%i\n", gpio); + old_mode = omap_mux_read(gpio_mux->reg_offset); + mux_mode = val & ~(OMAP_MUX_NR_MODES - 1); + if (omap_mux_flags & MUXABLE_GPIO_MODE3) + mux_mode |= OMAP_MUX_MODE3; + else + mux_mode |= OMAP_MUX_MODE4; + printk(KERN_DEBUG "mux: Setting signal %s.gpio%i 0x%04x -> 0x%04x\n", + gpio_mux->muxnames[0], gpio, old_mode, mux_mode); + omap_mux_write(mux_mode, gpio_mux->reg_offset); - return -ENODEV; + return 0; } int __init omap_mux_init_signal(char *muxname, int val) @@ -1032,6 +743,9 @@ int __init omap_mux_init(u32 mux_pbase, u32 mux_size, return -ENODEV; } + if (cpu_is_omap24xx()) + omap_mux_flags = MUXABLE_GPIO_MODE3; + omap_mux_init_package(superset, package_subset, package_balls); omap_mux_init_list(superset); omap_mux_init_signals(board_mux); @@ -1039,5 +753,3 @@ int __init omap_mux_init(u32 mux_pbase, u32 mux_size, return 0; } -#endif /* CONFIG_ARCH_OMAP3 */ - diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h index 480abc56e60..a8e040c2c7e 100644 --- a/arch/arm/mach-omap2/mux.h +++ b/arch/arm/mach-omap2/mux.h @@ -7,6 +7,8 @@ * published by the Free Software Foundation. */ +#include "mux2420.h" +#include "mux2430.h" #include "mux34xx.h" #define OMAP_MUX_TERMINATOR 0xffff @@ -56,10 +58,12 @@ /* Flags for omap_mux_init */ #define OMAP_PACKAGE_MASK 0xffff -#define OMAP_PACKAGE_CBP 4 /* 515-pin 0.40 0.50 */ -#define OMAP_PACKAGE_CUS 3 /* 423-pin 0.65 */ -#define OMAP_PACKAGE_CBB 2 /* 515-pin 0.40 0.50 */ -#define OMAP_PACKAGE_CBC 1 /* 515-pin 0.50 0.65 */ +#define OMAP_PACKAGE_CBP 6 /* 515-pin 0.40 0.50 */ +#define OMAP_PACKAGE_CUS 5 /* 423-pin 0.65 */ +#define OMAP_PACKAGE_CBB 4 /* 515-pin 0.40 0.50 */ +#define OMAP_PACKAGE_CBC 3 /* 515-pin 0.50 0.65 */ +#define OMAP_PACKAGE_ZAC 2 /* 24xx 447-pin POP */ +#define OMAP_PACKAGE_ZAF 1 /* 2420 447-pin SIP */ #define OMAP_MUX_NR_MODES 8 /* Available modes */ @@ -102,7 +106,7 @@ struct omap_board_mux { u16 value; }; -#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_ARCH_OMAP3) +#if defined(CONFIG_OMAP_MUX) /** * omap_mux_init_gpio - initialize a signal based on the GPIO number @@ -171,6 +175,20 @@ void omap_mux_write(u16 val, u16 mux_offset); void omap_mux_write_array(struct omap_board_mux *board_mux); /** + * omap2420_mux_init() - initialize mux system with board specific set + * @board_mux: Board specific mux table + * @flags: OMAP package type used for the board + */ +int omap2420_mux_init(struct omap_board_mux *board_mux, int flags); + +/** + * omap2430_mux_init() - initialize mux system with board specific set + * @board_mux: Board specific mux table + * @flags: OMAP package type used for the board + */ +int omap2430_mux_init(struct omap_board_mux *board_mux, int flags); + +/** * omap3_mux_init() - initialize mux system with board specific set * @board_mux: Board specific mux table * @flags: OMAP package type used for the board diff --git a/arch/arm/mach-omap2/mux2420.c b/arch/arm/mach-omap2/mux2420.c new file mode 100644 index 00000000000..fdb04a7eb8a --- /dev/null +++ b/arch/arm/mach-omap2/mux2420.c @@ -0,0 +1,688 @@ +/* + * Copyright (C) 2010 Nokia + * Copyright (C) 2010 Texas Instruments + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/module.h> +#include <linux/init.h> + +#include "mux.h" + +#ifdef CONFIG_OMAP_MUX + +#define _OMAP2420_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \ +{ \ + .reg_offset = (OMAP2420_CONTROL_PADCONF_##M0##_OFFSET), \ + .gpio = (g), \ + .muxnames = { m0, m1, m2, m3, m4, m5, m6, m7 }, \ +} + +#else + +#define _OMAP2420_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \ +{ \ + .reg_offset = (OMAP2420_CONTROL_PADCONF_##M0##_OFFSET), \ + .gpio = (g), \ +} + +#endif + +#define _OMAP2420_BALLENTRY(M0, bb, bt) \ +{ \ + .reg_offset = (OMAP2420_CONTROL_PADCONF_##M0##_OFFSET), \ + .balls = { bb, bt }, \ +} + +/* + * Superset of all mux modes for omap2420 + */ +static struct omap_mux __initdata omap2420_muxmodes[] = { + _OMAP2420_MUXENTRY(CAM_D0, 54, + "cam_d0", "hw_dbg2", "sti_dout", "gpio_54", + NULL, NULL, "etk_d2", NULL), + _OMAP2420_MUXENTRY(CAM_D1, 53, + "cam_d1", "hw_dbg3", "sti_din", "gpio_53", + NULL, NULL, "etk_d3", NULL), + _OMAP2420_MUXENTRY(CAM_D2, 52, + "cam_d2", "hw_dbg4", "mcbsp1_clkx", "gpio_52", + NULL, NULL, "etk_d4", NULL), + _OMAP2420_MUXENTRY(CAM_D3, 51, + "cam_d3", "hw_dbg5", "mcbsp1_dr", "gpio_51", + NULL, NULL, "etk_d5", NULL), + _OMAP2420_MUXENTRY(CAM_D4, 50, + "cam_d4", "hw_dbg6", "mcbsp1_fsr", "gpio_50", + NULL, NULL, "etk_d6", NULL), + _OMAP2420_MUXENTRY(CAM_D5, 49, + "cam_d5", "hw_dbg7", "mcbsp1_clkr", "gpio_49", + NULL, NULL, "etk_d7", NULL), + _OMAP2420_MUXENTRY(CAM_D6, 0, + "cam_d6", "hw_dbg8", NULL, NULL, + NULL, NULL, "etk_d8", NULL), + _OMAP2420_MUXENTRY(CAM_D7, 0, + "cam_d7", "hw_dbg9", NULL, NULL, + NULL, NULL, "etk_d9", NULL), + _OMAP2420_MUXENTRY(CAM_D8, 54, + "cam_d8", "hw_dbg10", NULL, "gpio_54", + NULL, NULL, "etk_d10", NULL), + _OMAP2420_MUXENTRY(CAM_D9, 53, + "cam_d9", "hw_dbg11", NULL, "gpio_53", + NULL, NULL, "etk_d11", NULL), + _OMAP2420_MUXENTRY(CAM_HS, 55, + "cam_hs", "hw_dbg1", "mcbsp1_dx", "gpio_55", + NULL, NULL, "etk_d1", NULL), + _OMAP2420_MUXENTRY(CAM_LCLK, 57, + "cam_lclk", NULL, "mcbsp_clks", "gpio_57", + NULL, NULL, "etk_c1", NULL), + _OMAP2420_MUXENTRY(CAM_VS, 56, + "cam_vs", "hw_dbg0", "mcbsp1_fsx", "gpio_56", + NULL, NULL, "etk_d0", NULL), + _OMAP2420_MUXENTRY(CAM_XCLK, 0, + "cam_xclk", NULL, "sti_clk", NULL, + NULL, NULL, "etk_c2", NULL), + _OMAP2420_MUXENTRY(DSS_ACBIAS, 48, + "dss_acbias", NULL, "mcbsp2_fsx", "gpio_48", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(DSS_DATA10, 40, + "dss_data10", NULL, NULL, "gpio_40", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(DSS_DATA11, 41, + "dss_data11", NULL, NULL, "gpio_41", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(DSS_DATA12, 42, + "dss_data12", NULL, NULL, "gpio_42", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(DSS_DATA13, 43, + "dss_data13", NULL, NULL, "gpio_43", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(DSS_DATA14, 44, + "dss_data14", NULL, NULL, "gpio_44", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(DSS_DATA15, 45, + "dss_data15", NULL, NULL, "gpio_45", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(DSS_DATA16, 46, + "dss_data16", NULL, NULL, "gpio_46", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(DSS_DATA17, 47, + "dss_data17", NULL, NULL, "gpio_47", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(DSS_DATA8, 38, + "dss_data8", NULL, NULL, "gpio_38", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(DSS_DATA9, 39, + "dss_data9", NULL, NULL, "gpio_39", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(EAC_AC_DIN, 115, + "eac_ac_din", "mcbsp2_dr", NULL, "gpio_115", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(EAC_AC_DOUT, 116, + "eac_ac_dout", "mcbsp2_dx", NULL, "gpio_116", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(EAC_AC_FS, 114, + "eac_ac_fs", "mcbsp2_fsx", NULL, "gpio_114", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(EAC_AC_MCLK, 117, + "eac_ac_mclk", NULL, NULL, "gpio_117", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(EAC_AC_RST, 118, + "eac_ac_rst", "eac_bt_din", NULL, "gpio_118", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(EAC_AC_SCLK, 113, + "eac_ac_sclk", "mcbsp2_clkx", NULL, "gpio_113", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(EAC_BT_DIN, 73, + "eac_bt_din", NULL, NULL, "gpio_73", + NULL, NULL, "etk_d9", NULL), + _OMAP2420_MUXENTRY(EAC_BT_DOUT, 74, + "eac_bt_dout", NULL, "sti_clk", "gpio_74", + NULL, NULL, "etk_d8", NULL), + _OMAP2420_MUXENTRY(EAC_BT_FS, 72, + "eac_bt_fs", NULL, NULL, "gpio_72", + NULL, NULL, "etk_d10", NULL), + _OMAP2420_MUXENTRY(EAC_BT_SCLK, 71, + "eac_bt_sclk", NULL, NULL, "gpio_71", + NULL, NULL, "etk_d11", NULL), + _OMAP2420_MUXENTRY(GPIO_119, 119, + "gpio_119", NULL, "sti_din", "gpio_119", + NULL, "sys_boot0", "etk_d12", NULL), + _OMAP2420_MUXENTRY(GPIO_120, 120, + "gpio_120", NULL, "sti_dout", "gpio_120", + "cam_d9", "sys_boot1", "etk_d13", NULL), + _OMAP2420_MUXENTRY(GPIO_121, 121, + "gpio_121", NULL, NULL, "gpio_121", + "jtag_emu2", "sys_boot2", "etk_d14", NULL), + _OMAP2420_MUXENTRY(GPIO_122, 122, + "gpio_122", NULL, NULL, "gpio_122", + "jtag_emu3", "sys_boot3", "etk_d15", NULL), + _OMAP2420_MUXENTRY(GPIO_124, 124, + "gpio_124", NULL, NULL, "gpio_124", + NULL, "sys_boot5", NULL, NULL), + _OMAP2420_MUXENTRY(GPIO_125, 125, + "gpio_125", "sys_jtagsel1", "sys_jtagsel2", "gpio_125", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPIO_36, 36, + "gpio_36", NULL, NULL, "gpio_36", + NULL, "sys_boot4", NULL, NULL), + _OMAP2420_MUXENTRY(GPIO_62, 62, + "gpio_62", "uart1_rx", "usb1_dat", "gpio_62", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPIO_6, 6, + "gpio_6", "tv_detpulse", NULL, "gpio_6", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_A10, 3, + "gpmc_a10", NULL, "sys_ndmareq5", "gpio_3", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_A1, 12, + "gpmc_a1", "dss_data18", NULL, "gpio_12", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_A2, 11, + "gpmc_a2", "dss_data19", NULL, "gpio_11", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_A3, 10, + "gpmc_a3", "dss_data20", NULL, "gpio_10", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_A4, 9, + "gpmc_a4", "dss_data21", NULL, "gpio_9", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_A5, 8, + "gpmc_a5", "dss_data22", NULL, "gpio_8", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_A6, 7, + "gpmc_a6", "dss_data23", NULL, "gpio_7", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_A7, 6, + "gpmc_a7", NULL, "sys_ndmareq2", "gpio_6", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_A8, 5, + "gpmc_a8", NULL, "sys_ndmareq3", "gpio_5", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_A9, 4, + "gpmc_a9", NULL, "sys_ndmareq4", "gpio_4", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_CLK, 21, + "gpmc_clk", NULL, NULL, "gpio_21", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_D10, 18, + "gpmc_d10", "ssi2_rdy_rx", NULL, "gpio_18", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_D11, 17, + "gpmc_d11", "ssi2_flag_rx", NULL, "gpio_17", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_D12, 16, + "gpmc_d12", "ssi2_dat_rx", NULL, "gpio_16", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_D13, 15, + "gpmc_d13", "ssi2_rdy_tx", NULL, "gpio_15", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_D14, 14, + "gpmc_d14", "ssi2_flag_tx", NULL, "gpio_14", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_D15, 13, + "gpmc_d15", "ssi2_dat_tx", NULL, "gpio_13", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_D8, 20, + "gpmc_d8", NULL, NULL, "gpio_20", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_D9, 19, + "gpmc_d9", "ssi2_wake", NULL, "gpio_19", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_NBE0, 29, + "gpmc_nbe0", NULL, NULL, "gpio_29", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_NBE1, 30, + "gpmc_nbe1", NULL, NULL, "gpio_30", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_NCS1, 22, + "gpmc_ncs1", NULL, NULL, "gpio_22", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_NCS2, 23, + "gpmc_ncs2", NULL, NULL, "gpio_23", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_NCS3, 24, + "gpmc_ncs3", "gpmc_io_dir", NULL, "gpio_24", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_NCS4, 25, + "gpmc_ncs4", NULL, NULL, "gpio_25", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_NCS5, 26, + "gpmc_ncs5", NULL, NULL, "gpio_26", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_NCS6, 27, + "gpmc_ncs6", NULL, NULL, "gpio_27", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_NCS7, 28, + "gpmc_ncs7", "gpmc_io_dir", "gpio_28", NULL, + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_NWP, 31, + "gpmc_nwp", NULL, NULL, "gpio_31", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_WAIT1, 33, + "gpmc_wait1", NULL, NULL, "gpio_33", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_WAIT2, 34, + "gpmc_wait2", NULL, NULL, "gpio_34", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(GPMC_WAIT3, 35, + "gpmc_wait3", NULL, NULL, "gpio_35", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(HDQ_SIO, 101, + "hdq_sio", "usb2_tllse0", "sys_altclk", "gpio_101", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(I2C2_SCL, 99, + "i2c2_scl", NULL, "gpt9_pwm_evt", "gpio_99", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(I2C2_SDA, 100, + "i2c2_sda", NULL, "spi2_ncs1", "gpio_100", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(JTAG_EMU0, 127, + "jtag_emu0", NULL, NULL, "gpio_127", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(JTAG_EMU1, 126, + "jtag_emu1", NULL, NULL, "gpio_126", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(MCBSP1_CLKR, 92, + "mcbsp1_clkr", "ssi2_dat_tx", "vlynq_tx1", "gpio_92", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(MCBSP1_CLKX, 98, + "mcbsp1_clkx", "ssi2_wake", "vlynq_nla", "gpio_98", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(MCBSP1_DR, 95, + "mcbsp1_dr", "ssi2_dat_rx", "vlynq_rx1", "gpio_95", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(MCBSP1_DX, 94, + "mcbsp1_dx", "ssi2_rdy_tx", "vlynq_clk", "gpio_94", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(MCBSP1_FSR, 93, + "mcbsp1_fsr", "ssi2_flag_tx", "vlynq_tx0", "gpio_93", + "spi2_ncs1", NULL, NULL, NULL), + _OMAP2420_MUXENTRY(MCBSP1_FSX, 97, + "mcbsp1_fsx", "ssi2_rdy_rx", NULL, "gpio_97", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(MCBSP2_CLKX, 12, + "mcbsp2_clkx", NULL, "dss_data23", "gpio_12", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(MCBSP2_DR, 11, + "mcbsp2_dr", NULL, "dss_data22", "gpio_11", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(MCBSP_CLKS, 96, + "mcbsp_clks", "ssi2_flag_rx", "vlynq_rx0", "gpio_96", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(MMC_CLKI, 59, + "sdmmc_clki", "ms_clki", NULL, "gpio_59", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(MMC_CLKO, 0, + "sdmmc_clko", "ms_clko", NULL, NULL, + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(MMC_CMD_DIR, 8, + "sdmmc_cmd_dir", NULL, NULL, "gpio_8", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(MMC_CMD, 0, + "sdmmc_cmd", "ms_bs", NULL, NULL, + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(MMC_DAT_DIR0, 7, + "sdmmc_dat_dir0", "ms_dat0_dir", NULL, "gpio_7", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(MMC_DAT0, 0, + "sdmmc_dat0", "ms_dat0", NULL, NULL, + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(MMC_DAT_DIR1, 78, + "sdmmc_dat_dir1", "ms_datu_dir", "uart2_rts", "gpio_78", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(MMC_DAT1, 75, + "sdmmc_dat1", "ms_dat1", NULL, "gpio_75", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(MMC_DAT_DIR2, 79, + "sdmmc_dat_dir2", "ms_datu_dir", "uart2_tx", "gpio_79", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(MMC_DAT2, 76, + "sdmmc_dat2", "ms_dat2", "uart2_cts", "gpio_76", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(MMC_DAT_DIR3, 80, + "sdmmc_dat_dir3", "ms_datu_dir", "uart2_rx", "gpio_80", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(MMC_DAT3, 77, + "sdmmc_dat3", "ms_dat3", NULL, "gpio_77", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(SDRC_A12, 2, + "sdrc_a12", NULL, NULL, "gpio_2", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(SDRC_A13, 1, + "sdrc_a13", NULL, NULL, "gpio_1", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(SDRC_A14, 0, + "sdrc_a14", NULL, NULL, "gpio_0", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(SDRC_CKE1, 38, + "sdrc_cke1", NULL, NULL, "gpio_38", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(SDRC_NCS1, 37, + "sdrc_ncs1", NULL, NULL, "gpio_37", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(SPI1_CLK, 81, + "spi1_clk", NULL, NULL, "gpio_81", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(SPI1_NCS0, 84, + "spi1_ncs0", NULL, NULL, "gpio_84", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(SPI1_NCS1, 85, + "spi1_ncs1", NULL, NULL, "gpio_85", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(SPI1_NCS2, 86, + "spi1_ncs2", NULL, NULL, "gpio_86", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(SPI1_NCS3, 87, + "spi1_ncs3", NULL, NULL, "gpio_87", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(SPI1_SIMO, 82, + "spi1_simo", NULL, NULL, "gpio_82", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(SPI1_SOMI, 83, + "spi1_somi", NULL, NULL, "gpio_83", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(SPI2_CLK, 88, + "spi2_clk", NULL, NULL, "gpio_88", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(SPI2_NCS0, 91, + "spi2_ncs0", "gpt12_pwm_evt", NULL, "gpio_91", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(SPI2_SIMO, 89, + "spi2_simo", "gpt10_pwm_evt", NULL, "gpio_89", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(SPI2_SOMI, 90, + "spi2_somi", "gpt11_pwm_evt", NULL, "gpio_90", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(SSI1_DAT_RX, 63, + "ssi1_dat_rx", "eac_md_sclk", NULL, "gpio_63", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(SSI1_DAT_TX, 59, + "ssi1_dat_tx", "uart1_tx", "usb1_se0", "gpio_59", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(SSI1_FLAG_RX, 64, + "ssi1_flag_rx", "eac_md_din", NULL, "gpio_64", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(SSI1_FLAG_TX, 25, + "ssi1_flag_tx", "uart1_rts", "usb1_rcv", "gpio_25", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(SSI1_RDY_RX, 65, + "ssi1_rdy_rx", "eac_md_dout", NULL, "gpio_65", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(SSI1_RDY_TX, 61, + "ssi1_rdy_tx", "uart1_cts", "usb1_txen", "gpio_61", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(SSI1_WAKE, 66, + "ssi1_wake", "eac_md_fs", NULL, "gpio_66", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(SYS_CLKOUT, 123, + "sys_clkout", NULL, NULL, "gpio_123", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(SYS_CLKREQ, 52, + "sys_clkreq", NULL, NULL, "gpio_52", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(SYS_NIRQ, 60, + "sys_nirq", NULL, NULL, "gpio_60", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(UART1_CTS, 32, + "uart1_cts", NULL, "dss_data18", "gpio_32", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(UART1_RTS, 8, + "uart1_rts", NULL, "dss_data19", "gpio_8", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(UART1_RX, 10, + "uart1_rx", NULL, "dss_data21", "gpio_10", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(UART1_TX, 9, + "uart1_tx", NULL, "dss_data20", "gpio_9", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(UART2_CTS, 67, + "uart2_cts", "usb1_rcv", "gpt9_pwm_evt", "gpio_67", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(UART2_RTS, 68, + "uart2_rts", "usb1_txen", "gpt10_pwm_evt", "gpio_68", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(UART2_RX, 70, + "uart2_rx", "usb1_dat", "gpt12_pwm_evt", "gpio_70", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(UART2_TX, 69, + "uart2_tx", "usb1_se0", "gpt11_pwm_evt", "gpio_69", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(UART3_CTS_RCTX, 102, + "uart3_cts_rctx", "uart3_rx_irrx", NULL, "gpio_102", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(UART3_RTS_SD, 103, + "uart3_rts_sd", "uart3_tx_irtx", NULL, "gpio_103", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(UART3_RX_IRRX, 105, + "uart3_rx_irrx", NULL, NULL, "gpio_105", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(UART3_TX_IRTX, 104, + "uart3_tx_irtx", "uart3_cts_rctx", NULL, "gpio_104", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(USB0_DAT, 112, + "usb0_dat", "uart3_rx_irrx", "uart2_rx", "gpio_112", + "uart2_tx", NULL, NULL, NULL), + _OMAP2420_MUXENTRY(USB0_PUEN, 106, + "usb0_puen", "mcbsp2_dx", NULL, "gpio_106", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(USB0_RCV, 109, + "usb0_rcv", "mcbsp2_fsx", NULL, "gpio_109", + "uart2_cts", NULL, NULL, NULL), + _OMAP2420_MUXENTRY(USB0_SE0, 111, + "usb0_se0", "uart3_tx_irtx", "uart2_tx", "gpio_111", + "uart2_rx", NULL, NULL, NULL), + _OMAP2420_MUXENTRY(USB0_TXEN, 110, + "usb0_txen", "uart3_cts_rctx", "uart2_cts", "gpio_110", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(USB0_VM, 108, + "usb0_vm", "mcbsp2_clkx", NULL, "gpio_108", + "uart2_rx", NULL, NULL, NULL), + _OMAP2420_MUXENTRY(USB0_VP, 107, + "usb0_vp", "mcbsp2_dr", NULL, "gpio_107", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(VLYNQ_CLK, 13, + "vlynq_clk", "usb2_se0", "sys_ndmareq0", "gpio_13", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(VLYNQ_NLA, 58, + "vlynq_nla", NULL, NULL, "gpio_58", + "cam_d6", NULL, NULL, NULL), + _OMAP2420_MUXENTRY(VLYNQ_RX0, 15, + "vlynq_rx0", "usb2_tllse0", NULL, "gpio_15", + "cam_d7", NULL, NULL, NULL), + _OMAP2420_MUXENTRY(VLYNQ_RX1, 14, + "vlynq_rx1", "usb2_rcv", "sys_ndmareq1", "gpio_14", + "cam_d8", NULL, NULL, NULL), + _OMAP2420_MUXENTRY(VLYNQ_TX0, 17, + "vlynq_tx0", "usb2_txen", NULL, "gpio_17", + NULL, NULL, NULL, NULL), + _OMAP2420_MUXENTRY(VLYNQ_TX1, 16, + "vlynq_tx1", "usb2_dat", "sys_clkout2", "gpio_16", + NULL, NULL, NULL, NULL), + { .reg_offset = OMAP_MUX_TERMINATOR }, +}; + +/* + * Balls for 447-pin POP package + */ +#ifdef CONFIG_DEBUG_FS +struct omap_ball __initdata omap2420_pop_ball[] = { + _OMAP2420_BALLENTRY(CAM_D0, "y4", NULL), + _OMAP2420_BALLENTRY(CAM_D1, "y3", NULL), + _OMAP2420_BALLENTRY(CAM_D2, "u7", NULL), + _OMAP2420_BALLENTRY(CAM_D3, "ab3", NULL), + _OMAP2420_BALLENTRY(CAM_D4, "v2", NULL), + _OMAP2420_BALLENTRY(CAM_D5, "ad3", NULL), + _OMAP2420_BALLENTRY(CAM_D6, "aa4", NULL), + _OMAP2420_BALLENTRY(CAM_D7, "ab4", NULL), + _OMAP2420_BALLENTRY(CAM_D8, "ac6", NULL), + _OMAP2420_BALLENTRY(CAM_D9, "ac7", NULL), + _OMAP2420_BALLENTRY(CAM_HS, "v4", NULL), + _OMAP2420_BALLENTRY(CAM_LCLK, "ad6", NULL), + _OMAP2420_BALLENTRY(CAM_VS, "p7", NULL), + _OMAP2420_BALLENTRY(CAM_XCLK, "w4", NULL), + _OMAP2420_BALLENTRY(DSS_ACBIAS, "ae8", NULL), + _OMAP2420_BALLENTRY(DSS_DATA10, "ac12", NULL), + _OMAP2420_BALLENTRY(DSS_DATA11, "ae11", NULL), + _OMAP2420_BALLENTRY(DSS_DATA12, "ae13", NULL), + _OMAP2420_BALLENTRY(DSS_DATA13, "ad13", NULL), + _OMAP2420_BALLENTRY(DSS_DATA14, "ac13", NULL), + _OMAP2420_BALLENTRY(DSS_DATA15, "y12", NULL), + _OMAP2420_BALLENTRY(DSS_DATA16, "ad14", NULL), + _OMAP2420_BALLENTRY(DSS_DATA17, "y13", NULL), + _OMAP2420_BALLENTRY(DSS_DATA8, "ad11", NULL), + _OMAP2420_BALLENTRY(DSS_DATA9, "ad12", NULL), + _OMAP2420_BALLENTRY(EAC_AC_DIN, "ad19", NULL), + _OMAP2420_BALLENTRY(EAC_AC_DOUT, "af22", NULL), + _OMAP2420_BALLENTRY(EAC_AC_FS, "ad16", NULL), + _OMAP2420_BALLENTRY(EAC_AC_MCLK, "y17", NULL), + _OMAP2420_BALLENTRY(EAC_AC_RST, "ae22", NULL), + _OMAP2420_BALLENTRY(EAC_AC_SCLK, "ac18", NULL), + _OMAP2420_BALLENTRY(EAC_BT_DIN, "u8", NULL), + _OMAP2420_BALLENTRY(EAC_BT_DOUT, "ad5", NULL), + _OMAP2420_BALLENTRY(EAC_BT_FS, "w7", NULL), + _OMAP2420_BALLENTRY(EAC_BT_SCLK, "ad4", NULL), + _OMAP2420_BALLENTRY(GPIO_119, "af6", NULL), + _OMAP2420_BALLENTRY(GPIO_120, "af4", NULL), + _OMAP2420_BALLENTRY(GPIO_121, "ae6", NULL), + _OMAP2420_BALLENTRY(GPIO_122, "w3", NULL), + _OMAP2420_BALLENTRY(GPIO_124, "y19", NULL), + _OMAP2420_BALLENTRY(GPIO_125, "ae24", NULL), + _OMAP2420_BALLENTRY(GPIO_36, "y18", NULL), + _OMAP2420_BALLENTRY(GPIO_6, "d6", NULL), + _OMAP2420_BALLENTRY(GPIO_62, "ad18", NULL), + _OMAP2420_BALLENTRY(GPMC_A1, "m8", NULL), + _OMAP2420_BALLENTRY(GPMC_A10, "d5", NULL), + _OMAP2420_BALLENTRY(GPMC_A2, "w9", NULL), + _OMAP2420_BALLENTRY(GPMC_A3, "af10", NULL), + _OMAP2420_BALLENTRY(GPMC_A4, "w8", NULL), + _OMAP2420_BALLENTRY(GPMC_A5, "ae16", NULL), + _OMAP2420_BALLENTRY(GPMC_A6, "af9", NULL), + _OMAP2420_BALLENTRY(GPMC_A7, "e4", NULL), + _OMAP2420_BALLENTRY(GPMC_A8, "j7", NULL), + _OMAP2420_BALLENTRY(GPMC_A9, "ae18", NULL), + _OMAP2420_BALLENTRY(GPMC_CLK, "p1", "l1"), + _OMAP2420_BALLENTRY(GPMC_D10, "t1", "n1"), + _OMAP2420_BALLENTRY(GPMC_D11, "u2", "p2"), + _OMAP2420_BALLENTRY(GPMC_D12, "u1", "p1"), + _OMAP2420_BALLENTRY(GPMC_D13, "p2", "m1"), + _OMAP2420_BALLENTRY(GPMC_D14, "h2", "j2"), + _OMAP2420_BALLENTRY(GPMC_D15, "h1", "k2"), + _OMAP2420_BALLENTRY(GPMC_D8, "v1", "r1"), + _OMAP2420_BALLENTRY(GPMC_D9, "y1", "t1"), + _OMAP2420_BALLENTRY(GPMC_NBE0, "af12", "aa10"), + _OMAP2420_BALLENTRY(GPMC_NBE1, "u3", NULL), + _OMAP2420_BALLENTRY(GPMC_NCS1, "af14", "w1"), + _OMAP2420_BALLENTRY(GPMC_NCS2, "g4", NULL), + _OMAP2420_BALLENTRY(GPMC_NCS3, "t8", NULL), + _OMAP2420_BALLENTRY(GPMC_NCS4, "h8", NULL), + _OMAP2420_BALLENTRY(GPMC_NCS5, "k3", NULL), + _OMAP2420_BALLENTRY(GPMC_NCS6, "m7", NULL), + _OMAP2420_BALLENTRY(GPMC_NCS7, "p3", NULL), + _OMAP2420_BALLENTRY(GPMC_NWP, "ae15", "y5"), + _OMAP2420_BALLENTRY(GPMC_WAIT1, "ae20", "y8"), + _OMAP2420_BALLENTRY(GPMC_WAIT2, "n2", NULL), + _OMAP2420_BALLENTRY(GPMC_WAIT3, "t4", NULL), + _OMAP2420_BALLENTRY(HDQ_SIO, "t23", NULL), + _OMAP2420_BALLENTRY(I2C2_SCL, "l2", NULL), + _OMAP2420_BALLENTRY(I2C2_SDA, "k19", NULL), + _OMAP2420_BALLENTRY(JTAG_EMU0, "n24", NULL), + _OMAP2420_BALLENTRY(JTAG_EMU1, "ac22", NULL), + _OMAP2420_BALLENTRY(MCBSP1_CLKR, "y24", NULL), + _OMAP2420_BALLENTRY(MCBSP1_CLKX, "t19", NULL), + _OMAP2420_BALLENTRY(MCBSP1_DR, "u23", NULL), + _OMAP2420_BALLENTRY(MCBSP1_DX, "r24", NULL), + _OMAP2420_BALLENTRY(MCBSP1_FSR, "r20", NULL), + _OMAP2420_BALLENTRY(MCBSP1_FSX, "r23", NULL), + _OMAP2420_BALLENTRY(MCBSP2_CLKX, "t24", NULL), + _OMAP2420_BALLENTRY(MCBSP2_DR, "p20", NULL), + _OMAP2420_BALLENTRY(MCBSP_CLKS, "p23", NULL), + _OMAP2420_BALLENTRY(MMC_CLKI, "c23", NULL), + _OMAP2420_BALLENTRY(MMC_CLKO, "h23", NULL), + _OMAP2420_BALLENTRY(MMC_CMD, "j23", NULL), + _OMAP2420_BALLENTRY(MMC_CMD_DIR, "j24", NULL), + _OMAP2420_BALLENTRY(MMC_DAT0, "h17", NULL), + _OMAP2420_BALLENTRY(MMC_DAT_DIR0, "f23", NULL), + _OMAP2420_BALLENTRY(MMC_DAT1, "g19", NULL), + _OMAP2420_BALLENTRY(MMC_DAT_DIR1, "d23", NULL), + _OMAP2420_BALLENTRY(MMC_DAT2, "h20", NULL), + _OMAP2420_BALLENTRY(MMC_DAT_DIR2, "g23", NULL), + _OMAP2420_BALLENTRY(MMC_DAT3, "d24", NULL), + _OMAP2420_BALLENTRY(MMC_DAT_DIR3, "e23", NULL), + _OMAP2420_BALLENTRY(SDRC_A12, "w26", "r21"), + _OMAP2420_BALLENTRY(SDRC_A13, "w25", "aa15"), + _OMAP2420_BALLENTRY(SDRC_A14, "aa26", "y12"), + _OMAP2420_BALLENTRY(SDRC_CKE1, "ae25", "y13"), + _OMAP2420_BALLENTRY(SDRC_NCS1, "y25", "t20"), + _OMAP2420_BALLENTRY(SPI1_CLK, "y23", NULL), + _OMAP2420_BALLENTRY(SPI1_NCS0, "w24", NULL), + _OMAP2420_BALLENTRY(SPI1_NCS1, "w23", NULL), + _OMAP2420_BALLENTRY(SPI1_NCS2, "v23", NULL), + _OMAP2420_BALLENTRY(SPI1_NCS3, "u20", NULL), + _OMAP2420_BALLENTRY(SPI1_SIMO, "h10", NULL), + _OMAP2420_BALLENTRY(SPI1_SOMI, "v19", NULL), + _OMAP2420_BALLENTRY(SPI2_CLK, "v24", NULL), + _OMAP2420_BALLENTRY(SPI2_NCS0, "aa24", NULL), + _OMAP2420_BALLENTRY(SPI2_SIMO, "u24", NULL), + _OMAP2420_BALLENTRY(SPI2_SOMI, "v25", NULL), + _OMAP2420_BALLENTRY(SSI1_DAT_RX, "w15", NULL), + _OMAP2420_BALLENTRY(SSI1_DAT_TX, "w13", NULL), + _OMAP2420_BALLENTRY(SSI1_FLAG_RX, "af11", NULL), + _OMAP2420_BALLENTRY(SSI1_FLAG_TX, "ac15", NULL), + _OMAP2420_BALLENTRY(SSI1_RDY_RX, "ac16", NULL), + _OMAP2420_BALLENTRY(SSI1_RDY_TX, "af15", NULL), + _OMAP2420_BALLENTRY(SSI1_WAKE, "ad15", NULL), + _OMAP2420_BALLENTRY(SYS_CLKOUT, "ae19", NULL), + _OMAP2420_BALLENTRY(SYS_CLKREQ, "ad20", NULL), + _OMAP2420_BALLENTRY(SYS_NIRQ, "y20", NULL), + _OMAP2420_BALLENTRY(UART1_CTS, "g20", NULL), + _OMAP2420_BALLENTRY(UART1_RTS, "k20", NULL), + _OMAP2420_BALLENTRY(UART1_RX, "t20", NULL), + _OMAP2420_BALLENTRY(UART1_TX, "h12", NULL), + _OMAP2420_BALLENTRY(UART2_CTS, "ac24", NULL), + _OMAP2420_BALLENTRY(UART2_RTS, "w20", NULL), + _OMAP2420_BALLENTRY(UART2_RX, "ad24", NULL), + _OMAP2420_BALLENTRY(UART2_TX, "ab24", NULL), + _OMAP2420_BALLENTRY(UART3_CTS_RCTX, "k24", NULL), + _OMAP2420_BALLENTRY(UART3_RTS_SD, "m20", NULL), + _OMAP2420_BALLENTRY(UART3_RX_IRRX, "h24", NULL), + _OMAP2420_BALLENTRY(UART3_TX_IRTX, "g24", NULL), + _OMAP2420_BALLENTRY(USB0_DAT, "j25", NULL), + _OMAP2420_BALLENTRY(USB0_PUEN, "l23", NULL), + _OMAP2420_BALLENTRY(USB0_RCV, "k23", NULL), + _OMAP2420_BALLENTRY(USB0_SE0, "l24", NULL), + _OMAP2420_BALLENTRY(USB0_TXEN, "m24", NULL), + _OMAP2420_BALLENTRY(USB0_VM, "n23", NULL), + _OMAP2420_BALLENTRY(USB0_VP, "m23", NULL), + _OMAP2420_BALLENTRY(VLYNQ_CLK, "w12", NULL), + _OMAP2420_BALLENTRY(VLYNQ_NLA, "ae10", NULL), + _OMAP2420_BALLENTRY(VLYNQ_RX0, "ad7", NULL), + _OMAP2420_BALLENTRY(VLYNQ_RX1, "w10", NULL), + _OMAP2420_BALLENTRY(VLYNQ_TX0, "y15", NULL), + _OMAP2420_BALLENTRY(VLYNQ_TX1, "w14", NULL), + { .reg_offset = OMAP_MUX_TERMINATOR }, +}; +#else +#define omap2420_pop_ball NULL +#endif + +int __init omap2420_mux_init(struct omap_board_mux *board_subset, int flags) +{ + struct omap_ball *package_balls = NULL; + + switch (flags & OMAP_PACKAGE_MASK) { + case OMAP_PACKAGE_ZAC: + package_balls = omap2420_pop_ball; + break; + case OMAP_PACKAGE_ZAF: + /* REVISIT: Please add data */ + default: + pr_warning("mux: No ball data available for omap2420 package\n"); + } + + return omap_mux_init(OMAP2420_CONTROL_PADCONF_MUX_PBASE, + OMAP2420_CONTROL_PADCONF_MUX_SIZE, + omap2420_muxmodes, NULL, board_subset, + package_balls); +} diff --git a/arch/arm/mach-omap2/mux2420.h b/arch/arm/mach-omap2/mux2420.h new file mode 100644 index 00000000000..0f555aa847b --- /dev/null +++ b/arch/arm/mach-omap2/mux2420.h @@ -0,0 +1,282 @@ +/* + * Copyright (C) 2009 Nokia + * Copyright (C) 2009 Texas Instruments + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#define OMAP2420_CONTROL_PADCONF_MUX_PBASE 0x48000030LU + +#define OMAP2420_MUX(mode0, mux_value) \ +{ \ + .reg_offset = (OMAP2420_CONTROL_PADCONF_##mode0##_OFFSET), \ + .value = (mux_value), \ +} + +/* + * OMAP2420 CONTROL_PADCONF* register offsets for pin-muxing + * + * Extracted from the TRM. Add 0x48000030 to these values to get the + * absolute addresses. The name in the macro is the mode-0 name of + * the pin. NOTE: These registers are 8-bits wide. + */ +#define OMAP2420_CONTROL_PADCONF_SDRC_A14_OFFSET 0x000 +#define OMAP2420_CONTROL_PADCONF_SDRC_A13_OFFSET 0x001 +#define OMAP2420_CONTROL_PADCONF_SDRC_A12_OFFSET 0x002 +#define OMAP2420_CONTROL_PADCONF_SDRC_BA1_OFFSET 0x003 +#define OMAP2420_CONTROL_PADCONF_SDRC_BA0_OFFSET 0x004 +#define OMAP2420_CONTROL_PADCONF_SDRC_A11_OFFSET 0x005 +#define OMAP2420_CONTROL_PADCONF_SDRC_A10_OFFSET 0x006 +#define OMAP2420_CONTROL_PADCONF_SDRC_A9_OFFSET 0x007 +#define OMAP2420_CONTROL_PADCONF_SDRC_A8_OFFSET 0x008 +#define OMAP2420_CONTROL_PADCONF_SDRC_A7_OFFSET 0x009 +#define OMAP2420_CONTROL_PADCONF_SDRC_A6_OFFSET 0x00a +#define OMAP2420_CONTROL_PADCONF_SDRC_A5_OFFSET 0x00b +#define OMAP2420_CONTROL_PADCONF_SDRC_A4_OFFSET 0x00c +#define OMAP2420_CONTROL_PADCONF_SDRC_A3_OFFSET 0x00d +#define OMAP2420_CONTROL_PADCONF_SDRC_A2_OFFSET 0x00e +#define OMAP2420_CONTROL_PADCONF_SDRC_A1_OFFSET 0x00f +#define OMAP2420_CONTROL_PADCONF_SDRC_A0_OFFSET 0x010 +#define OMAP2420_CONTROL_PADCONF_SDRC_D31_OFFSET 0x021 +#define OMAP2420_CONTROL_PADCONF_SDRC_D30_OFFSET 0x022 +#define OMAP2420_CONTROL_PADCONF_SDRC_D29_OFFSET 0x023 +#define OMAP2420_CONTROL_PADCONF_SDRC_D28_OFFSET 0x024 +#define OMAP2420_CONTROL_PADCONF_SDRC_D27_OFFSET 0x025 +#define OMAP2420_CONTROL_PADCONF_SDRC_D26_OFFSET 0x026 +#define OMAP2420_CONTROL_PADCONF_SDRC_D25_OFFSET 0x027 +#define OMAP2420_CONTROL_PADCONF_SDRC_D24_OFFSET 0x028 +#define OMAP2420_CONTROL_PADCONF_SDRC_D23_OFFSET 0x029 +#define OMAP2420_CONTROL_PADCONF_SDRC_D22_OFFSET 0x02a +#define OMAP2420_CONTROL_PADCONF_SDRC_D21_OFFSET 0x02b +#define OMAP2420_CONTROL_PADCONF_SDRC_D20_OFFSET 0x02c +#define OMAP2420_CONTROL_PADCONF_SDRC_D19_OFFSET 0x02d +#define OMAP2420_CONTROL_PADCONF_SDRC_D18_OFFSET 0x02e +#define OMAP2420_CONTROL_PADCONF_SDRC_D17_OFFSET 0x02f +#define OMAP2420_CONTROL_PADCONF_SDRC_D16_OFFSET 0x030 +#define OMAP2420_CONTROL_PADCONF_SDRC_D15_OFFSET 0x031 +#define OMAP2420_CONTROL_PADCONF_SDRC_D14_OFFSET 0x032 +#define OMAP2420_CONTROL_PADCONF_SDRC_D13_OFFSET 0x033 +#define OMAP2420_CONTROL_PADCONF_SDRC_D12_OFFSET 0x034 +#define OMAP2420_CONTROL_PADCONF_SDRC_D11_OFFSET 0x035 +#define OMAP2420_CONTROL_PADCONF_SDRC_D10_OFFSET 0x036 +#define OMAP2420_CONTROL_PADCONF_SDRC_D9_OFFSET 0x037 +#define OMAP2420_CONTROL_PADCONF_SDRC_D8_OFFSET 0x038 +#define OMAP2420_CONTROL_PADCONF_SDRC_D7_OFFSET 0x039 +#define OMAP2420_CONTROL_PADCONF_SDRC_D6_OFFSET 0x03a +#define OMAP2420_CONTROL_PADCONF_SDRC_D5_OFFSET 0x03b +#define OMAP2420_CONTROL_PADCONF_SDRC_D4_OFFSET 0x03c +#define OMAP2420_CONTROL_PADCONF_SDRC_D3_OFFSET 0x03d +#define OMAP2420_CONTROL_PADCONF_SDRC_D2_OFFSET 0x03e +#define OMAP2420_CONTROL_PADCONF_SDRC_D1_OFFSET 0x03f +#define OMAP2420_CONTROL_PADCONF_SDRC_D0_OFFSET 0x040 +#define OMAP2420_CONTROL_PADCONF_GPMC_A10_OFFSET 0x041 +#define OMAP2420_CONTROL_PADCONF_GPMC_A9_OFFSET 0x042 +#define OMAP2420_CONTROL_PADCONF_GPMC_A8_OFFSET 0x043 +#define OMAP2420_CONTROL_PADCONF_GPMC_A7_OFFSET 0x044 +#define OMAP2420_CONTROL_PADCONF_GPMC_A6_OFFSET 0x045 +#define OMAP2420_CONTROL_PADCONF_GPMC_A5_OFFSET 0x046 +#define OMAP2420_CONTROL_PADCONF_GPMC_A4_OFFSET 0x047 +#define OMAP2420_CONTROL_PADCONF_GPMC_A3_OFFSET 0x048 +#define OMAP2420_CONTROL_PADCONF_GPMC_A2_OFFSET 0x049 +#define OMAP2420_CONTROL_PADCONF_GPMC_A1_OFFSET 0x04a +#define OMAP2420_CONTROL_PADCONF_GPMC_D15_OFFSET 0x04b +#define OMAP2420_CONTROL_PADCONF_GPMC_D14_OFFSET 0x04c +#define OMAP2420_CONTROL_PADCONF_GPMC_D13_OFFSET 0x04d +#define OMAP2420_CONTROL_PADCONF_GPMC_D12_OFFSET 0x04e +#define OMAP2420_CONTROL_PADCONF_GPMC_D11_OFFSET 0x04f +#define OMAP2420_CONTROL_PADCONF_GPMC_D10_OFFSET 0x050 +#define OMAP2420_CONTROL_PADCONF_GPMC_D9_OFFSET 0x051 +#define OMAP2420_CONTROL_PADCONF_GPMC_D8_OFFSET 0x052 +#define OMAP2420_CONTROL_PADCONF_GPMC_D7_OFFSET 0x053 +#define OMAP2420_CONTROL_PADCONF_GPMC_D6_OFFSET 0x054 +#define OMAP2420_CONTROL_PADCONF_GPMC_D5_OFFSET 0x055 +#define OMAP2420_CONTROL_PADCONF_GPMC_D4_OFFSET 0x056 +#define OMAP2420_CONTROL_PADCONF_GPMC_D3_OFFSET 0x057 +#define OMAP2420_CONTROL_PADCONF_GPMC_D2_OFFSET 0x058 +#define OMAP2420_CONTROL_PADCONF_GPMC_D1_OFFSET 0x059 +#define OMAP2420_CONTROL_PADCONF_GPMC_D0_OFFSET 0x05a +#define OMAP2420_CONTROL_PADCONF_GPMC_CLK_OFFSET 0x05b +#define OMAP2420_CONTROL_PADCONF_GPMC_NCS0_OFFSET 0x05c +#define OMAP2420_CONTROL_PADCONF_GPMC_NCS1_OFFSET 0x05d +#define OMAP2420_CONTROL_PADCONF_GPMC_NCS2_OFFSET 0x05e +#define OMAP2420_CONTROL_PADCONF_GPMC_NCS3_OFFSET 0x05f +#define OMAP2420_CONTROL_PADCONF_GPMC_NCS4_OFFSET 0x060 +#define OMAP2420_CONTROL_PADCONF_GPMC_NCS5_OFFSET 0x061 +#define OMAP2420_CONTROL_PADCONF_GPMC_NCS6_OFFSET 0x062 +#define OMAP2420_CONTROL_PADCONF_GPMC_NCS7_OFFSET 0x063 +#define OMAP2420_CONTROL_PADCONF_GPMC_NALE_ALE_OFFSET 0x064 +#define OMAP2420_CONTROL_PADCONF_GPMC_NOE_OFFSET 0x065 +#define OMAP2420_CONTROL_PADCONF_GPMC_NWE_OFFSET 0x066 +#define OMAP2420_CONTROL_PADCONF_GPMC_NBE0_OFFSET 0x067 +#define OMAP2420_CONTROL_PADCONF_GPMC_NBE1_OFFSET 0x068 +#define OMAP2420_CONTROL_PADCONF_GPMC_NWP_OFFSET 0x069 +#define OMAP2420_CONTROL_PADCONF_GPMC_WAIT0_OFFSET 0x06a +#define OMAP2420_CONTROL_PADCONF_GPMC_WAIT1_OFFSET 0x06b +#define OMAP2420_CONTROL_PADCONF_GPMC_WAIT2_OFFSET 0x06c +#define OMAP2420_CONTROL_PADCONF_GPMC_WAIT3_OFFSET 0x06d +#define OMAP2420_CONTROL_PADCONF_SDRC_CLK_OFFSET 0x06e +#define OMAP2420_CONTROL_PADCONF_SDRC_NCLK_OFFSET 0x06f +#define OMAP2420_CONTROL_PADCONF_SDRC_NCS0_OFFSET 0x070 +#define OMAP2420_CONTROL_PADCONF_SDRC_NCS1_OFFSET 0x071 +#define OMAP2420_CONTROL_PADCONF_SDRC_CKE0_OFFSET 0x072 +#define OMAP2420_CONTROL_PADCONF_SDRC_CKE1_OFFSET 0x073 +#define OMAP2420_CONTROL_PADCONF_SDRC_NRAS_OFFSET 0x074 +#define OMAP2420_CONTROL_PADCONF_SDRC_NCAS_OFFSET 0x075 +#define OMAP2420_CONTROL_PADCONF_SDRC_NWE_OFFSET 0x076 +#define OMAP2420_CONTROL_PADCONF_SDRC_DM0_OFFSET 0x077 +#define OMAP2420_CONTROL_PADCONF_SDRC_DM1_OFFSET 0x078 +#define OMAP2420_CONTROL_PADCONF_SDRC_DM2_OFFSET 0x079 +#define OMAP2420_CONTROL_PADCONF_SDRC_DM3_OFFSET 0x07a +#define OMAP2420_CONTROL_PADCONF_SDRC_DQS0_OFFSET 0x07f +#define OMAP2420_CONTROL_PADCONF_SDRC_DQS1_OFFSET 0x080 +#define OMAP2420_CONTROL_PADCONF_SDRC_DQS2_OFFSET 0x081 +#define OMAP2420_CONTROL_PADCONF_SDRC_DQS3_OFFSET 0x082 +#define OMAP2420_CONTROL_PADCONF_DSS_DATA0_OFFSET 0x083 +#define OMAP2420_CONTROL_PADCONF_DSS_DATA1_OFFSET 0x084 +#define OMAP2420_CONTROL_PADCONF_DSS_DATA2_OFFSET 0x085 +#define OMAP2420_CONTROL_PADCONF_DSS_DATA3_OFFSET 0x086 +#define OMAP2420_CONTROL_PADCONF_DSS_DATA4_OFFSET 0x087 +#define OMAP2420_CONTROL_PADCONF_DSS_DATA5_OFFSET 0x088 +#define OMAP2420_CONTROL_PADCONF_DSS_DATA6_OFFSET 0x089 +#define OMAP2420_CONTROL_PADCONF_DSS_DATA7_OFFSET 0x08a +#define OMAP2420_CONTROL_PADCONF_DSS_DATA8_OFFSET 0x08b +#define OMAP2420_CONTROL_PADCONF_DSS_DATA9_OFFSET 0x08c +#define OMAP2420_CONTROL_PADCONF_DSS_DATA10_OFFSET 0x08d +#define OMAP2420_CONTROL_PADCONF_DSS_DATA11_OFFSET 0x08e +#define OMAP2420_CONTROL_PADCONF_DSS_DATA12_OFFSET 0x08f +#define OMAP2420_CONTROL_PADCONF_DSS_DATA13_OFFSET 0x090 +#define OMAP2420_CONTROL_PADCONF_DSS_DATA14_OFFSET 0x091 +#define OMAP2420_CONTROL_PADCONF_DSS_DATA15_OFFSET 0x092 +#define OMAP2420_CONTROL_PADCONF_DSS_DATA16_OFFSET 0x093 +#define OMAP2420_CONTROL_PADCONF_DSS_DATA17_OFFSET 0x094 +#define OMAP2420_CONTROL_PADCONF_UART1_CTS_OFFSET 0x095 +#define OMAP2420_CONTROL_PADCONF_UART1_RTS_OFFSET 0x096 +#define OMAP2420_CONTROL_PADCONF_UART1_TX_OFFSET 0x097 +#define OMAP2420_CONTROL_PADCONF_UART1_RX_OFFSET 0x098 +#define OMAP2420_CONTROL_PADCONF_MCBSP2_DR_OFFSET 0x099 +#define OMAP2420_CONTROL_PADCONF_MCBSP2_CLKX_OFFSET 0x09a +#define OMAP2420_CONTROL_PADCONF_DSS_PCL_OFFSET 0x09b +#define OMAP2420_CONTROL_PADCONF_DSS_VSYNC_OFFSET 0x09c +#define OMAP2420_CONTROL_PADCONF_DSS_HSYNC_OFFSET 0x09d +#define OMAP2420_CONTROL_PADCONF_DSS_ACBIAS_OFFSET 0x09e +#define OMAP2420_CONTROL_PADCONF_CAM_D9_OFFSET 0x09f +#define OMAP2420_CONTROL_PADCONF_CAM_D8_OFFSET 0x0a0 +#define OMAP2420_CONTROL_PADCONF_CAM_D7_OFFSET 0x0a1 +#define OMAP2420_CONTROL_PADCONF_CAM_D6_OFFSET 0x0a2 +#define OMAP2420_CONTROL_PADCONF_CAM_D5_OFFSET 0x0a3 +#define OMAP2420_CONTROL_PADCONF_CAM_D4_OFFSET 0x0a4 +#define OMAP2420_CONTROL_PADCONF_CAM_D3_OFFSET 0x0a5 +#define OMAP2420_CONTROL_PADCONF_CAM_D2_OFFSET 0x0a6 +#define OMAP2420_CONTROL_PADCONF_CAM_D1_OFFSET 0x0a7 +#define OMAP2420_CONTROL_PADCONF_CAM_D0_OFFSET 0x0a8 +#define OMAP2420_CONTROL_PADCONF_CAM_HS_OFFSET 0x0a9 +#define OMAP2420_CONTROL_PADCONF_CAM_VS_OFFSET 0x0aa +#define OMAP2420_CONTROL_PADCONF_CAM_LCLK_OFFSET 0x0ab +#define OMAP2420_CONTROL_PADCONF_CAM_XCLK_OFFSET 0x0ac +#define OMAP2420_CONTROL_PADCONF_SSI1_DAT_TX_OFFSET 0x0ad +#define OMAP2420_CONTROL_PADCONF_SSI1_FLAG_TX_OFFSET 0x0ae +#define OMAP2420_CONTROL_PADCONF_SSI1_RDY_TX_OFFSET 0x0af +#define OMAP2420_CONTROL_PADCONF_GPIO_62_OFFSET 0x0b0 +#define OMAP2420_CONTROL_PADCONF_SSI1_DAT_RX_OFFSET 0x0b1 +#define OMAP2420_CONTROL_PADCONF_SSI1_FLAG_RX_OFFSET 0x0b2 +#define OMAP2420_CONTROL_PADCONF_SSI1_RDY_RX_OFFSET 0x0b3 +#define OMAP2420_CONTROL_PADCONF_SSI1_WAKE_OFFSET 0x0b4 +#define OMAP2420_CONTROL_PADCONF_VLYNQ_CLK_OFFSET 0x0b5 +#define OMAP2420_CONTROL_PADCONF_VLYNQ_RX1_OFFSET 0x0b6 +#define OMAP2420_CONTROL_PADCONF_VLYNQ_RX0_OFFSET 0x0b7 +#define OMAP2420_CONTROL_PADCONF_VLYNQ_TX1_OFFSET 0x0b8 +#define OMAP2420_CONTROL_PADCONF_VLYNQ_TX0_OFFSET 0x0b9 +#define OMAP2420_CONTROL_PADCONF_VLYNQ_NLA_OFFSET 0x0ba +#define OMAP2420_CONTROL_PADCONF_UART2_CTS_OFFSET 0x0bb +#define OMAP2420_CONTROL_PADCONF_UART2_RTS_OFFSET 0x0bc +#define OMAP2420_CONTROL_PADCONF_UART2_TX_OFFSET 0x0bd +#define OMAP2420_CONTROL_PADCONF_UART2_RX_OFFSET 0x0be +#define OMAP2420_CONTROL_PADCONF_EAC_BT_SCLK_OFFSET 0x0bf +#define OMAP2420_CONTROL_PADCONF_EAC_BT_FS_OFFSET 0x0c0 +#define OMAP2420_CONTROL_PADCONF_EAC_BT_DIN_OFFSET 0x0c1 +#define OMAP2420_CONTROL_PADCONF_EAC_BT_DOUT_OFFSET 0x0c2 +#define OMAP2420_CONTROL_PADCONF_MMC_CLKO_OFFSET 0x0c3 +#define OMAP2420_CONTROL_PADCONF_MMC_CMD_OFFSET 0x0c4 +#define OMAP2420_CONTROL_PADCONF_MMC_DAT0_OFFSET 0x0c5 +#define OMAP2420_CONTROL_PADCONF_MMC_DAT1_OFFSET 0x0c6 +#define OMAP2420_CONTROL_PADCONF_MMC_DAT2_OFFSET 0x0c7 +#define OMAP2420_CONTROL_PADCONF_MMC_DAT3_OFFSET 0x0c8 +#define OMAP2420_CONTROL_PADCONF_MMC_DAT_DIR0_OFFSET 0x0c9 +#define OMAP2420_CONTROL_PADCONF_MMC_DAT_DIR1_OFFSET 0x0ca +#define OMAP2420_CONTROL_PADCONF_MMC_DAT_DIR2_OFFSET 0x0cb +#define OMAP2420_CONTROL_PADCONF_MMC_DAT_DIR3_OFFSET 0x0cc +#define OMAP2420_CONTROL_PADCONF_MMC_CMD_DIR_OFFSET 0x0cd +#define OMAP2420_CONTROL_PADCONF_MMC_CLKI_OFFSET 0x0ce +#define OMAP2420_CONTROL_PADCONF_SPI1_CLK_OFFSET 0x0cf +#define OMAP2420_CONTROL_PADCONF_SPI1_SIMO_OFFSET 0x0d0 +#define OMAP2420_CONTROL_PADCONF_SPI1_SOMI_OFFSET 0x0d1 +#define OMAP2420_CONTROL_PADCONF_SPI1_NCS0_OFFSET 0x0d2 +#define OMAP2420_CONTROL_PADCONF_SPI1_NCS1_OFFSET 0x0d3 +#define OMAP2420_CONTROL_PADCONF_SPI1_NCS2_OFFSET 0x0d4 +#define OMAP2420_CONTROL_PADCONF_SPI1_NCS3_OFFSET 0x0d5 +#define OMAP2420_CONTROL_PADCONF_SPI2_CLK_OFFSET 0x0d6 +#define OMAP2420_CONTROL_PADCONF_SPI2_SIMO_OFFSET 0x0d7 +#define OMAP2420_CONTROL_PADCONF_SPI2_SOMI_OFFSET 0x0d8 +#define OMAP2420_CONTROL_PADCONF_SPI2_NCS0_OFFSET 0x0d9 +#define OMAP2420_CONTROL_PADCONF_MCBSP1_CLKR_OFFSET 0x0da +#define OMAP2420_CONTROL_PADCONF_MCBSP1_FSR_OFFSET 0x0db +#define OMAP2420_CONTROL_PADCONF_MCBSP1_DX_OFFSET 0x0dc +#define OMAP2420_CONTROL_PADCONF_MCBSP1_DR_OFFSET 0x0dd +#define OMAP2420_CONTROL_PADCONF_MCBSP_CLKS_OFFSET 0x0de +#define OMAP2420_CONTROL_PADCONF_MCBSP1_FSX_OFFSET 0x0df +#define OMAP2420_CONTROL_PADCONF_MCBSP1_CLKX_OFFSET 0x0e0 +#define OMAP2420_CONTROL_PADCONF_I2C1_SCL_OFFSET 0x0e1 +#define OMAP2420_CONTROL_PADCONF_I2C1_SDA_OFFSET 0x0e2 +#define OMAP2420_CONTROL_PADCONF_I2C2_SCL_OFFSET 0x0e3 +#define OMAP2420_CONTROL_PADCONF_I2C2_SDA_OFFSET 0x0e4 +#define OMAP2420_CONTROL_PADCONF_HDQ_SIO_OFFSET 0x0e5 +#define OMAP2420_CONTROL_PADCONF_UART3_CTS_RCTX_OFFSET 0x0e6 +#define OMAP2420_CONTROL_PADCONF_UART3_RTS_SD_OFFSET 0x0e7 +#define OMAP2420_CONTROL_PADCONF_UART3_TX_IRTX_OFFSET 0x0e8 +#define OMAP2420_CONTROL_PADCONF_UART3_RX_IRRX_OFFSET 0x0e9 +#define OMAP2420_CONTROL_PADCONF_TV_CVBS_OFFSET 0x0ea +#define OMAP2420_CONTROL_PADCONF_TV_VREF_OFFSET 0x0eb +#define OMAP2420_CONTROL_PADCONF_TV_RREF_OFFSET 0x0ec +#define OMAP2420_CONTROL_PADCONF_USB0_PUEN_OFFSET 0x0ed +#define OMAP2420_CONTROL_PADCONF_USB0_VP_OFFSET 0x0ee +#define OMAP2420_CONTROL_PADCONF_USB0_VM_OFFSET 0x0ef +#define OMAP2420_CONTROL_PADCONF_USB0_RCV_OFFSET 0x0f0 +#define OMAP2420_CONTROL_PADCONF_USB0_TXEN_OFFSET 0x0f1 +#define OMAP2420_CONTROL_PADCONF_USB0_SE0_OFFSET 0x0f2 +#define OMAP2420_CONTROL_PADCONF_USB0_DAT_OFFSET 0x0f3 +#define OMAP2420_CONTROL_PADCONF_EAC_AC_SCLK_OFFSET 0x0f4 +#define OMAP2420_CONTROL_PADCONF_EAC_AC_FS_OFFSET 0x0f5 +#define OMAP2420_CONTROL_PADCONF_EAC_AC_DIN_OFFSET 0x0f6 +#define OMAP2420_CONTROL_PADCONF_EAC_AC_DOUT_OFFSET 0x0f7 +#define OMAP2420_CONTROL_PADCONF_EAC_AC_MCLK_OFFSET 0x0f8 +#define OMAP2420_CONTROL_PADCONF_EAC_AC_RST_OFFSET 0x0f9 +#define OMAP2420_CONTROL_PADCONF_SYS_NRESPWRON_OFFSET 0x0fa +#define OMAP2420_CONTROL_PADCONF_SYS_NRESWARM_OFFSET 0x0fb +#define OMAP2420_CONTROL_PADCONF_SYS_NIRQ_OFFSET 0x0fc +#define OMAP2420_CONTROL_PADCONF_SYS_NV_OFFSET 0x0fd +#define OMAP2420_CONTROL_PADCONF_GPIO_119_OFFSET 0x0fe +#define OMAP2420_CONTROL_PADCONF_GPIO_120_OFFSET 0x0ff +#define OMAP2420_CONTROL_PADCONF_GPIO_121_OFFSET 0x100 +#define OMAP2420_CONTROL_PADCONF_GPIO_122_OFFSET 0x101 +#define OMAP2420_CONTROL_PADCONF_SYS_32K_OFFSET 0x102 +#define OMAP2420_CONTROL_PADCONF_SYS_XTALIN_OFFSET 0x103 +#define OMAP2420_CONTROL_PADCONF_SYS_XTALOUT_OFFSET 0x104 +#define OMAP2420_CONTROL_PADCONF_GPIO_36_OFFSET 0x105 +#define OMAP2420_CONTROL_PADCONF_SYS_CLKREQ_OFFSET 0x106 +#define OMAP2420_CONTROL_PADCONF_SYS_CLKOUT_OFFSET 0x107 +#define OMAP2420_CONTROL_PADCONF_GPIO_6_OFFSET 0x108 +#define OMAP2420_CONTROL_PADCONF_GPIO_124_OFFSET 0x109 +#define OMAP2420_CONTROL_PADCONF_GPIO_125_OFFSET 0x10a +#define OMAP2420_CONTROL_PADCONF_JTAG_EMU1_OFFSET 0x10b +#define OMAP2420_CONTROL_PADCONF_JTAG_EMU0_OFFSET 0x10c +#define OMAP2420_CONTROL_PADCONF_JTAG_NTRST_OFFSET 0x10d +#define OMAP2420_CONTROL_PADCONF_JTAG_TCK_OFFSET 0x10e +#define OMAP2420_CONTROL_PADCONF_JTAG_RTCK_OFFSET 0x10f +#define OMAP2420_CONTROL_PADCONF_JTAG_TMS_OFFSET 0x110 +#define OMAP2420_CONTROL_PADCONF_JTAG_TDI_OFFSET 0x111 +#define OMAP2420_CONTROL_PADCONF_JTAG_TDO_OFFSET 0x112 + +#define OMAP2420_CONTROL_PADCONF_MUX_SIZE \ + (OMAP2420_CONTROL_PADCONF_JTAG_TDO_OFFSET + 0x1) diff --git a/arch/arm/mach-omap2/mux2430.c b/arch/arm/mach-omap2/mux2430.c new file mode 100644 index 00000000000..7dcaaa8af32 --- /dev/null +++ b/arch/arm/mach-omap2/mux2430.c @@ -0,0 +1,791 @@ +/* + * Copyright (C) 2010 Nokia + * Copyright (C) 2010 Texas Instruments + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/module.h> +#include <linux/init.h> + +#include "mux.h" + +#ifdef CONFIG_OMAP_MUX + +#define _OMAP2430_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \ +{ \ + .reg_offset = (OMAP2430_CONTROL_PADCONF_##M0##_OFFSET), \ + .gpio = (g), \ + .muxnames = { m0, m1, m2, m3, m4, m5, m6, m7 }, \ +} + +#else + +#define _OMAP2430_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \ +{ \ + .reg_offset = (OMAP2430_CONTROL_PADCONF_##M0##_OFFSET), \ + .gpio = (g), \ +} + +#endif + +#define _OMAP2430_BALLENTRY(M0, bb, bt) \ +{ \ + .reg_offset = (OMAP2430_CONTROL_PADCONF_##M0##_OFFSET), \ + .balls = { bb, bt }, \ +} + +/* + * Superset of all mux modes for omap2430 + */ +static struct omap_mux __initdata omap2430_muxmodes[] = { + _OMAP2430_MUXENTRY(CAM_D0, 133, + "cam_d0", "hw_dbg0", "sti_dout", "gpio_133", + NULL, NULL, "etk_d2", "safe_mode"), + _OMAP2430_MUXENTRY(CAM_D10, 146, + "cam_d10", NULL, NULL, "gpio_146", + NULL, NULL, "etk_d12", "safe_mode"), + _OMAP2430_MUXENTRY(CAM_D11, 145, + "cam_d11", NULL, NULL, "gpio_145", + NULL, NULL, "etk_d13", "safe_mode"), + _OMAP2430_MUXENTRY(CAM_D1, 132, + "cam_d1", "hw_dbg1", "sti_din", "gpio_132", + NULL, NULL, "etk_d3", "safe_mode"), + _OMAP2430_MUXENTRY(CAM_D2, 129, + "cam_d2", "hw_dbg2", "mcbsp1_clkx", "gpio_129", + NULL, NULL, "etk_d4", "safe_mode"), + _OMAP2430_MUXENTRY(CAM_D3, 128, + "cam_d3", "hw_dbg3", "mcbsp1_dr", "gpio_128", + NULL, NULL, "etk_d5", "safe_mode"), + _OMAP2430_MUXENTRY(CAM_D4, 143, + "cam_d4", "hw_dbg4", "mcbsp1_fsr", "gpio_143", + NULL, NULL, "etk_d6", "safe_mode"), + _OMAP2430_MUXENTRY(CAM_D5, 112, + "cam_d5", "hw_dbg5", "mcbsp1_clkr", "gpio_112", + NULL, NULL, "etk_d7", "safe_mode"), + _OMAP2430_MUXENTRY(CAM_D6, 137, + "cam_d6", "hw_dbg6", NULL, "gpio_137", + NULL, NULL, "etk_d8", "safe_mode"), + _OMAP2430_MUXENTRY(CAM_D7, 136, + "cam_d7", "hw_dbg7", NULL, "gpio_136", + NULL, NULL, "etk_d9", "safe_mode"), + _OMAP2430_MUXENTRY(CAM_D8, 135, + "cam_d8", "hw_dbg8", NULL, "gpio_135", + NULL, NULL, "etk_d10", "safe_mode"), + _OMAP2430_MUXENTRY(CAM_D9, 134, + "cam_d9", "hw_dbg9", NULL, "gpio_134", + NULL, NULL, "etk_d11", "safe_mode"), + _OMAP2430_MUXENTRY(CAM_HS, 11, + "cam_hs", "hw_dbg10", "mcbsp1_dx", "gpio_11", + NULL, NULL, "etk_d1", "safe_mode"), + _OMAP2430_MUXENTRY(CAM_LCLK, 0, + "cam_lclk", NULL, "mcbsp_clks", NULL, + NULL, NULL, "etk_c1", "safe_mode"), + _OMAP2430_MUXENTRY(CAM_VS, 12, + "cam_vs", "hw_dbg11", "mcbsp1_fsx", "gpio_12", + NULL, NULL, "etk_d0", "safe_mode"), + _OMAP2430_MUXENTRY(CAM_XCLK, 0, + "cam_xclk", NULL, "sti_clk", NULL, + NULL, NULL, "etk_c2", NULL), + _OMAP2430_MUXENTRY(DSS_ACBIAS, 48, + "dss_acbias", NULL, "mcbsp2_fsx", "gpio_48", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(DSS_DATA0, 40, + "dss_data0", "uart1_cts", NULL, "gpio_40", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(DSS_DATA10, 128, + "dss_data10", "sdi_data1n", NULL, "gpio_128", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(DSS_DATA11, 129, + "dss_data11", "sdi_data1p", NULL, "gpio_129", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(DSS_DATA12, 130, + "dss_data12", "sdi_data2n", NULL, "gpio_130", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(DSS_DATA13, 131, + "dss_data13", "sdi_data2p", NULL, "gpio_131", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(DSS_DATA14, 132, + "dss_data14", "sdi_data3n", NULL, "gpio_132", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(DSS_DATA15, 133, + "dss_data15", "sdi_data3p", NULL, "gpio_133", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(DSS_DATA16, 46, + "dss_data16", NULL, NULL, "gpio_46", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(DSS_DATA17, 47, + "dss_data17", NULL, NULL, "gpio_47", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(DSS_DATA1, 41, + "dss_data1", "uart1_rts", NULL, "gpio_41", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(DSS_DATA2, 42, + "dss_data2", "uart1_tx", NULL, "gpio_42", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(DSS_DATA3, 43, + "dss_data3", "uart1_rx", NULL, "gpio_43", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(DSS_DATA4, 44, + "dss_data4", "uart3_rx_irrx", NULL, "gpio_44", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(DSS_DATA5, 45, + "dss_data5", "uart3_tx_irtx", NULL, "gpio_45", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(DSS_DATA6, 144, + "dss_data6", NULL, NULL, "gpio_144", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(DSS_DATA7, 147, + "dss_data7", NULL, NULL, "gpio_147", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(DSS_DATA8, 38, + "dss_data8", NULL, NULL, "gpio_38", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(DSS_DATA9, 39, + "dss_data9", NULL, NULL, "gpio_39", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(DSS_HSYNC, 110, + "dss_hsync", NULL, NULL, "gpio_110", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_113, 113, + "gpio_113", "mcbsp2_clkx", NULL, "gpio_113", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_114, 114, + "gpio_114", "mcbsp2_fsx", NULL, "gpio_114", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_115, 115, + "gpio_115", "mcbsp2_dr", NULL, "gpio_115", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_116, 116, + "gpio_116", "mcbsp2_dx", NULL, "gpio_116", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_128, 128, + "gpio_128", NULL, "sti_din", "gpio_128", + NULL, "sys_boot0", NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_129, 129, + "gpio_129", NULL, "sti_dout", "gpio_129", + NULL, "sys_boot1", NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_130, 130, + "gpio_130", NULL, NULL, "gpio_130", + "jtag_emu2", "sys_boot2", NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_131, 131, + "gpio_131", NULL, NULL, "gpio_131", + "jtag_emu3", "sys_boot3", NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_132, 132, + "gpio_132", NULL, NULL, "gpio_132", + NULL, "sys_boot4", NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_133, 133, + "gpio_133", NULL, NULL, "gpio_133", + NULL, "sys_boot5", NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_134, 134, + "gpio_134", "ccp_datn", NULL, "gpio_134", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_135, 135, + "gpio_135", "ccp_datp", NULL, "gpio_135", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_136, 136, + "gpio_136", "ccp_clkn", NULL, "gpio_136", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_137, 137, + "gpio_137", "ccp_clkp", NULL, "gpio_137", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_138, 138, + "gpio_138", "spi3_clk", NULL, "gpio_138", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_139, 139, + "gpio_139", "spi3_cs0", "sys_ndmareq3", "gpio_139", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_140, 140, + "gpio_140", "spi3_simo", "sys_ndmareq4", "gpio_140", + NULL, NULL, "etk_d14", "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_141, 141, + "gpio_141", "spi3_somi", NULL, "gpio_141", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_142, 142, + "gpio_142", "spi3_cs1", "sys_ndmareq2", "gpio_142", + NULL, NULL, "etk_d15", "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_148, 148, + "gpio_148", "mcbsp5_fsx", NULL, "gpio_148", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_149, 149, + "gpio_149", "mcbsp5_dx", NULL, "gpio_149", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_150, 150, + "gpio_150", "mcbsp5_dr", NULL, "gpio_150", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_151, 151, + "gpio_151", "sys_pwrok", NULL, "gpio_151", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_152, 152, + "gpio_152", "uart1_cts", "sys_ndmareq1", "gpio_152", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_153, 153, + "gpio_153", "uart1_rx", "sys_ndmareq0", "gpio_153", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_154, 154, + "gpio_154", "mcbsp5_clkx", NULL, "gpio_154", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_63, 63, + "gpio_63", "mcbsp4_clkx", NULL, "gpio_63", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_78, 78, + "gpio_78", NULL, "uart2_rts", "gpio_78", + "uart3_rts_sd", NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_79, 79, + "gpio_79", "secure_indicator", "uart2_tx", "gpio_79", + "uart3_tx_irtx", NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_7, 7, + "gpio_7", NULL, "uart2_cts", "gpio_7", + "uart3_cts_rctx", NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPIO_80, 80, + "gpio_80", NULL, "uart2_rx", "gpio_80", + "uart3_rx_irrx", NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPMC_A10, 3, + "gpmc_a10", NULL, "sys_ndmareq0", "gpio_3", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPMC_A1, 31, + "gpmc_a1", NULL, NULL, "gpio_31", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPMC_A2, 30, + "gpmc_a2", NULL, NULL, "gpio_30", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPMC_A3, 29, + "gpmc_a3", NULL, NULL, "gpio_29", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPMC_A4, 49, + "gpmc_a4", NULL, NULL, "gpio_49", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPMC_A5, 53, + "gpmc_a5", NULL, NULL, "gpio_53", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPMC_A6, 52, + "gpmc_a6", NULL, NULL, "gpio_52", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPMC_A7, 6, + "gpmc_a7", NULL, NULL, "gpio_6", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPMC_A8, 5, + "gpmc_a8", NULL, NULL, "gpio_5", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPMC_A9, 4, + "gpmc_a9", NULL, "sys_ndmareq1", "gpio_4", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPMC_CLK, 21, + "gpmc_clk", NULL, NULL, "gpio_21", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPMC_D10, 18, + "gpmc_d10", NULL, NULL, "gpio_18", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPMC_D11, 57, + "gpmc_d11", NULL, NULL, "gpio_57", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPMC_D12, 77, + "gpmc_d12", NULL, NULL, "gpio_77", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPMC_D13, 76, + "gpmc_d13", NULL, NULL, "gpio_76", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPMC_D14, 55, + "gpmc_d14", NULL, NULL, "gpio_55", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPMC_D15, 54, + "gpmc_d15", NULL, NULL, "gpio_54", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPMC_D8, 20, + "gpmc_d8", NULL, NULL, "gpio_20", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPMC_D9, 19, + "gpmc_d9", NULL, NULL, "gpio_19", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPMC_NCS1, 22, + "gpmc_ncs1", NULL, NULL, "gpio_22", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPMC_NCS2, 23, + "gpmc_ncs2", NULL, NULL, "gpio_23", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPMC_NCS3, 24, + "gpmc_ncs3", "gpmc_io_dir", NULL, "gpio_24", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPMC_NCS4, 25, + "gpmc_ncs4", NULL, NULL, "gpio_25", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPMC_NCS5, 26, + "gpmc_ncs5", NULL, NULL, "gpio_26", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPMC_NCS6, 27, + "gpmc_ncs6", NULL, NULL, "gpio_27", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPMC_NCS7, 28, + "gpmc_ncs7", "gpmc_io_dir", NULL, "gpio_28", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPMC_WAIT1, 33, + "gpmc_wait1", NULL, NULL, "gpio_33", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPMC_WAIT2, 34, + "gpmc_wait2", NULL, NULL, "gpio_34", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(GPMC_WAIT3, 35, + "gpmc_wait3", NULL, NULL, "gpio_35", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(HDQ_SIO, 101, + "hdq_sio", "usb2_tllse0", "sys_altclk", "gpio_101", + "uart3_rx_irrx", NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(I2C1_SCL, 50, + "i2c1_scl", NULL, NULL, "gpio_50", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(I2C1_SDA, 51, + "i2c1_sda", NULL, NULL, "gpio_51", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(I2C2_SCL, 99, + "i2c2_scl", NULL, NULL, "gpio_99", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(I2C2_SDA, 100, + "i2c2_sda", NULL, NULL, "gpio_100", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(JTAG_EMU0, 127, + "jtag_emu0", "secure_indicator", NULL, "gpio_127", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(JTAG_EMU1, 126, + "jtag_emu1", NULL, NULL, "gpio_126", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(MCBSP1_CLKR, 92, + "mcbsp1_clkr", "ssi2_dat_tx", NULL, "gpio_92", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(MCBSP1_CLKX, 98, + "mcbsp1_clkx", "ssi2_wake", NULL, "gpio_98", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(MCBSP1_DR, 95, + "mcbsp1_dr", "ssi2_dat_rx", NULL, "gpio_95", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(MCBSP1_DX, 94, + "mcbsp1_dx", "ssi2_rdy_tx", NULL, "gpio_94", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(MCBSP1_FSR, 93, + "mcbsp1_fsr", "ssi2_flag_tx", NULL, "gpio_93", + "spi2_cs1", NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(MCBSP1_FSX, 97, + "mcbsp1_fsx", "ssi2_rdy_rx", NULL, "gpio_97", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(MCBSP2_CLKX, 147, + "mcbsp2_clkx", "sdi_clkp", "dss_data23", "gpio_147", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(MCBSP2_DR, 144, + "mcbsp2_dr", "sdi_clkn", "dss_data22", "gpio_144", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(MCBSP3_CLKX, 71, + "mcbsp3_clkx", NULL, NULL, "gpio_71", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(MCBSP3_DR, 73, + "mcbsp3_dr", NULL, NULL, "gpio_73", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(MCBSP3_DX, 74, + "mcbsp3_dx", NULL, "sti_clk", "gpio_74", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(MCBSP3_FSX, 72, + "mcbsp3_fsx", NULL, NULL, "gpio_72", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(MCBSP_CLKS, 96, + "mcbsp_clks", "ssi2_flag_rx", NULL, "gpio_96", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SDMMC1_CLKO, 0, + "sdmmc1_clko", "ms_clko", NULL, NULL, + NULL, "hw_dbg9", "hw_dbg3", "safe_mode"), + _OMAP2430_MUXENTRY(SDMMC1_CMD, 0, + "sdmmc1_cmd", "ms_bs", NULL, NULL, + NULL, "hw_dbg8", "hw_dbg2", "safe_mode"), + _OMAP2430_MUXENTRY(SDMMC1_DAT0, 0, + "sdmmc1_dat0", "ms_dat0", NULL, NULL, + NULL, "hw_dbg7", "hw_dbg1", "safe_mode"), + _OMAP2430_MUXENTRY(SDMMC1_DAT1, 75, + "sdmmc1_dat1", "ms_dat1", NULL, "gpio_75", + NULL, "hw_dbg6", "hw_dbg0", "safe_mode"), + _OMAP2430_MUXENTRY(SDMMC1_DAT2, 0, + "sdmmc1_dat2", "ms_dat2", NULL, NULL, + NULL, "hw_dbg5", "hw_dbg10", "safe_mode"), + _OMAP2430_MUXENTRY(SDMMC1_DAT3, 0, + "sdmmc1_dat3", "ms_dat3", NULL, NULL, + NULL, "hw_dbg4", "hw_dbg11", "safe_mode"), + _OMAP2430_MUXENTRY(SDMMC2_CLKO, 13, + "sdmmc2_clko", NULL, NULL, "gpio_13", + NULL, "spi3_clk", NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SDMMC2_CMD, 15, + "sdmmc2_cmd", "usb2_rcv", NULL, "gpio_15", + NULL, "spi3_simo", NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SDMMC2_DAT0, 16, + "sdmmc2_dat0", "usb2_tllse0", NULL, "gpio_16", + NULL, "spi3_somi", NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SDMMC2_DAT1, 58, + "sdmmc2_dat1", "usb2_txen", NULL, "gpio_58", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SDMMC2_DAT2, 17, + "sdmmc2_dat2", "usb2_dat", NULL, "gpio_17", + NULL, "spi3_cs1", NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SDMMC2_DAT3, 14, + "sdmmc2_dat3", "usb2_se0", NULL, "gpio_14", + NULL, "spi3_cs0", NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SDRC_A12, 2, + "sdrc_a12", NULL, NULL, "gpio_2", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SDRC_A13, 1, + "sdrc_a13", NULL, NULL, "gpio_1", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SDRC_A14, 0, + "sdrc_a14", NULL, NULL, "gpio_0", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SDRC_CKE1, 36, + "sdrc_cke1", NULL, NULL, "gpio_36", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SDRC_NCS1, 37, + "sdrc_ncs1", NULL, NULL, "gpio_37", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SPI1_CLK, 81, + "spi1_clk", NULL, NULL, "gpio_81", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SPI1_CS0, 84, + "spi1_cs0", NULL, NULL, "gpio_84", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SPI1_CS1, 85, + "spi1_cs1", NULL, NULL, "gpio_85", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SPI1_CS2, 86, + "spi1_cs2", NULL, NULL, "gpio_86", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SPI1_CS3, 87, + "spi1_cs3", "spi2_cs1", NULL, "gpio_87", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SPI1_SIMO, 82, + "spi1_simo", NULL, NULL, "gpio_82", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SPI1_SOMI, 83, + "spi1_somi", NULL, NULL, "gpio_83", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SPI2_CLK, 88, + "spi2_clk", "gpt9_pwm_evt", NULL, "gpio_88", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SPI2_CS0, 91, + "spi2_cs0", "gpt12_pwm_evt", NULL, "gpio_91", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SPI2_SIMO, 89, + "spi2_simo", "gpt10_pwm_evt", NULL, "gpio_89", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SPI2_SOMI, 90, + "spi2_somi", "gpt11_pwm_evt", NULL, "gpio_90", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SSI1_DAT_RX, 62, + "ssi1_dat_rx", "uart1_rx", "usb1_dat", "gpio_62", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SSI1_DAT_TX, 59, + "ssi1_dat_tx", "uart1_tx", "usb1_se0", "gpio_59", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SSI1_FLAG_RX, 64, + "ssi1_flag_rx", "mcbsp4_dr", NULL, "gpio_64", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SSI1_FLAG_TX, 60, + "ssi1_flag_tx", "uart1_rts", "usb1_rcv", "gpio_60", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SSI1_RDY_RX, 65, + "ssi1_rdy_rx", "mcbsp4_dx", NULL, "gpio_65", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SSI1_RDY_TX, 61, + "ssi1_rdy_tx", "uart1_cts", "usb1_txen", "gpio_61", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SSI1_WAKE, 66, + "ssi1_wake", "mcbsp4_fsx", NULL, "gpio_66", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SYS_CLKOUT, 111, + "sys_clkout", NULL, NULL, "gpio_111", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SYS_DRM_MSECURE, 118, + "sys_drm_msecure", NULL, "sys_ndmareq6", "gpio_118", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SYS_NIRQ0, 56, + "sys_nirq0", NULL, NULL, "gpio_56", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(SYS_NIRQ1, 125, + "sys_nirq1", NULL, "sys_ndmareq5", "gpio_125", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(UART1_CTS, 32, + "uart1_cts", "sdi_vsync", "dss_data18", "gpio_32", + "mcbsp5_clkx", NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(UART1_RTS, 8, + "uart1_rts", "sdi_hsync", "dss_data19", "gpio_8", + "mcbsp5_fsx", NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(UART1_RX, 10, + "uart1_rx", "sdi_stp", "dss_data21", "gpio_10", + "mcbsp5_dr", NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(UART1_TX, 9, + "uart1_tx", "sdi_den", "dss_data20", "gpio_9", + "mcbsp5_dx", NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(UART2_CTS, 67, + "uart2_cts", "usb1_rcv", "gpt9_pwm_evt", "gpio_67", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(UART2_RTS, 68, + "uart2_rts", "usb1_txen", "gpt10_pwm_evt", "gpio_68", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(UART2_RX, 70, + "uart2_rx", "usb1_dat", "gpt12_pwm_evt", "gpio_70", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(UART2_TX, 69, + "uart2_tx", "usb1_se0", "gpt11_pwm_evt", "gpio_69", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(UART3_CTS_RCTX, 102, + "uart3_cts_rctx", "uart3_rx_irrx", NULL, "gpio_102", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(UART3_RTS_SD, 103, + "uart3_rts_sd", "uart3_tx_irtx", NULL, "gpio_103", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(UART3_RX_IRRX, 105, + "uart3_rx_irrx", NULL, NULL, "gpio_105", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(UART3_TX_IRTX, 104, + "uart3_tx_irtx", "uart3_cts_rctx", NULL, "gpio_104", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(USB0HS_CLK, 120, + "usb0hs_clk", NULL, NULL, "gpio_120", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(USB0HS_DATA0, 0, + "usb0hs_data0", "uart3_tx_irtx", NULL, NULL, + "usb0_txen", NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(USB0HS_DATA1, 0, + "usb0hs_data1", "uart3_rx_irrx", NULL, NULL, + "usb0_dat", NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(USB0HS_DATA2, 0, + "usb0hs_data2", "uart3_rts_sd", NULL, NULL, + "usb0_se0", NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(USB0HS_DATA3, 106, + "usb0hs_data3", NULL, "uart3_cts_rctx", "gpio_106", + "usb0_puen", NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(USB0HS_DATA4, 107, + "usb0hs_data4", "mcbsp2_dr", NULL, "gpio_107", + "usb0_vp", NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(USB0HS_DATA5, 108, + "usb0hs_data5", "mcbsp2_dx", NULL, "gpio_108", + "usb0_vm", NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(USB0HS_DATA6, 109, + "usb0hs_data6", "mcbsp2_fsx", NULL, "gpio_109", + "usb0_rcv", NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(USB0HS_DATA7, 124, + "usb0hs_data7", "mcbsp2_clkx", NULL, "gpio_124", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(USB0HS_DIR, 121, + "usb0hs_dir", NULL, NULL, "gpio_121", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(USB0HS_NXT, 123, + "usb0hs_nxt", NULL, NULL, "gpio_123", + NULL, NULL, NULL, "safe_mode"), + _OMAP2430_MUXENTRY(USB0HS_STP, 122, + "usb0hs_stp", NULL, NULL, "gpio_122", + NULL, NULL, NULL, "safe_mode"), + { .reg_offset = OMAP_MUX_TERMINATOR }, +}; + +/* + * Balls for POP package + * 447-pin s-PBGA Package, 0.00mm Ball Pitch (Bottom) + */ +#ifdef CONFIG_DEBUG_FS +struct omap_ball __initdata omap2430_pop_ball[] = { + _OMAP2430_BALLENTRY(CAM_D0, "t8", NULL), + _OMAP2430_BALLENTRY(CAM_D1, "t4", NULL), + _OMAP2430_BALLENTRY(CAM_D10, "r4", NULL), + _OMAP2430_BALLENTRY(CAM_D11, "w3", NULL), + _OMAP2430_BALLENTRY(CAM_D2, "r2", NULL), + _OMAP2430_BALLENTRY(CAM_D3, "u3", NULL), + _OMAP2430_BALLENTRY(CAM_D4, "u2", NULL), + _OMAP2430_BALLENTRY(CAM_D5, "v1", NULL), + _OMAP2430_BALLENTRY(CAM_D6, "t3", NULL), + _OMAP2430_BALLENTRY(CAM_D7, "r3", NULL), + _OMAP2430_BALLENTRY(CAM_D8, "u7", NULL), + _OMAP2430_BALLENTRY(CAM_D9, "t7", NULL), + _OMAP2430_BALLENTRY(CAM_HS, "p2", NULL), + _OMAP2430_BALLENTRY(CAM_LCLK, "r7", NULL), + _OMAP2430_BALLENTRY(CAM_VS, "n2", NULL), + _OMAP2430_BALLENTRY(CAM_XCLK, "p3", NULL), + _OMAP2430_BALLENTRY(DSS_ACBIAS, "y3", NULL), + _OMAP2430_BALLENTRY(DSS_DATA0, "v8", NULL), + _OMAP2430_BALLENTRY(DSS_DATA1, "w1", NULL), + _OMAP2430_BALLENTRY(DSS_DATA10, "k25", NULL), + _OMAP2430_BALLENTRY(DSS_DATA11, "j25", NULL), + _OMAP2430_BALLENTRY(DSS_DATA12, "k24", NULL), + _OMAP2430_BALLENTRY(DSS_DATA13, "j24", NULL), + _OMAP2430_BALLENTRY(DSS_DATA14, "h25", NULL), + _OMAP2430_BALLENTRY(DSS_DATA15, "g25", NULL), + _OMAP2430_BALLENTRY(DSS_DATA16, "ac3", NULL), + _OMAP2430_BALLENTRY(DSS_DATA17, "y7", NULL), + _OMAP2430_BALLENTRY(DSS_DATA2, "u8", NULL), + _OMAP2430_BALLENTRY(DSS_DATA3, "u4", NULL), + _OMAP2430_BALLENTRY(DSS_DATA4, "v3", NULL), + _OMAP2430_BALLENTRY(DSS_DATA5, "aa4", NULL), + _OMAP2430_BALLENTRY(DSS_DATA6, "w8", NULL), + _OMAP2430_BALLENTRY(DSS_DATA7, "y1", NULL), + _OMAP2430_BALLENTRY(DSS_DATA8, "aa2", NULL), + _OMAP2430_BALLENTRY(DSS_DATA9, "ab4", NULL), + _OMAP2430_BALLENTRY(DSS_HSYNC, "v2", NULL), + _OMAP2430_BALLENTRY(GPIO_113, "ad16", NULL), + _OMAP2430_BALLENTRY(GPIO_114, "ac10", NULL), + _OMAP2430_BALLENTRY(GPIO_115, "ad13", NULL), + _OMAP2430_BALLENTRY(GPIO_116, "ae15", NULL), + _OMAP2430_BALLENTRY(GPIO_128, "p1", NULL), + _OMAP2430_BALLENTRY(GPIO_129, "r1", NULL), + _OMAP2430_BALLENTRY(GPIO_130, "p7", NULL), + _OMAP2430_BALLENTRY(GPIO_131, "l8", NULL), + _OMAP2430_BALLENTRY(GPIO_132, "w24", NULL), + _OMAP2430_BALLENTRY(GPIO_133, "aa24", NULL), + _OMAP2430_BALLENTRY(GPIO_134, "ae12", NULL), + _OMAP2430_BALLENTRY(GPIO_135, "ae11", NULL), + _OMAP2430_BALLENTRY(GPIO_136, "ad12", NULL), + _OMAP2430_BALLENTRY(GPIO_137, "ad11", NULL), + _OMAP2430_BALLENTRY(GPIO_138, "y12", NULL), + _OMAP2430_BALLENTRY(GPIO_139, "ad17", NULL), + _OMAP2430_BALLENTRY(GPIO_140, "l7", NULL), + _OMAP2430_BALLENTRY(GPIO_141, "ac24", NULL), + _OMAP2430_BALLENTRY(GPIO_142, "m3", NULL), + _OMAP2430_BALLENTRY(GPIO_148, "af12", NULL), + _OMAP2430_BALLENTRY(GPIO_149, "k7", NULL), + _OMAP2430_BALLENTRY(GPIO_150, "m1", NULL), + _OMAP2430_BALLENTRY(GPIO_151, "ad14", NULL), + _OMAP2430_BALLENTRY(GPIO_152, "ad18", NULL), + _OMAP2430_BALLENTRY(GPIO_153, "u24", NULL), + _OMAP2430_BALLENTRY(GPIO_154, "ae16", NULL), + _OMAP2430_BALLENTRY(GPIO_63, "n3", NULL), + _OMAP2430_BALLENTRY(GPIO_7, "ac23", NULL), + _OMAP2430_BALLENTRY(GPIO_78, "ad10", NULL), + _OMAP2430_BALLENTRY(GPIO_79, "ae10", NULL), + _OMAP2430_BALLENTRY(GPIO_80, "ae13", NULL), + _OMAP2430_BALLENTRY(GPMC_A1, "a9", NULL), + _OMAP2430_BALLENTRY(GPMC_A10, "g12", NULL), + _OMAP2430_BALLENTRY(GPMC_A2, "b8", NULL), + _OMAP2430_BALLENTRY(GPMC_A3, "g10", NULL), + _OMAP2430_BALLENTRY(GPMC_A4, "g11", NULL), + _OMAP2430_BALLENTRY(GPMC_A5, "a10", NULL), + _OMAP2430_BALLENTRY(GPMC_A6, "g13", NULL), + _OMAP2430_BALLENTRY(GPMC_A7, "a6", NULL), + _OMAP2430_BALLENTRY(GPMC_A8, "h1", NULL), + _OMAP2430_BALLENTRY(GPMC_A9, "c8", NULL), + _OMAP2430_BALLENTRY(GPMC_CLK, "n1", "l1"), + _OMAP2430_BALLENTRY(GPMC_D10, "d1", "n1"), + _OMAP2430_BALLENTRY(GPMC_D11, "d2", "p2"), + _OMAP2430_BALLENTRY(GPMC_D12, "e1", "p1"), + _OMAP2430_BALLENTRY(GPMC_D13, "e3", "m1"), + _OMAP2430_BALLENTRY(GPMC_D14, "c7", "j2"), + _OMAP2430_BALLENTRY(GPMC_D15, "f3", "k2"), + _OMAP2430_BALLENTRY(GPMC_D8, "e2", "r1"), + _OMAP2430_BALLENTRY(GPMC_D9, "ab1", "t1"), + _OMAP2430_BALLENTRY(GPMC_NCS1, "ac1", "w1"), + _OMAP2430_BALLENTRY(GPMC_NCS2, "c6", NULL), + _OMAP2430_BALLENTRY(GPMC_NCS3, "b9", NULL), + _OMAP2430_BALLENTRY(GPMC_NCS4, "b4", NULL), + _OMAP2430_BALLENTRY(GPMC_NCS5, "a4", NULL), + _OMAP2430_BALLENTRY(GPMC_NCS6, "f1", NULL), + _OMAP2430_BALLENTRY(GPMC_NCS7, "a7", NULL), + _OMAP2430_BALLENTRY(GPMC_WAIT1, "j1", "y8"), + _OMAP2430_BALLENTRY(GPMC_WAIT2, "b7", NULL), + _OMAP2430_BALLENTRY(GPMC_WAIT3, "g14", NULL), + _OMAP2430_BALLENTRY(HDQ_SIO, "h20", NULL), + _OMAP2430_BALLENTRY(I2C1_SCL, "y17", NULL), + _OMAP2430_BALLENTRY(I2C1_SDA, "ac19", NULL), + _OMAP2430_BALLENTRY(I2C2_SCL, "n7", NULL), + _OMAP2430_BALLENTRY(I2C2_SDA, "m4", NULL), + _OMAP2430_BALLENTRY(JTAG_EMU0, "e25", NULL), + _OMAP2430_BALLENTRY(JTAG_EMU1, "e24", NULL), + _OMAP2430_BALLENTRY(MCBSP1_CLKR, "ab2", NULL), + _OMAP2430_BALLENTRY(MCBSP1_CLKX, "y9", NULL), + _OMAP2430_BALLENTRY(MCBSP1_DR, "af3", NULL), + _OMAP2430_BALLENTRY(MCBSP1_DX, "aa1", NULL), + _OMAP2430_BALLENTRY(MCBSP1_FSR, "ad5", NULL), + _OMAP2430_BALLENTRY(MCBSP1_FSX, "ab3", NULL), + _OMAP2430_BALLENTRY(MCBSP2_CLKX, "j26", NULL), + _OMAP2430_BALLENTRY(MCBSP2_DR, "k26", NULL), + _OMAP2430_BALLENTRY(MCBSP3_CLKX, "ac9", NULL), + _OMAP2430_BALLENTRY(MCBSP3_DR, "ae2", NULL), + _OMAP2430_BALLENTRY(MCBSP3_DX, "af4", NULL), + _OMAP2430_BALLENTRY(MCBSP3_FSX, "ae4", NULL), + _OMAP2430_BALLENTRY(MCBSP_CLKS, "ad6", NULL), + _OMAP2430_BALLENTRY(SDMMC1_CLKO, "n23", NULL), + _OMAP2430_BALLENTRY(SDMMC1_CMD, "l23", NULL), + _OMAP2430_BALLENTRY(SDMMC1_DAT0, "m24", NULL), + _OMAP2430_BALLENTRY(SDMMC1_DAT1, "p23", NULL), + _OMAP2430_BALLENTRY(SDMMC1_DAT2, "t20", NULL), + _OMAP2430_BALLENTRY(SDMMC1_DAT3, "r20", NULL), + _OMAP2430_BALLENTRY(SDMMC2_CLKO, "v26", NULL), + _OMAP2430_BALLENTRY(SDMMC2_CMD, "w20", NULL), + _OMAP2430_BALLENTRY(SDMMC2_DAT0, "v23", NULL), + _OMAP2430_BALLENTRY(SDMMC2_DAT1, "y24", NULL), + _OMAP2430_BALLENTRY(SDMMC2_DAT2, "v25", NULL), + _OMAP2430_BALLENTRY(SDMMC2_DAT3, "v24", NULL), + _OMAP2430_BALLENTRY(SDRC_A12, "w26", "r21"), + _OMAP2430_BALLENTRY(SDRC_A13, "af20", "aa15"), + _OMAP2430_BALLENTRY(SDRC_A14, "af16", "y12"), + _OMAP2430_BALLENTRY(SDRC_CKE1, "af15", "y13"), + _OMAP2430_BALLENTRY(SDRC_NCS1, "aa25", "t20"), + _OMAP2430_BALLENTRY(SPI1_CLK, "y18", NULL), + _OMAP2430_BALLENTRY(SPI1_CS0, "u1", NULL), + _OMAP2430_BALLENTRY(SPI1_CS1, "af19", NULL), + _OMAP2430_BALLENTRY(SPI1_CS2, "ae19", NULL), + _OMAP2430_BALLENTRY(SPI1_CS3, "h24", NULL), + _OMAP2430_BALLENTRY(SPI1_SIMO, "ad15", NULL), + _OMAP2430_BALLENTRY(SPI1_SOMI, "ae17", NULL), + _OMAP2430_BALLENTRY(SPI2_CLK, "y20", NULL), + _OMAP2430_BALLENTRY(SPI2_CS0, "y19", NULL), + _OMAP2430_BALLENTRY(SPI2_SIMO, "ac20", NULL), + _OMAP2430_BALLENTRY(SPI2_SOMI, "ad19", NULL), + _OMAP2430_BALLENTRY(SSI1_DAT_RX, "aa26", NULL), + _OMAP2430_BALLENTRY(SSI1_DAT_TX, "ad24", NULL), + _OMAP2430_BALLENTRY(SSI1_FLAG_RX, "ad23", NULL), + _OMAP2430_BALLENTRY(SSI1_FLAG_TX, "ab24", NULL), + _OMAP2430_BALLENTRY(SSI1_RDY_RX, "ab25", NULL), + _OMAP2430_BALLENTRY(SSI1_RDY_TX, "y25", NULL), + _OMAP2430_BALLENTRY(SSI1_WAKE, "ac25", NULL), + _OMAP2430_BALLENTRY(SYS_CLKOUT, "r25", NULL), + _OMAP2430_BALLENTRY(SYS_DRM_MSECURE, "ae3", NULL), + _OMAP2430_BALLENTRY(SYS_NIRQ0, "w25", NULL), + _OMAP2430_BALLENTRY(SYS_NIRQ1, "ad21", NULL), + _OMAP2430_BALLENTRY(UART1_CTS, "p24", NULL), + _OMAP2430_BALLENTRY(UART1_RTS, "p25", NULL), + _OMAP2430_BALLENTRY(UART1_RX, "n24", NULL), + _OMAP2430_BALLENTRY(UART1_TX, "r24", NULL), + _OMAP2430_BALLENTRY(UART2_CTS, "u25", NULL), + _OMAP2430_BALLENTRY(UART2_RTS, "t23", NULL), + _OMAP2430_BALLENTRY(UART2_RX, "t24", NULL), + _OMAP2430_BALLENTRY(UART2_TX, "u20", NULL), + _OMAP2430_BALLENTRY(UART3_CTS_RCTX, "m2", NULL), + _OMAP2430_BALLENTRY(UART3_RTS_SD, "k2", NULL), + _OMAP2430_BALLENTRY(UART3_RX_IRRX, "l3", NULL), + _OMAP2430_BALLENTRY(UART3_TX_IRTX, "l2", NULL), + _OMAP2430_BALLENTRY(USB0HS_CLK, "ae8", NULL), + _OMAP2430_BALLENTRY(USB0HS_DATA0, "ad4", NULL), + _OMAP2430_BALLENTRY(USB0HS_DATA1, "ae6", NULL), + _OMAP2430_BALLENTRY(USB0HS_DATA2, "af9", NULL), + _OMAP2430_BALLENTRY(USB0HS_DATA3, "ad9", NULL), + _OMAP2430_BALLENTRY(USB0HS_DATA4, "y11", NULL), + _OMAP2430_BALLENTRY(USB0HS_DATA5, "ad7", NULL), + _OMAP2430_BALLENTRY(USB0HS_DATA6, "ae7", NULL), + _OMAP2430_BALLENTRY(USB0HS_DATA7, "ac7", NULL), + _OMAP2430_BALLENTRY(USB0HS_DIR, "ad8", NULL), + _OMAP2430_BALLENTRY(USB0HS_NXT, "ae9", NULL), + _OMAP2430_BALLENTRY(USB0HS_STP, "ae5", NULL), + { .reg_offset = OMAP_MUX_TERMINATOR }, +}; +#else +#define omap2430_pop_ball NULL +#endif + +int __init omap2430_mux_init(struct omap_board_mux *board_subset, int flags) +{ + struct omap_ball *package_balls = NULL; + + switch (flags & OMAP_PACKAGE_MASK) { + case OMAP_PACKAGE_ZAC: + package_balls = omap2430_pop_ball; + break; + default: + pr_warning("mux: No ball data available for omap2420 package\n"); + } + + return omap_mux_init(OMAP2430_CONTROL_PADCONF_MUX_PBASE, + OMAP2430_CONTROL_PADCONF_MUX_SIZE, + omap2430_muxmodes, NULL, board_subset, + package_balls); +} diff --git a/arch/arm/mach-omap2/mux2430.h b/arch/arm/mach-omap2/mux2430.h new file mode 100644 index 00000000000..adbea0d03e0 --- /dev/null +++ b/arch/arm/mach-omap2/mux2430.h @@ -0,0 +1,370 @@ +/* + * Copyright (C) 2009 Nokia + * Copyright (C) 2009 Texas Instruments + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#define OMAP2430_CONTROL_PADCONF_MUX_PBASE 0x49002030LU + +#define OMAP2430_MUX(mode0, mux_value) \ +{ \ + .reg_offset = (OMAP2430_CONTROL_PADCONF_##mode0##_OFFSET), \ + .value = (mux_value), \ +} + +/* + * OMAP2430 CONTROL_PADCONF* register offsets for pin-muxing + * + * Extracted from the TRM. Add 0x49002030 to these values to get the + * absolute addresses. The name in the macro is the mode-0 name of + * the pin. NOTE: These registers are 8-bits wide. + * + * Note that these defines use SDMMC instead of MMC for compability + * with signal names used in 3630. + */ +#define OMAP2430_CONTROL_PADCONF_GPMC_CLK_OFFSET 0x000 +#define OMAP2430_CONTROL_PADCONF_GPMC_NCS0_OFFSET 0x001 +#define OMAP2430_CONTROL_PADCONF_GPMC_NCS1_OFFSET 0x002 +#define OMAP2430_CONTROL_PADCONF_GPMC_NCS2_OFFSET 0x003 +#define OMAP2430_CONTROL_PADCONF_GPMC_NCS3_OFFSET 0x004 +#define OMAP2430_CONTROL_PADCONF_GPMC_NCS4_OFFSET 0x005 +#define OMAP2430_CONTROL_PADCONF_GPMC_NCS5_OFFSET 0x006 +#define OMAP2430_CONTROL_PADCONF_GPMC_NCS6_OFFSET 0x007 +#define OMAP2430_CONTROL_PADCONF_GPMC_NCS7_OFFSET 0x008 +#define OMAP2430_CONTROL_PADCONF_GPMC_NADV_ALE_OFFSET 0x009 +#define OMAP2430_CONTROL_PADCONF_GPMC_NOE_NRE_OFFSET 0x00a +#define OMAP2430_CONTROL_PADCONF_GPMC_NWE_OFFSET 0x00b +#define OMAP2430_CONTROL_PADCONF_GPMC_NBE0_CLE_OFFSET 0x00c +#define OMAP2430_CONTROL_PADCONF_GPMC_NBE1_OFFSET 0x00d +#define OMAP2430_CONTROL_PADCONF_GPMC_NWP_OFFSET 0x00e +#define OMAP2430_CONTROL_PADCONF_GPMC_WAIT0_OFFSET 0x00f +#define OMAP2430_CONTROL_PADCONF_GPMC_WAIT1_OFFSET 0x010 +#define OMAP2430_CONTROL_PADCONF_GPMC_WAIT2_OFFSET 0x011 +#define OMAP2430_CONTROL_PADCONF_GPMC_WAIT3_OFFSET 0x012 +#define OMAP2430_CONTROL_PADCONF_SDRC_CLK_OFFSET 0x013 +#define OMAP2430_CONTROL_PADCONF_SDRC_NCLK_OFFSET 0x014 +#define OMAP2430_CONTROL_PADCONF_SDRC_NCS0_OFFSET 0x015 +#define OMAP2430_CONTROL_PADCONF_SDRC_NCS1_OFFSET 0x016 +#define OMAP2430_CONTROL_PADCONF_SDRC_CKE0_OFFSET 0x017 +#define OMAP2430_CONTROL_PADCONF_SDRC_CKE1_OFFSET 0x018 +#define OMAP2430_CONTROL_PADCONF_SDRC_NRAS_OFFSET 0x019 +#define OMAP2430_CONTROL_PADCONF_SDRC_NCAS_OFFSET 0x01a +#define OMAP2430_CONTROL_PADCONF_SDRC_NWE_OFFSET 0x01b +#define OMAP2430_CONTROL_PADCONF_SDRC_DM0_OFFSET 0x01c +#define OMAP2430_CONTROL_PADCONF_SDRC_DM1_OFFSET 0x01d +#define OMAP2430_CONTROL_PADCONF_SDRC_DM2_OFFSET 0x01e +#define OMAP2430_CONTROL_PADCONF_SDRC_DM3_OFFSET 0x01f +#define OMAP2430_CONTROL_PADCONF_SDRC_DQS0_OFFSET 0x020 +#define OMAP2430_CONTROL_PADCONF_SDRC_DQS1_OFFSET 0x021 +#define OMAP2430_CONTROL_PADCONF_SDRC_DQS2_OFFSET 0x022 +#define OMAP2430_CONTROL_PADCONF_SDRC_DQS3_OFFSET 0x023 +#define OMAP2430_CONTROL_PADCONF_SDRC_A14_OFFSET 0x024 +#define OMAP2430_CONTROL_PADCONF_SDRC_A13_OFFSET 0x025 +#define OMAP2430_CONTROL_PADCONF_SDRC_A12_OFFSET 0x026 +#define OMAP2430_CONTROL_PADCONF_SDRC_BA1_OFFSET 0x027 +#define OMAP2430_CONTROL_PADCONF_SDRC_BA0_OFFSET 0x028 +#define OMAP2430_CONTROL_PADCONF_SDRC_A11_OFFSET 0x029 +#define OMAP2430_CONTROL_PADCONF_SDRC_A10_OFFSET 0x02a +#define OMAP2430_CONTROL_PADCONF_SDRC_A9_OFFSET 0x02b +#define OMAP2430_CONTROL_PADCONF_SDRC_A8_OFFSET 0x02c +#define OMAP2430_CONTROL_PADCONF_SDRC_A7_OFFSET 0x02d +#define OMAP2430_CONTROL_PADCONF_SDRC_A6_OFFSET 0x02e +#define OMAP2430_CONTROL_PADCONF_SDRC_A5_OFFSET 0x02f +#define OMAP2430_CONTROL_PADCONF_SDRC_A4_OFFSET 0x030 +#define OMAP2430_CONTROL_PADCONF_SDRC_A3_OFFSET 0x031 +#define OMAP2430_CONTROL_PADCONF_SDRC_A2_OFFSET 0x032 +#define OMAP2430_CONTROL_PADCONF_SDRC_A1_OFFSET 0x033 +#define OMAP2430_CONTROL_PADCONF_SDRC_A0_OFFSET 0x034 +#define OMAP2430_CONTROL_PADCONF_SDRC_D31_OFFSET 0x035 +#define OMAP2430_CONTROL_PADCONF_SDRC_D30_OFFSET 0x036 +#define OMAP2430_CONTROL_PADCONF_SDRC_D29_OFFSET 0x037 +#define OMAP2430_CONTROL_PADCONF_SDRC_D28_OFFSET 0x038 +#define OMAP2430_CONTROL_PADCONF_SDRC_D27_OFFSET 0x039 +#define OMAP2430_CONTROL_PADCONF_SDRC_D26_OFFSET 0x03a +#define OMAP2430_CONTROL_PADCONF_SDRC_D25_OFFSET 0x03b +#define OMAP2430_CONTROL_PADCONF_SDRC_D24_OFFSET 0x03c +#define OMAP2430_CONTROL_PADCONF_SDRC_D23_OFFSET 0x03d +#define OMAP2430_CONTROL_PADCONF_SDRC_D22_OFFSET 0x03e +#define OMAP2430_CONTROL_PADCONF_SDRC_D21_OFFSET 0x03f +#define OMAP2430_CONTROL_PADCONF_SDRC_D20_OFFSET 0x040 +#define OMAP2430_CONTROL_PADCONF_SDRC_D19_OFFSET 0x041 +#define OMAP2430_CONTROL_PADCONF_SDRC_D18_OFFSET 0x042 +#define OMAP2430_CONTROL_PADCONF_SDRC_D17_OFFSET 0x043 +#define OMAP2430_CONTROL_PADCONF_SDRC_D16_OFFSET 0x044 +#define OMAP2430_CONTROL_PADCONF_SDRC_D15_OFFSET 0x045 +#define OMAP2430_CONTROL_PADCONF_SDRC_D14_OFFSET 0x046 +#define OMAP2430_CONTROL_PADCONF_SDRC_D13_OFFSET 0x047 +#define OMAP2430_CONTROL_PADCONF_SDRC_D12_OFFSET 0x048 +#define OMAP2430_CONTROL_PADCONF_SDRC_D11_OFFSET 0x049 +#define OMAP2430_CONTROL_PADCONF_SDRC_D10_OFFSET 0x04a +#define OMAP2430_CONTROL_PADCONF_SDRC_D9_OFFSET 0x04b +#define OMAP2430_CONTROL_PADCONF_SDRC_D8_OFFSET 0x04c +#define OMAP2430_CONTROL_PADCONF_SDRC_D7_OFFSET 0x04d +#define OMAP2430_CONTROL_PADCONF_SDRC_D6_OFFSET 0x04e +#define OMAP2430_CONTROL_PADCONF_SDRC_D5_OFFSET 0x04f +#define OMAP2430_CONTROL_PADCONF_SDRC_D4_OFFSET 0x050 +#define OMAP2430_CONTROL_PADCONF_SDRC_D3_OFFSET 0x051 +#define OMAP2430_CONTROL_PADCONF_SDRC_D2_OFFSET 0x052 +#define OMAP2430_CONTROL_PADCONF_SDRC_D1_OFFSET 0x053 +#define OMAP2430_CONTROL_PADCONF_SDRC_D0_OFFSET 0x054 +#define OMAP2430_CONTROL_PADCONF_GPMC_A10_OFFSET 0x055 +#define OMAP2430_CONTROL_PADCONF_GPMC_A9_OFFSET 0x056 +#define OMAP2430_CONTROL_PADCONF_GPMC_A8_OFFSET 0x057 +#define OMAP2430_CONTROL_PADCONF_GPMC_A7_OFFSET 0x058 +#define OMAP2430_CONTROL_PADCONF_GPMC_A6_OFFSET 0x059 +#define OMAP2430_CONTROL_PADCONF_GPMC_A5_OFFSET 0x05a +#define OMAP2430_CONTROL_PADCONF_GPMC_A4_OFFSET 0x05b +#define OMAP2430_CONTROL_PADCONF_GPMC_A3_OFFSET 0x05c +#define OMAP2430_CONTROL_PADCONF_GPMC_A2_OFFSET 0x05d +#define OMAP2430_CONTROL_PADCONF_GPMC_A1_OFFSET 0x05e +#define OMAP2430_CONTROL_PADCONF_GPMC_D15_OFFSET 0x05f +#define OMAP2430_CONTROL_PADCONF_GPMC_D14_OFFSET 0x060 +#define OMAP2430_CONTROL_PADCONF_GPMC_D13_OFFSET 0x061 +#define OMAP2430_CONTROL_PADCONF_GPMC_D12_OFFSET 0x062 +#define OMAP2430_CONTROL_PADCONF_GPMC_D11_OFFSET 0x063 +#define OMAP2430_CONTROL_PADCONF_GPMC_D10_OFFSET 0x064 +#define OMAP2430_CONTROL_PADCONF_GPMC_D9_OFFSET 0x065 +#define OMAP2430_CONTROL_PADCONF_GPMC_D8_OFFSET 0x066 +#define OMAP2430_CONTROL_PADCONF_GPMC_D7_OFFSET 0x067 +#define OMAP2430_CONTROL_PADCONF_GPMC_D6_OFFSET 0x068 +#define OMAP2430_CONTROL_PADCONF_GPMC_D5_OFFSET 0x069 +#define OMAP2430_CONTROL_PADCONF_GPMC_D4_OFFSET 0x06a +#define OMAP2430_CONTROL_PADCONF_GPMC_D3_OFFSET 0x06b +#define OMAP2430_CONTROL_PADCONF_GPMC_D2_OFFSET 0x06c +#define OMAP2430_CONTROL_PADCONF_GPMC_D1_OFFSET 0x06d +#define OMAP2430_CONTROL_PADCONF_GPMC_D0_OFFSET 0x06e +#define OMAP2430_CONTROL_PADCONF_DSS_DATA0_OFFSET 0x06f +#define OMAP2430_CONTROL_PADCONF_DSS_DATA1_OFFSET 0x070 +#define OMAP2430_CONTROL_PADCONF_DSS_DATA2_OFFSET 0x071 +#define OMAP2430_CONTROL_PADCONF_DSS_DATA3_OFFSET 0x072 +#define OMAP2430_CONTROL_PADCONF_DSS_DATA4_OFFSET 0x073 +#define OMAP2430_CONTROL_PADCONF_DSS_DATA5_OFFSET 0x074 +#define OMAP2430_CONTROL_PADCONF_DSS_DATA6_OFFSET 0x075 +#define OMAP2430_CONTROL_PADCONF_DSS_DATA7_OFFSET 0x076 +#define OMAP2430_CONTROL_PADCONF_DSS_DATA8_OFFSET 0x077 +#define OMAP2430_CONTROL_PADCONF_DSS_DATA9_OFFSET 0x078 +#define OMAP2430_CONTROL_PADCONF_DSS_DATA10_OFFSET 0x079 +#define OMAP2430_CONTROL_PADCONF_DSS_DATA11_OFFSET 0x07a +#define OMAP2430_CONTROL_PADCONF_DSS_DATA12_OFFSET 0x07b +#define OMAP2430_CONTROL_PADCONF_DSS_DATA13_OFFSET 0x07c +#define OMAP2430_CONTROL_PADCONF_DSS_DATA14_OFFSET 0x07d +#define OMAP2430_CONTROL_PADCONF_DSS_DATA15_OFFSET 0x07e +#define OMAP2430_CONTROL_PADCONF_DSS_DATA16_OFFSET 0x07f +#define OMAP2430_CONTROL_PADCONF_DSS_DATA17_OFFSET 0x080 +#define OMAP2430_CONTROL_PADCONF_UART1_CTS_OFFSET 0x081 +#define OMAP2430_CONTROL_PADCONF_UART1_RTS_OFFSET 0x082 +#define OMAP2430_CONTROL_PADCONF_UART1_TX_OFFSET 0x083 +#define OMAP2430_CONTROL_PADCONF_UART1_RX_OFFSET 0x084 +#define OMAP2430_CONTROL_PADCONF_MCBSP2_DR_OFFSET 0x085 +#define OMAP2430_CONTROL_PADCONF_MCBSP2_CLKX_OFFSET 0x086 +#define OMAP2430_CONTROL_PADCONF_DSS_PCLK_OFFSET 0x087 +#define OMAP2430_CONTROL_PADCONF_DSS_VSYNC_OFFSET 0x088 +#define OMAP2430_CONTROL_PADCONF_DSS_HSYNC_OFFSET 0x089 +#define OMAP2430_CONTROL_PADCONF_DSS_ACBIAS_OFFSET 0x08a +#define OMAP2430_CONTROL_PADCONF_SYS_NRESPWRON_OFFSET 0x08b +#define OMAP2430_CONTROL_PADCONF_SYS_NRESWARM_OFFSET 0x08c +#define OMAP2430_CONTROL_PADCONF_SYS_NIRQ0_OFFSET 0x08d +#define OMAP2430_CONTROL_PADCONF_SYS_NIRQ1_OFFSET 0x08e +#define OMAP2430_CONTROL_PADCONF_SYS_VMODE_OFFSET 0x08f +#define OMAP2430_CONTROL_PADCONF_GPIO_128_OFFSET 0x090 +#define OMAP2430_CONTROL_PADCONF_GPIO_129_OFFSET 0x091 +#define OMAP2430_CONTROL_PADCONF_GPIO_130_OFFSET 0x092 +#define OMAP2430_CONTROL_PADCONF_GPIO_131_OFFSET 0x093 +#define OMAP2430_CONTROL_PADCONF_SYS_32K_OFFSET 0x094 +#define OMAP2430_CONTROL_PADCONF_SYS_XTALIN_OFFSET 0x095 +#define OMAP2430_CONTROL_PADCONF_SYS_XTALOUT_OFFSET 0x096 +#define OMAP2430_CONTROL_PADCONF_GPIO_132_OFFSET 0x097 +#define OMAP2430_CONTROL_PADCONF_SYS_CLKREQ_OFFSET 0x098 +#define OMAP2430_CONTROL_PADCONF_SYS_CLKOUT_OFFSET 0x099 +#define OMAP2430_CONTROL_PADCONF_GPIO_151_OFFSET 0x09a +#define OMAP2430_CONTROL_PADCONF_GPIO_133_OFFSET 0x09b +#define OMAP2430_CONTROL_PADCONF_JTAG_EMU1_OFFSET 0x09c +#define OMAP2430_CONTROL_PADCONF_JTAG_EMU0_OFFSET 0x09d +#define OMAP2430_CONTROL_PADCONF_JTAG_NTRST_OFFSET 0x09e +#define OMAP2430_CONTROL_PADCONF_JTAG_TCK_OFFSET 0x09f +#define OMAP2430_CONTROL_PADCONF_JTAG_RTCK_OFFSET 0x0a0 +#define OMAP2430_CONTROL_PADCONF_JTAG_TMS_OFFSET 0x0a1 +#define OMAP2430_CONTROL_PADCONF_JTAG_TDI_OFFSET 0x0a2 +#define OMAP2430_CONTROL_PADCONF_JTAG_TDO_OFFSET 0x0a3 +#define OMAP2430_CONTROL_PADCONF_CAM_D9_OFFSET 0x0a4 +#define OMAP2430_CONTROL_PADCONF_CAM_D8_OFFSET 0x0a5 +#define OMAP2430_CONTROL_PADCONF_CAM_D7_OFFSET 0x0a6 +#define OMAP2430_CONTROL_PADCONF_CAM_D6_OFFSET 0x0a7 +#define OMAP2430_CONTROL_PADCONF_CAM_D5_OFFSET 0x0a8 +#define OMAP2430_CONTROL_PADCONF_CAM_D4_OFFSET 0x0a9 +#define OMAP2430_CONTROL_PADCONF_CAM_D3_OFFSET 0x0aa +#define OMAP2430_CONTROL_PADCONF_CAM_D2_OFFSET 0x0ab +#define OMAP2430_CONTROL_PADCONF_CAM_D1_OFFSET 0x0ac +#define OMAP2430_CONTROL_PADCONF_CAM_D0_OFFSET 0x0ad +#define OMAP2430_CONTROL_PADCONF_CAM_HS_OFFSET 0x0ae +#define OMAP2430_CONTROL_PADCONF_CAM_VS_OFFSET 0x0af +#define OMAP2430_CONTROL_PADCONF_CAM_LCLK_OFFSET 0x0b0 +#define OMAP2430_CONTROL_PADCONF_CAM_XCLK_OFFSET 0x0b1 +#define OMAP2430_CONTROL_PADCONF_CAM_D11_OFFSET 0x0b2 +#define OMAP2430_CONTROL_PADCONF_CAM_D10_OFFSET 0x0b3 +#define OMAP2430_CONTROL_PADCONF_GPIO_134_OFFSET 0x0b4 +#define OMAP2430_CONTROL_PADCONF_GPIO_135_OFFSET 0x0b5 +#define OMAP2430_CONTROL_PADCONF_GPIO_136_OFFSET 0x0b6 +#define OMAP2430_CONTROL_PADCONF_GPIO_137_OFFSET 0x0b7 +#define OMAP2430_CONTROL_PADCONF_GPIO_138_OFFSET 0x0b8 +#define OMAP2430_CONTROL_PADCONF_GPIO_139_OFFSET 0x0b9 +#define OMAP2430_CONTROL_PADCONF_GPIO_140_OFFSET 0x0ba +#define OMAP2430_CONTROL_PADCONF_GPIO_141_OFFSET 0x0bb +#define OMAP2430_CONTROL_PADCONF_GPIO_142_OFFSET 0x0bc +#define OMAP2430_CONTROL_PADCONF_GPIO_154_OFFSET 0x0bd +#define OMAP2430_CONTROL_PADCONF_GPIO_148_OFFSET 0x0be +#define OMAP2430_CONTROL_PADCONF_GPIO_149_OFFSET 0x0bf +#define OMAP2430_CONTROL_PADCONF_GPIO_150_OFFSET 0x0c0 +#define OMAP2430_CONTROL_PADCONF_GPIO_152_OFFSET 0x0c1 +#define OMAP2430_CONTROL_PADCONF_GPIO_153_OFFSET 0x0c2 +#define OMAP2430_CONTROL_PADCONF_SDMMC1_CLKO_OFFSET 0x0c3 +#define OMAP2430_CONTROL_PADCONF_SDMMC1_CMD_OFFSET 0x0c4 +#define OMAP2430_CONTROL_PADCONF_SDMMC1_DAT0_OFFSET 0x0c5 +#define OMAP2430_CONTROL_PADCONF_SDMMC1_DAT1_OFFSET 0x0c6 +#define OMAP2430_CONTROL_PADCONF_SDMMC1_DAT2_OFFSET 0x0c7 +#define OMAP2430_CONTROL_PADCONF_SDMMC1_DAT3_OFFSET 0x0c8 +#define OMAP2430_CONTROL_PADCONF_SDMMC2_CLKO_OFFSET 0x0c9 +#define OMAP2430_CONTROL_PADCONF_SDMMC2_DAT3_OFFSET 0x0ca +#define OMAP2430_CONTROL_PADCONF_SDMMC2_CMD_OFFSET 0x0cb +#define OMAP2430_CONTROL_PADCONF_SDMMC2_DAT0_OFFSET 0x0cc +#define OMAP2430_CONTROL_PADCONF_SDMMC2_DAT2_OFFSET 0x0cd +#define OMAP2430_CONTROL_PADCONF_SDMMC2_DAT1_OFFSET 0x0ce +#define OMAP2430_CONTROL_PADCONF_UART2_CTS_OFFSET 0x0cf +#define OMAP2430_CONTROL_PADCONF_UART2_RTS_OFFSET 0x0d0 +#define OMAP2430_CONTROL_PADCONF_UART2_TX_OFFSET 0x0d1 +#define OMAP2430_CONTROL_PADCONF_UART2_RX_OFFSET 0x0d2 +#define OMAP2430_CONTROL_PADCONF_MCBSP3_CLKX_OFFSET 0x0d3 +#define OMAP2430_CONTROL_PADCONF_MCBSP3_FSX_OFFSET 0x0d4 +#define OMAP2430_CONTROL_PADCONF_MCBSP3_DR_OFFSET 0x0d5 +#define OMAP2430_CONTROL_PADCONF_MCBSP3_DX_OFFSET 0x0d6 +#define OMAP2430_CONTROL_PADCONF_SSI1_DAT_TX_OFFSET 0x0d7 +#define OMAP2430_CONTROL_PADCONF_SSI1_FLAG_TX_OFFSET 0x0d8 +#define OMAP2430_CONTROL_PADCONF_SSI1_RDY_TX_OFFSET 0x0d9 +#define OMAP2430_CONTROL_PADCONF_SSI1_DAT_RX_OFFSET 0x0da +#define OMAP2430_CONTROL_PADCONF_GPIO_63_OFFSET 0x0db +#define OMAP2430_CONTROL_PADCONF_SSI1_FLAG_RX_OFFSET 0x0dc +#define OMAP2430_CONTROL_PADCONF_SSI1_RDY_RX_OFFSET 0x0dd +#define OMAP2430_CONTROL_PADCONF_SSI1_WAKE_OFFSET 0x0de +#define OMAP2430_CONTROL_PADCONF_SPI1_CLK_OFFSET 0x0df +#define OMAP2430_CONTROL_PADCONF_SPI1_SIMO_OFFSET 0x0e0 +#define OMAP2430_CONTROL_PADCONF_SPI1_SOMI_OFFSET 0x0e1 +#define OMAP2430_CONTROL_PADCONF_SPI1_CS0_OFFSET 0x0e2 +#define OMAP2430_CONTROL_PADCONF_SPI1_CS1_OFFSET 0x0e3 +#define OMAP2430_CONTROL_PADCONF_SPI1_CS2_OFFSET 0x0e4 +#define OMAP2430_CONTROL_PADCONF_SPI1_CS3_OFFSET 0x0e5 +#define OMAP2430_CONTROL_PADCONF_SPI2_CLK_OFFSET 0x0e6 +#define OMAP2430_CONTROL_PADCONF_SPI2_SIMO_OFFSET 0x0e7 +#define OMAP2430_CONTROL_PADCONF_SPI2_SOMI_OFFSET 0x0e8 +#define OMAP2430_CONTROL_PADCONF_SPI2_CS0_OFFSET 0x0e9 +#define OMAP2430_CONTROL_PADCONF_MCBSP1_CLKR_OFFSET 0x0ea +#define OMAP2430_CONTROL_PADCONF_MCBSP1_FSR_OFFSET 0x0eb +#define OMAP2430_CONTROL_PADCONF_MCBSP1_DX_OFFSET 0x0ec +#define OMAP2430_CONTROL_PADCONF_MCBSP1_DR_OFFSET 0x0ed +#define OMAP2430_CONTROL_PADCONF_MCBSP_CLKS_OFFSET 0x0ee +#define OMAP2430_CONTROL_PADCONF_MCBSP1_FSX_OFFSET 0x0ef +#define OMAP2430_CONTROL_PADCONF_MCBSP1_CLKX_OFFSET 0x0f0 +#define OMAP2430_CONTROL_PADCONF_I2C1_SCL_OFFSET 0x0f1 +#define OMAP2430_CONTROL_PADCONF_I2C1_SDA_OFFSET 0x0f2 +#define OMAP2430_CONTROL_PADCONF_I2C2_SCL_OFFSET 0x0f3 +#define OMAP2430_CONTROL_PADCONF_I2C2_SDA_OFFSET 0x0f4 +#define OMAP2430_CONTROL_PADCONF_HDQ_SIO_OFFSET 0x0f5 +#define OMAP2430_CONTROL_PADCONF_UART3_CTS_RCTX_OFFSET 0x0f6 +#define OMAP2430_CONTROL_PADCONF_UART3_RTS_SD_OFFSET 0x0f7 +#define OMAP2430_CONTROL_PADCONF_UART3_TX_IRTX_OFFSET 0x0f8 +#define OMAP2430_CONTROL_PADCONF_UART3_RX_IRRX_OFFSET 0x0f9 +#define OMAP2430_CONTROL_PADCONF_GPIO_7_OFFSET 0x0fa +#define OMAP2430_CONTROL_PADCONF_GPIO_78_OFFSET 0x0fb +#define OMAP2430_CONTROL_PADCONF_GPIO_79_OFFSET 0x0fc +#define OMAP2430_CONTROL_PADCONF_GPIO_80_OFFSET 0x0fd +#define OMAP2430_CONTROL_PADCONF_GPIO_113_OFFSET 0x0fe +#define OMAP2430_CONTROL_PADCONF_GPIO_114_OFFSET 0x0ff +#define OMAP2430_CONTROL_PADCONF_GPIO_115_OFFSET 0x100 +#define OMAP2430_CONTROL_PADCONF_GPIO_116_OFFSET 0x101 +#define OMAP2430_CONTROL_PADCONF_SYS_DRM_MSECURE_OFFSET 0x102 +#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA3_OFFSET 0x103 +#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA4_OFFSET 0x104 +#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA5_OFFSET 0x105 +#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA6_OFFSET 0x106 +#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA2_OFFSET 0x107 +#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA0_OFFSET 0x108 +#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA1_OFFSET 0x109 +#define OMAP2430_CONTROL_PADCONF_USB0HS_CLK_OFFSET 0x10a +#define OMAP2430_CONTROL_PADCONF_USB0HS_DIR_OFFSET 0x10b +#define OMAP2430_CONTROL_PADCONF_USB0HS_STP_OFFSET 0x10c +#define OMAP2430_CONTROL_PADCONF_USB0HS_NXT_OFFSET 0x10d +#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA7_OFFSET 0x10e +#define OMAP2430_CONTROL_PADCONF_TV_OUT_OFFSET 0x10f +#define OMAP2430_CONTROL_PADCONF_TV_VREF_OFFSET 0x110 +#define OMAP2430_CONTROL_PADCONF_TV_RSET_OFFSET 0x111 +#define OMAP2430_CONTROL_PADCONF_TV_VFB_OFFSET 0x112 +#define OMAP2430_CONTROL_PADCONF_TV_DACOUT_OFFSET 0x113 +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD0_OFFSET 0x114 +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD1_OFFSET 0x115 +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD2_OFFSET 0x116 +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD3_OFFSET 0x117 +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD4_OFFSET 0x118 +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD5_OFFSET 0x119 +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD6_OFFSET 0x11a +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD7_OFFSET 0x11b +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD8_OFFSET 0x11c +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD9_OFFSET 0x11d +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD10_OFFSET 0x11e +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD11_OFFSET 0x11f +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD12_OFFSET 0x120 +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD13_OFFSET 0x121 +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD14_OFFSET 0x122 +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD15_OFFSET 0x123 +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD16_OFFSET 0x124 +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD17_OFFSET 0x125 +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD18_OFFSET 0x126 +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD19_OFFSET 0x127 +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD20_OFFSET 0x128 +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD21_OFFSET 0x129 +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD22_OFFSET 0x12a +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD23_OFFSET 0x12b +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD24_OFFSET 0x12c +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD25_OFFSET 0x12d +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD26_OFFSET 0x12e +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD27_OFFSET 0x12f +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD28_OFFSET 0x130 +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD29_OFFSET 0x131 +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD30_OFFSET 0x132 +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD31_OFFSET 0x133 +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD32_OFFSET 0x134 +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD33_OFFSET 0x135 +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD34_OFFSET 0x136 +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD35_OFFSET 0x137 +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD36_OFFSET 0x138 +#define OMAP2430_CONTROL_PADCONF_AD2DMCAD37_OFFSET 0x139 +#define OMAP2430_CONTROL_PADCONF_AD2DMWRITE_OFFSET 0x13a +#define OMAP2430_CONTROL_PADCONF_D2DCLK26MI_OFFSET 0x13b +#define OMAP2430_CONTROL_PADCONF_D2DNRESPWRON1_OFFSET 0x13c +#define OMAP2430_CONTROL_PADCONF_D2DNRESWARM_OFFSET 0x13d +#define OMAP2430_CONTROL_PADCONF_D2DARM9NIRQ_OFFSET 0x13e +#define OMAP2430_CONTROL_PADCONF_D2DUMA2P6FIQ_OFFSET 0x13f +#define OMAP2430_CONTROL_PADCONF_D2DSPINT_OFFSET 0x140 +#define OMAP2430_CONTROL_PADCONF_D2DFRINT_OFFSET 0x141 +#define OMAP2430_CONTROL_PADCONF_D2DDMAREQ0_OFFSET 0x142 +#define OMAP2430_CONTROL_PADCONF_D2DDMAREQ1_OFFSET 0x143 +#define OMAP2430_CONTROL_PADCONF_D2DDMAREQ2_OFFSET 0x144 +#define OMAP2430_CONTROL_PADCONF_D2DDMAREQ3_OFFSET 0x145 +#define OMAP2430_CONTROL_PADCONF_D2DN3GTRST_OFFSET 0x146 +#define OMAP2430_CONTROL_PADCONF_D2DN3GTDI_OFFSET 0x147 +#define OMAP2430_CONTROL_PADCONF_D2DN3GTDO_OFFSET 0x148 +#define OMAP2430_CONTROL_PADCONF_D2DN3GTMS_OFFSET 0x149 +#define OMAP2430_CONTROL_PADCONF_D2DN3GTCK_OFFSET 0x14a +#define OMAP2430_CONTROL_PADCONF_D2DN3GRTCK_OFFSET 0x14b +#define OMAP2430_CONTROL_PADCONF_D2DMSTDBY_OFFSET 0x14c +#define OMAP2430_CONTROL_PADCONF_AD2DSREAD_OFFSET 0x14d +#define OMAP2430_CONTROL_PADCONF_D2DSWAKEUP_OFFSET 0x14e +#define OMAP2430_CONTROL_PADCONF_D2DIDLEREQ_OFFSET 0x14f +#define OMAP2430_CONTROL_PADCONF_D2DIDLEACK_OFFSET 0x150 +#define OMAP2430_CONTROL_PADCONF_D2DSPARE0_OFFSET 0x151 +#define OMAP2430_CONTROL_PADCONF_AD2DSWRITE_OFFSET 0x152 +#define OMAP2430_CONTROL_PADCONF_AD2DMREAD_OFFSET 0x153 + +#define OMAP2430_CONTROL_PADCONF_MUX_SIZE \ + (OMAP2430_CONTROL_PADCONF_AD2DMREAD_OFFSET + 0x1) diff --git a/arch/arm/mach-omap2/mux34xx.c b/arch/arm/mach-omap2/mux34xx.c index 2ff4dce95ee..f64d7eea345 100644 --- a/arch/arm/mach-omap2/mux34xx.c +++ b/arch/arm/mach-omap2/mux34xx.c @@ -2032,19 +2032,19 @@ int __init omap3_mux_init(struct omap_board_mux *board_subset, int flags) struct omap_ball *package_balls; switch (flags & OMAP_PACKAGE_MASK) { - case (OMAP_PACKAGE_CBC): + case OMAP_PACKAGE_CBC: package_subset = omap3_cbc_subset; package_balls = omap3_cbc_ball; break; - case (OMAP_PACKAGE_CBB): + case OMAP_PACKAGE_CBB: package_subset = omap3_cbb_subset; package_balls = omap3_cbb_ball; break; - case (OMAP_PACKAGE_CUS): + case OMAP_PACKAGE_CUS: package_subset = omap3_cus_subset; package_balls = omap3_cus_ball; break; - case (OMAP_PACKAGE_CBP): + case OMAP_PACKAGE_CBP: package_subset = omap36xx_cbp_subset; package_balls = omap36xx_cbp_ball; break; diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S index ef0e7a00dd6..6ae937a06cc 100644 --- a/arch/arm/mach-omap2/omap-headsmp.S +++ b/arch/arm/mach-omap2/omap-headsmp.S @@ -47,19 +47,3 @@ hold: ldr r12,=0x103 b secondary_startup END(omap_secondary_startup) - -ENTRY(omap_modify_auxcoreboot0) - stmfd sp!, {r1-r12, lr} - ldr r12, =0x104 - dsb - smc #0 - ldmfd sp!, {r1-r12, pc} -END(omap_modify_auxcoreboot0) - -ENTRY(omap_auxcoreboot_addr) - stmfd sp!, {r2-r12, lr} - ldr r12, =0x105 - dsb - smc #0 - ldmfd sp!, {r2-r12, pc} -END(omap_auxcoreboot_addr) diff --git a/arch/arm/mach-omap2/omap-hotplug.c b/arch/arm/mach-omap2/omap-hotplug.c new file mode 100644 index 00000000000..6cee456ca54 --- /dev/null +++ b/arch/arm/mach-omap2/omap-hotplug.c @@ -0,0 +1,79 @@ +/* + * OMAP4 SMP cpu-hotplug support + * + * Copyright (C) 2010 Texas Instruments, Inc. + * Author: + * Santosh Shilimkar <santosh.shilimkar@ti.com> + * + * Platform file needed for the OMAP4 SMP. This file is based on arm + * realview smp platform. + * Copyright (c) 2002 ARM Limited. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/errno.h> +#include <linux/smp.h> +#include <linux/completion.h> + +#include <asm/cacheflush.h> +#include <mach/omap4-common.h> + +static DECLARE_COMPLETION(cpu_killed); + +int platform_cpu_kill(unsigned int cpu) +{ + return wait_for_completion_timeout(&cpu_killed, 5000); +} + +/* + * platform-specific code to shutdown a CPU + * Called with IRQs disabled + */ +void platform_cpu_die(unsigned int cpu) +{ + unsigned int this_cpu = hard_smp_processor_id(); + + if (cpu != this_cpu) { + pr_crit("platform_cpu_die running on %u, should be %u\n", + this_cpu, cpu); + BUG(); + } + pr_notice("CPU%u: shutdown\n", cpu); + complete(&cpu_killed); + flush_cache_all(); + dsb(); + + /* + * we're ready for shutdown now, so do it + */ + if (omap_modify_auxcoreboot0(0x0, 0x200) != 0x0) + printk(KERN_CRIT "Secure clear status failed\n"); + + for (;;) { + /* + * Execute WFI + */ + do_wfi(); + + if (omap_read_auxcoreboot0() == cpu) { + /* + * OK, proper wakeup, we're done + */ + break; + } + pr_debug("CPU%u: spurious wakeup call\n", cpu); + } +} + +int platform_cpu_disable(unsigned int cpu) +{ + /* + * we don't allow CPU 0 to be shutdown (it is still too special + * e.g. clock tick interrupts) + */ + return cpu == 0 ? -EPERM : 0; +} diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c index eb9bee73e0c..f5a1aad1a5c 100644 --- a/arch/arm/mach-omap2/omap-iommu.c +++ b/arch/arm/mach-omap2/omap-iommu.c @@ -59,7 +59,7 @@ static struct platform_device *omap3_iommu_pdev[NR_OMAP3_IOMMU_DEVICES]; static struct iommu_device omap4_devices[] = { { .base = OMAP4_MMU1_BASE, - .irq = INT_44XX_DUCATI_MMU_IRQ, + .irq = OMAP44XX_IRQ_DUCATI_MMU, .pdata = { .name = "ducati", .nr_tlb_entries = 32, diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c index 1cf52313759..af3c20c8d3f 100644 --- a/arch/arm/mach-omap2/omap-smp.c +++ b/arch/arm/mach-omap2/omap-smp.c @@ -73,9 +73,10 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) * the AuxCoreBoot1 register is updated with cpu state * A barrier is added to ensure that write buffer is drained */ - omap_modify_auxcoreboot0(0x200, 0x0); + omap_modify_auxcoreboot0(0x200, 0xfffffdff); flush_cache_all(); smp_wmb(); + smp_cross_call(cpumask_of(cpu)); /* * Now the secondary core is starting up let it run its diff --git a/arch/arm/mach-omap2/omap44xx-smc.S b/arch/arm/mach-omap2/omap44xx-smc.S index f61c7771ca4..1980dc31a1a 100644 --- a/arch/arm/mach-omap2/omap44xx-smc.S +++ b/arch/arm/mach-omap2/omap44xx-smc.S @@ -30,3 +30,28 @@ ENTRY(omap_smc1) smc #0 ldmfd sp!, {r2-r12, pc} END(omap_smc1) + +ENTRY(omap_modify_auxcoreboot0) + stmfd sp!, {r1-r12, lr} + ldr r12, =0x104 + dsb + smc #0 + ldmfd sp!, {r1-r12, pc} +END(omap_modify_auxcoreboot0) + +ENTRY(omap_auxcoreboot_addr) + stmfd sp!, {r2-r12, lr} + ldr r12, =0x105 + dsb + smc #0 + ldmfd sp!, {r2-r12, pc} +END(omap_auxcoreboot_addr) + +ENTRY(omap_read_auxcoreboot0) + stmfd sp!, {r2-r12, lr} + ldr r12, =0x103 + dsb + smc #0 + mov r0, r0, lsr #9 + ldmfd sp!, {r2-r12, pc} +END(omap_read_auxcoreboot0) diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index b7a4133267d..cb911d7d1a3 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -1,7 +1,7 @@ /* * omap_hwmod implementation for OMAP2/3/4 * - * Copyright (C) 2009 Nokia Corporation + * Copyright (C) 2009-2010 Nokia Corporation * * Paul Walmsley, Benoît Cousson, Kevin Hilman * @@ -423,7 +423,7 @@ static int _init_main_clk(struct omap_hwmod *oh) } /** - * _init_interface_clk - get a struct clk * for the the hwmod's interface clks + * _init_interface_clks - get a struct clk * for the the hwmod's interface clks * @oh: struct omap_hwmod * * * Called from _init_clocks(). Populates the @oh OCP slave interface @@ -764,6 +764,7 @@ static struct omap_hwmod *_lookup(const char *name) /** * _init_clocks - clk_get() all clocks associated with this hwmod * @oh: struct omap_hwmod * + * @data: not used; pass NULL * * Called by omap_hwmod_late_init() (after omap2_clk_init()). * Resolves all clock names embedded in the hwmod. Must be called @@ -771,7 +772,7 @@ static struct omap_hwmod *_lookup(const char *name) * has not yet been registered or if the clocks have already been * initialized, 0 on success, or a non-zero error on failure. */ -static int _init_clocks(struct omap_hwmod *oh) +static int _init_clocks(struct omap_hwmod *oh, void *data) { int ret = 0; @@ -886,7 +887,7 @@ static int _reset(struct omap_hwmod *oh) } /** - * _enable - enable an omap_hwmod + * _omap_hwmod_enable - enable an omap_hwmod * @oh: struct omap_hwmod * * * Enables an omap_hwmod @oh such that the MPU can access the hwmod's @@ -894,7 +895,7 @@ static int _reset(struct omap_hwmod *oh) * Returns -EINVAL if the hwmod is in the wrong state or passes along * the return value of _wait_target_ready(). */ -static int _enable(struct omap_hwmod *oh) +int _omap_hwmod_enable(struct omap_hwmod *oh) { int r; @@ -939,7 +940,7 @@ static int _enable(struct omap_hwmod *oh) * no further work. Returns -EINVAL if the hwmod is in the wrong * state or returns 0. */ -static int _idle(struct omap_hwmod *oh) +int _omap_hwmod_idle(struct omap_hwmod *oh) { if (oh->_state != _HWMOD_STATE_ENABLED) { WARN(1, "omap_hwmod: %s: idle state can only be entered from " @@ -996,19 +997,25 @@ static int _shutdown(struct omap_hwmod *oh) /** * _setup - do initial configuration of omap_hwmod * @oh: struct omap_hwmod * + * @skip_setup_idle_p: do not idle hwmods at the end of the fn if 1 * * Writes the CLOCKACTIVITY bits @clockact to the hwmod @oh - * OCP_SYSCONFIG register. Must be called with omap_hwmod_mutex - * held. Returns -EINVAL if the hwmod is in the wrong state or returns - * 0. + * OCP_SYSCONFIG register. Must be called with omap_hwmod_mutex held. + * @skip_setup_idle is intended to be used on a system that will not + * call omap_hwmod_enable() to enable devices (e.g., a system without + * PM runtime). Returns -EINVAL if the hwmod is in the wrong state or + * returns 0. */ -static int _setup(struct omap_hwmod *oh) +static int _setup(struct omap_hwmod *oh, void *data) { int i, r; + u8 skip_setup_idle; - if (!oh) + if (!oh || !data) return -EINVAL; + skip_setup_idle = *(u8 *)data; + /* Set iclk autoidle mode */ if (oh->slaves_cnt > 0) { for (i = 0; i < oh->slaves_cnt; i++) { @@ -1029,7 +1036,7 @@ static int _setup(struct omap_hwmod *oh) oh->_state = _HWMOD_STATE_INITIALIZED; - r = _enable(oh); + r = _omap_hwmod_enable(oh); if (r) { pr_warning("omap_hwmod: %s: cannot be enabled (%d)\n", oh->name, oh->_state); @@ -1041,7 +1048,7 @@ static int _setup(struct omap_hwmod *oh) * XXX Do the OCP_SYSCONFIG bits need to be * reprogrammed after a reset? If not, then this can * be removed. If they do, then probably the - * _enable() function should be split to avoid the + * _omap_hwmod_enable() function should be split to avoid the * rewrite of the OCP_SYSCONFIG register. */ if (oh->class->sysc) { @@ -1050,8 +1057,8 @@ static int _setup(struct omap_hwmod *oh) } } - if (!(oh->flags & HWMOD_INIT_NO_IDLE)) - _idle(oh); + if (!(oh->flags & HWMOD_INIT_NO_IDLE) && !skip_setup_idle) + _omap_hwmod_idle(oh); return 0; } @@ -1062,14 +1069,29 @@ static int _setup(struct omap_hwmod *oh) u32 omap_hwmod_readl(struct omap_hwmod *oh, u16 reg_offs) { - return __raw_readl(oh->_rt_va + reg_offs); + return __raw_readl(oh->_mpu_rt_va + reg_offs); } void omap_hwmod_writel(u32 v, struct omap_hwmod *oh, u16 reg_offs) { - __raw_writel(v, oh->_rt_va + reg_offs); + __raw_writel(v, oh->_mpu_rt_va + reg_offs); } +/** + * omap_hwmod_set_slave_idlemode - set the hwmod's OCP slave idlemode + * @oh: struct omap_hwmod * + * @idlemode: SIDLEMODE field bits (shifted to bit 0) + * + * Sets the IP block's OCP slave idlemode in hardware, and updates our + * local copy. Intended to be used by drivers that have some erratum + * that requires direct manipulation of the SIDLEMODE bits. Returns + * -EINVAL if @oh is null, or passes along the return value from + * _set_slave_idlemode(). + * + * XXX Does this function have any current users? If not, we should + * remove it; it is better to let the rest of the hwmod code handle this. + * Any users of this function should be scrutinized carefully. + */ int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode) { u32 v; @@ -1124,7 +1146,7 @@ int omap_hwmod_register(struct omap_hwmod *oh) ms_id = _find_mpu_port_index(oh); if (!IS_ERR_VALUE(ms_id)) { oh->_mpu_port_index = ms_id; - oh->_rt_va = _find_mpu_rt_base(oh, oh->_mpu_port_index); + oh->_mpu_rt_va = _find_mpu_rt_base(oh, oh->_mpu_port_index); } else { oh->_int_flags |= _HWMOD_NO_MPU_PORT; } @@ -1164,6 +1186,7 @@ struct omap_hwmod *omap_hwmod_lookup(const char *name) /** * omap_hwmod_for_each - call function for each registered omap_hwmod * @fn: pointer to a callback function + * @data: void * data to pass to callback function * * Call @fn for each registered omap_hwmod, passing @data to each * function. @fn must return 0 for success or any other value for @@ -1172,7 +1195,8 @@ struct omap_hwmod *omap_hwmod_lookup(const char *name) * caller of omap_hwmod_for_each(). @fn is called with * omap_hwmod_for_each() held. */ -int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh)) +int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data), + void *data) { struct omap_hwmod *temp_oh; int ret; @@ -1182,7 +1206,7 @@ int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh)) mutex_lock(&omap_hwmod_mutex); list_for_each_entry(temp_oh, &omap_hwmod_list, node) { - ret = (*fn)(temp_oh); + ret = (*fn)(temp_oh, data); if (ret) break; } @@ -1229,24 +1253,28 @@ int omap_hwmod_init(struct omap_hwmod **ohs) /** * omap_hwmod_late_init - do some post-clock framework initialization + * @skip_setup_idle: if 1, do not idle hwmods in _setup() * * Must be called after omap2_clk_init(). Resolves the struct clk names * to struct clk pointers for each registered omap_hwmod. Also calls * _setup() on each hwmod. Returns 0. */ -int omap_hwmod_late_init(void) +int omap_hwmod_late_init(u8 skip_setup_idle) { int r; /* XXX check return value */ - r = omap_hwmod_for_each(_init_clocks); + r = omap_hwmod_for_each(_init_clocks, NULL); WARN(r, "omap_hwmod: omap_hwmod_late_init(): _init_clocks failed\n"); mpu_oh = omap_hwmod_lookup(MPU_INITIATOR_NAME); WARN(!mpu_oh, "omap_hwmod: could not find MPU initiator hwmod %s\n", MPU_INITIATOR_NAME); - omap_hwmod_for_each(_setup); + if (skip_setup_idle) + pr_debug("omap_hwmod: will leave hwmods enabled during setup\n"); + + omap_hwmod_for_each(_setup, &skip_setup_idle); return 0; } @@ -1270,7 +1298,7 @@ int omap_hwmod_unregister(struct omap_hwmod *oh) pr_debug("omap_hwmod: %s: unregistering\n", oh->name); mutex_lock(&omap_hwmod_mutex); - iounmap(oh->_rt_va); + iounmap(oh->_mpu_rt_va); list_del(&oh->node); mutex_unlock(&omap_hwmod_mutex); @@ -1292,12 +1320,13 @@ int omap_hwmod_enable(struct omap_hwmod *oh) return -EINVAL; mutex_lock(&omap_hwmod_mutex); - r = _enable(oh); + r = _omap_hwmod_enable(oh); mutex_unlock(&omap_hwmod_mutex); return r; } + /** * omap_hwmod_idle - idle an omap_hwmod * @oh: struct omap_hwmod * @@ -1311,7 +1340,7 @@ int omap_hwmod_idle(struct omap_hwmod *oh) return -EINVAL; mutex_lock(&omap_hwmod_mutex); - _idle(oh); + _omap_hwmod_idle(oh); mutex_unlock(&omap_hwmod_mutex); return 0; @@ -1413,7 +1442,7 @@ int omap_hwmod_reset(struct omap_hwmod *oh) mutex_lock(&omap_hwmod_mutex); r = _reset(oh); if (!r) - r = _enable(oh); + r = _omap_hwmod_enable(oh); mutex_unlock(&omap_hwmod_mutex); return r; @@ -1530,6 +1559,29 @@ struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh) } /** + * omap_hwmod_get_mpu_rt_va - return the module's base address (for the MPU) + * @oh: struct omap_hwmod * + * + * Returns the virtual address corresponding to the beginning of the + * module's register target, in the address range that is intended to + * be used by the MPU. Returns the virtual address upon success or NULL + * upon error. + */ +void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh) +{ + if (!oh) + return NULL; + + if (oh->_int_flags & _HWMOD_NO_MPU_PORT) + return NULL; + + if (oh->_state == _HWMOD_STATE_UNKNOWN) + return NULL; + + return oh->_mpu_rt_va; +} + +/** * omap_hwmod_add_initiator_dep - add sleepdep from @init_oh to @oh * @oh: struct omap_hwmod * * @init_oh: struct omap_hwmod * (initiator) diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index e5530c51f77..3cc768e8bc0 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -30,42 +30,44 @@ */ static struct omap_hwmod omap2420_mpu_hwmod; -static struct omap_hwmod omap2420_l3_hwmod; +static struct omap_hwmod omap2420_iva_hwmod; +static struct omap_hwmod omap2420_l3_main_hwmod; static struct omap_hwmod omap2420_l4_core_hwmod; /* L3 -> L4_CORE interface */ -static struct omap_hwmod_ocp_if omap2420_l3__l4_core = { - .master = &omap2420_l3_hwmod, +static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = { + .master = &omap2420_l3_main_hwmod, .slave = &omap2420_l4_core_hwmod, .user = OCP_USER_MPU | OCP_USER_SDMA, }; /* MPU -> L3 interface */ -static struct omap_hwmod_ocp_if omap2420_mpu__l3 = { +static struct omap_hwmod_ocp_if omap2420_mpu__l3_main = { .master = &omap2420_mpu_hwmod, - .slave = &omap2420_l3_hwmod, + .slave = &omap2420_l3_main_hwmod, .user = OCP_USER_MPU, }; /* Slave interfaces on the L3 interconnect */ -static struct omap_hwmod_ocp_if *omap2420_l3_slaves[] = { - &omap2420_mpu__l3, +static struct omap_hwmod_ocp_if *omap2420_l3_main_slaves[] = { + &omap2420_mpu__l3_main, }; /* Master interfaces on the L3 interconnect */ -static struct omap_hwmod_ocp_if *omap2420_l3_masters[] = { - &omap2420_l3__l4_core, +static struct omap_hwmod_ocp_if *omap2420_l3_main_masters[] = { + &omap2420_l3_main__l4_core, }; /* L3 */ -static struct omap_hwmod omap2420_l3_hwmod = { - .name = "l3_hwmod", +static struct omap_hwmod omap2420_l3_main_hwmod = { + .name = "l3_main", .class = &l3_hwmod_class, - .masters = omap2420_l3_masters, - .masters_cnt = ARRAY_SIZE(omap2420_l3_masters), - .slaves = omap2420_l3_slaves, - .slaves_cnt = ARRAY_SIZE(omap2420_l3_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) + .masters = omap2420_l3_main_masters, + .masters_cnt = ARRAY_SIZE(omap2420_l3_main_masters), + .slaves = omap2420_l3_main_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_l3_main_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), + .flags = HWMOD_NO_IDLEST, }; static struct omap_hwmod omap2420_l4_wkup_hwmod; @@ -79,7 +81,7 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = { /* Slave interfaces on the L4_CORE interconnect */ static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = { - &omap2420_l3__l4_core, + &omap2420_l3_main__l4_core, }; /* Master interfaces on the L4_CORE interconnect */ @@ -89,13 +91,14 @@ static struct omap_hwmod_ocp_if *omap2420_l4_core_masters[] = { /* L4 CORE */ static struct omap_hwmod omap2420_l4_core_hwmod = { - .name = "l4_core_hwmod", + .name = "l4_core", .class = &l4_hwmod_class, .masters = omap2420_l4_core_masters, .masters_cnt = ARRAY_SIZE(omap2420_l4_core_masters), .slaves = omap2420_l4_core_slaves, .slaves_cnt = ARRAY_SIZE(omap2420_l4_core_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), + .flags = HWMOD_NO_IDLEST, }; /* Slave interfaces on the L4_WKUP interconnect */ @@ -109,18 +112,19 @@ static struct omap_hwmod_ocp_if *omap2420_l4_wkup_masters[] = { /* L4 WKUP */ static struct omap_hwmod omap2420_l4_wkup_hwmod = { - .name = "l4_wkup_hwmod", + .name = "l4_wkup", .class = &l4_hwmod_class, .masters = omap2420_l4_wkup_masters, .masters_cnt = ARRAY_SIZE(omap2420_l4_wkup_masters), .slaves = omap2420_l4_wkup_slaves, .slaves_cnt = ARRAY_SIZE(omap2420_l4_wkup_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), + .flags = HWMOD_NO_IDLEST, }; /* Master interfaces on the MPU device */ static struct omap_hwmod_ocp_if *omap2420_mpu_masters[] = { - &omap2420_mpu__l3, + &omap2420_mpu__l3_main, }; /* MPU */ @@ -133,11 +137,40 @@ static struct omap_hwmod omap2420_mpu_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), }; +/* + * IVA1 interface data + */ + +/* IVA <- L3 interface */ +static struct omap_hwmod_ocp_if omap2420_l3__iva = { + .master = &omap2420_l3_main_hwmod, + .slave = &omap2420_iva_hwmod, + .clk = "iva1_ifck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if *omap2420_iva_masters[] = { + &omap2420_l3__iva, +}; + +/* + * IVA2 (IVA2) + */ + +static struct omap_hwmod omap2420_iva_hwmod = { + .name = "iva", + .class = &iva_hwmod_class, + .masters = omap2420_iva_masters, + .masters_cnt = ARRAY_SIZE(omap2420_iva_masters), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) +}; + static __initdata struct omap_hwmod *omap2420_hwmods[] = { - &omap2420_l3_hwmod, + &omap2420_l3_main_hwmod, &omap2420_l4_core_hwmod, &omap2420_l4_wkup_hwmod, &omap2420_mpu_hwmod, + &omap2420_iva_hwmod, NULL, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index 0852d954da4..4526628ed28 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -30,47 +30,47 @@ */ static struct omap_hwmod omap2430_mpu_hwmod; -static struct omap_hwmod omap2430_l3_hwmod; +static struct omap_hwmod omap2430_iva_hwmod; +static struct omap_hwmod omap2430_l3_main_hwmod; static struct omap_hwmod omap2430_l4_core_hwmod; /* L3 -> L4_CORE interface */ -static struct omap_hwmod_ocp_if omap2430_l3__l4_core = { - .master = &omap2430_l3_hwmod, +static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = { + .master = &omap2430_l3_main_hwmod, .slave = &omap2430_l4_core_hwmod, .user = OCP_USER_MPU | OCP_USER_SDMA, }; /* MPU -> L3 interface */ -static struct omap_hwmod_ocp_if omap2430_mpu__l3 = { +static struct omap_hwmod_ocp_if omap2430_mpu__l3_main = { .master = &omap2430_mpu_hwmod, - .slave = &omap2430_l3_hwmod, + .slave = &omap2430_l3_main_hwmod, .user = OCP_USER_MPU, }; /* Slave interfaces on the L3 interconnect */ -static struct omap_hwmod_ocp_if *omap2430_l3_slaves[] = { - &omap2430_mpu__l3, +static struct omap_hwmod_ocp_if *omap2430_l3_main_slaves[] = { + &omap2430_mpu__l3_main, }; /* Master interfaces on the L3 interconnect */ -static struct omap_hwmod_ocp_if *omap2430_l3_masters[] = { - &omap2430_l3__l4_core, +static struct omap_hwmod_ocp_if *omap2430_l3_main_masters[] = { + &omap2430_l3_main__l4_core, }; /* L3 */ -static struct omap_hwmod omap2430_l3_hwmod = { - .name = "l3_hwmod", +static struct omap_hwmod omap2430_l3_main_hwmod = { + .name = "l3_main", .class = &l3_hwmod_class, - .masters = omap2430_l3_masters, - .masters_cnt = ARRAY_SIZE(omap2430_l3_masters), - .slaves = omap2430_l3_slaves, - .slaves_cnt = ARRAY_SIZE(omap2430_l3_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) + .masters = omap2430_l3_main_masters, + .masters_cnt = ARRAY_SIZE(omap2430_l3_main_masters), + .slaves = omap2430_l3_main_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_l3_main_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), + .flags = HWMOD_NO_IDLEST, }; static struct omap_hwmod omap2430_l4_wkup_hwmod; -static struct omap_hwmod omap2430_mmc1_hwmod; -static struct omap_hwmod omap2430_mmc2_hwmod; /* L4_CORE -> L4_WKUP interface */ static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = { @@ -81,7 +81,7 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = { /* Slave interfaces on the L4_CORE interconnect */ static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = { - &omap2430_l3__l4_core, + &omap2430_l3_main__l4_core, }; /* Master interfaces on the L4_CORE interconnect */ @@ -91,13 +91,14 @@ static struct omap_hwmod_ocp_if *omap2430_l4_core_masters[] = { /* L4 CORE */ static struct omap_hwmod omap2430_l4_core_hwmod = { - .name = "l4_core_hwmod", + .name = "l4_core", .class = &l4_hwmod_class, .masters = omap2430_l4_core_masters, .masters_cnt = ARRAY_SIZE(omap2430_l4_core_masters), .slaves = omap2430_l4_core_slaves, .slaves_cnt = ARRAY_SIZE(omap2430_l4_core_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), + .flags = HWMOD_NO_IDLEST, }; /* Slave interfaces on the L4_WKUP interconnect */ @@ -111,18 +112,19 @@ static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = { /* L4 WKUP */ static struct omap_hwmod omap2430_l4_wkup_hwmod = { - .name = "l4_wkup_hwmod", + .name = "l4_wkup", .class = &l4_hwmod_class, .masters = omap2430_l4_wkup_masters, .masters_cnt = ARRAY_SIZE(omap2430_l4_wkup_masters), .slaves = omap2430_l4_wkup_slaves, .slaves_cnt = ARRAY_SIZE(omap2430_l4_wkup_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), + .flags = HWMOD_NO_IDLEST, }; /* Master interfaces on the MPU device */ static struct omap_hwmod_ocp_if *omap2430_mpu_masters[] = { - &omap2430_mpu__l3, + &omap2430_mpu__l3_main, }; /* MPU */ @@ -135,11 +137,40 @@ static struct omap_hwmod omap2430_mpu_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), }; +/* + * IVA2_1 interface data + */ + +/* IVA2 <- L3 interface */ +static struct omap_hwmod_ocp_if omap2430_l3__iva = { + .master = &omap2430_l3_main_hwmod, + .slave = &omap2430_iva_hwmod, + .clk = "dsp_fck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if *omap2430_iva_masters[] = { + &omap2430_l3__iva, +}; + +/* + * IVA2 (IVA2) + */ + +static struct omap_hwmod omap2430_iva_hwmod = { + .name = "iva", + .class = &iva_hwmod_class, + .masters = omap2430_iva_masters, + .masters_cnt = ARRAY_SIZE(omap2430_iva_masters), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) +}; + static __initdata struct omap_hwmod *omap2430_hwmods[] = { - &omap2430_l3_hwmod, + &omap2430_l3_main_hwmod, &omap2430_l4_core_hwmod, &omap2430_l4_wkup_hwmod, &omap2430_mpu_hwmod, + &omap2430_iva_hwmod, NULL, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index 39b0c0eaa37..5d8eb58ba5e 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -32,51 +32,53 @@ */ static struct omap_hwmod omap3xxx_mpu_hwmod; -static struct omap_hwmod omap3xxx_l3_hwmod; +static struct omap_hwmod omap3xxx_iva_hwmod; +static struct omap_hwmod omap3xxx_l3_main_hwmod; static struct omap_hwmod omap3xxx_l4_core_hwmod; static struct omap_hwmod omap3xxx_l4_per_hwmod; /* L3 -> L4_CORE interface */ -static struct omap_hwmod_ocp_if omap3xxx_l3__l4_core = { - .master = &omap3xxx_l3_hwmod, +static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = { + .master = &omap3xxx_l3_main_hwmod, .slave = &omap3xxx_l4_core_hwmod, .user = OCP_USER_MPU | OCP_USER_SDMA, }; /* L3 -> L4_PER interface */ -static struct omap_hwmod_ocp_if omap3xxx_l3__l4_per = { - .master = &omap3xxx_l3_hwmod, +static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = { + .master = &omap3xxx_l3_main_hwmod, .slave = &omap3xxx_l4_per_hwmod, .user = OCP_USER_MPU | OCP_USER_SDMA, }; /* MPU -> L3 interface */ -static struct omap_hwmod_ocp_if omap3xxx_mpu__l3 = { +static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = { .master = &omap3xxx_mpu_hwmod, - .slave = &omap3xxx_l3_hwmod, + .slave = &omap3xxx_l3_main_hwmod, .user = OCP_USER_MPU, }; /* Slave interfaces on the L3 interconnect */ -static struct omap_hwmod_ocp_if *omap3xxx_l3_slaves[] = { - &omap3xxx_mpu__l3, +static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = { + &omap3xxx_mpu__l3_main, }; /* Master interfaces on the L3 interconnect */ -static struct omap_hwmod_ocp_if *omap3xxx_l3_masters[] = { - &omap3xxx_l3__l4_core, - &omap3xxx_l3__l4_per, +static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = { + &omap3xxx_l3_main__l4_core, + &omap3xxx_l3_main__l4_per, }; /* L3 */ -static struct omap_hwmod omap3xxx_l3_hwmod = { - .name = "l3_hwmod", +static struct omap_hwmod omap3xxx_l3_main_hwmod = { + .name = "l3_main", .class = &l3_hwmod_class, - .masters = omap3xxx_l3_masters, - .masters_cnt = ARRAY_SIZE(omap3xxx_l3_masters), - .slaves = omap3xxx_l3_slaves, - .slaves_cnt = ARRAY_SIZE(omap3xxx_l3_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) + .masters = omap3xxx_l3_main_masters, + .masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters), + .slaves = omap3xxx_l3_main_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_l3_main_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), + .flags = HWMOD_NO_IDLEST, }; static struct omap_hwmod omap3xxx_l4_wkup_hwmod; @@ -90,7 +92,7 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { /* Slave interfaces on the L4_CORE interconnect */ static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = { - &omap3xxx_l3__l4_core, + &omap3xxx_l3_main__l4_core, }; /* Master interfaces on the L4_CORE interconnect */ @@ -100,18 +102,19 @@ static struct omap_hwmod_ocp_if *omap3xxx_l4_core_masters[] = { /* L4 CORE */ static struct omap_hwmod omap3xxx_l4_core_hwmod = { - .name = "l4_core_hwmod", + .name = "l4_core", .class = &l4_hwmod_class, .masters = omap3xxx_l4_core_masters, .masters_cnt = ARRAY_SIZE(omap3xxx_l4_core_masters), .slaves = omap3xxx_l4_core_slaves, .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_core_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), + .flags = HWMOD_NO_IDLEST, }; /* Slave interfaces on the L4_PER interconnect */ static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = { - &omap3xxx_l3__l4_per, + &omap3xxx_l3_main__l4_per, }; /* Master interfaces on the L4_PER interconnect */ @@ -120,13 +123,14 @@ static struct omap_hwmod_ocp_if *omap3xxx_l4_per_masters[] = { /* L4 PER */ static struct omap_hwmod omap3xxx_l4_per_hwmod = { - .name = "l4_per_hwmod", + .name = "l4_per", .class = &l4_hwmod_class, .masters = omap3xxx_l4_per_masters, .masters_cnt = ARRAY_SIZE(omap3xxx_l4_per_masters), .slaves = omap3xxx_l4_per_slaves, .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_per_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), + .flags = HWMOD_NO_IDLEST, }; /* Slave interfaces on the L4_WKUP interconnect */ @@ -140,18 +144,19 @@ static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_masters[] = { /* L4 WKUP */ static struct omap_hwmod omap3xxx_l4_wkup_hwmod = { - .name = "l4_wkup_hwmod", + .name = "l4_wkup", .class = &l4_hwmod_class, .masters = omap3xxx_l4_wkup_masters, .masters_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_masters), .slaves = omap3xxx_l4_wkup_slaves, .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), + .flags = HWMOD_NO_IDLEST, }; /* Master interfaces on the MPU device */ static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = { - &omap3xxx_mpu__l3, + &omap3xxx_mpu__l3_main, }; /* MPU */ @@ -164,12 +169,41 @@ static struct omap_hwmod omap3xxx_mpu_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), }; +/* + * IVA2_2 interface data + */ + +/* IVA2 <- L3 interface */ +static struct omap_hwmod_ocp_if omap3xxx_l3__iva = { + .master = &omap3xxx_l3_main_hwmod, + .slave = &omap3xxx_iva_hwmod, + .clk = "iva2_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = { + &omap3xxx_l3__iva, +}; + +/* + * IVA2 (IVA2) + */ + +static struct omap_hwmod omap3xxx_iva_hwmod = { + .name = "iva", + .class = &iva_hwmod_class, + .masters = omap3xxx_iva_masters, + .masters_cnt = ARRAY_SIZE(omap3xxx_iva_masters), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) +}; + static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { - &omap3xxx_l3_hwmod, + &omap3xxx_l3_main_hwmod, &omap3xxx_l4_core_hwmod, &omap3xxx_l4_per_hwmod, &omap3xxx_l4_wkup_hwmod, &omap3xxx_mpu_hwmod, + &omap3xxx_iva_hwmod, NULL, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.c b/arch/arm/mach-omap2/omap_hwmod_common_data.c index 1e80b914fa1..08a134243ec 100644 --- a/arch/arm/mach-omap2/omap_hwmod_common_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_common_data.c @@ -66,3 +66,6 @@ struct omap_hwmod_class mpu_hwmod_class = { .name = "mpu" }; +struct omap_hwmod_class iva_hwmod_class = { + .name = "iva" +}; diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h index 3645a28c7c2..c34e98bf124 100644 --- a/arch/arm/mach-omap2/omap_hwmod_common_data.h +++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h @@ -20,5 +20,6 @@ extern struct omap_hwmod_class l3_hwmod_class; extern struct omap_hwmod_class l4_hwmod_class; extern struct omap_hwmod_class mpu_hwmod_class; +extern struct omap_hwmod_class iva_hwmod_class; #endif diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c new file mode 100644 index 00000000000..68f9f2e9589 --- /dev/null +++ b/arch/arm/mach-omap2/pm.c @@ -0,0 +1,84 @@ +/* + * pm.c - Common OMAP2+ power management-related code + * + * Copyright (C) 2010 Texas Instruments, Inc. + * Copyright (C) 2010 Nokia Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/err.h> + +#include <plat/omap-pm.h> +#include <plat/omap_device.h> +#include <plat/common.h> + +static struct omap_device_pm_latency *pm_lats; + +static struct device *mpu_dev; +static struct device *dsp_dev; +static struct device *l3_dev; + +struct device *omap2_get_mpuss_device(void) +{ + WARN_ON_ONCE(!mpu_dev); + return mpu_dev; +} + +struct device *omap2_get_dsp_device(void) +{ + WARN_ON_ONCE(!dsp_dev); + return dsp_dev; +} + +struct device *omap2_get_l3_device(void) +{ + WARN_ON_ONCE(!l3_dev); + return l3_dev; +} + +/* static int _init_omap_device(struct omap_hwmod *oh, void *user) */ +static int _init_omap_device(char *name, struct device **new_dev) +{ + struct omap_hwmod *oh; + struct omap_device *od; + + oh = omap_hwmod_lookup(name); + if (WARN(!oh, "%s: could not find omap_hwmod for %s\n", + __func__, name)) + return -ENODEV; + + od = omap_device_build(oh->name, 0, oh, NULL, 0, pm_lats, 0, false); + if (WARN(IS_ERR(od), "%s: could not build omap_device for %s\n", + __func__, name)) + return -ENODEV; + + *new_dev = &od->pdev.dev; + + return 0; +} + +/* + * Build omap_devices for processors and bus. + */ +static void omap2_init_processor_devices(void) +{ + _init_omap_device("mpu", &mpu_dev); + _init_omap_device("iva", &dsp_dev); + _init_omap_device("l3_main", &l3_dev); +} + +static int __init omap2_common_pm_init(void) +{ + omap2_init_processor_devices(); + omap_pm_if_init(); + + return 0; +} +device_initcall(omap2_common_pm_init); + diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index e321281ab6e..6aeedeacdad 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c @@ -39,7 +39,6 @@ #include <plat/clock.h> #include <plat/sram.h> #include <plat/control.h> -#include <plat/mux.h> #include <plat/dma.h> #include <plat/board.h> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index b88737fd6cf..fb4994ad622 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -385,8 +385,9 @@ void omap_sram_idle(void) /* Enable IO-PAD and IO-CHAIN wakeups */ per_next_state = pwrdm_read_next_pwrst(per_pwrdm); core_next_state = pwrdm_read_next_pwrst(core_pwrdm); - if (per_next_state < PWRDM_POWER_ON || - core_next_state < PWRDM_POWER_ON) { + if (omap3_has_io_wakeup() && \ + (per_next_state < PWRDM_POWER_ON || + core_next_state < PWRDM_POWER_ON)) { prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN); omap3_enable_io_chain(); } @@ -479,7 +480,7 @@ void omap_sram_idle(void) } /* Disable IO-PAD and IO-CHAIN wakeup */ - if (core_next_state < PWRDM_POWER_ON) { + if (omap3_has_io_wakeup() && core_next_state < PWRDM_POWER_ON) { prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN); omap3_disable_io_chain(); } diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c new file mode 100644 index 00000000000..54544b4fc76 --- /dev/null +++ b/arch/arm/mach-omap2/pm44xx.c @@ -0,0 +1,135 @@ +/* + * OMAP4 Power Management Routines + * + * Copyright (C) 2010 Texas Instruments, Inc. + * Rajendra Nayak <rnayak@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/pm.h> +#include <linux/suspend.h> +#include <linux/module.h> +#include <linux/list.h> +#include <linux/err.h> +#include <linux/slab.h> + +#include <plat/powerdomain.h> +#include <mach/omap4-common.h> + +struct power_state { + struct powerdomain *pwrdm; + u32 next_state; +#ifdef CONFIG_SUSPEND + u32 saved_state; +#endif + struct list_head node; +}; + +static LIST_HEAD(pwrst_list); + +#ifdef CONFIG_SUSPEND +static int omap4_pm_prepare(void) +{ + disable_hlt(); + return 0; +} + +static int omap4_pm_suspend(void) +{ + do_wfi(); + return 0; +} + +static int omap4_pm_enter(suspend_state_t suspend_state) +{ + int ret = 0; + + switch (suspend_state) { + case PM_SUSPEND_STANDBY: + case PM_SUSPEND_MEM: + ret = omap4_pm_suspend(); + break; + default: + ret = -EINVAL; + } + + return ret; +} + +static void omap4_pm_finish(void) +{ + enable_hlt(); + return; +} + +static int omap4_pm_begin(suspend_state_t state) +{ + return 0; +} + +static void omap4_pm_end(void) +{ + return; +} + +static struct platform_suspend_ops omap_pm_ops = { + .begin = omap4_pm_begin, + .end = omap4_pm_end, + .prepare = omap4_pm_prepare, + .enter = omap4_pm_enter, + .finish = omap4_pm_finish, + .valid = suspend_valid_only_mem, +}; +#endif /* CONFIG_SUSPEND */ + +static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) +{ + struct power_state *pwrst; + + if (!pwrdm->pwrsts) + return 0; + + pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC); + if (!pwrst) + return -ENOMEM; + pwrst->pwrdm = pwrdm; + pwrst->next_state = PWRDM_POWER_ON; + list_add(&pwrst->node, &pwrst_list); + + return pwrdm_set_next_pwrst(pwrst->pwrdm, pwrst->next_state); +} + +/** + * omap4_pm_init - Init routine for OMAP4 PM + * + * Initializes all powerdomain and clockdomain target states + * and all PRCM settings. + */ +static int __init omap4_pm_init(void) +{ + int ret; + + if (!cpu_is_omap44xx()) + return -ENODEV; + + pr_err("Power Management for TI OMAP4.\n"); + +#ifdef CONFIG_PM + ret = pwrdm_for_each(pwrdms_setup, NULL); + if (ret) { + pr_err("Failed to setup powerdomains\n"); + goto err2; + } +#endif + +#ifdef CONFIG_SUSPEND + suspend_set_ops(&omap_pm_ops); +#endif /* CONFIG_SUSPEND */ + +err2: + return ret; +} +late_initcall(omap4_pm_init); diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c index a2904aa7065..6527ec30dc1 100644 --- a/arch/arm/mach-omap2/powerdomain.c +++ b/arch/arm/mach-omap2/powerdomain.c @@ -875,6 +875,7 @@ int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) break; case 4: m = OMAP_MEM4_RETSTATE_MASK; + break; default: WARN_ON(1); /* should never happen */ return -EEXIST; diff --git a/arch/arm/mach-omap2/powerdomains34xx.h b/arch/arm/mach-omap2/powerdomains34xx.h index bd87112beea..fa904861668 100644 --- a/arch/arm/mach-omap2/powerdomains34xx.h +++ b/arch/arm/mach-omap2/powerdomains34xx.h @@ -75,12 +75,19 @@ static struct powerdomain mpu_3xxx_pwrdm = { }, }; +/* + * The USBTLL Save-and-Restore mechanism is broken on + * 3430s upto ES3.0 and 3630ES1.0. Hence this feature + * needs to be disabled on these chips. + * Refer: 3430 errata ID i459 and 3630 errata ID i579 + */ static struct powerdomain core_3xxx_pre_es3_1_pwrdm = { .name = "core_pwrdm", .prcm_offs = CORE_MOD, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 | CHIP_IS_OMAP3430ES2 | - CHIP_IS_OMAP3430ES3_0), + CHIP_IS_OMAP3430ES3_0 | + CHIP_IS_OMAP3630ES1), .pwrsts = PWRSTS_OFF_RET_ON, .pwrsts_logic_ret = PWRSTS_OFF_RET, .banks = 2, @@ -97,7 +104,8 @@ static struct powerdomain core_3xxx_pre_es3_1_pwrdm = { static struct powerdomain core_3xxx_es3_1_pwrdm = { .name = "core_pwrdm", .prcm_offs = CORE_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES3_1), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1 | + CHIP_GE_OMAP3630ES1_1), .pwrsts = PWRSTS_OFF_RET_ON, .pwrsts_logic_ret = PWRSTS_OFF_RET, .flags = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */ diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index 3771254dfa8..566e991ede8 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c @@ -37,6 +37,9 @@ #define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV 0x52 #define UART_OMAP_WER 0x17 /* Wake-up enable register */ +#define UART_ERRATA_FIFO_FULL_ABORT (0x1 << 0) +#define UART_ERRATA_i202_MDR1_ACCESS (0x1 << 1) + /* * NOTE: By default the serial timeout is disabled as it causes lost characters * over the serial ports. This means that the UART clocks will stay on until @@ -64,6 +67,7 @@ struct omap_uart_state { struct list_head node; struct platform_device pdev; + u32 errata; #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) int context_valid; @@ -74,6 +78,7 @@ struct omap_uart_state { u16 sysc; u16 scr; u16 wer; + u16 mcr; #endif }; @@ -180,6 +185,42 @@ static inline void __init omap_uart_reset(struct omap_uart_state *uart) #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) +/* + * Work Around for Errata i202 (3430 - 1.12, 3630 - 1.6) + * The access to uart register after MDR1 Access + * causes UART to corrupt data. + * + * Need a delay = + * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) + * give 10 times as much + */ +static void omap_uart_mdr1_errataset(struct omap_uart_state *uart, u8 mdr1_val, + u8 fcr_val) +{ + struct plat_serial8250_port *p = uart->p; + u8 timeout = 255; + + serial_write_reg(p, UART_OMAP_MDR1, mdr1_val); + udelay(2); + serial_write_reg(p, UART_FCR, fcr_val | UART_FCR_CLEAR_XMIT | + UART_FCR_CLEAR_RCVR); + /* + * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and + * TX_FIFO_E bit is 1. + */ + while (UART_LSR_THRE != (serial_read_reg(p, UART_LSR) & + (UART_LSR_THRE | UART_LSR_DR))) { + timeout--; + if (!timeout) { + /* Should *never* happen. we warn and carry on */ + dev_crit(&uart->pdev.dev, "Errata i202: timedout %x\n", + serial_read_reg(p, UART_LSR)); + break; + } + udelay(1); + } +} + static void omap_uart_save_context(struct omap_uart_state *uart) { u16 lcr = 0; @@ -197,6 +238,9 @@ static void omap_uart_save_context(struct omap_uart_state *uart) uart->sysc = serial_read_reg(p, UART_OMAP_SYSC); uart->scr = serial_read_reg(p, UART_OMAP_SCR); uart->wer = serial_read_reg(p, UART_OMAP_WER); + serial_write_reg(p, UART_LCR, 0x80); + uart->mcr = serial_read_reg(p, UART_MCR); + serial_write_reg(p, UART_LCR, lcr); uart->context_valid = 1; } @@ -214,7 +258,10 @@ static void omap_uart_restore_context(struct omap_uart_state *uart) uart->context_valid = 0; - serial_write_reg(p, UART_OMAP_MDR1, 0x7); + if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS) + omap_uart_mdr1_errataset(uart, 0x07, 0xA0); + else + serial_write_reg(p, UART_OMAP_MDR1, 0x7); serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */ efr = serial_read_reg(p, UART_EFR); serial_write_reg(p, UART_EFR, UART_EFR_ECB); @@ -225,14 +272,18 @@ static void omap_uart_restore_context(struct omap_uart_state *uart) serial_write_reg(p, UART_DLM, uart->dlh); serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */ serial_write_reg(p, UART_IER, uart->ier); - serial_write_reg(p, UART_FCR, 0xA1); + serial_write_reg(p, UART_LCR, 0x80); + serial_write_reg(p, UART_MCR, uart->mcr); serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */ serial_write_reg(p, UART_EFR, efr); serial_write_reg(p, UART_LCR, UART_LCR_WLEN8); serial_write_reg(p, UART_OMAP_SCR, uart->scr); serial_write_reg(p, UART_OMAP_WER, uart->wer); serial_write_reg(p, UART_OMAP_SYSC, uart->sysc); - serial_write_reg(p, UART_OMAP_MDR1, 0x00); /* UART 16x mode */ + if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS) + omap_uart_mdr1_errataset(uart, 0x00, 0xA1); + else + serial_write_reg(p, UART_OMAP_MDR1, 0x00); /* UART 16x mode */ } #else static inline void omap_uart_save_context(struct omap_uart_state *uart) {} @@ -489,8 +540,8 @@ static void omap_uart_idle_init(struct omap_uart_state *uart) } uart->wk_mask = wk_mask; } else { - uart->wk_en = 0; - uart->wk_st = 0; + uart->wk_en = NULL; + uart->wk_st = NULL; uart->wk_mask = 0; uart->padconf = 0; } @@ -552,7 +603,8 @@ static ssize_t sleep_timeout_store(struct device *dev, return n; } -DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show, sleep_timeout_store); +static DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show, + sleep_timeout_store); #define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr)) #else static inline void omap_uart_idle_init(struct omap_uart_state *uart) {} @@ -749,14 +801,20 @@ void __init omap_serial_init_port(int port) * omap3xxx: Never read empty UART fifo on UARTs * with IP rev >=0x52 */ - if (cpu_is_omap44xx()) { - uart->p->serial_in = serial_in_override; - uart->p->serial_out = serial_out_override; - } else if ((serial_read_reg(uart->p, UART_OMAP_MVER) & 0xFF) - >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV) { + if (cpu_is_omap44xx()) + uart->errata |= UART_ERRATA_FIFO_FULL_ABORT; + else if ((serial_read_reg(uart->p, UART_OMAP_MVER) & 0xFF) + >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV) + uart->errata |= UART_ERRATA_FIFO_FULL_ABORT; + + if (uart->errata & UART_ERRATA_FIFO_FULL_ABORT) { uart->p->serial_in = serial_in_override; uart->p->serial_out = serial_out_override; } + + /* Enable the MDR1 errata for OMAP3 */ + if (cpu_is_omap34xx()) + uart->errata |= UART_ERRATA_i202_MDR1_ACCESS; } /** diff --git a/arch/arm/mach-omap2/usb-ehci.c b/arch/arm/mach-omap2/usb-ehci.c index d72d1ac3033..b11bf385d36 100644 --- a/arch/arm/mach-omap2/usb-ehci.c +++ b/arch/arm/mach-omap2/usb-ehci.c @@ -23,7 +23,6 @@ #include <linux/dma-mapping.h> #include <asm/io.h> -#include <plat/mux.h> #include <mach/hardware.h> #include <mach/irqs.h> diff --git a/arch/arm/mach-omap2/usb-fs.c b/arch/arm/mach-omap2/usb-fs.c new file mode 100644 index 00000000000..a216d88b04b --- /dev/null +++ b/arch/arm/mach-omap2/usb-fs.c @@ -0,0 +1,359 @@ +/* + * Platform level USB initialization for FS USB OTG controller on omap1 and 24xx + * + * Copyright (C) 2004 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/errno.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/clk.h> +#include <linux/err.h> + +#include <asm/irq.h> + +#include <plat/control.h> +#include <plat/usb.h> +#include <plat/board.h> + +#define INT_USB_IRQ_GEN INT_24XX_USB_IRQ_GEN +#define INT_USB_IRQ_NISO INT_24XX_USB_IRQ_NISO +#define INT_USB_IRQ_ISO INT_24XX_USB_IRQ_ISO +#define INT_USB_IRQ_HGEN INT_24XX_USB_IRQ_HGEN +#define INT_USB_IRQ_OTG INT_24XX_USB_IRQ_OTG + +#include "mux.h" + +#if defined(CONFIG_ARCH_OMAP2) + +#ifdef CONFIG_USB_GADGET_OMAP + +static struct resource udc_resources[] = { + /* order is significant! */ + { /* registers */ + .start = UDC_BASE, + .end = UDC_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, { /* general IRQ */ + .start = INT_USB_IRQ_GEN, + .flags = IORESOURCE_IRQ, + }, { /* PIO IRQ */ + .start = INT_USB_IRQ_NISO, + .flags = IORESOURCE_IRQ, + }, { /* SOF IRQ */ + .start = INT_USB_IRQ_ISO, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 udc_dmamask = ~(u32)0; + +static struct platform_device udc_device = { + .name = "omap_udc", + .id = -1, + .dev = { + .dma_mask = &udc_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .num_resources = ARRAY_SIZE(udc_resources), + .resource = udc_resources, +}; + +static inline void udc_device_init(struct omap_usb_config *pdata) +{ + pdata->udc_device = &udc_device; +} + +#else + +static inline void udc_device_init(struct omap_usb_config *pdata) +{ +} + +#endif + +#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) + +/* The dmamask must be set for OHCI to work */ +static u64 ohci_dmamask = ~(u32)0; + +static struct resource ohci_resources[] = { + { + .start = OMAP_OHCI_BASE, + .end = OMAP_OHCI_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_USB_IRQ_HGEN, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device ohci_device = { + .name = "ohci", + .id = -1, + .dev = { + .dma_mask = &ohci_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .num_resources = ARRAY_SIZE(ohci_resources), + .resource = ohci_resources, +}; + +static inline void ohci_device_init(struct omap_usb_config *pdata) +{ + pdata->ohci_device = &ohci_device; +} + +#else + +static inline void ohci_device_init(struct omap_usb_config *pdata) +{ +} + +#endif + +#if defined(CONFIG_USB_OTG) && defined(CONFIG_ARCH_OMAP_OTG) + +static struct resource otg_resources[] = { + /* order is significant! */ + { + .start = OTG_BASE, + .end = OTG_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, { + .start = INT_USB_IRQ_OTG, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device otg_device = { + .name = "omap_otg", + .id = -1, + .num_resources = ARRAY_SIZE(otg_resources), + .resource = otg_resources, +}; + +static inline void otg_device_init(struct omap_usb_config *pdata) +{ + pdata->otg_device = &otg_device; +} + +#else + +static inline void otg_device_init(struct omap_usb_config *pdata) +{ +} + +#endif + +static void omap2_usb_devconf_clear(u8 port, u32 mask) +{ + u32 r; + + r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); + r &= ~USBTXWRMODEI(port, mask); + omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0); +} + +static void omap2_usb_devconf_set(u8 port, u32 mask) +{ + u32 r; + + r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); + r |= USBTXWRMODEI(port, mask); + omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0); +} + +static void omap2_usb2_disable_5pinbitll(void) +{ + u32 r; + + r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); + r &= ~(USBTXWRMODEI(2, USB_BIDIR_TLL) | USBT2TLL5PI); + omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0); +} + +static void omap2_usb2_enable_5pinunitll(void) +{ + u32 r; + + r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); + r |= USBTXWRMODEI(2, USB_UNIDIR_TLL) | USBT2TLL5PI; + omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0); +} + +static u32 __init omap2_usb0_init(unsigned nwires, unsigned is_device) +{ + u32 syscon1 = 0; + + omap2_usb_devconf_clear(0, USB_BIDIR_TLL); + + if (nwires == 0) + return 0; + + if (is_device) + omap_mux_init_signal("usb0_puen", 0); + + omap_mux_init_signal("usb0_dat", 0); + omap_mux_init_signal("usb0_txen", 0); + omap_mux_init_signal("usb0_se0", 0); + if (nwires != 3) + omap_mux_init_signal("usb0_rcv", 0); + + switch (nwires) { + case 3: + syscon1 = 2; + omap2_usb_devconf_set(0, USB_BIDIR); + break; + case 4: + syscon1 = 1; + omap2_usb_devconf_set(0, USB_BIDIR); + break; + case 6: + syscon1 = 3; + omap_mux_init_signal("usb0_vp", 0); + omap_mux_init_signal("usb0_vm", 0); + omap2_usb_devconf_set(0, USB_UNIDIR); + break; + default: + printk(KERN_ERR "illegal usb%d %d-wire transceiver\n", + 0, nwires); + } + + return syscon1 << 16; +} + +static u32 __init omap2_usb1_init(unsigned nwires) +{ + u32 syscon1 = 0; + + omap2_usb_devconf_clear(1, USB_BIDIR_TLL); + + if (nwires == 0) + return 0; + + /* NOTE: board-specific code must set up pin muxing for usb1, + * since each signal could come out on either of two balls. + */ + + switch (nwires) { + case 2: + /* NOTE: board-specific code must override this setting if + * this TLL link is not using DP/DM + */ + syscon1 = 1; + omap2_usb_devconf_set(1, USB_BIDIR_TLL); + break; + case 3: + syscon1 = 2; + omap2_usb_devconf_set(1, USB_BIDIR); + break; + case 4: + syscon1 = 1; + omap2_usb_devconf_set(1, USB_BIDIR); + break; + case 6: + default: + printk(KERN_ERR "illegal usb%d %d-wire transceiver\n", + 1, nwires); + } + + return syscon1 << 20; +} + +static u32 __init omap2_usb2_init(unsigned nwires, unsigned alt_pingroup) +{ + u32 syscon1 = 0; + + omap2_usb2_disable_5pinbitll(); + alt_pingroup = 0; + + /* NOTE omap1 erratum: must leave USB2_UNI_R set if usb0 in use */ + if (alt_pingroup || nwires == 0) + return 0; + + omap_mux_init_signal("usb2_dat", 0); + omap_mux_init_signal("usb2_se0", 0); + if (nwires > 2) + omap_mux_init_signal("usb2_txen", 0); + if (nwires > 3) + omap_mux_init_signal("usb2_rcv", 0); + + switch (nwires) { + case 2: + /* NOTE: board-specific code must override this setting if + * this TLL link is not using DP/DM + */ + syscon1 = 1; + omap2_usb_devconf_set(2, USB_BIDIR_TLL); + break; + case 3: + syscon1 = 2; + omap2_usb_devconf_set(2, USB_BIDIR); + break; + case 4: + syscon1 = 1; + omap2_usb_devconf_set(2, USB_BIDIR); + break; + case 5: + /* NOTE: board-specific code must mux this setting depending + * on TLL link using DP/DM. Something must also + * set up OTG_SYSCON2.HMC_TLL{ATTACH,SPEED} + * 2420: hdq_sio.usb2_tllse0 or vlynq_rx0.usb2_tllse0 + * 2430: hdq_sio.usb2_tllse0 or sdmmc2_dat0.usb2_tllse0 + */ + + syscon1 = 3; + omap2_usb2_enable_5pinunitll(); + break; + case 6: + default: + printk(KERN_ERR "illegal usb%d %d-wire transceiver\n", + 2, nwires); + } + + return syscon1 << 24; +} + +void __init omap2_usbfs_init(struct omap_usb_config *pdata) +{ + struct clk *ick; + + if (!cpu_is_omap24xx()) + return; + + ick = clk_get(NULL, "usb_l4_ick"); + if (IS_ERR(ick)) + return; + + clk_enable(ick); + pdata->usb0_init = omap2_usb0_init; + pdata->usb1_init = omap2_usb1_init; + pdata->usb2_init = omap2_usb2_init; + udc_device_init(pdata); + ohci_device_init(pdata); + otg_device_init(pdata); + omap_otg_init(pdata); + clk_disable(ick); + clk_put(ick); +} + +#endif diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c index 96f6787e00b..33a5cde1c22 100644 --- a/arch/arm/mach-omap2/usb-musb.c +++ b/arch/arm/mach-omap2/usb-musb.c @@ -28,7 +28,6 @@ #include <mach/hardware.h> #include <mach/irqs.h> -#include <plat/mux.h> #include <plat/usb.h> #ifdef CONFIG_USB_MUSB_SOC diff --git a/arch/arm/mach-omap2/usb-tusb6010.c b/arch/arm/mach-omap2/usb-tusb6010.c index 10a2013c110..64a0112b70a 100644 --- a/arch/arm/mach-omap2/usb-tusb6010.c +++ b/arch/arm/mach-omap2/usb-tusb6010.c @@ -17,8 +17,8 @@ #include <linux/usb/musb.h> #include <plat/gpmc.h> -#include <plat/mux.h> +#include "mux.h" static u8 async_cs, sync_cs; static unsigned refclk_psec; @@ -325,17 +325,17 @@ tusb6010_setup_interface(struct musb_hdrc_platform_data *data, else { /* assume OMAP 2420 ES2.0 and later */ if (dmachan & (1 << 0)) - omap_cfg_reg(AA10_242X_DMAREQ0); + omap_mux_init_signal("sys_ndmareq0", 0); if (dmachan & (1 << 1)) - omap_cfg_reg(AA6_242X_DMAREQ1); + omap_mux_init_signal("sys_ndmareq1", 0); if (dmachan & (1 << 2)) - omap_cfg_reg(E4_242X_DMAREQ2); + omap_mux_init_signal("sys_ndmareq2", 0); if (dmachan & (1 << 3)) - omap_cfg_reg(G4_242X_DMAREQ3); + omap_mux_init_signal("sys_ndmareq3", 0); if (dmachan & (1 << 4)) - omap_cfg_reg(D3_242X_DMAREQ4); + omap_mux_init_signal("sys_ndmareq4", 0); if (dmachan & (1 << 5)) - omap_cfg_reg(E3_242X_DMAREQ5); + omap_mux_init_signal("sys_ndmareq5", 0); } /* so far so good ... register the device */ |