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authorSergei Shtylyov <sshtylyov@ru.mvista.com>2007-01-30 20:40:30 +0300
committerJeff Garzik <jeff@garzik.org>2007-02-09 17:39:38 -0500
commit24a01453892e0a4a6ad38460541bd0dae9b1837f (patch)
treebcf4e72523a229a67d12eb9798b40f975eeb04fc /drivers/ata
parent246ce3b675843e0369643cceb4faeb6cf6d19a30 (diff)
downloadlinux-2.6.34-ux500-24a01453892e0a4a6ad38460541bd0dae9b1837f.tar.gz
pata_sl82c105: wrong assumptions about compatible PIO modes
Fix the wrong "compatible" PIO mode choices: MWDMA0 has 480 ns cycle while PIO1 only has 383 ns cycle, and MWDMA2 timings matchs those of PIO4 exactly. Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/ata')
-rw-r--r--drivers/ata/pata_sl82c105.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/ata/pata_sl82c105.c b/drivers/ata/pata_sl82c105.c
index a4034567437..f2fa158d07c 100644
--- a/drivers/ata/pata_sl82c105.c
+++ b/drivers/ata/pata_sl82c105.c
@@ -139,13 +139,13 @@ static void sl82c105_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
switch(adev->dma_mode) {
case XFER_MW_DMA_0:
- sl82c105_configure_piomode(ap, adev, 1);
+ sl82c105_configure_piomode(ap, adev, 0);
break;
case XFER_MW_DMA_1:
sl82c105_configure_piomode(ap, adev, 3);
break;
case XFER_MW_DMA_2:
- sl82c105_configure_piomode(ap, adev, 3);
+ sl82c105_configure_piomode(ap, adev, 4);
break;
default:
BUG();