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authorJimmy Rubin <ejimrub@steludxu031.lud.stericsson.com>2010-05-27 15:25:41 +0200
committerJohn Rigby <john.rigby@linaro.org>2010-09-02 22:45:30 -0600
commit1453f8259ef4100ca689884d5d754761cc10a64f (patch)
tree4a61257b603468c878b3e7cf7c5eea59fb9b2c9e /arch
parent63cfdf397fd4502644ea06bcb764e9c4179f7cd3 (diff)
downloadlinux-2.6.34-ux500-1453f8259ef4100ca689884d5d754761cc10a64f.tar.gz
MCDE: Adding new MCDE display, AB8500 Denc and AV8100 driver
This patch does the following: * Removes display support on ED! * Removes the old MCDE display driver and adds the new MCDE drivers to drivers/video/mcde. * Removes the old AV8100 driver and adds the new AV8100 drivers to drivers/video/av8100. * Moves the mcde and av8100 specific header files from machine to include/video. * Adds AB8500 Denc driver to drivers/misc/ab8500_denc. * Power management support added to the MCDE display driver. * Removes old MCDE specific configurations. * Adds new menuconfig selection SystemType/Display Selection where it is possbile to choose display types. * Updated standard configurations (mop500_defconfig, mop500_power_defconfig and mop500_USB_HOST_defconfig). * Landscape mode removed from menuconfig for main display. ST Ericsson Change-ID: WP259355 Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/369 Reviewed-by: Dan JOHANSSON <dan.johansson@stericsson.com> Tested-by: Dan JOHANSSON <dan.johansson@stericsson.com> Signed-off-by: Mian Yousaf Kaukab <mian.yousaf.kaukab@stericsson.com> Change-Id: I0c5e5c0f80fde304d8b96e3faee0e8b1819d1ae7 Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/2378 Reviewed-by: Jonas ABERG <jonas.aberg@stericsson.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/configs/mop500_USB_HOST_defconfig50
-rwxr-xr-xarch/arm/configs/mop500_defconfig50
-rwxr-xr-xarch/arm/configs/mop500_ed_defconfig43
-rwxr-xr-xarch/arm/configs/mop500_power_defconfig50
-rwxr-xr-xarch/arm/mach-ux500/Kconfig-arch696
-rwxr-xr-xarch/arm/mach-ux500/board-mop500.c478
-rwxr-xr-xarch/arm/mach-ux500/clock.c21
-rw-r--r--arch/arm/mach-ux500/include/mach/ab8500_denc.h76
-rwxr-xr-xarch/arm/mach-ux500/include/mach/av8100.h553
-rwxr-xr-xarch/arm/mach-ux500/include/mach/av8100_fw.h1041
-rwxr-xr-xarch/arm/mach-ux500/include/mach/av8100_p.h227
-rwxr-xr-xarch/arm/mach-ux500/include/mach/devices.h5
-rwxr-xr-xarch/arm/mach-ux500/include/mach/dsi.h770
-rwxr-xr-xarch/arm/mach-ux500/include/mach/dsi_reg.h488
-rwxr-xr-xarch/arm/mach-ux500/include/mach/hardware.h6
-rw-r--r--arch/arm/mach-ux500/include/mach/mcde-base.h83
-rwxr-xr-xarch/arm/mach-ux500/include/mach/mcde.h1387
-rwxr-xr-xarch/arm/mach-ux500/include/mach/mcde_a0.h896
-rwxr-xr-xarch/arm/mach-ux500/include/mach/mcde_common.h168
-rwxr-xr-xarch/arm/mach-ux500/include/mach/mcde_ioctls.h737
-rwxr-xr-xarch/arm/mach-ux500/include/mach/mcde_reg.h787
-rw-r--r--arch/arm/mach-ux500/mcde.c788
-rw-r--r--arch/arm/mach-ux500/mop500-regulators.c46
23 files changed, 644 insertions, 8802 deletions
diff --git a/arch/arm/configs/mop500_USB_HOST_defconfig b/arch/arm/configs/mop500_USB_HOST_defconfig
index 4dc0676c98d..7a672a088b4 100644
--- a/arch/arm/configs/mop500_USB_HOST_defconfig
+++ b/arch/arm/configs/mop500_USB_HOST_defconfig
@@ -242,7 +242,6 @@ CONFIG_MACH_U8500_MOP=y
CONFIG_U8500_CPUFREQ=y
CONFIG_U8500_PM=y
CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y
-CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT=y
CONFIG_GPIO_STM=y
CONFIG_STM_DMA=y
# CONFIG_U8500_SECURE is not set
@@ -252,44 +251,12 @@ CONFIG_STM_DMA=y
#
#
-# Display Channel Selection
-#
-# CONFIG_FB_U8500_MCDE_CHANNELA is not set
-CONFIG_FB_U8500_MCDE_CHANNELA_INPUT_16BPP_TYPE=0
-CONFIG_FB_U8500_MCDE_CHANNELA_INPUT_BGR=0x0
-# CONFIG_FB_U8500_MCDE_CHANNELB is not set
-CONFIG_FB_U8500_MCDE_CHANNELB_INPUT_16BPP_TYPE=0
-CONFIG_FB_U8500_MCDE_CHANNELB_INPUT_BGR=0x0
-CONFIG_FB_U8500_MCDE_CHANNELC0=y
-# CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_WVGA_PORTRAIT is not set
-CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_WVGA=y
-# CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_VGA is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_CRT is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_SDTV is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_QVGA_PORTRAIT is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_QVGA_LANDSCAPE is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_IRGB is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_8BPP is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_12BPP is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_ARGB is not set
-CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_RGB=y
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_24BPP is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_24BPP_PACKED is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_32BPP is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_YCBCR is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_OUTPUT_12BPP is not set
-CONFIG_FB_U8500_MCDE_CHANNELC0_OUTPUT_16BPP=y
-# CONFIG_FB_U8500_MCDE_CHANNELC0_OUTPUT_18BPP is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_OUTPUT_24BPP is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_BGRDATA is not set
-CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_BPP=16
-CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_TYPE=1
-CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_TYPE="WVGA"
-CONFIG_FB_U8500_MCDE_CHANNELC0_OUTPUT_BPP=0x2
-CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_BGR=0x0
-# CONFIG_FB_U8500_MCDE_CHANNELC1 is not set
-CONFIG_FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_TYPE=0
-CONFIG_FB_U8500_MCDE_CHANNELC1_INPUT_BGR=0x0
+# Display Selection
+#
+CONFIG_DISPLAY_GENERIC_DSI_PRIMARY=y
+# CONFIG_DISPLAY_GENERIC_DSI_SECONDARY is not set
+# CONFIG_DISPLAY_AB8500_TERTIARY is not set
+# CONFIG_DISPLAY_AV8100_TERTIARY is not set
CONFIG_FORCE_MAX_ZONEORDER=12
#
@@ -1035,8 +1002,9 @@ CONFIG_FB_CFB_IMAGEBLIT=y
# Frame buffer hardware drivers
#
CONFIG_FB_MCDE=y
-CONFIG_FB_MCDE_MULTIBUFFER=y
-CONFIG_FB_HDMI=y
+CONFIG_MCDE_DISPLAY_GENERIC_DSI=y
+# CONFIG_MCDE_DISPLAY_AB8500_DENC is not set
+# CONFIG_MCDE_DISPLAY_AV8100 is not set
# CONFIG_FB_ARMCLCD is not set
CONFIG_FB_B2R2=y
# CONFIG_FB_S1D13XXX is not set
diff --git a/arch/arm/configs/mop500_defconfig b/arch/arm/configs/mop500_defconfig
index c6721c8605f..1ac286833be 100755
--- a/arch/arm/configs/mop500_defconfig
+++ b/arch/arm/configs/mop500_defconfig
@@ -241,7 +241,6 @@ CONFIG_U8500_CPUFREQ=y
CONFIG_U8500_PM=y
CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y
CONFIG_SENSORS1P_MOP=y
-CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT=y
CONFIG_GPIO_STM=y
CONFIG_STM_DMA=y
# CONFIG_U8500_SECURE is not set
@@ -251,44 +250,12 @@ CONFIG_STM_DMA=y
#
#
-# Display Channel Selection
-#
-# CONFIG_FB_U8500_MCDE_CHANNELA is not set
-CONFIG_FB_U8500_MCDE_CHANNELA_INPUT_16BPP_TYPE=0
-CONFIG_FB_U8500_MCDE_CHANNELA_INPUT_BGR=0x0
-# CONFIG_FB_U8500_MCDE_CHANNELB is not set
-CONFIG_FB_U8500_MCDE_CHANNELB_INPUT_16BPP_TYPE=0
-CONFIG_FB_U8500_MCDE_CHANNELB_INPUT_BGR=0x0
-CONFIG_FB_U8500_MCDE_CHANNELC0=y
-CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_WVGA_PORTRAIT=y
-# CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_WVGA is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_VGA is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_CRT is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_SDTV is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_QVGA_PORTRAIT is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_QVGA_LANDSCAPE is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_IRGB is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_8BPP is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_12BPP is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_ARGB is not set
-CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_RGB=y
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_24BPP is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_24BPP_PACKED is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_32BPP is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_YCBCR is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_OUTPUT_12BPP is not set
-CONFIG_FB_U8500_MCDE_CHANNELC0_OUTPUT_16BPP=y
-# CONFIG_FB_U8500_MCDE_CHANNELC0_OUTPUT_18BPP is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_OUTPUT_24BPP is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_BGRDATA is not set
-CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_BPP=16
-CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_TYPE=1
-CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_TYPE="WVGA_Portrait"
-CONFIG_FB_U8500_MCDE_CHANNELC0_OUTPUT_BPP=0x2
-CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_BGR=0x0
-# CONFIG_FB_U8500_MCDE_CHANNELC1 is not set
-CONFIG_FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_TYPE=0
-CONFIG_FB_U8500_MCDE_CHANNELC1_INPUT_BGR=0x0
+# Display Selection
+#
+CONFIG_DISPLAY_GENERIC_DSI_PRIMARY=y
+# CONFIG_DISPLAY_GENERIC_DSI_SECONDARY is not set
+# CONFIG_DISPLAY_AB8500_TERTIARY is not set
+# CONFIG_DISPLAY_AV8100_TERTIARY is not set
CONFIG_FORCE_MAX_ZONEORDER=12
#
@@ -1299,8 +1266,9 @@ CONFIG_FB_CFB_IMAGEBLIT=y
# Frame buffer hardware drivers
#
CONFIG_FB_MCDE=y
-CONFIG_FB_MCDE_MULTIBUFFER=y
-CONFIG_FB_HDMI=y
+CONFIG_MCDE_DISPLAY_GENERIC_DSI=y
+# CONFIG_MCDE_DISPLAY_AB8500_DENC is not set
+# CONFIG_MCDE_DISPLAY_AV8100 is not set
# CONFIG_FB_ARMCLCD is not set
CONFIG_FB_B2R2=y
# CONFIG_FB_S1D13XXX is not set
diff --git a/arch/arm/configs/mop500_ed_defconfig b/arch/arm/configs/mop500_ed_defconfig
index 9cf47fef7af..23ec4889f89 100755
--- a/arch/arm/configs/mop500_ed_defconfig
+++ b/arch/arm/configs/mop500_ed_defconfig
@@ -240,7 +240,6 @@ CONFIG_MACH_U8500_MOP=y
CONFIG_U8500_PM=y
CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y
CONFIG_SENSORS1P_MOP=y
-# CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT is not set
CONFIG_GPIO_STM=y
CONFIG_STM_DMA=y
# CONFIG_U8500_SECURE is not set
@@ -250,44 +249,6 @@ CONFIG_STM_DMA=y
#
#
-# Display Channel Selection
-#
-# CONFIG_FB_U8500_MCDE_CHANNELA is not set
-CONFIG_FB_U8500_MCDE_CHANNELA_INPUT_16BPP_TYPE=0
-CONFIG_FB_U8500_MCDE_CHANNELA_INPUT_BGR=0x0
-# CONFIG_FB_U8500_MCDE_CHANNELB is not set
-CONFIG_FB_U8500_MCDE_CHANNELB_INPUT_16BPP_TYPE=0
-CONFIG_FB_U8500_MCDE_CHANNELB_INPUT_BGR=0x0
-CONFIG_FB_U8500_MCDE_CHANNELC0=y
-CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_WVGA_PORTRAIT=y
-# CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_WVGA is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_VGA is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_CRT is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_SDTV is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_QVGA_PORTRAIT is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_QVGA_LANDSCAPE is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_IRGB is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_8BPP is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_12BPP is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_ARGB is not set
-CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_RGB=y
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_24BPP is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_24BPP_PACKED is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_32BPP is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_YCBCR is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_OUTPUT_12BPP is not set
-CONFIG_FB_U8500_MCDE_CHANNELC0_OUTPUT_16BPP=y
-# CONFIG_FB_U8500_MCDE_CHANNELC0_OUTPUT_18BPP is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_OUTPUT_24BPP is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_BGRDATA is not set
-CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_BPP=16
-CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_TYPE=1
-CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_TYPE="WVGA_Portrait"
-CONFIG_FB_U8500_MCDE_CHANNELC0_OUTPUT_BPP=0x2
-CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_BGR=0x0
-# CONFIG_FB_U8500_MCDE_CHANNELC1 is not set
-CONFIG_FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_TYPE=0
-CONFIG_FB_U8500_MCDE_CHANNELC1_INPUT_BGR=0x0
CONFIG_FORCE_MAX_ZONEORDER=12
#
@@ -1225,11 +1186,9 @@ CONFIG_FB_CFB_IMAGEBLIT=y
#
# Frame buffer hardware drivers
#
-CONFIG_FB_MCDE=y
-CONFIG_FB_MCDE_MULTIBUFFER=y
# CONFIG_FB_HDMI is not set
# CONFIG_FB_ARMCLCD is not set
-CONFIG_FB_B2R2=y
+# CONFIG_FB_B2R2 is not set
# CONFIG_FB_S1D13XXX is not set
# CONFIG_FB_VIRTUAL is not set
# CONFIG_FB_METRONOME is not set
diff --git a/arch/arm/configs/mop500_power_defconfig b/arch/arm/configs/mop500_power_defconfig
index 8ca53dcf082..3d0ec148809 100755
--- a/arch/arm/configs/mop500_power_defconfig
+++ b/arch/arm/configs/mop500_power_defconfig
@@ -241,7 +241,6 @@ CONFIG_U8500_CPUFREQ=y
CONFIG_U8500_PM=y
CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y
CONFIG_SENSORS1P_MOP=y
-CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT=y
CONFIG_GPIO_STM=y
CONFIG_STM_DMA=y
# CONFIG_U8500_SECURE is not set
@@ -251,44 +250,12 @@ CONFIG_STM_DMA=y
#
#
-# Display Channel Selection
-#
-# CONFIG_FB_U8500_MCDE_CHANNELA is not set
-CONFIG_FB_U8500_MCDE_CHANNELA_INPUT_16BPP_TYPE=0
-CONFIG_FB_U8500_MCDE_CHANNELA_INPUT_BGR=0x0
-# CONFIG_FB_U8500_MCDE_CHANNELB is not set
-CONFIG_FB_U8500_MCDE_CHANNELB_INPUT_16BPP_TYPE=0
-CONFIG_FB_U8500_MCDE_CHANNELB_INPUT_BGR=0x0
-CONFIG_FB_U8500_MCDE_CHANNELC0=y
-CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_WVGA_PORTRAIT=y
-# CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_WVGA is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_VGA is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_CRT is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_SDTV is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_QVGA_PORTRAIT is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_QVGA_LANDSCAPE is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_IRGB is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_8BPP is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_12BPP is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_ARGB is not set
-CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_RGB=y
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_24BPP is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_24BPP_PACKED is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_32BPP is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_YCBCR is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_OUTPUT_12BPP is not set
-CONFIG_FB_U8500_MCDE_CHANNELC0_OUTPUT_16BPP=y
-# CONFIG_FB_U8500_MCDE_CHANNELC0_OUTPUT_18BPP is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_OUTPUT_24BPP is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_BGRDATA is not set
-CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_BPP=16
-CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_TYPE=1
-CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_TYPE="WVGA_Portrait"
-CONFIG_FB_U8500_MCDE_CHANNELC0_OUTPUT_BPP=0x2
-CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_BGR=0x0
-# CONFIG_FB_U8500_MCDE_CHANNELC1 is not set
-CONFIG_FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_TYPE=0
-CONFIG_FB_U8500_MCDE_CHANNELC1_INPUT_BGR=0x0
+# Display Selection
+#
+CONFIG_DISPLAY_GENERIC_DSI_PRIMARY=y
+# CONFIG_DISPLAY_GENERIC_DSI_SECONDARY is not set
+# CONFIG_DISPLAY_AB8500_TERTIARY is not set
+# CONFIG_DISPLAY_AV8100_TERTIARY is not set
CONFIG_FORCE_MAX_ZONEORDER=12
#
@@ -1312,8 +1279,9 @@ CONFIG_FB_CFB_IMAGEBLIT=y
# Frame buffer hardware drivers
#
CONFIG_FB_MCDE=y
-CONFIG_FB_MCDE_MULTIBUFFER=y
-CONFIG_FB_HDMI=y
+CONFIG_MCDE_DISPLAY_GENERIC_DSI=y
+# CONFIG_MCDE_DISPLAY_AB8500_DENC is not set
+# CONFIG_MCDE_DISPLAY_AV8100 is not set
# CONFIG_FB_ARMCLCD is not set
CONFIG_FB_B2R2=y
# CONFIG_FB_S1D13XXX is not set
diff --git a/arch/arm/mach-ux500/Kconfig-arch b/arch/arm/mach-ux500/Kconfig-arch
index c2235c53682..cbfdd4d3758 100755
--- a/arch/arm/mach-ux500/Kconfig-arch
+++ b/arch/arm/mach-ux500/Kconfig-arch
@@ -1,9 +1,3 @@
-config MCDE_ENABLE_FEATURE_HW_V1_SUPPORT
- bool "MCDE HW V1 support"
- default n
- help
- Say yes here if V1 HW
-
config GPIO_STM
bool "STM GPIO driver support"
default y
@@ -41,676 +35,50 @@ config STM_ALSA_DEBUG
* 0 OFF
* 1 ON
endmenu
-#Configuration for MCDE setup
-
-menu "Display Channel Selection"
-
-menuconfig FB_U8500_MCDE_CHANNELA
- depends on FB
- bool "MCDE Channel A configuration"
- default y
- help
- If you want to connect your panel to MCDE channel A then configure this option
-
-choice
- prompt "Display Panel Type"
- depends on FB && FB_U8500_MCDE_CHANNELA
- default FB_U8500_MCDE_CHANNELA_DISPLAY_HDMI
-
-config FB_U8500_MCDE_CHANNELA_DISPLAY_WVGA
- bool "CLCD WVGA"
-
-config FB_U8500_MCDE_CHANNELA_DISPLAY_VGA
- bool "CLCD VGA"
-
-config FB_U8500_MCDE_CHANNELA_DISPLAY_CRT
- bool "CRT VGA"
-
-config FB_U8500_MCDE_CHANNELA_DISPLAY_PAL_THRU_AV8100
- bool "AV8100 PAL"
-
-config FB_U8500_MCDE_CHANNELA_DISPLAY_NTSC_THRU_AV8100
- bool "AV8100 NTSC"
-
-config FB_U8500_MCDE_CHANNELA_DISPLAY_HDMI
- depends on MCDE_ENABLE_FEATURE_HW_V1_SUPPORT && FB_HDMI
- bool "HDMI A"
-
-config FB_U8500_MCDE_CHANNELA_DISPLAY_QVGA_PORTRAIT
- bool "CLCD QVGA Portrait"
-
-config FB_U8500_MCDE_CHANNELA_DISPLAY_QVGA_LANDSCAPE
- bool "CLCD QVGA Landscape"
-
-endchoice
-
-choice
- prompt "HDMI resolution"
- depends on FB && FB_U8500_MCDE_CHANNELA && FB_U8500_MCDE_CHANNELA_DISPLAY_HDMI
- default FB_U8500_MCDE_HDMI_1280x720P60
-
-config FB_U8500_MCDE_HDMI_1920x1080P30
- bool "1920x1080P @ 30Hz"
-
-config FB_U8500_MCDE_HDMI_1280x720P60
- bool "1280x720P @ 60Hz"
-
-config FB_U8500_MCDE_HDMI_1920x1080I60
- bool "1920x1080I @ 60Hz"
-
-config FB_U8500_MCDE_HDMI_1920x1080I50
- bool "1920x1080I @ 50Hz"
-
-config FB_U8500_MCDE_HDMI_720x576I50
- bool "720x576I @ 50Hz"
-
-config FB_U8500_MCDE_HDMI_720x480I60
- bool "720x480I @ 60Hz"
-
-#config FB_U8500_MCDE_HDMI_720x480P60
-# bool "720x480P@60Hz"
-
-#config FB_U8500_MCDE_HDMI_640x480P60
-# bool "640x480P@60Hz"
-
-endchoice
-
-
-choice
- prompt "InputSource BPP"
- depends on FB && FB_U8500_MCDE_CHANNELA
- default FB_U8500_MCDE_CHANNELA_INPUT_16BPP_RGB
-
-
-config FB_U8500_MCDE_CHANNELA_INPUT_16BPP_IRGB
- bool "16 BPP IRGB"
-
-config FB_U8500_MCDE_CHANNELA_INPUT_8BPP
- bool "8 BPP"
-
-config FB_U8500_MCDE_CHANNELA_INPUT_12BPP
- bool "12 BPP"
-
-config FB_U8500_MCDE_CHANNELA_INPUT_16BPP_ARGB
- bool "16 BPP ARGB"
-
-config FB_U8500_MCDE_CHANNELA_INPUT_16BPP_RGB
- bool "16 BPP RGB"
-
-config FB_U8500_MCDE_CHANNELA_INPUT_24BPP
- bool "24 BPP"
-
-config FB_U8500_MCDE_CHANNELA_INPUT_24BPP_PACKED
- bool "24 BPP Packed"
-
-config FB_U8500_MCDE_CHANNELA_INPUT_32BPP
- bool "32 BPP"
-
-config FB_U8500_MCDE_CHANNELA_INPUT_YCBCR
- bool "YCbCr422"
-
-
-endchoice
-
-
-choice
- prompt "OutputPanel BPP"
- depends on FB && FB_U8500_MCDE_CHANNELA
- default FB_U8500_MCDE_CHANNELA_OUTPUT_16BPP
-
-config FB_U8500_MCDE_CHANNELA_OUTPUT_12BPP
- bool "12 BPP"
-
-config FB_U8500_MCDE_CHANNELA_OUTPUT_16BPP
- bool "16 BPP"
-
-config FB_U8500_MCDE_CHANNELA_OUTPUT_18BPP
- bool "18 BPP"
-
-config FB_U8500_MCDE_CHANNELA_OUTPUT_24BPP
- bool "24 BPP"
-
-
-endchoice
-
-config FB_U8500_MCDE_CHANNELA_INPUT_BGRDATA
- bool "BGR Input data"
- depends on FB && FB_U8500_MCDE_CHANNELA
- default no
- help
- Select this option if your input data is in BGR format
-
-
-config FB_U8500_MCDE_CHANNELA_INPUT_BPP
- int
- default 16 if !FB
- default 8 if FB_U8500_MCDE_CHANNELA_INPUT_8BPP
- default 16 if FB_U8500_MCDE_CHANNELA_INPUT_12BPP
- default 16 if FB_U8500_MCDE_CHANNELA_INPUT_16BPP_ARGB
- default 16 if FB_U8500_MCDE_CHANNELA_INPUT_16BPP_IRGB
- default 16 if FB_U8500_MCDE_CHANNELA_INPUT_16BPP_RGB
- default 25 if FB_U8500_MCDE_CHANNELA_INPUT_24BPP
- default 24 if FB_U8500_MCDE_CHANNELA_INPUT_24BPP_PACKED
- default 32 if FB_U8500_MCDE_CHANNELA_INPUT_32BPP
- default 11 if FB_U8500_MCDE_CHANNELA_INPUT_YCBCR
-
-
-config FB_U8500_MCDE_CHANNELA_INPUT_16BPP_TYPE
- int
- default 0 if ((!FB_U8500_MCDE_CHANNELA_INPUT_12BPP) && (!FB_U8500_MCDE_CHANNELA_INPUT_16BPP_RGB) && (!FB_U8500_MCDE_CHANNELA_INPUT_16BPP_IRGB) && (!FB_U8500_MCDE_CHANNELA_INPUT_16BPP_ARGB))
- default 35 if FB_U8500_MCDE_CHANNELA_INPUT_16BPP_RGB
- default 36 if FB_U8500_MCDE_CHANNELA_INPUT_16BPP_IRGB
- default 37 if FB_U8500_MCDE_CHANNELA_INPUT_16BPP_ARGB
- default 38 if FB_U8500_MCDE_CHANNELA_INPUT_12BPP
-
-
-config FB_U8500_MCDE_CHANNELA_DISPLAY_SDTV
- boolean
- depends on FB_U8500_MCDE_CHANNELA_DISPLAY_PAL_THRU_AV8100 || FB_U8500_MCDE_CHANNELA_DISPLAY_NTSC_THRU_AV8100
- default y
-
-config FB_U8500_MCDE_CHANNELA_DISPLAY_TYPE
- string
- default "VGA" if !FB
- default "WVGA" if FB_U8500_MCDE_CHANNELA_DISPLAY_WVGA
- default "VGA" if FB_U8500_MCDE_CHANNELA_DISPLAY_VGA
- default "CRT" if FB_U8500_MCDE_CHANNELA_DISPLAY_CRT
- default "PAL" if FB_U8500_MCDE_CHANNELA_DISPLAY_PAL_THRU_AV8100
- default "NTSC" if FB_U8500_MCDE_CHANNELA_DISPLAY_NTSC_THRU_AV8100
- default "1920x1080I60" if FB_U8500_MCDE_HDMI_1920x1080I60
- default "1920x1080I50" if FB_U8500_MCDE_HDMI_1920x1080I50
- default "1920x1080P30" if FB_U8500_MCDE_HDMI_1920x1080P30
- default "1280x720P60" if FB_U8500_MCDE_HDMI_1280x720P60
- default "NTSC" if FB_U8500_MCDE_HDMI_720x480I60
- default "PAL" if FB_U8500_MCDE_HDMI_720x576I50
- default "HDMI A" if FB_U8500_MCDE_CHANNELA_DISPLAY_HDMI
- default "QVGA_Portrait" if FB_U8500_MCDE_CHANNELA_DISPLAY_QVGA_PORTRAIT
- default "QVGA_Landscape" if FB_U8500_MCDE_CHANNELA_DISPLAY_QVGA_LANDSCAPE
-
-config FB_U8500_MCDE_CHANNELA_OUTPUT_BPP
- hex
- default 0x2 if !FB
- default 0x1 if FB_U8500_MCDE_CHANNELA_OUTPUT_12BPP
- default 0x2 if FB_U8500_MCDE_CHANNELA_OUTPUT_16BPP
- default 0x3 if FB_U8500_MCDE_CHANNELA_OUTPUT_18BPP
- default 0x4 if FB_U8500_MCDE_CHANNELA_OUTPUT_24BPP
-
-config FB_U8500_MCDE_CHANNELA_INPUT_BGR
- hex
- default 0x0 if !FB || !FB_U8500_MCDE_CHANNELA_INPUT_BGRDATA
- default 0x1 if FB_U8500_MCDE_CHANNELA_INPUT_BGRDATA
-
-
-menuconfig FB_U8500_MCDE_CHANNELB
- depends on FB
- bool "MCDE Channel B configuration"
- default n
- help
- If you want to connect your panel to MCDE channel B then configure this option
-
-choice
- prompt "Display Panel Type"
- depends on FB && FB_U8500_MCDE_CHANNELB
- default FB_U8500_MCDE_CHANNELB_DISPLAY_SDTV
-
-config FB_U8500_MCDE_CHANNELB_DISPLAY_WVGA
- bool "CLCD WVGA"
-
-config FB_U8500_MCDE_CHANNELB_DISPLAY_VGA
- bool "CLCD VGA"
-
-config FB_U8500_MCDE_CHANNELB_DISPLAY_CRT
- bool "CRT VGA"
-
-config FB_U8500_MCDE_CHANNELB_DISPLAY_SDTV
- depends on !FB_U8500_MCDE_CHANNELA_DISPLAY_HDMI && !FB_U8500_MCDE_CHANNELA_DISPLAY_PAL_THRU_AV8100 && !FB_U8500_MCDE_CHANNELA_DISPLAY_NTSC_THRU_AV8100
- bool "SDTV"
-
-config FB_U8500_MCDE_CHANNELB_DISPLAY_QVGA_PORTRAIT
- bool "CLCD QVGA Portrait"
-
-config FB_U8500_MCDE_CHANNELB_DISPLAY_QVGA_LANDSCAPE
- bool "CLCD QVGA Landscape"
-
-config FB_U8500_MCDE_CHANNELB_DISPLAY_VUIB_WVGA
- bool "VUIB WVGA"
-
-endchoice
-
-
-choice
- prompt "InputDataFormat BPP"
- depends on FB && FB_U8500_MCDE_CHANNELB
- default FB_U8500_MCDE_CHANNELB_INPUT_16BPP_RGB
-
-
-config FB_U8500_MCDE_CHANNELB_INPUT_16BPP_IRGB
- bool "16 BPP IRGB"
-
-config FB_U8500_MCDE_CHANNELB_INPUT_8BPP
- bool "8 BPP"
-
-config FB_U8500_MCDE_CHANNELB_INPUT_12BPP
- bool "12 BPP"
-
-config FB_U8500_MCDE_CHANNELB_INPUT_16BPP_ARGB
- bool "16 BPP ARGB"
-
-config FB_U8500_MCDE_CHANNELB_INPUT_16BPP_RGB
- bool "16 BPP RGB"
-
-config FB_U8500_MCDE_CHANNELB_INPUT_24BPP
- bool "24 BPP"
-
-config FB_U8500_MCDE_CHANNELB_INPUT_24BPP_PACKED
- bool "24 BPP Packed"
-
-config FB_U8500_MCDE_CHANNELB_INPUT_32BPP
- bool "32 BPP"
-
-config FB_U8500_MCDE_CHANNELB_INPUT_YCBCR
- bool "YCbCr422"
-
-endchoice
-
-
-choice
- prompt "OutputPanel BPP"
- depends on FB && FB_U8500_MCDE_CHANNELB
- default FB_U8500_MCDE_CHANNELB_OUTPUT_24BPP if FB_U8500_MCDE_CHANNELB_DISPLAY_SDTV
- default FB_U8500_MCDE_CHANNELB_OUTPUT_16BPP
-
-config FB_U8500_MCDE_CHANNELB_OUTPUT_12BPP
- bool "12 BPP"
-
-config FB_U8500_MCDE_CHANNELB_OUTPUT_16BPP
- bool "16 BPP"
-
-config FB_U8500_MCDE_CHANNELB_OUTPUT_18BPP
- bool "18 BPP"
-
-config FB_U8500_MCDE_CHANNELB_OUTPUT_24BPP
- bool "24 BPP"
-
-
-endchoice
+#Configuration for MCDE setup
+menu "Display selection"
-config FB_U8500_MCDE_CHANNELB_INPUT_BGRDATA
- bool "BGR Input data"
- depends on FB && FB_U8500_MCDE_CHANNELB
- default no
+config DISPLAY_GENERIC_DSI_PRIMARY
+ bool "Main display support"
+ depends on MACH_U8500_MOP && FB_MCDE
+ select MCDE_DISPLAY_GENERIC_DSI
+ default y
help
- Select this option if your input data is in BGR format
+ Say yes here if main display exists
-
-config FB_U8500_MCDE_CHANNELB_INPUT_BPP
- int
- default 16 if !FB
- default 8 if FB_U8500_MCDE_CHANNELB_INPUT_8BPP
- default 16 if FB_U8500_MCDE_CHANNELB_INPUT_12BPP
- default 16 if FB_U8500_MCDE_CHANNELB_INPUT_16BPP_ARGB
- default 16 if FB_U8500_MCDE_CHANNELB_INPUT_16BPP_IRGB
- default 16 if FB_U8500_MCDE_CHANNELB_INPUT_16BPP_RGB
- default 25 if FB_U8500_MCDE_CHANNELB_INPUT_24BPP
- default 24 if FB_U8500_MCDE_CHANNELB_INPUT_24BPP_PACKED
- default 32 if FB_U8500_MCDE_CHANNELB_INPUT_32BPP
- default 11 if FB_U8500_MCDE_CHANNELB_INPUT_YCBCR
-
-
-config FB_U8500_MCDE_CHANNELB_INPUT_16BPP_TYPE
- int
- default 0 if ((!FB_U8500_MCDE_CHANNELB_INPUT_12BPP) && (!FB_U8500_MCDE_CHANNELB_INPUT_16BPP_RGB) && (!FB_U8500_MCDE_CHANNELB_INPUT_16BPP_IRGB) && (!FB_U8500_MCDE_CHANNELB_INPUT_16BPP_ARGB))
- default 1 if FB_U8500_MCDE_CHANNELB_INPUT_16BPP_RGB
- default 2 if FB_U8500_MCDE_CHANNELB_INPUT_16BPP_IRGB
- default 3 if FB_U8500_MCDE_CHANNELB_INPUT_16BPP_ARGB
- default 4 if FB_U8500_MCDE_CHANNELB_INPUT_12BPP
-
-
-config FB_U8500_MCDE_CHANNELB_DISPLAY_TYPE
- string
- default "VGA" if !FB
- default "WVGA" if FB_U8500_MCDE_CHANNELB_DISPLAY_WVGA
- default "VGA" if FB_U8500_MCDE_CHANNELB_DISPLAY_VGA
- default "CRT" if FB_U8500_MCDE_CHANNELB_DISPLAY_CRT
- default "PAL" if FB_U8500_MCDE_CHANNELB_DISPLAY_SDTV
- default "QVGA_Portrait" if FB_U8500_MCDE_CHANNELB_DISPLAY_QVGA_PORTRAIT
- default "QVGA_Landscape" if FB_U8500_MCDE_CHANNELB_DISPLAY_QVGA_LANDSCAPE
- default "VUIB WVGA" if FB_U8500_MCDE_CHANNELB_DISPLAY_VUIB_WVGA
-
-config FB_U8500_MCDE_CHANNELB_OUTPUT_BPP
- hex
- default 0x2 if !FB
- default 0x1 if FB_U8500_MCDE_CHANNELB_OUTPUT_12BPP
- default 0x2 if FB_U8500_MCDE_CHANNELB_OUTPUT_16BPP
- default 0x3 if FB_U8500_MCDE_CHANNELB_OUTPUT_18BPP
- default 0x4 if FB_U8500_MCDE_CHANNELB_OUTPUT_24BPP
-
-config FB_U8500_MCDE_CHANNELB_INPUT_BGR
- hex
- default 0x0 if !FB || !FB_U8500_MCDE_CHANNELB_INPUT_BGRDATA
- default 0x1 if FB_U8500_MCDE_CHANNELB_INPUT_BGRDATA
-
-config U8500_MCDE_DHO_LBW_SWAPPED
- bool "SDTV-MCDE: Swap LBW and DHO fields"
- depends on FB_U8500_MCDE_CHANNELB_DISPLAY_SDTV || FB_U8500_MCDE_CHANNEL
- default y
- help
- In early development the MCDE register fields DHO and LBW are sw
-
-config U8500_TVOUT_DDR_MODE
- bool "SDTV: use Dual Data Rate"
- depends on FB_U8500_MCDE_CHANNELB_DISPLAY_SDTV || FB_U8500_MCDE_CHANNEL
- default y
- help
- Set to use dual data rate (using 4 data lines instead of 8)
-
-config TVOUT_TEST_PATTERN
- bool "SDTV: Generate Test Pattern"
- depends on FB_U8500_MCDE_CHANNELB_DISPLAY_SDTV || FB_U8500_MCDE_CHANNEL
- default n
- help
- Only generate a test pattern (MCDE is not used)
-
-menuconfig FB_U8500_MCDE_CHANNELC0
- depends on FB
- bool "MCDE Channel C0 configuration"
- default n
+config DISPLAY_GENERIC_DSI_SECONDARY
+ bool "Sub display support"
+ depends on MACH_U8500_MOP && FB_MCDE
+ select MCDE_DISPLAY_GENERIC_DSI
+ default n
help
- If you want to connect your panel to MCDE channel C then configure this option
-
-choice
- prompt "Display Panel Type"
- depends on FB && FB_U8500_MCDE_CHANNELC0
- default FB_U8500_MCDE_CHANNELC0_DISPLAY_WVGA
-
-config FB_U8500_MCDE_CHANNELC0_DISPLAY_WVGA_PORTRAIT
-# depends on MCDE_ENABLE_FEATURE_HW_V1_SUPPORT
- bool "CLCD WVGA Portrait"
-
-config FB_U8500_MCDE_CHANNELC0_DISPLAY_WVGA
- bool "CLCD WVGA"
-
-config FB_U8500_MCDE_CHANNELC0_DISPLAY_VGA
- bool "CLCD VGA"
-
-config FB_U8500_MCDE_CHANNELC0_DISPLAY_CRT
- bool "CRT VGA"
-
-config FB_U8500_MCDE_CHANNELC0_DISPLAY_SDTV
- bool "SDTV"
-
-config FB_U8500_MCDE_CHANNELC0_DISPLAY_QVGA_PORTRAIT
- bool "CLCD QVGA Portrait"
-
-config FB_U8500_MCDE_CHANNELC0_DISPLAY_QVGA_LANDSCAPE
- bool "CLCD QVGA Landscape"
-
-endchoice
-
-
-choice
- prompt "InputDataFormat BPP"
- depends on FB && FB_U8500_MCDE_CHANNELC0
- default FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_RGB
-
+ Say yes here if sub display exists
-config FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_IRGB
- bool "16 BPP IRGB"
-
-config FB_U8500_MCDE_CHANNELC0_INPUT_8BPP
- bool "8 BPP"
-
-config FB_U8500_MCDE_CHANNELC0_INPUT_12BPP
- bool "12 BPP"
-
-config FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_ARGB
- bool "16 BPP ARGB"
-
-config FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_RGB
- bool "16 BPP RGB"
-
-config FB_U8500_MCDE_CHANNELC0_INPUT_24BPP
- bool "24 BPP"
-
-config FB_U8500_MCDE_CHANNELC0_INPUT_24BPP_PACKED
- bool "24 BPP Packed"
-
-config FB_U8500_MCDE_CHANNELC0_INPUT_32BPP
- bool "32 BPP"
-
-config FB_U8500_MCDE_CHANNELC0_INPUT_YCBCR
- bool "YCbCr422"
-
-endchoice
-
-
-choice
- prompt "OutputPanel BPP"
- depends on FB && FB_U8500_MCDE_CHANNELC0
- default FB_U8500_MCDE_CHANNELC0_OUTPUT_16BPP
-
-config FB_U8500_MCDE_CHANNELC0_OUTPUT_12BPP
- bool "12 BPP"
-
-config FB_U8500_MCDE_CHANNELC0_OUTPUT_16BPP
- bool "16 BPP"
-
-config FB_U8500_MCDE_CHANNELC0_OUTPUT_18BPP
- bool "18 BPP"
-
-config FB_U8500_MCDE_CHANNELC0_OUTPUT_24BPP
- bool "24 BPP"
-
-
-endchoice
-
-
-
-config FB_U8500_MCDE_CHANNELC0_INPUT_BGRDATA
- bool "BGR Input data"
- depends on FB && FB_U8500_MCDE_CHANNELC0
- default no
+config DISPLAY_AB8500_TERTIARY
+ bool "AB8500 TVout display support"
+ depends on MACH_U8500_MOP && !AV8100_SDTV && FB_MCDE
+ select MCDE_DISPLAY_AB8500_DENC
+ default n
help
- Select this option if your input data is in BGR format
-
-
-config FB_U8500_MCDE_CHANNELC0_INPUT_BPP
- int
- default 16 if !FB
- default 8 if FB_U8500_MCDE_CHANNELC0_INPUT_8BPP
- default 16 if FB_U8500_MCDE_CHANNELC0_INPUT_12BPP
- default 16 if FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_ARGB
- default 16 if FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_IRGB
- default 16 if FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_RGB
- default 25 if FB_U8500_MCDE_CHANNELC0_INPUT_24BPP
- default 24 if FB_U8500_MCDE_CHANNELC0_INPUT_24BPP_PACKED
- default 32 if FB_U8500_MCDE_CHANNELC0_INPUT_32BPP
- default 11 if FB_U8500_MCDE_CHANNELC0_INPUT_YCBCR
-
+ Say yes here if tv out support
-config FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_TYPE
- int
- default 0 if ((!FB_U8500_MCDE_CHANNELC0_INPUT_12BPP) && (!FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_RGB) && (!FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_IRGB) && (!FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_ARGB))
- default 1 if FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_RGB
- default 2 if FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_IRGB
- default 3 if FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_ARGB
- default 4 if FB_U8500_MCDE_CHANNELC0_INPUT_12BPP
-
-
-config FB_U8500_MCDE_CHANNELC0_DISPLAY_TYPE
- string
- default "VGA" if !FB
- default "WVGA_Portrait" if FB_U8500_MCDE_CHANNELC0_DISPLAY_WVGA_PORTRAIT
- default "WVGA" if FB_U8500_MCDE_CHANNELC0_DISPLAY_WVGA
- default "VGA" if FB_U8500_MCDE_CHANNELC0_DISPLAY_VGA
- default "CRT" if FB_U8500_MCDE_CHANNELC0_DISPLAY_CRT
- default "SDTV" if FB_U8500_MCDE_CHANNELC0_DISPLAY_SDTV
- default "QVGA_Portrait" if FB_U8500_MCDE_CHANNELC0_DISPLAY_QVGA_PORTRAIT
- default "QVGA_Landscape" if FB_U8500_MCDE_CHANNELC0_DISPLAY_QVGA_LANDSCAPE
-
-config FB_U8500_MCDE_CHANNELC0_OUTPUT_BPP
- hex
- default 0x2 if !FB
- default 0x1 if FB_U8500_MCDE_CHANNELC0_OUTPUT_12BPP
- default 0x2 if FB_U8500_MCDE_CHANNELC0_OUTPUT_16BPP
- default 0x3 if FB_U8500_MCDE_CHANNELC0_OUTPUT_18BPP
- default 0x4 if FB_U8500_MCDE_CHANNELC0_OUTPUT_24BPP
-
-config FB_U8500_MCDE_CHANNELC0_INPUT_BGR
- hex
- default 0x0 if !FB || !FB_U8500_MCDE_CHANNELC0_INPUT_BGRDATA
- default 0x1 if FB_U8500_MCDE_CHANNELC0_INPUT_BGRDATA
-
-menuconfig FB_U8500_MCDE_CHANNELC1
- depends on FB
- bool "MCDE Channel C1 configuration"
- default n
+config DISPLAY_AV8100_TERTIARY
+ bool "AV8100 HDMI/CVBS display support"
+ depends on MACH_U8500_MOP && FB_MCDE
+ select MCDE_DISPLAY_AV8100
+ default n
help
- If you want to connect your panel to MCDE channel C then configure this option
-
-choice
- prompt "Display Panel Type"
- depends on FB && FB_U8500_MCDE_CHANNELC1
- default FB_U8500_MCDE_CHANNELC1_DISPLAY_WVGA
-
-config FB_U8500_MCDE_CHANNELC1_DISPLAY_WVGA_PORTRAIT
- bool "CLCD WVGA Portrait"
-
-config FB_U8500_MCDE_CHANNELC1_DISPLAY_WVGA
- bool "CLCD WVGA"
-
-config FB_U8500_MCDE_CHANNELC1_DISPLAY_VGA
- bool "CLCD VGA"
-
-config FB_U8500_MCDE_CHANNELC1_DISPLAY_CRT
- bool "CRT VGA"
-
-config FB_U8500_MCDE_CHANNELC1_DISPLAY_SDTV
- bool "SDTV"
-
-config FB_U8500_MCDE_CHANNELC1_DISPLAY_QVGA_PORTRAIT
- bool "CLCD QVGA Portrait"
-
-config FB_U8500_MCDE_CHANNELC1_DISPLAY_QVGA_LANDSCAPE
- bool "CLCD QVGA Landscape"
-
-endchoice
-
-
-choice
- prompt "InputDataFormat BPP"
- depends on FB && FB_U8500_MCDE_CHANNELC1
- default FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_RGB
-
-
-config FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_IRGB
- bool "16 BPP IRGB"
-
-config FB_U8500_MCDE_CHANNELC1_INPUT_8BPP
- bool "8 BPP"
-
-config FB_U8500_MCDE_CHANNELC1_INPUT_12BPP
- bool "12 BPP"
-
-config FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_ARGB
- bool "16 BPP ARGB"
-
-config FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_RGB
- bool "16 BPP RGB"
-
-config FB_U8500_MCDE_CHANNELC1_INPUT_24BPP
- bool "24 BPP"
+ Say yes here if HDMI output support
-config FB_U8500_MCDE_CHANNELC1_INPUT_24BPP_PACKED
- bool "24 BPP Packed"
-
-config FB_U8500_MCDE_CHANNELC1_INPUT_32BPP
- bool "32 BPP"
-
-config FB_U8500_MCDE_CHANNELC1_INPUT_YCBCR
- bool "YCbCr422"
-
-endchoice
-
-
-choice
- prompt "OutputPanel BPP"
- depends on FB && FB_U8500_MCDE_CHANNELC1
- default FB_U8500_MCDE_CHANNELC1_OUTPUT_16BPP
-
-config FB_U8500_MCDE_CHANNELC1_OUTPUT_12BPP
- bool "12 BPP"
-
-config FB_U8500_MCDE_CHANNELC1_OUTPUT_16BPP
- bool "16 BPP"
-
-config FB_U8500_MCDE_CHANNELC1_OUTPUT_18BPP
- bool "18 BPP"
-
-config FB_U8500_MCDE_CHANNELC1_OUTPUT_24BPP
- bool "24 BPP"
-
-
-endchoice
-
-
-
-config FB_U8500_MCDE_CHANNELC1_INPUT_BGRDATA
- bool "BGR Input data"
- depends on FB && FB_U8500_MCDE_CHANNELC1
- default no
+config AV8100_SDTV
+ bool "set AV8100 in CVBS mode"
+ depends on DISPLAY_AV8100_TERTIARY
+ default n
help
- Select this option if your input data is in BGR format
-
-
-config FB_U8500_MCDE_CHANNELC1_INPUT_BPP
- int
- default 16 if !FB
- default 8 if FB_U8500_MCDE_CHANNELC1_INPUT_8BPP
- default 16 if FB_U8500_MCDE_CHANNELC1_INPUT_12BPP
- default 16 if FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_ARGB
- default 16 if FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_IRGB
- default 16 if FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_RGB
- default 25 if FB_U8500_MCDE_CHANNELC1_INPUT_24BPP
- default 24 if FB_U8500_MCDE_CHANNELC1_INPUT_24BPP_PACKED
- default 32 if FB_U8500_MCDE_CHANNELC1_INPUT_32BPP
- default 11 if FB_U8500_MCDE_CHANNELC1_INPUT_YCBCR
-
-
-config FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_TYPE
- int
- default 0 if ((!FB_U8500_MCDE_CHANNELC1_INPUT_12BPP) && (!FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_RGB) && (!FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_IRGB) && (!FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_ARGB))
- default 1 if FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_RGB
- default 2 if FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_IRGB
- default 3 if FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_ARGB
- default 4 if FB_U8500_MCDE_CHANNELC1_INPUT_12BPP
-
-
-config FB_U8500_MCDE_CHANNELC1_DISPLAY_TYPE
- string
- default "VGA" if !FB
- default "WVGA_Portrait" if FB_U8500_MCDE_CHANNELC1_DISPLAY_WVGA_PORTRAIT
- default "WVGA" if FB_U8500_MCDE_CHANNELC1_DISPLAY_WVGA
- default "VGA" if FB_U8500_MCDE_CHANNELC1_DISPLAY_VGA
- default "CRT" if FB_U8500_MCDE_CHANNELC1_DISPLAY_CRT
- default "SDTV" if FB_U8500_MCDE_CHANNELC1_DISPLAY_SDTV
- default "QVGA_Portrait" if FB_U8500_MCDE_CHANNELC1_DISPLAY_QVGA_PORTRAIT
- default "QVGA_Landscape" if FB_U8500_MCDE_CHANNELC1_DISPLAY_QVGA_LANDSCAPE
-
-config FB_U8500_MCDE_CHANNELC1_OUTPUT_BPP
- hex
- default 0x2 if !FB
- default 0x1 if FB_U8500_MCDE_CHANNELC1_OUTPUT_12BPP
- default 0x2 if FB_U8500_MCDE_CHANNELC1_OUTPUT_16BPP
- default 0x3 if FB_U8500_MCDE_CHANNELC1_OUTPUT_18BPP
- default 0x4 if FB_U8500_MCDE_CHANNELC1_OUTPUT_24BPP
-
-config FB_U8500_MCDE_CHANNELC1_INPUT_BGR
- hex
- default 0x0 if !FB || !FB_U8500_MCDE_CHANNELC1_INPUT_BGRDATA
- default 0x1 if FB_U8500_MCDE_CHANNELC1_INPUT_BGRDATA
+ Say yes here if tv out support
endmenu
+
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index dbe51a938e8..5e1e8b1bd59 100755
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -32,7 +32,6 @@
#include <mach/stmpe1601.h>
#include <mach/tc35892.h>
#include <mach/sensors1p.h>
-#include <mach/av8100_p.h>
#include <mach/ab8500.h>
#include <mach/ab8500_bm.h>
#include <mach/mmc.h>
@@ -40,6 +39,15 @@
#include <mach/i2c.h>
#include <mach/u8500_tsc.h>
+#include <video/mcde_display.h>
+#include <video/mcde_display-generic_dsi.h>
+#include <video/mcde_display-av8100.h>
+#include <video/mcde_display-ab8500.h>
+#include <video/mcde_fb.h>
+#include <video/mcde_dss.h>
+#include <video/av8100.h>
+#include <mach/ab8500_denc.h>
+
#define IRQ_KP 1 /*To DO*/
int href_v1_board;
@@ -48,6 +56,8 @@ extern int platform_id;
#define MOP500_PLATFORM_ID 0
#define HREF_PLATFORM_ID 1
+#define AV8100_CUT_1_0
+
/*
* This is only non-static because MCDE accesses it directly. Make this static
* once MCDE is fixed to not depend on these variables.
@@ -111,15 +121,8 @@ static struct gpio_altfun_data gpio_altfun_table[] = {
__GPIO_ALT(GPIO_ALT_SDIO, 208, 214, 0, NMK_GPIO_ALT_A, "sdio"),
__GPIO_ALT(GPIO_ALT_TRACE, 70, 74, 0, NMK_GPIO_ALT_C, "stm"),
__GPIO_ALT(GPIO_ALT_SDMMC2, 128, 138, 0, NMK_GPIO_ALT_A, "mmc2"),
-#ifndef CONFIG_FB_NOMADIK_MCDE_CHANNELB_DISPLAY_VUIB_WVGA
- __GPIO_ALT(GPIO_ALT_LCD_PANELB_ED, 78, 85, 1, NMK_GPIO_ALT_A, "mcde tvout"),
- __GPIO_ALT(GPIO_ALT_LCD_PANELB_ED, 150, 150, 0, NMK_GPIO_ALT_B, "mcde tvout"),
__GPIO_ALT(GPIO_ALT_LCD_PANELB, 78, 81, 1, NMK_GPIO_ALT_A, "mcde tvout"),
__GPIO_ALT(GPIO_ALT_LCD_PANELB, 150, 150, 0, NMK_GPIO_ALT_B, "mcde tvout"),
-#else
- __GPIO_ALT(GPIO_ALT_LCD_PANELB, 153, 171, 1, NMK_GPIO_ALT_B, "mcde tvout"),
- __GPIO_ALT(GPIO_ALT_LCD_PANELB, 64, 77, 0, NMK_GPIO_ALT_A, "mcde tvout"),
-#endif
__GPIO_ALT(GPIO_ALT_LCD_PANELA, 68, 68, 0, NMK_GPIO_ALT_A, "mcde tvout"),
__GPIO_ALT(GPIO_ALT_MMIO_INIT_BOARD, 141, 142, 0, NMK_GPIO_ALT_B, "mmio"),
__GPIO_ALT(GPIO_ALT_MMIO_CAM_SET_I2C, 8, 9, 0, NMK_GPIO_ALT_A, "mmio"),
@@ -414,17 +417,17 @@ static struct tp_device tsc_plat_device = {
#endif
/* Portrait */
-#ifdef CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_WVGA_PORTRAIT
-
+#ifdef CONFIG_DISPLAY_GENERIC_DSI_PRIMARY
+/* Rotation always on */
static struct lsm303dlh_platform_data __initdata lsm303dlh_pdata = {
- .register_irq = NULL,
- .free_irq = NULL,
- .axis_map_x = 0, /* Axis map for HREF ED, HREF v1 and mop500 */
- .axis_map_y = 1,
- .axis_map_z = 2,
- .negative_x = 0,
- .negative_y = 0,
- .negative_z = 0,
+ .register_irq = NULL,
+ .free_irq = NULL,
+ .axis_map_x = 0, /* Axis map for HREF ED, HREF v1 and mop500 */
+ .axis_map_y = 1,
+ .axis_map_z = 2,
+ .negative_x = 0,
+ .negative_y = 0,
+ .negative_z = 0,
};
#else /* Landsacpe */
@@ -900,6 +903,432 @@ struct platform_device sensors1p_device = {
};
#endif
+#ifdef CONFIG_FB_MCDE
+#define DSI_UNIT_INTERVAL_0 0xA
+#define DSI_UNIT_INTERVAL_1 0xA
+#define DSI_UNIT_INTERVAL_2 0x6
+
+static bool rotate_main = true;
+static bool display_initialize_during_boot;
+
+#ifdef CONFIG_DISPLAY_GENERIC_DSI_PRIMARY
+static struct mcde_port port0 = {
+ .type = MCDE_PORTTYPE_DSI,
+ .mode = MCDE_PORTMODE_CMD,
+ .ifc = 1,
+ .link = 0,
+ .sync_src = MCDE_SYNCSRC_BTA,
+ .update_auto_trig = false,
+ .phy = {
+ .dsi = {
+ .virt_id = 0,
+ .num_data_lanes = 2,
+ .ui = DSI_UNIT_INTERVAL_0,
+ },
+ },
+};
+
+struct mcde_display_generic_platform_data generic_display0_pdata = {
+ .reset_gpio = EGPIO_PIN_15,
+ .reset_delay = 1,
+#ifdef CONFIG_REGULATOR
+ .regulator_id = "v-display",
+#endif
+};
+
+struct mcde_display_device generic_display0 = {
+ .name = "mcde_disp_generic",
+ .id = 0,
+ .port = &port0,
+ .chnl_id = MCDE_CHNL_A,
+ .fifo = MCDE_FIFO_C0,
+ .default_pixel_format = MCDE_OVLYPIXFMT_RGB565,
+ .port_pixel_format = MCDE_PORTPIXFMT_DSI_24BPP,
+ .native_x_res = 864,
+ .native_y_res = 480,
+ .synchronized_update = false,
+ /* TODO: Remove rotation buffers once ESRAM driver is completed */
+ .rotbuf1 = U8500_ESRAM_BASE + 0x20000 * 4,
+ .rotbuf2 = U8500_ESRAM_BASE + 0x20000 * 4 + 0x10000,
+ .dev = {
+ .platform_data = &generic_display0_pdata,
+ },
+};
+#endif /* CONFIG_DISPLAY_GENERIC_DSI_PRIMARY */
+
+#ifdef CONFIG_DISPLAY_GENERIC_DSI_SECONDARY
+static struct mcde_port subdisplay_port = {
+ .type = MCDE_PORTTYPE_DSI,
+ .mode = MCDE_PORTMODE_CMD,
+ .ifc = 1,
+ .link = 1,
+ .sync_src = MCDE_SYNCSRC_BTA,
+ .update_auto_trig = false,
+ .phy = {
+ .dsi = {
+ .virt_id = 0,
+ .num_data_lanes = 2,
+ .ui = DSI_UNIT_INTERVAL_1,
+ },
+ },
+};
+
+static struct mcde_display_generic_platform_data generic_subdisplay_pdata = {
+ .reset_gpio = EGPIO_PIN_14,
+ .reset_delay = 1,
+#ifdef CONFIG_REGULATOR
+ .regulator_id = "v-display",
+#endif
+};
+
+static struct mcde_display_device generic_subdisplay = {
+ .name = "mcde_disp_generic_subdisplay",
+ .id = 1,
+ .port = &subdisplay_port,
+ .chnl_id = MCDE_CHNL_C1,
+ .fifo = MCDE_FIFO_C1,
+ .default_pixel_format = MCDE_OVLYPIXFMT_RGB565,
+ .port_pixel_format = MCDE_PORTPIXFMT_DSI_24BPP,
+ .native_x_res = 864,
+ .native_y_res = 480,
+ .synchronized_update = false,
+ .dev = {
+ .platform_data = &generic_subdisplay_pdata,
+ },
+};
+#endif /* CONFIG_DISPLAY_GENERIC_DSI_SECONDARY */
+
+
+#ifdef CONFIG_DISPLAY_AB8500_TERTIARY
+static struct mcde_port port_tvout1 = {
+ .type = MCDE_PORTTYPE_DPI,
+ .ifc = 0,
+ .link = 1,
+ .sync_src = MCDE_SYNCSRC_OFF,
+ .update_auto_trig = true,
+ .phy = {
+ .dpi = {
+ .num_data_lanes = 4, /* DDR mode */
+ },
+ },
+};
+
+static struct ab8500_display_platform_data ab8500_display_pdata = {
+ /* TODO use this ID as soon as we switch to newer kernel with support or
+ * ab8500 TVout regulator
+ .regulator_id = "v-tvout",
+ */
+};
+
+static int ab8500_platform_enable(struct mcde_display_device *ddev)
+{
+ int res = 0;
+ /* probe checks for pdata */
+ struct ab8500_display_platform_data *pdata = ddev->dev.platform_data;
+
+ pr_info("%s\n", __func__);
+ res = stm_gpio_altfuncenable(GPIO_ALT_LCD_PANELB);
+ if (res != 0)
+ goto alt_func_failed;
+
+ if (pdata->regulator) {
+ res = regulator_enable(pdata->regulator);
+ if (res != 0)
+ goto regu_failed;
+ }
+
+out:
+ return res;
+
+regu_failed:
+ (void) stm_gpio_altfuncdisable(GPIO_ALT_LCD_PANELB);
+alt_func_failed:
+ dev_warn(&ddev->dev, "Failure during %s\n", __func__);
+ goto out;
+}
+
+static int ab8500_platform_disable(struct mcde_display_device *ddev)
+{
+ int res;
+ /* probe checks for pdata */
+ struct ab8500_display_platform_data *pdata = ddev->dev.platform_data;
+
+ dev_info(&ddev->dev, "%s\n", __func__);
+
+ res = stm_gpio_altfuncdisable(GPIO_ALT_LCD_PANELB);
+ if (res != 0)
+ goto alt_func_failed;
+
+ if (pdata->regulator) {
+ res = regulator_disable(pdata->regulator);
+ if (res != 0)
+ goto regu_failed;
+ }
+
+out:
+ return res;
+regu_failed:
+ (void) stm_gpio_altfuncenable(GPIO_ALT_LCD_PANELB);
+alt_func_failed:
+ dev_warn(&ddev->dev, "Failure during %s\n", __func__);
+ goto out;
+
+}
+
+static struct mcde_display_device tvout_ab8500_display = {
+ .name = "mcde_tv_ab8500",
+ .id = 2,
+ .port = &port_tvout1,
+ .chnl_id = MCDE_CHNL_B,
+ .fifo = MCDE_FIFO_B,
+ .default_pixel_format = MCDE_OVLYPIXFMT_RGB565,
+ .port_pixel_format = MCDE_PORTPIXFMT_DPI_24BPP,
+ .native_x_res = 720,
+ .native_y_res = 576,
+ .synchronized_update = true,
+ .video_mode = {
+ .xres = 720,
+ .yres = 576,
+ },
+ .dev = {
+ .platform_data = &ab8500_display_pdata,
+ },
+
+ /* We might need to describe the std here:
+ * - there are different PAL / NTSC formats (do they require MCDE
+ * settings?)
+ */
+ .platform_enable = ab8500_platform_enable,
+ .platform_disable = ab8500_platform_disable,
+};
+
+static struct ab8500_denc_platform_data ab8500_denc_pdata = {
+ .ddr_enable = true,
+ .ddr_little_endian = false,
+};
+
+static struct platform_device ab8500_denc = {
+ .name = "ab8500_denc",
+ .id = -1,
+ .dev = {
+ .platform_data = &ab8500_denc_pdata,
+ },
+};
+#endif /* CONFIG_DISPLAY_AB8500_TERTIARY */
+
+#ifdef CONFIG_DISPLAY_AV8100_TERTIARY
+static struct mcde_port port2 = {
+ .type = MCDE_PORTTYPE_DSI,
+ .mode = MCDE_PORTMODE_CMD,
+ .ifc = 1,
+ .link = 2,
+ .sync_src = MCDE_SYNCSRC_TE0,
+ .update_auto_trig = true,
+ .phy = {
+ .dsi = {
+ .virt_id = 0,
+ .num_data_lanes = 2,
+ .ui = DSI_UNIT_INTERVAL_2,
+ },
+ },
+};
+
+struct mcde_display_generic_platform_data av8100_hdmi_pdata = {
+ .reset_gpio = 0,
+ .reset_delay = 1,
+ .regulator_id = NULL, /* TODO: "display_main" */
+ .ddb_id = 1,
+};
+
+static int av8100_platform_enable(struct mcde_display_device *dev)
+{
+#define GPIO1B_AFSLA_REG_OFFSET 0x20
+#define GPIO1B_AFSLB_REG_OFFSET 0x24
+
+ int ret = 0;
+ struct mcde_display_hdmi_platform_data *pdata =
+ dev->dev.platform_data;
+
+#ifdef AV8100_CUT_1_0
+ volatile u32 __iomem *gpio_68_remap;
+#endif
+#ifdef AV8100_CUT_2_1
+ volatile u32 __iomem *gpio_69_remap;
+#endif
+
+ /* HW trig begin */
+#ifdef AV8100_CUT_1_0
+ gpio_68_remap = (u32 *) ioremap(
+ U8500_GPIO1_BASE + GPIO1B_AFSLB_REG_OFFSET,
+ (U8500_GPIO1_BASE + GPIO1B_AFSLB_REG_OFFSET + 3) -
+ (U8500_GPIO1_BASE + GPIO1B_AFSLB_REG_OFFSET) + 1);
+
+ *gpio_68_remap &= 0xffffffef;
+ iounmap(gpio_68_remap);
+
+ gpio_68_remap = (u32 *) ioremap(
+ U8500_GPIO1_BASE + GPIO1B_AFSLA_REG_OFFSET,
+ (U8500_GPIO1_BASE + GPIO1B_AFSLA_REG_OFFSET + 3) -
+ (U8500_GPIO1_BASE + GPIO1B_AFSLA_REG_OFFSET) + 1);
+ *gpio_68_remap |= 0x10;
+ iounmap(gpio_68_remap);
+#endif
+
+#ifdef AV8100_CUT_2_1
+ gpio_69_remap = (u32 *) ioremap(
+ U8500_GPIO1_BASE + GPIO1B_AFSLB_REG_OFFSET,
+ (U8500_GPIO1_BASE + GPIO1B_AFSLB_REG_OFFSET + 3) -
+ (U8500_GPIO1_BASE + GPIO1B_AFSLB_REG_OFFSET) + 1);
+
+ *gpio_69_remap &= 0xffffffdf;
+ iounmap(gpio_69_remap);
+
+ gpio_69_remap = (u32 *) ioremap(
+ U8500_GPIO1_BASE + GPIO1B_AFSLA_REG_OFFSET,
+ (U8500_GPIO1_BASE + GPIO1B_AFSLA_REG_OFFSET + 3) -
+ (U8500_GPIO1_BASE + GPIO1B_AFSLA_REG_OFFSET) + 1);
+ *gpio_69_remap |= 0x20;
+ iounmap(gpio_69_remap);
+#endif
+ /* HW trig end */
+
+ if (pdata->reset_gpio)
+ gpio_set_value(pdata->reset_gpio, pdata->reset_high);
+ if (pdata->regulator)
+ ret = regulator_enable(pdata->regulator);
+ return ret;
+}
+
+static int av8100_platform_disable(struct mcde_display_device *dev)
+{
+ int ret = 0;
+ struct mcde_display_hdmi_platform_data *pdata =
+ dev->dev.platform_data;
+
+ if (pdata->reset_gpio)
+ gpio_set_value(pdata->reset_gpio, !pdata->reset_high);
+ if (pdata->regulator)
+ ret = regulator_disable(pdata->regulator);
+
+ return ret;
+}
+
+static struct mcde_display_device av8100_hdmi = {
+ .name = "av8100_hdmi",
+ .id = 2,
+ .port = &port2,
+ .chnl_id = MCDE_CHNL_B,
+ .fifo = MCDE_FIFO_B,
+ .default_pixel_format = MCDE_OVLYPIXFMT_RGB565,
+ .port_pixel_format = MCDE_PORTPIXFMT_DSI_24BPP,
+#ifdef CONFIG_AV8100_SDTV
+ .native_x_res = 720,
+ .native_y_res = 576,
+#else
+ .native_x_res = 1280,
+ .native_y_res = 720,
+#endif
+ .synchronized_update = true,
+ .dev = {
+ .platform_data = &av8100_hdmi_pdata,
+ },
+ .platform_enable = av8100_platform_enable,
+ .platform_disable = av8100_platform_disable,
+};
+#endif /* CONFIG_DISPLAY_AV8100_TERTIARY */
+
+static struct fb_info *fbs[3] = { NULL, NULL, NULL };
+static struct mcde_display_device *displays[3] = { NULL, NULL, NULL };
+
+static int display_registered_callback(struct notifier_block *nb,
+ unsigned long event, void *dev)
+{
+ struct mcde_display_device *ddev = dev;
+ u16 width, height;
+ bool rotate;
+ bool display_initialized;
+
+ if (event != MCDE_DSS_EVENT_DISPLAY_REGISTERED)
+ return 0;
+
+ if (ddev->id < 0 || ddev->id >= ARRAY_SIZE(fbs))
+ return 0;
+
+ mcde_dss_get_native_resolution(ddev, &width, &height);
+
+ display_initialized = (ddev->id == 0 && display_initialize_during_boot);
+ rotate = (ddev->id == 0 && rotate_main);
+ if (rotate) {
+ u16 tmp = height;
+ height = width;
+ width = tmp;
+ }
+
+ /* Create frame buffer */
+ fbs[ddev->id] = mcde_fb_create(ddev,
+ width, height,
+ width, height * 2,
+ ddev->default_pixel_format,
+ rotate ? FB_ROTATE_CW : FB_ROTATE_UR,
+ display_initialized);
+ if (IS_ERR(fbs[ddev->id]))
+ pr_warning("Failed to create fb for display %s\n", ddev->name);
+ else
+ pr_info("Framebuffer created (%s)\n", ddev->name);
+
+ return 0;
+}
+
+static struct notifier_block display_nb = {
+ .notifier_call = display_registered_callback,
+};
+
+int __init init_display_devices(void)
+{
+ int ret;
+
+ ret = mcde_dss_register_notifier(&display_nb);
+ if (ret)
+ pr_warning("Failed to register dss notifier\n");
+
+#ifdef CONFIG_DISPLAY_GENERIC_DSI_PRIMARY
+ ret = mcde_display_device_register(&generic_display0);
+ if (ret)
+ pr_warning("Failed to register generic display device 0\n");
+ displays[0] = &generic_display0;
+#endif
+
+#ifdef CONFIG_DISPLAY_GENERIC_DSI_SECONDARY
+ ret = mcde_display_device_register(&generic_subdisplay);
+ if (ret)
+ pr_warning("Failed to register generic sub display device\n");
+ displays[1] = &generic_subdisplay;
+#endif
+
+#ifdef CONFIG_DISPLAY_AV8100_TERTIARY
+ ret = mcde_display_device_register(&av8100_hdmi);
+ if (ret)
+ pr_warning("Failed to register av8100_hdmi\n");
+ displays[2] = &av8100_hdmi;
+#endif
+#ifdef CONFIG_DISPLAY_AB8500_TERTIARY
+ ret = platform_device_register(&ab8500_denc);
+ if (ret)
+ pr_warning("Failed to register ab8500_denc device\n");
+ else {
+ ret = mcde_display_device_register(&tvout_ab8500_display);
+ if (ret)
+ pr_warning("Failed to register ab8500 tvout device\n");
+ displays[2] = &tvout_ab8500_display;
+ }
+#endif
+
+ return ret;
+}
+
+module_init(init_display_devices);
+#endif /* CONFIG_FB_MCDE */
+
static struct i2s_board_info stm_i2s_board_info[] __initdata = {
{
.modalias = "i2s_device.0",
@@ -1034,19 +1463,8 @@ static struct platform_device *platform_board_devs[] __initdata = {
&ab8500_gpadc_device,
&ab8500_bm_device,
&ux500_musb_device,
-#ifdef CONFIG_FB_U8500_MCDE_CHANNELC0
- &u8500_mcde2_device,
-#endif /* CONFIG_FB_U8500_MCDE_CHANNELC0 */
-#ifdef CONFIG_FB_U8500_MCDE_CHANNELC1
- &u8500_mcde3_device,
-#endif /* CONFIG_FB_U8500_MCDE_CHANNELC1 */
-#ifdef CONFIG_FB_U8500_MCDE_CHANNELB
- &u8500_mcde1_device,
-#endif /* CONFIG_FB_U8500_MCDE_CHANNELB */
-#ifdef CONFIG_FB_U8500_MCDE_CHANNELA
- &u8500_mcde0_device,
-#endif /* CONFIG_FB_U8500_MCDE_CHANNELA */
&ux500_b2r2_device,
+ &ux500_mcde_device,
#ifdef CONFIG_ANDROID_PMEM
&u8500_pmem_device,
&u8500_pmem_mio_device,
diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c
index 66e3e98259a..056ecc26140 100755
--- a/arch/arm/mach-ux500/clock.c
+++ b/arch/arm/mach-ux500/clock.c
@@ -480,22 +480,11 @@ static struct clk_lookup u8500_common_clkregs[] = {
CLK(tvclk, "tv", NULL),
/* With device names */
- CLK(mcdeclk, "U8500-MCDE.0", "mcde"),
- CLK(hdmiclk, "U8500-MCDE.0", "hdmi"),
- CLK(tvclk, "U8500-MCDE.0", "tv"),
- CLK(lcdclk, "U8500-MCDE.0", "lcd"),
- CLK(mcdeclk, "U8500-MCDE.1", "mcde"),
- CLK(hdmiclk, "U8500-MCDE.1", "hdmi"),
- CLK(tvclk, "U8500-MCDE.1", "tv"),
- CLK(lcdclk, "U8500-MCDE.1", "lcd"),
- CLK(mcdeclk, "U8500-MCDE.2", "mcde"),
- CLK(hdmiclk, "U8500-MCDE.2", "hdmi"),
- CLK(tvclk, "U8500-MCDE.2", "tv"),
- CLK(lcdclk, "U8500-MCDE.2", "lcd"),
- CLK(mcdeclk, "U8500-MCDE.3", "mcde"),
- CLK(hdmiclk, "U8500-MCDE.3", "hdmi"),
- CLK(tvclk, "U8500-MCDE.3", "tv"),
- CLK(lcdclk, "U8500-MCDE.3", "lcd"),
+
+ CLK(mcdeclk, "mcde", "mcde"),
+ CLK(hdmiclk, "mcde", "hdmi"),
+ CLK(tvclk, "mcde", "tv"),
+ CLK(lcdclk, "mcde", "lcd"),
CLK(b2r2clk, "U8500-B2R2.0", NULL),
/* Register the clock sources */
diff --git a/arch/arm/mach-ux500/include/mach/ab8500_denc.h b/arch/arm/mach-ux500/include/mach/ab8500_denc.h
new file mode 100644
index 00000000000..917f75d01a1
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/ab8500_denc.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * AB8500 tvout driver interface
+ *
+ * Author: Marcel Tunnissen <marcel.tuennissen@stericsson.com>
+ * for ST-Ericsson.
+ *
+ * License terms: GNU General Public License (GPL), version 2.
+ */
+#ifndef __AB8500_DENC__H__
+#define __AB8500_DENC__H__
+
+struct ab8500_denc_platform_data {
+ /* Platform info */
+ bool ddr_enable;
+ bool ddr_little_endian;
+};
+
+enum ab8500_denc_TV_std {
+ TV_STD_PAL_BDGHI,
+ TV_STD_PAL_N,
+ TV_STD_PAL_M,
+ TV_STD_NTSC_M,
+};
+
+enum ab8500_denc_cr_filter_bandwidth {
+ TV_CR_NTSC_LOW_DEF_FILTER,
+ TV_CR_PAL_LOW_DEF_FILTER,
+ TV_CR_NTSC_HIGH_DEF_FILTER,
+ TV_CR_PAL_HIGH_DEF_FILTER,
+};
+
+enum ab8500_denc_phase_reset_mode {
+ TV_PHASE_RST_MOD_DISABLE,
+ TV_PHASE_RST_MOD_FROM_PHASE_BUF,
+ TV_PHASE_RST_MOD_FROM_INC_DFS,
+ TV_PHASE_RST_MOD_RST,
+};
+
+enum ab8500_denc_plug_time {
+ TV_PLUG_TIME_0_5S,
+ TV_PLUG_TIME_1S,
+ TV_PLUG_TIME_1_5S,
+ TV_PLUG_TIME_2S,
+ TV_PLUG_TIME_2_5S,
+ TV_PLUG_TIME_3S,
+};
+
+struct ab8500_denc_conf {
+ /* register settings for DENC_configuration */
+ bool act_output;
+ enum ab8500_denc_TV_std TV_std;
+ bool progressive;
+ bool test_pattern;
+ bool partial_blanking;
+ bool blank_all;
+ bool black_level_setup;
+ enum ab8500_denc_cr_filter_bandwidth cr_filter;
+ bool suppress_col;
+ enum ab8500_denc_phase_reset_mode phase_reset_mode;
+ bool dac_enable;
+ bool act_dc_output;
+};
+
+void ab8500_denc_power_up(void);
+void ab8500_denc_power_down(void);
+void ab8500_denc_reset(bool hard);
+
+void ab8500_denc_regu_setup(bool enable_v_tv, bool enable_lp_mode);
+void ab8500_denc_conf(struct ab8500_denc_conf *conf);
+void ab8500_denc_conf_plug_detect(bool enable, bool load_RC,
+ enum ab8500_denc_plug_time time);
+void ab8500_denc_mask_int_plug_det(bool plug, bool unplug);
+#endif /* __AB8500_DENC__H__ */
+
diff --git a/arch/arm/mach-ux500/include/mach/av8100.h b/arch/arm/mach-ux500/include/mach/av8100.h
deleted file mode 100755
index 73355229b6a..00000000000
--- a/arch/arm/mach-ux500/include/mach/av8100.h
+++ /dev/null
@@ -1,553 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * License terms:
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#ifndef __AV8100_H
-#define __AV8100_H
-
-#ifdef _cplusplus
-extern "C" {
-#endif /* _cplusplus */
-
-typedef enum av8100_error
-{
- AV8100_OK = 0x0,
- AV8100_INVALID_COMMAND = 0x1,
- AV8100_INVALID_INTERFACE = 0x2,
- AV8100_INVALID_IOCTL = 0x3,
- AV8100_COMMAND_FAIL = 0x4,
- AV8100_FWDOWNLOAD_FAIL = 0x5,
- AV8100_FAIL = 0xFF,
-}av8100_error;
-
-typedef enum interface
-{
- I2C_INTERFACE = 0x0,
- DSI_INTERFACE = 0x1,
-}interface;
-
-/** AV8100 - DSI dcs command set */
-typedef enum
-{
- DCS_VSYNC_START = 0x1,
- DCS_VSYNC_END = 0x11,
- DCS_HSYNC_START = 0x21,
- DCS_HSYNC_END = 0x31,
- DCS_SHORT_WRITE = 0x15,
- DCS_LONG_WRITE = 0x39,
- DCS_RGB565_PACKED = 0xE,
- DCS_RGB666_PACKED = 0x1E,
- DCS_RGB666_UNPACKED = 0x2E,
- DCS_RGB888_PACKED = 0x3E,
- DCS_RAM_WRITE = 0x3C,
- DCS_RAM_WRITE_CONTINUE = 0x2C,
- DCS_FW_DOWNLOAD = 0xDB,
- DCS_WRITE_UC = 0xDC,
- DCS_READ_UC = 0xDB,
- DCS_NEXT_FILED_TYPE = 0xDA,
- DCS_EXEC_UC = 0xDD,
-}dsi_dcs_command_type;
-
-/** AV8100 Operating modes */
-typedef enum
-{
- AV8100_OPMODE_SHUTDOWN = 0x1,
- AV8100_OPMODE_STANDBY,
- AV8100_OPMODE_SCAN,
- AV8100_OPMODE_INIT,
- AV8100_OPMODE_IDLE,
- AV8100_OPMODE_VIDEO
-}av8100_operating_mode;
-
-/** AV8100 status */
-#define AV8100_PLUGIN_NONE 0x00
-#define AV8100_HDMI_PLUGIN 0x01
-#define AV8100_CVBS_PLUGIN 0x02
-
-/** AV8100 Command Type */
-typedef enum
-{
- AV8100_COMMAND_VIDEO_INPUT_FORMAT = 0x1,
- AV8100_COMMAND_AUDIO_INPUT_FORMAT = 0x2,
- AV8100_COMMAND_VIDEO_OUTPUT_FORMAT = 0x3,
- AV8100_COMMAND_VIDEO_SCALING_FORMAT,
- AV8100_COMMAND_COLORSPACECONVERSION,
- AV8100_COMMAND_CEC_MESSAGEWRITE,
- AV8100_COMMAND_CEC_MESSAGEREAD_BACK,
- AV8100_COMMAND_DENC,
- AV8100_COMMAND_HDMI,
- AV8100_COMMAND_HDCP_SENDKEY,
- AV8100_COMMAND_HDCP_MANAGEMENT,
- AV8100_COMMAND_INFOFRAMES,
- AV8100_COMMAND_EDID_SECTIONREADBACK,
- AV8100_COMMAND_PATTERNGENERATOR,
-
-}av8100_command_type;
-
-/** AV8100 Command Type */
-typedef enum
-{
- AV8100_COMMAND_VIDEO_INPUT_FORMAT_SIZE = 0x17,
- AV8100_COMMAND_AUDIO_INPUT_FORMAT_SIZE = 0x8,
- AV8100_COMMAND_VIDEO_OUTPUT_FORMAT_SIZE = 0x18,
- AV8100_COMMAND_VIDEO_SCALING_FORMAT_SIZE = 0x9,
- AV8100_COMMAND_COLORSPACECONVERSION_SIZE = 0x21,
- AV8100_COMMAND_CEC_MESSAGEWRITE_SIZE = 0x14,
- AV8100_COMMAND_CEC_MESSAGEREAD_BACK_SIZE = 0x14,
- AV8100_COMMAND_DENC_SIZE = 0x7,
- AV8100_COMMAND_HDMI_SIZE = 0x4,
- AV8100_COMMAND_HDCP_SENDKEY_SIZE = 0x9,
- AV8100_COMMAND_HDCP_MANAGEMENT_SIZE = 0x4,
- AV8100_COMMAND_INFOFRAMES_SIZE = 0x22,
- AV8100_COMMAND_EDID_SECTIONREADBACK_SIZE = 0x81,
- AV8100_COMMAND_PATTERNGENERATOR_SIZE = 0x4,
-}av8100_command_size;
-
-/** AV8100 structures register & command definitions */
-
-/** AV8100 Internal registers ~ Register 0x0 to 0xF */
-/** Internal registers for I2C operations */
-
-typedef enum
-{
- STANDBY_REG = 0x0,
- AV8100_5_VOLT_TIME_REG = 0x1,
- STANDBY_INTERRUPT_MASK_REG = 0x2,
- STANDBY_PENDING_INTERRUPT_REG = 0x3,
- GENERAL_INTERRUPT_MASK_REG = 0x4,
- GENERAL_INTERRUPT_REG = 0x5,
- GENERAL_STATUS_REG = 0x6,
- GPIO_CONFIGURATION_REG = 0x7,
- GENERAL_CONTROL_REG = 0x8,
- FIRMWARE_DOWNLOAD_ENTRY_REG = 0xF
-}internal_reg;
-
-struct av8100_registers_internal
-{
- volatile char standby;
- volatile char av8100_5_volt_time;
- volatile char standby_interrupt_mask;
- volatile char standby_pending_interrupt;
- volatile char general_interrupt_mask;
- volatile char general_interrupt;
- volatile char general_status;
- volatile char gpio_configuration;
- volatile char general_control;
- volatile char firmware_download_entry;
-};
-
-/** AV8100 Video Input Format Command */
-struct av8100_video_input_format_command
-{
-
- volatile char Identifier;
- volatile char Mode;
- volatile char Pixel_format;
- volatile char Htotal[2];
- volatile char Hactive[2];
- volatile char Vtotal[2];
- volatile char Vactive[2];
- volatile char Videomode;
- volatile char Number_DSI;
- volatile char Virtualchannelcommandmode;
- volatile char Virtualchannelvideomode;
- volatile char Linenumber[2];
- volatile char Tearingeffect;
- volatile char Master_Clock_frequency[4];
-};
-
-/** AV8100 Audio Input Format Command */
-struct av8100_audio_input_format_command
-{
-
- volatile char Identifier;
- volatile char I2SOrTDM;
- volatile char NumberofI2SentriesFreq;
- volatile char BitFormat;
- volatile char LPCMOrCompress;
- volatile char SlaveOrMaster;
- volatile char Mute;
-
-};
-
-/** AV8100 Video Output Format Command */
-struct av8100_video_output_format_command
-{
-
- volatile char Identifier;
- volatile char Formatter;
- volatile char VSYNCpolarity;
- volatile char HSYNCpolarity;
- volatile char Htotal[2];
- volatile char Hactive[2];
- volatile char Vtotal[2];
- volatile char Vactive[2];
- volatile char HSYNCstart[2];
- volatile char HSYNClength[2];
- volatile char VSYNCstart[2];
- volatile char VSYNClength[2];
- volatile char Pixelfrequency[4];
-};
-
-/** AV8100 Video Video Scaling Format Command */
-struct av8100_video_scaling_format_command
-{
- volatile char Identifier;
- volatile char Hstart[2];
- volatile char Hstop[2];
- volatile char Vstart[2];
- volatile char Vstop[2];
-};
-
-/** AV8100 Video Colorspace Conversion Command */
-struct av8100_colorspace_conversion_command
-{
- volatile char Identifier;
- volatile char C0[2];
- volatile char C1[2];
- volatile char C2[2];
- volatile char C3[2];
- volatile char C4[2];
- volatile char C5[2];
- volatile char C6[2];
- volatile char C7[2];
- volatile char C8[21];
- volatile char AOFFSET[2];
- volatile char BOFFSET[2];
- volatile char COFFSET[2];
- volatile char AMINIMUM;
- volatile char AMAXIMUM;
- volatile char BMINIMUM;
- volatile char BMAXIMUM;
- volatile char CMINIMUM;
- volatile char CMAXIMUM;
-};
-
-/** AV8100 Video CEC message */
-struct av8100_CEC_message
-{
- volatile char Identifier;
- volatile char PhysicaladdressAB;
- volatile char PhysicaladdressCD;
- volatile char Bufferlength;
- volatile char BufferData[16];
-};
-
-/** AV8100 Video CEC message Readback Command */
-struct av8100_CEC_message_readback_command
-{
- volatile char Identifier;
-};
-
-/** AV8100 Video HDMI Command */
-struct av8100_HDMI_command
-{
- volatile char Identifier;
- volatile char OFF_ON_AVMUTE;
- volatile char HDMI_DVI;
- volatile char DVIcontrolbit;
-};
-
-/** AV8100 Video HDCP sendkey Command */
-struct av8100_HDCP_sendkey_command
-{
- volatile char Identifier;
- volatile char Keynumber;
- volatile char Key[7];
-};
-
-/** AV8100 Video HDCP management Command */
-struct av8100_HDCP_management_command
-{
- volatile char Identifier;
- volatile char RequestHDCPauthentication;
- volatile char Requestencryptedtransmission;
- volatile char OESS_EESS;
-};
-
-/** AV8100 Video Infoframe Command */
-struct av8100_Infoframe_command
-{
- volatile char Identifier;
- volatile char Infoframetype;
- volatile char Infoframedata[30];
- volatile char InfoframeCRC;
-};
-
-/** AV8100 Video EDID section readback Command */
-struct av8100_EDIDsectionreadback_command
-{
- volatile char Identifier;
- volatile char EDIDaddress;
- volatile char EDIDblocknumber;
-};
-
-/** AV8100 Video Pattern Generator Command */
-struct av8100_PatternGenerator_command
-{
- volatile char Identifier;
- volatile char Testtypeselection;
- volatile char VideoPatterngeneratorselection;
- volatile char AudioSound;
-};
-
-/** AV8100 Video Command return */
-struct av8100_command_return
-{
- volatile char Identifier;
- volatile char OK_FAIL;
-};
-
-/** AV8100 Video CEC messgae readback command */
-struct av8100_EDID_section_readback
-{
- volatile char Identifier;
- volatile char OK_FAIL;
- volatile char EDID[128];
-};
-
-typedef enum{
- AV8100_AUDIO_I2S_MODE,
- AV8100_AUDIO_I2SDELAYED_MODE, /* I2S Mode by default*/
- AV8100_AUDIO_TDM_MODE /* 8 Channels by default*/
-} av8100_audio_if_format;
-
-typedef enum{
- AV8100_AUDIO_MUTE_DISABLE,
- AV8100_AUDIO_MUTE_ENABLE
-} av8100_audio_mute;
-
-typedef enum{
- AV8100_AUDIO_SLAVE,
- AV8100_AUDIO_MASTER
-} av8100_audio_if_mode;
-
-typedef enum{
- AV8100_AUDIO_LPCM_MODE,
- AV8100_AUDIO_COMPRESS_MODE
-} av8100_audio_format;
-
-typedef enum{
- AV8100_AUDIO_16BITS,
- AV8100_AUDIO_20BITS,
- AV8100_AUDIO_24BITS
-} av8100_audio_word_length;
-
-typedef enum{
- AV8100_AUDIO_FREQ_32KHZ,
- AV8100_AUDIO_FREQ_44_1KHZ,
- AV8100_AUDIO_FREQ_48KHZ,
- AV8100_AUDIO_FREQ_64KHZ,
- AV8100_AUDIO_FREQ_88_2KHZ,
- AV8100_AUDIO_FREQ_96KHZ,
- AV8100_AUDIO_FREQ_128KHZ,
- AV8100_AUDIO_FREQ_176_1KHZ,
- AV8100_AUDIO_FREQ_192KHZ
-} av8100_sample_freq;
-
-
-typedef enum{
- AV8100_PATTERN_AUDIO_OFF,
- AV8100_PATTERN_AUDIO_ON,
- AV8100_PATTERN_AUDIO_I2S_MEM
-} av8100_pattern_audio;
-
-typedef enum{
- AV8100_PATTERN_OFF,
- AV8100_PATTERN_GENERATOR,
- AV8100_PRODUCTION_TESTING
-} av8100_pattern_type;
-
-typedef enum{
- AV8100_NO_PATTERN,
- AV8100_PATTERN_VGA,
- AV8100_PATTERN_720P,
- AV8100_PATTERN_1080P
-} av8100_pattern_format;
-
-typedef enum{
- AV8100_HDMI_OFF,
- AV8100_HDMI_ON,
- AV8100_HDMI_AVMUTE
-} av8100_hdmi_mode;
-
-typedef enum{
- AV8100_HDMI,
- AV8100_DVI
-} av8100_hdmi_format;
-
-typedef enum{
- AV8100_DVI_CTRL_CTL0,
- AV8100_DVI_CTRL_CTL1,
- AV8100_DVI_CTRL_CTL2
-} av8100_DVI_format;
-
-typedef enum{
- AV8100_TV_LINES_625 = 0,
- AV8100_TV_LINES_525
-} av8100_TV_lines;
-
-typedef enum{
- AV8100_TV_STD_PALBDGHI = 0,
- AV8100_TV_STD_PALN,
- AV8100_TV_STD_NTSCM,
- AV8100_TV_STD_PALM
-} av8100_TV_std;
-
-typedef enum{
- AV8100_DENC_OFF = 0,
- AV8100_DENC_ON
-} av8100_DENC_State;
-
-typedef enum{
- AV8100_MACROVISION_OFF = 0,
- AV8100_MACROVISION_ON
-} av8100_macrovision_state;
-
-typedef enum{
- AV8100_INTERNAL_GENERATOR_OFF = 0,
- AV8100_INTERNAL_GENERATOR_ON
-} av8100_internal_generator_state;
-
-typedef enum{
- AV8100_CHROMA_CWS_CAPTURE_OFF = 0,
- AV8100_CHROMA_CWS_CAPTURE_ON
-} av8100_chroma_cws_capture_state;
-
-typedef enum{
- AV8100_SYNC_POSITIVE,
- AV8100_SYNC_NEGATIVE
-} av8100_video_sync_pol;
-
-typedef enum{
-
- AV8100_INPUT_PIX_RGB565,
- AV8100_INPUT_PIX_RGB666,
- AV8100_INPUT_PIX_RGB666P,
- AV8100_INPUT_PIX_RGB888,
- AV8100_INPUT_PIX_YCBCR422
-} av8100_pixel_format;
-
-typedef enum{
- AV8100_TE_OFF, /* NO TE*/
- AV8100_TE_DSI_LANE, /* TE generated on DSI lane */
- AV8100_TE_IT_LINE, /* TE generated on IT line (GPIO) */
- AV8100_TE_DSI_IT /* TE generatedon both DSI lane & IT line*/
-} av8100_te_config;
-
-typedef enum{
-
- AV8100_DATA_LANES_USED_0, /* 0 DSI data lane connected*/
- AV8100_DATA_LANES_USED_1, /* 1 DSI data lane connected */
- AV8100_DATA_LANES_USED_2, /* 2 DSI data lane connected */
- AV8100_DATA_LANES_USED_3, /* 3 DSI data lane connected */
- AV8100_DATA_LANES_USED_4 /* 4 DSI data lane connected */
-} av8100_dsi_nb_data_lane;
-
-typedef enum{
-
- AV8100_VIDEO_INTERLACE,
- AV8100_VIDEO_PROGRESSIVE
-} av8100_video_mode;
-
-typedef enum{
-
- AV8100_HDMI_DSI_OFF,
- AV8100_HDMI_DSI_COMMAND_MODE,
- AV8100_HDMI_DSI_VIDEO_MODE
-} av8100_dsi_mode;
-
-/* AV8100 video modes */
-typedef enum{
- AV8100_CUSTOM,
- AV8100_CEA1_640X480P_59_94HZ,
- AV8100_CEA2_3_720X480P_59_94HZ, // new
- AV8100_CEA4_1280X720P_60HZ,
- AV8100_CEA5_1920X1080I_60HZ,
- AV8100_CEA6_7_NTSC_60HZ, //new
- AV8100_CEA14_15_480p_60HZ, //new
- AV8100_CEA16_1920X1080P_60HZ, //new
- AV8100_CEA17_18_720X576P_50HZ, //new
- AV8100_CEA19_1280X720P_50HZ,
- AV8100_CEA20_1920X1080I_50HZ,
- AV8100_CEA21_22_576I_PAL_50HZ, //new
- AV8100_CEA29_30_576P_50HZ, //new
- AV8100_CEA31_1920x1080P_50Hz, //new
- AV8100_CEA32_1920X1080P_24HZ,
- AV8100_CEA33_1920X1080P_25HZ,
- AV8100_CEA34_1920X1080P_30HZ,
- AV8100_CEA60_1280X720P_24HZ,
- AV8100_CEA61_1280X720P_25HZ,
- AV8100_CEA62_1280X720P_30HZ,
- AV8100_VESA9_800X600P_60_32HZ,
- AV8100_VESA14_848X480P_60HZ,
- AV8100_VESA16_1024X768P_60HZ,
- AV8100_VESA22_1280X768P_59_99HZ,
- AV8100_VESA23_1280X768P_59_87HZ,
- AV8100_VESA27_1280X800P_59_91HZ,
- AV8100_VESA28_1280X800P_59_81HZ,
- AV8100_VESA39_1360X768P_60_02HZ,
- AV8100_VESA81_1366X768P_59_79HZ,
- AV8100_VIDEO_OUTPUT_CEA_VESA_MAX
-} av8100_output_CEA_VESA;
-
-/** AV8100 internal register access structure*/
-struct av8100_register
-{
- char value;
- char offset;
-};
-
-/** AV8100 command configuration registers access structure*/
-struct av8100_command_register
-{
- unsigned char cmd_id; /* input */
- unsigned char buf_len; /* input, output */
- unsigned char buf[128]; /* input, output */
- unsigned char return_status; /* output */
-};
-
-/* IOCTL return status */
-#define HDMI_COMMAND_RETURN_STATUS_OK 0
-#define HDMI_COMMAND_RETURN_STATUS_FAIL 1
-
-#define HDMI_REQUEST_FOR_REVOCATION_LIST_INPUT 2
-#define HDMI_CEC_MESSAGE_READBACK_MAXSIZE 16
-
-/** AV8100 status structure*/
-struct av8100_status
-{
- char av8100_state;
- char av8100_plugin_status;
-};
-
-/** Maximum size of the structure need to passed to AV8100 */
-
-#define AV8100_IOC_MAGIC 0xcc
-
-/** IOCTL Operations for accessing information from AV8100 */
-
-#define IOC_AV8100_READ_REGISTER _IOWR(AV8100_IOC_MAGIC,1,struct av8100_register)
-#define IOC_AV8100_WRITE_REGISTER _IOWR(AV8100_IOC_MAGIC,2,struct av8100_register)
-#define IOC_AV8100_SEND_CONFIGURATION_COMMAND _IOWR(AV8100_IOC_MAGIC,3,struct av8100_command_register)
-//#define IOC_AV8100_READ_CONFIGURATION_COMMAND _IOWR(AV8100_IOC_MAGIC,4,struct av8100_command_register)
-#define IOC_AV8100_GET_STATUS _IOWR(AV8100_IOC_MAGIC,4,struct av8100_status)
-#define IOC_AV8100_ENABLE _IOWR(AV8100_IOC_MAGIC,5,struct av8100_status)
-#define IOC_AV8100_DISABLE _IOWR(AV8100_IOC_MAGIC,6,struct av8100_status)
-#define IOC_AV8100_SET_VIDEO_FORMAT _IOWR(AV8100_IOC_MAGIC,7,struct av8100_status)
-#define IOC_AV8100_HDMI_ON _IOWR(AV8100_IOC_MAGIC,8,struct av8100_status)
-#define IOC_AV8100_HDMI_OFF _IOWR(AV8100_IOC_MAGIC,9,struct av8100_status)
-
-#define AV8100_IOC_MAXNR (1)
-
-#ifdef _cplusplus
-}
-#endif /* _cplusplus */
-
-#endif /* !defined(__AV8100_H) */
diff --git a/arch/arm/mach-ux500/include/mach/av8100_fw.h b/arch/arm/mach-ux500/include/mach/av8100_fw.h
deleted file mode 100755
index b4243c00c55..00000000000
--- a/arch/arm/mach-ux500/include/mach/av8100_fw.h
+++ /dev/null
@@ -1,1041 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * License terms:
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-/* AV8100 Firmware version : V3.03 */
-#define fw_size 16384
-char ReceiveTab[fw_size];
-char TransmitTab[fw_size];
-char av8100_fw_buff[fw_size] = {
-0x80,0xfe,0xcb,0xfe,0xbc,0xc2,0x73,0xc4,0x73,0xc4,0xc9,0xc5,0x72,0xc3,0xce,0xc5,
-0x16,0xc7,0xd8,0xc8,0xed,0xc8,0xfe,0xc8,0x10,0xc9,0x23,0xc9,0x28,0xc9,0x2d,0xc9,
-0x32,0xc9,0x37,0xc9,0x4c,0xc9,0x86,0xc9,0x02,0xca,0xb6,0xc2,0xb6,0xc2,0xb7,0xc2,
-0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x81,0xea,0xad,0xec,0xad,
-0x38,0x20,0x1b,0x72,0x80,0x81,0x4d,0x51,0x4d,0x51,0x4d,0x51,0x4d,0x51,0x4d,0x51,
-0x4d,0x51,0xb4,0x20,0xf4,0x2a,0x5a,0x90,0x82,0xfe,0xcd,0x80,0x00,0xaf,0x72,0x93,
-0xa3,0x20,0x5f,0x90,0x80,0x80,0x97,0x90,0x8d,0x20,0x0f,0xab,0x01,0xa6,0x88,0x89,
-0x90,0x96,0xad,0x97,0x90,0x9a,0xad,0x8b,0x93,0x9e,0xad,0x97,0x90,0xa2,0xad,0x80,
-0xb7,0xa6,0xad,0x81,0xb7,0xaa,0xad,0x82,0xb7,0xae,0xad,0x26,0x31,0x20,0x08,0x72,
-0x82,0xb7,0x21,0xa6,0x81,0xb7,0xc2,0xa6,0x80,0xb7,0x01,0xa6,0xb4,0x20,0xf5,0x2a,
-0x5a,0x90,0x80,0x00,0xa7,0x72,0x93,0xcc,0xad,0x49,0x27,0x97,0x90,0x5d,0x90,0xd4,
-0xad,0x82,0xb7,0xd8,0xad,0x81,0xb7,0xdc,0xad,0x80,0xb7,0xe0,0xad,0xff,0xae,0x90,
-0x81,0x59,0x29,0xea,0x26,0x5a,0xfb,0x38,0x20,0x07,0x72,0x4d,0x38,0x20,0x1a,0x72,
-0x49,0x00,0x38,0x20,0x05,0x72,0xbc,0xff,0xcd,0x08,0xae,0xf3,0x20,0x79,0x24,0x49,
-0x44,0x24,0x49,0x23,0x24,0x49,0x0b,0xad,0x82,0xfe,0xcd,0x9e,0x82,0xfe,0xcd,0x9f,
-0x5b,0x82,0xfe,0xcd,0x80,0xb6,0x82,0xfe,0xcd,0x81,0xb6,0x82,0xfe,0xcd,0x82,0xb6,
-0x82,0xad,0x9f,0x90,0x86,0xad,0x85,0x90,0x84,0x42,0x8c,0x20,0x9f,0x90,0x01,0xab,
-0x0f,0xa6,0x2a,0x31,0x20,0x08,0x72,0xfb,0x38,0x20,0x07,0x72,0x4d,0x38,0x20,0x1a,
-0x72,0xbc,0xff,0xcd,0xfb,0x38,0x20,0x07,0x72,0x30,0x20,0x10,0x72,0x31,0x20,0x1e,
-0x72,0x30,0x20,0x1c,0x72,0x95,0x05,0xa0,0x9e,0x52,0xc0,0xcc,0x5f,0x90,0x5f,0x4f,
-0x07,0x38,0x20,0x05,0x72,0x0c,0x39,0x20,0x05,0x72,0x81,0x41,0x29,0x38,0x20,0x18,
-0x72,0xd5,0x26,0x5a,0xfb,0x38,0x20,0x07,0x72,0x9d,0x9d,0x4d,0x38,0x20,0x1a,0x72,
-0x4d,0xae,0xff,0xcd,0x4d,0xae,0xff,0xcd,0x38,0x20,0x1b,0x72,0x4d,0x4d,0x4d,0x4d,
-0x4d,0x38,0x20,0x19,0x72,0x04,0x25,0x49,0x38,0x20,0x18,0x72,0x08,0xae,0x34,0x20,
-0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-0x00,0x00,0x81,0xa5,0xbe,0x84,0xa3,0xb7,0xa4,0xd6,0x92,0x5c,0xa2,0xb7,0xa4,0xd6,
-0x92,0x5c,0xa1,0xb7,0xa4,0xd6,0x92,0x01,0xae,0xa0,0xb7,0xa4,0xc6,0x92,0x88,0xa5,
-0xbf,0x81,0xa0,0xb7,0xa4,0xc2,0x92,0xa0,0xb6,0xa1,0xb7,0xa4,0xd2,0x92,0x5a,0xa1,
-0xb6,0xa2,0xb7,0xa4,0xd2,0x92,0x5a,0xa2,0xb6,0xa3,0xb7,0xa4,0xd0,0x92,0xa3,0xb6,
-0x03,0xae,0xa5,0xbf,0x81,0xa3,0xb7,0xa4,0xda,0x92,0x5c,0xa3,0xb6,0xa2,0xb7,0xa4,
-0xda,0x92,0x5c,0xa2,0xb6,0xa1,0xb7,0xa4,0xda,0x92,0x01,0xae,0xa1,0xb6,0xa0,0xb7,
-0xa4,0xca,0x92,0xa0,0xb6,0xa5,0xbf,0x81,0xa5,0xbe,0xe9,0x26,0x4a,0xa4,0x00,0x66,
-0x72,0x5c,0xa4,0x00,0x66,0x72,0x5c,0xa4,0x00,0x66,0x72,0x01,0xae,0xa4,0x00,0x34,
-0x72,0xa5,0xbf,0x1b,0x27,0x4d,0xea,0xfa,0xcc,0xd9,0xfb,0xcd,0x81,0xa5,0xbe,0xe9,
-0x26,0x4a,0xa4,0x00,0x39,0x72,0xa4,0x00,0x69,0x72,0x5a,0xa4,0x00,0x69,0x72,0x5a,
-0xa4,0x00,0x68,0x72,0x03,0xae,0xa5,0xbf,0x1b,0x27,0x4d,0x81,0xa0,0xb7,0xa4,0xc9,
-0x92,0xa0,0xb6,0xa1,0xb7,0xa4,0xd9,0x92,0x5a,0xa1,0xb6,0xa2,0xb7,0xa4,0xd9,0x92,
-0x5a,0xa2,0xb6,0xa3,0xb7,0xa4,0xdb,0x92,0xa3,0xb6,0x03,0xae,0xa5,0xbf,0xea,0xfa,
-0xcc,0x72,0xfb,0xcd,0x81,0x01,0xa6,0x02,0x20,0xff,0xa6,0x04,0x24,0x08,0x27,0xa4,
-0xd1,0x92,0xa3,0xb6,0xa5,0x3c,0x09,0x26,0xa4,0xd1,0x92,0xa2,0xb6,0xa5,0x3c,0x12,
-0x26,0xa4,0xd1,0x92,0xa1,0xb6,0xa5,0x3c,0x23,0x26,0xa4,0xd1,0x92,0xa0,0xb6,0xa5,
-0x3f,0x81,0xa0,0x3c,0x02,0x24,0xa1,0xb7,0xa1,0xb9,0x9f,0xa2,0xb7,0xa2,0xbb,0x42,
-0x93,0x0f,0x27,0x4d,0x84,0x30,0xfb,0xcd,0xa8,0xb6,0x05,0x27,0xa7,0xbe,0xa3,0xb7,
-0xa2,0xbf,0x42,0x93,0xa8,0xb6,0xa1,0xb7,0xa0,0xbf,0x42,0xa7,0xb6,0x89,0xa8,0xb7,
-0x81,0xa0,0x3f,0xa1,0x3f,0xa2,0xbf,0xa3,0xb7,0x81,0xa5,0xbe,0x84,0xa4,0xd7,0x92,
-0xa3,0xb6,0x5c,0xa4,0xd7,0x92,0xa2,0xb6,0x5c,0xa4,0xd7,0x92,0xa1,0xb6,0x01,0xae,
-0xa4,0xc7,0x92,0xa0,0xb6,0x88,0xa5,0xbf,0x81,0xa5,0xbe,0xa4,0xd7,0x92,0xa3,0xb6,
-0x5c,0xa4,0xd7,0x92,0xa2,0xb6,0x5c,0xa4,0xd7,0x92,0xa1,0xb6,0x01,0xae,0xa4,0xc7,
-0x92,0xa0,0xb6,0xa5,0xbf,0x81,0x01,0xa6,0x02,0x27,0x03,0x6d,0x04,0x26,0x02,0x6d,
-0x08,0x26,0x01,0x6d,0x0e,0x26,0x7d,0x81,0x84,0xa3,0xb7,0x03,0xe6,0xa2,0xb7,0x02,
-0xe6,0xa1,0xb7,0x01,0xe6,0xa0,0xb7,0xf6,0x88,0x81,0x01,0xa6,0x02,0x27,0xa3,0x3d,
-0x04,0x26,0xa2,0x3d,0x08,0x26,0xa1,0x3d,0x0e,0x26,0xa0,0x3d,0x81,0xf5,0x26,0x4a,
-0xa0,0x39,0xa1,0x39,0xa2,0x39,0xa3,0x38,0x0b,0x27,0x4d,0x81,0xa0,0x3f,0xa1,0x3f,
-0x81,0xa0,0xb7,0xa1,0xb7,0xff,0xa6,0x07,0x2a,0xa2,0xbf,0xa3,0xb7,0x81,0x41,0xa8,
-0xbb,0x41,0x52,0x93,0x84,0xa8,0xb7,0xa8,0xbb,0x52,0x01,0x7b,0xa7,0xbe,0xa8,0xb7,
-0x52,0x9f,0x90,0x88,0x81,0xa5,0xbe,0xa3,0xb7,0xa4,0xd6,0x92,0x5c,0xa2,0xb7,0xa4,
-0xd6,0x92,0x5c,0xa1,0xb7,0xa4,0xd6,0x92,0x01,0xae,0xa0,0xb7,0xa4,0xc6,0x92,0xa5,
-0xbf,0x81,0xa0,0x3f,0xa2,0xb7,0xa1,0xbf,0x5c,0x01,0x24,0xa2,0xbb,0x42,0x93,0xa0,
-0xb6,0xa3,0xb7,0xa2,0xbf,0x42,0x93,0xa0,0xbf,0x81,0x39,0x01,0xc6,0x39,0x01,0xc7,
-0x60,0xa6,0x02,0x20,0xa0,0xa6,0x09,0x26,0x2f,0x01,0x5a,0x72,0x0f,0x20,0x2f,0x01,
-0x02,0x35,0x39,0x01,0xc0,0x35,0x0a,0x27,0x4d,0xdf,0xf7,0xcd,0x1a,0x27,0x30,0x01,
-0xc6,0x21,0x20,0xa0,0xa6,0x25,0x20,0xc0,0xa6,0x04,0x27,0x4d,0xdf,0xf7,0xcd,0x2f,
-0x01,0x02,0x35,0x33,0x20,0x82,0xa6,0x3a,0x26,0x68,0x01,0xca,0x69,0x01,0xc6,0x3f,
-0x20,0x81,0xa6,0x46,0x26,0x68,0x01,0xca,0x69,0x01,0xc6,0x4b,0x20,0x20,0xa6,0xf1,
-0x27,0x4d,0x86,0xf7,0xcd,0x53,0x27,0x30,0x01,0xc6,0x5a,0x20,0x40,0xa6,0x0f,0x26,
-0x4d,0x86,0xf7,0xcd,0x62,0x27,0x30,0x01,0xc6,0x69,0x20,0x80,0xa6,0x1e,0x27,0x31,
-0x01,0xc6,0x14,0x27,0x4d,0x86,0xf7,0xcd,0x76,0x27,0x30,0x01,0xc6,0x2e,0x27,0x07,
-0x01,0xc4,0x4f,0x01,0x20,0x4c,0x03,0x26,0x68,0x01,0xca,0x69,0x01,0xc6,0x20,0xfa,
-0xcc,0x21,0xa6,0x49,0xdf,0xcd,0x02,0xae,0x94,0xa6,0x0c,0x27,0x07,0x01,0xc6,0x50,
-0x20,0xf8,0x27,0x32,0x01,0xc6,0x23,0xfa,0xcc,0xf9,0x27,0x20,0xa0,0xff,0xf9,0xcc,
-0x03,0x26,0x20,0xa0,0x5a,0x27,0x1e,0xa0,0xed,0xf9,0xcc,0x03,0x26,0x4a,0xe1,0xf9,
-0xcc,0x03,0x26,0x4a,0x79,0x27,0x20,0xa0,0x6e,0x27,0x20,0xa0,0x63,0x27,0x1f,0xa0,
-0x42,0x27,0x4a,0x34,0x27,0x20,0xa0,0x31,0x27,0x4d,0xd1,0xf9,0xcc,0x03,0x26,0x07,
-0x01,0xce,0x08,0x27,0x38,0x01,0xc6,0x20,0xfa,0xcc,0x03,0x26,0x32,0x01,0xc6,0x08,
-0x27,0x38,0x01,0xc6,0x39,0x01,0x38,0x01,0x55,0x81,0x84,0x05,0x20,0x18,0x72,0x06,
-0x20,0xc7,0x01,0x6b,0x01,0xea,0x72,0xe0,0xa4,0x38,0x01,0xc6,0x01,0x6b,0x1f,0xa4,
-0x06,0x20,0xc6,0x2a,0xf6,0xcd,0x03,0x20,0xa7,0xf5,0xcd,0x08,0x20,0xe2,0xf4,0xcd,
-0x02,0xa6,0x0f,0x27,0x32,0x01,0xc6,0x14,0x26,0x01,0x7b,0x18,0x20,0x49,0xdf,0xcd,
-0x5f,0x32,0xa6,0x01,0x6b,0xe2,0xf4,0xcd,0x4c,0x26,0x27,0x32,0x01,0xce,0x2b,0x26,
-0x01,0x7b,0x0d,0x20,0x39,0xf7,0xcd,0x34,0x27,0x32,0x01,0xc6,0x39,0x26,0x01,0x6b,
-0x63,0xf6,0xcd,0x40,0x27,0x32,0x01,0xc6,0x45,0x26,0x01,0x6b,0xe2,0xf4,0xcd,0x4c,
-0x27,0x32,0x01,0xce,0x51,0x26,0x01,0x6b,0xa7,0xf5,0xcd,0x58,0x27,0x32,0x01,0xc6,
-0x5d,0x20,0xa7,0xf5,0xcd,0x62,0x20,0xa7,0xf5,0xcd,0x67,0x26,0x07,0x01,0xc6,0x6c,
-0x20,0x6b,0x27,0x20,0xa0,0x6a,0x27,0x1e,0xa0,0x5e,0x27,0x4a,0x4a,0x27,0x4a,0x1f,
-0x27,0x20,0xa0,0x1e,0x27,0x20,0xa0,0x22,0x27,0x20,0xa0,0x1c,0x27,0x20,0xa0,0x38,
-0x01,0xc7,0x25,0xf9,0xcc,0x03,0x26,0x38,0x01,0xc1,0x39,0x01,0xc7,0x27,0xf9,0xcd,
-0x88,0x81,0xa4,0xb7,0x00,0xa9,0x41,0x06,0xab,0x81,0x84,0x8b,0x41,0x00,0xa9,0x41,
-0x08,0xab,0x5b,0x09,0x6b,0x01,0x6b,0x4f,0x01,0x20,0x01,0xa6,0x04,0x26,0x05,0xe1,
-0x72,0x4f,0x01,0xc6,0x0c,0x26,0x04,0xe1,0x72,0x0d,0x20,0x13,0x26,0x4f,0x01,0xc1,
-0x05,0x7b,0x09,0x26,0x4e,0x01,0xc6,0xca,0x26,0x3f,0xfb,0xcd,0xa4,0xb7,0x00,0xa9,
-0x41,0x02,0xab,0x5b,0x1f,0xfc,0xcd,0x3e,0xad,0x5b,0xe8,0xfa,0xcd,0x44,0xad,0x5b,
-0x72,0xf5,0xcd,0x84,0x4f,0xf2,0xcd,0x74,0xae,0x08,0xa6,0x02,0x4b,0x02,0x6b,0x06,
-0x7b,0x03,0x6b,0x07,0x7b,0x04,0x6b,0x08,0x7b,0x05,0x6b,0x09,0x7b,0xe8,0xfa,0xcd,
-0x67,0xad,0x5b,0x72,0xf5,0xcd,0x01,0x6b,0x06,0x6b,0x07,0x6b,0x08,0x6b,0x09,0x6b,
-0x02,0x6b,0x03,0x6b,0x04,0x6b,0x05,0x6b,0x4f,0x8b,0x41,0x00,0xa2,0x41,0x09,0xa0,
-0x5b,0x81,0x85,0x85,0x85,0x85,0x85,0x4f,0x01,0x20,0x01,0xa6,0x04,0x26,0x14,0xa1,
-0x02,0x7b,0x0a,0x26,0x14,0xa1,0x03,0x7b,0xcc,0x25,0x05,0xa1,0x04,0x6b,0x4c,0x04,
-0x7b,0xe2,0x25,0x08,0xa1,0x05,0x6b,0x4c,0x05,0x7b,0x4e,0x01,0x54,0x72,0x02,0x6b,
-0x4c,0x02,0x7b,0x05,0x20,0x03,0x6b,0x4c,0x03,0x7b,0x07,0x4e,0x01,0x00,0x72,0x05,
-0x6b,0x4f,0x84,0x4f,0xf2,0xcd,0x74,0xae,0x05,0x7b,0x01,0x4b,0x04,0x6b,0x03,0x6b,
-0x02,0x6b,0x01,0x6b,0x4f,0x88,0x88,0x88,0x88,0x88,0x81,0x85,0x4f,0x7b,0xf5,0xcd,
-0x84,0x33,0x01,0x4e,0x01,0x55,0x4f,0xf2,0xcd,0x74,0xae,0x04,0xa6,0x01,0x4b,0xcc,
-0x25,0x04,0xa1,0x01,0x6b,0x4c,0x01,0x7b,0xb4,0xfb,0xcd,0x34,0xae,0xa4,0x00,0x01,
-0x35,0x73,0xfa,0xcd,0xfa,0x26,0x5a,0x90,0x59,0x48,0x06,0x27,0x58,0x90,0x58,0x90,
-0x58,0x90,0x01,0xe6,0x72,0x5f,0x4e,0x01,0xc6,0x84,0x4f,0xf2,0xcd,0x74,0xae,0x02,
-0x7b,0x01,0x4b,0x01,0x6b,0x4f,0x88,0x81,0xba,0xfb,0xcd,0x08,0xa6,0xa4,0xb7,0x81,
-0x84,0x8b,0x41,0x00,0xa9,0x41,0x0f,0xab,0x5b,0x10,0x6b,0x4f,0x84,0x22,0xf3,0xcd,
-0x74,0xae,0x14,0xa6,0x88,0x0e,0x6b,0x01,0x7b,0xe0,0x25,0x04,0xa1,0x10,0x6b,0x4c,
-0x10,0x7b,0x23,0xad,0x00,0xa9,0x41,0x0a,0xab,0x5b,0x84,0x22,0xf3,0xcd,0x74,0xae,
-0x10,0xab,0x11,0x7b,0x88,0x0e,0x6b,0x0d,0x7b,0x10,0x6b,0x4f,0x01,0x6b,0x49,0x01,
-0xc6,0x0a,0x6b,0x42,0x01,0xc6,0x0b,0x6b,0x43,0x01,0xc6,0x0c,0x6b,0x44,0x01,0xc6,
-0x0d,0x6b,0x45,0x01,0xc6,0xe0,0x25,0x08,0xa1,0x10,0x6b,0x4c,0x10,0x7b,0x5f,0xad,
-0x00,0xa9,0x41,0x06,0xab,0x5b,0x84,0x22,0xf3,0xcd,0x74,0xae,0x18,0xab,0x11,0x7b,
-0x88,0x0f,0x6b,0x09,0x7b,0x10,0x6b,0x04,0xa6,0xdf,0x25,0x04,0xa1,0x10,0x6b,0x4c,
-0x10,0x7b,0x31,0xf7,0xcd,0x00,0xa9,0x41,0x02,0xab,0x5b,0x84,0x22,0xf3,0xcd,0x74,
-0xae,0x18,0xab,0x11,0x7b,0x88,0x0f,0x6b,0x05,0x7b,0x10,0x6b,0x4f,0x06,0x6b,0x1c,
-0x48,0xc6,0x07,0x6b,0x1d,0x48,0xc6,0x08,0x6b,0x1e,0x48,0xc6,0x09,0x6b,0x1f,0x48,
-0xc6,0x02,0x6b,0x18,0x48,0xc6,0x03,0x6b,0x19,0x48,0xc6,0x04,0x6b,0x1a,0x48,0xc6,
-0x05,0x6b,0x1b,0x48,0xc6,0x8b,0x41,0x00,0xa2,0x41,0x10,0xa0,0x5b,0x81,0x84,0x84,
-0x84,0x84,0x9a,0xe8,0xfa,0xcd,0x04,0xae,0xa4,0x00,0x48,0x35,0xa3,0x14,0xa3,0x12,
-0xa3,0x10,0x1f,0xfc,0xcd,0xa4,0xb7,0x00,0xa9,0x41,0x01,0xab,0x5b,0x9b,0x01,0x6b,
-0x04,0x48,0xc6,0x02,0x6b,0x05,0x48,0xc6,0x03,0x6b,0x06,0x48,0xc6,0x04,0x6b,0x07,
-0x48,0xc6,0x88,0x88,0x88,0x88,0x81,0x84,0x84,0x84,0x84,0x9a,0xe8,0xfa,0xcd,0x04,
-0xae,0xa4,0x00,0x48,0x35,0xa0,0x3f,0xa1,0x3f,0xa2,0x3f,0xa3,0xb7,0x3f,0xa4,0xa3,
-0xb6,0xa0,0xb7,0xa1,0xb7,0xa2,0xb7,0x4f,0xa3,0xb7,0x03,0xaa,0x04,0x7b,0x9b,0x01,
-0x6b,0x04,0x48,0xc6,0x02,0x6b,0x05,0x48,0xc6,0x03,0x6b,0x06,0x48,0xc6,0x04,0x6b,
-0x07,0x48,0xc6,0x88,0x88,0x88,0x88,0x81,0x85,0x85,0x85,0x85,0x4f,0x9a,0xe8,0xfa,
-0xcd,0x04,0xae,0xa4,0x00,0x48,0x35,0xa0,0x3f,0xa1,0x3f,0xa2,0x3f,0xa3,0xb7,0x3f,
-0xa4,0xa3,0xb6,0xa0,0xb7,0xa1,0xb7,0xa2,0xb7,0x4f,0xa3,0xb7,0xfc,0xa4,0x04,0x7b,
-0x9b,0x01,0x6b,0x04,0x48,0xc6,0x02,0x6b,0x05,0x48,0xc6,0x03,0x6b,0x06,0x48,0xc6,
-0x04,0x6b,0x07,0x48,0xc6,0x88,0x88,0x88,0x88,0x81,0x9a,0xe8,0xfa,0xcd,0x14,0xae,
-0xa4,0x00,0x48,0x35,0xa0,0xb7,0xa1,0xb7,0xa2,0xb7,0x4f,0xa3,0x00,0x33,0x01,0x55,
-0x10,0x48,0x34,0x01,0x55,0x11,0x48,0x35,0x01,0x55,0x12,0x48,0x36,0x01,0x55,0x13,
-0x48,0x37,0x01,0x55,0x9b,0x1f,0xfc,0xcc,0x30,0xae,0xa4,0x00,0x48,0x35,0x81,0x85,
-0x85,0x85,0x85,0x85,0x85,0x85,0x85,0x01,0x7b,0x91,0xf4,0xcd,0x02,0x7b,0x01,0x6b,
-0x4c,0x05,0x26,0x02,0x6b,0x01,0xa6,0x02,0x27,0x01,0xa4,0x07,0x6b,0x8d,0xf4,0xcd,
-0xf7,0x27,0x07,0x7b,0x07,0x6b,0x8d,0xf4,0xcd,0x05,0x20,0x9a,0xe8,0xfa,0xcd,0x5f,
-0xa4,0x00,0x48,0x35,0xa0,0x3f,0xa1,0x3f,0xa2,0x3f,0xa0,0xb7,0xa1,0xb7,0xa2,0xb7,
-0x4f,0xa3,0xb7,0x06,0x7b,0x9b,0x06,0x6b,0x83,0xaa,0x06,0x7b,0x04,0x20,0x03,0xaa,
-0x06,0x7b,0x0a,0x20,0x02,0xaa,0x06,0x7b,0x10,0x20,0x01,0xaa,0x06,0x7b,0x18,0x20,
-0x14,0x27,0x4a,0x11,0x27,0x4a,0x0e,0x27,0x4a,0x0b,0x27,0x08,0x7b,0x03,0x6b,0x00,
-0x48,0xc6,0x04,0x6b,0x01,0x48,0xc6,0x05,0x6b,0x02,0x48,0xc6,0x06,0x6b,0x03,0x48,
-0xc6,0x01,0x6b,0x07,0x6b,0x4f,0x88,0x88,0x88,0x88,0x88,0x88,0x88,0x88,0x81,0x84,
-0x84,0x84,0x84,0x84,0x9a,0xe8,0xfa,0xcd,0x0c,0xae,0xa4,0x00,0x48,0x35,0xa0,0x3f,
-0xa1,0x3f,0xa2,0x3f,0xa3,0xb7,0x03,0xa4,0xa3,0xb6,0xa0,0xb7,0xa1,0xb7,0xa2,0xb7,
-0x4f,0xa3,0xb7,0x04,0x7b,0x9b,0x04,0x6b,0x02,0xaa,0x04,0x7b,0x04,0x20,0x01,0xaa,
-0x04,0x7b,0x06,0x27,0x05,0x7b,0x01,0x6b,0x0c,0x48,0xc6,0x02,0x6b,0x0d,0x48,0xc6,
-0x03,0x6b,0x0e,0x48,0xc6,0x04,0x6b,0x0f,0x48,0xc6,0x88,0x88,0x88,0x88,0x88,0x81,
-0x0f,0x48,0xc6,0x81,0x84,0x84,0x84,0x84,0x84,0x9a,0xe8,0xfa,0xcd,0x04,0xae,0xa4,
-0x00,0x48,0x35,0xa0,0x3f,0xa1,0x3f,0xa2,0x3f,0xa3,0xb7,0x3f,0xa4,0xa3,0xb6,0xa0,
-0xb7,0xa1,0xb7,0xa2,0xb7,0x4f,0xa3,0xb7,0x04,0x7b,0x9b,0x04,0x6b,0xfb,0xa4,0x04,
-0x7b,0x04,0x20,0x04,0xaa,0x04,0x7b,0x06,0x27,0x05,0x7b,0x01,0x6b,0x04,0x48,0xc6,
-0x02,0x6b,0x05,0x48,0xc6,0x03,0x6b,0x06,0x48,0xc6,0x04,0x6b,0x07,0x48,0xc6,0x88,
-0x88,0x88,0x88,0x88,0x81,0x84,0x84,0x84,0x84,0x9a,0xe8,0xfa,0xcd,0x04,0xae,0xa4,
-0x00,0x48,0x35,0xa0,0x3f,0xa1,0x3f,0xa2,0x3f,0xa3,0xb7,0x3f,0xa4,0xa3,0xb6,0xa0,
-0xb7,0xa1,0xb7,0xa2,0xb7,0x4f,0xa3,0xb7,0xfc,0xa4,0x04,0x7b,0x9b,0x01,0x6b,0x04,
-0x48,0xc6,0x02,0x6b,0x05,0x48,0xc6,0x03,0x6b,0x06,0x48,0xc6,0x04,0x6b,0x07,0x48,
-0xc6,0x88,0x88,0x88,0x88,0x81,0x84,0x84,0x84,0x84,0x9a,0xe8,0xfa,0xcd,0x04,0xae,
-0xa4,0x00,0x48,0x35,0xa0,0x3f,0xa1,0x3f,0xa2,0x3f,0xa3,0xb7,0x3f,0xa4,0xa3,0xb6,
-0xa0,0xb7,0xa1,0xb7,0xa2,0xb7,0x4f,0xa3,0xb7,0x03,0xaa,0x04,0x7b,0x9b,0x01,0x6b,
-0x04,0x48,0xc6,0x02,0x6b,0x05,0x48,0xc6,0x03,0x6b,0x06,0x48,0xc6,0x04,0x6b,0x07,
-0x48,0xc6,0x88,0x88,0x88,0x88,0x81,0x4f,0x13,0xb7,0x53,0x20,0xc6,0x50,0x20,0x12,
-0x72,0x81,0x01,0xa6,0x03,0x27,0x4d,0xd6,0xf1,0xcd,0x88,0xa6,0x12,0xb7,0x53,0x20,
-0xc6,0x50,0x20,0x15,0x72,0x81,0x01,0xa6,0x03,0x27,0x4d,0xd6,0xf1,0xcd,0x88,0xa6,
-0x81,0x01,0xa6,0x03,0x27,0x4d,0x33,0xf2,0xcd,0x41,0xa6,0x81,0x01,0xa6,0x03,0x27,
-0x4d,0x1e,0xf2,0xcd,0xae,0x00,0x5f,0x72,0x50,0x20,0x20,0x35,0x52,0x20,0x07,0x35,
-0x81,0x4d,0xd6,0xf1,0xcd,0x88,0xa6,0x50,0x20,0x20,0x35,0x53,0x20,0xc7,0xde,0x20,
-0x50,0x20,0x12,0x72,0xe2,0x26,0x08,0xad,0x05,0x7b,0x63,0xdf,0xcd,0x05,0xa6,0xed,
-0x26,0x13,0xad,0x02,0x7b,0xf3,0x26,0x4d,0xd6,0xf1,0xcd,0x88,0xa6,0x81,0x85,0x85,
-0x01,0xa6,0x05,0x27,0x4d,0x33,0xf2,0xcd,0x01,0x7b,0x08,0x26,0x4d,0x1e,0xf2,0xcd,
-0xae,0x00,0x5f,0x72,0x50,0x20,0x20,0x35,0x52,0x20,0x07,0x35,0x89,0x88,0x81,0x4d,
-0xd6,0xf1,0xcd,0x88,0xa6,0x6f,0xf2,0xcc,0x4f,0x63,0xdf,0xcd,0x05,0xa6,0x9d,0x25,
-0x06,0xe1,0x72,0x01,0x7b,0x4e,0x01,0xd7,0x53,0x20,0xc6,0x01,0x6b,0x08,0x20,0x11,
-0xe7,0x53,0x20,0xc6,0x01,0x6b,0x09,0x25,0x4c,0x9f,0x01,0xee,0x72,0x09,0xa1,0x06,
-0x7b,0x50,0x20,0x22,0x35,0x04,0x26,0xa8,0xb1,0xa8,0xbf,0x90,0x0b,0x26,0xa7,0xb3,
-0xa7,0x3f,0x01,0xe6,0x72,0x4a,0x5a,0x01,0x26,0x4d,0x5f,0x06,0x7b,0x50,0x20,0x15,
-0x72,0x04,0x26,0xa8,0xb1,0xa8,0xbf,0x90,0x0b,0x26,0xa7,0xb3,0xa7,0x3f,0x01,0xe6,
-0x72,0x5a,0x01,0x24,0x02,0xa0,0x5f,0x1a,0x25,0x02,0xa1,0x06,0x7b,0xba,0x26,0x6a,
-0xad,0x50,0x20,0x15,0x72,0x04,0x26,0x4a,0x06,0x7b,0xc7,0x26,0x4d,0x90,0xad,0x01,
-0xaa,0x02,0x7b,0xd0,0x26,0x4d,0x84,0xad,0x63,0xdf,0xcd,0x05,0xa6,0xda,0x26,0x1b,
-0xf3,0xcd,0x50,0x20,0x20,0x35,0x53,0x20,0xc7,0x03,0x7b,0x02,0x20,0x52,0x80,0xae,
-0x03,0x7b,0x07,0x26,0x80,0xa1,0x06,0x7b,0xf5,0x26,0x1b,0xf3,0xcd,0x81,0x85,0x85,
-0x85,0x01,0xa6,0x06,0x27,0x4d,0xc9,0xad,0x02,0x7b,0x07,0x26,0x4d,0xbb,0xad,0xae,
-0x00,0x5f,0x72,0x01,0x6b,0x4f,0x50,0x20,0x20,0x35,0x52,0x20,0x07,0x35,0x88,0x89,
-0x88,0x81,0x4f,0x50,0x20,0x24,0x35,0x63,0xdf,0xcd,0x05,0xa6,0x81,0x01,0xa6,0x03,
-0x27,0x4d,0xb7,0xad,0x82,0xa6,0x50,0x20,0x21,0x35,0x53,0x20,0xc7,0x81,0x4f,0x63,
-0xdf,0xcd,0x05,0xa6,0x81,0x01,0xa6,0x03,0x27,0x4d,0xcf,0xad,0x81,0xa6,0x50,0x20,
-0x29,0x35,0x81,0x85,0x4f,0xae,0x00,0x5f,0x72,0x81,0x85,0x01,0xa6,0xae,0x00,0x5f,
-0x72,0x50,0x20,0x22,0x35,0x0c,0xae,0x00,0x0d,0x72,0x05,0x26,0x01,0xe1,0x72,0x01,
-0xe4,0x72,0xfa,0x27,0xae,0x00,0xc6,0x8f,0x01,0x20,0x88,0x81,0x85,0x4f,0x81,0x85,
-0x01,0xa6,0x50,0x20,0x05,0x35,0x08,0x27,0x01,0xe1,0x72,0x01,0xe4,0x72,0x51,0x20,
-0xc6,0xfa,0x51,0x20,0x0f,0x72,0x9d,0x01,0x20,0x88,0xfe,0xce,0x80,0x3d,0xe1,0xb7,
-0x80,0x3d,0xab,0x93,0x80,0x3d,0x25,0x6e,0x9f,0x3d,0x81,0x5a,0xc0,0xcd,0x11,0xb7,
-0x95,0xf0,0xcd,0xda,0x20,0x3a,0xef,0xcd,0x08,0x20,0x3a,0xef,0xcd,0x05,0x26,0x04,
-0xa1,0x12,0xb6,0x06,0x27,0x02,0xa1,0x12,0xb6,0x11,0x26,0x02,0xa1,0x11,0xb6,0x21,
-0x20,0x15,0xef,0xcd,0x65,0xc0,0xcc,0x11,0xb7,0x00,0xee,0xcd,0x03,0x20,0xfa,0xed,
-0xcd,0x08,0x20,0x74,0xec,0xcd,0x0d,0x20,0xe4,0xeb,0xcd,0x12,0x20,0x60,0xe9,0xcd,
-0x40,0x20,0xcb,0xe8,0xcd,0x1c,0x20,0xec,0xe8,0xcd,0x21,0x20,0xf3,0xe7,0xcd,0x26,
-0x20,0x9d,0xe7,0xcd,0x2b,0x20,0x6d,0xe7,0xcd,0x30,0x20,0x2a,0xe7,0xcd,0x35,0x20,
-0x25,0xe6,0xcd,0x81,0x88,0x2f,0xf1,0xd6,0x88,0x30,0xf1,0xd6,0x58,0x97,0x73,0x24,
-0x0f,0xa1,0x4a,0xbd,0xf1,0xa1,0xf1,0x9c,0xf1,0x94,0xf1,0x8f,0xf1,0x8a,0xf1,0x85,
-0xf1,0x80,0xf1,0x7b,0xf1,0x76,0xf1,0x71,0xf1,0x6c,0xf1,0x67,0xf1,0x62,0xf1,0x5d,
-0xf1,0x81,0x1f,0xfc,0xcd,0xa4,0xb7,0x00,0xa9,0x41,0x01,0xab,0x81,0x85,0x85,0x85,
-0x85,0x01,0xa6,0x02,0x20,0x4f,0x12,0x00,0xc0,0x84,0x55,0x63,0xdf,0xcd,0x0a,0xa6,
-0x9a,0x78,0x84,0xc7,0x01,0x7b,0x79,0x84,0xc7,0x02,0x7b,0x7a,0x84,0xc7,0x03,0x7b,
-0x7b,0x84,0xc7,0x04,0x7b,0xe8,0xfa,0xcd,0x78,0xae,0xa4,0x00,0x84,0x35,0xa0,0x18,
-0x34,0xad,0x5b,0x9b,0x01,0x6b,0x78,0x84,0xc6,0x02,0x6b,0x79,0x84,0xc6,0x03,0x6b,
-0x7a,0x84,0xc6,0x04,0x6b,0x7b,0x84,0xc6,0x9a,0xac,0xe5,0xcd,0x01,0xa6,0xac,0xe5,
-0xcd,0x4f,0x9b,0x50,0x26,0x94,0xfa,0xcd,0xa1,0x3f,0xa2,0x3f,0xa3,0x3f,0x62,0xad,
-0x5b,0x01,0x6b,0xc0,0x84,0xc6,0x02,0x6b,0xc1,0x84,0xc6,0x03,0x6b,0xc2,0x84,0xc6,
-0x04,0x6b,0xc3,0x84,0xc6,0x9a,0xb4,0x84,0x00,0x35,0xb5,0x84,0x00,0x35,0xb6,0x84,
-0x00,0x35,0xb7,0x84,0x02,0x35,0x9b,0x88,0x88,0x88,0x88,0x81,0xe8,0xfa,0xcd,0xb4,
-0xae,0xa4,0x00,0x84,0x35,0x81,0x1f,0xfc,0xcd,0xa4,0xb7,0x00,0xa9,0x41,0x01,0xab,
-0x81,0x85,0x85,0x85,0x85,0x85,0x05,0x7b,0x05,0x6b,0x01,0xa6,0xd4,0x20,0x12,0x00,
-0x4e,0x01,0x55,0x07,0x20,0x15,0x00,0xde,0x35,0x14,0x00,0xc0,0x35,0x13,0x00,0xad,
-0x35,0x12,0x00,0xde,0x35,0x65,0xc0,0xcd,0x15,0x27,0x85,0x4d,0x4f,0xf2,0xcd,0x13,
-0xbe,0x14,0xb6,0x01,0x4b,0x2b,0x20,0x4f,0x84,0x22,0xf3,0xcd,0x13,0xbe,0x14,0xb6,
-0x15,0x00,0x3b,0x1b,0x20,0x3b,0x27,0x4d,0x70,0xf3,0xcd,0x43,0x20,0x9a,0x59,0xad,
-0xa2,0x18,0x52,0xad,0x5b,0x9b,0x01,0x6b,0xb4,0x84,0xc6,0x02,0x6b,0xb5,0x84,0xc6,
-0x03,0x6b,0xb6,0x84,0xc6,0x04,0x6b,0xb7,0x84,0xc6,0x63,0xdf,0xcd,0xfa,0xa6,0x9a,
-0x18,0x84,0x00,0x35,0x19,0x84,0x03,0x35,0x1a,0x84,0x83,0x35,0x1b,0x84,0x00,0x35,
-0x14,0x45,0x00,0x35,0x15,0x45,0x00,0x35,0x16,0x45,0x00,0x35,0x17,0x45,0x02,0x35,
-0x8b,0xf0,0xcd,0xa2,0x16,0xa3,0x12,0x80,0xf0,0xcd,0x5b,0x9b,0x01,0x6b,0xb4,0x84,
-0xc6,0x02,0x6b,0xb5,0x84,0xc6,0x03,0x6b,0xb6,0x84,0xc6,0x04,0x6b,0xb7,0x84,0xc6,
-0x74,0xf0,0xcc,0x4b,0xf0,0xcc,0x03,0x26,0x4a,0x76,0x27,0x4a,0x71,0x27,0x4a,0x0f,
-0x27,0x4a,0x12,0xb6,0x74,0xf0,0xcc,0x03,0x27,0x02,0xa1,0x11,0xb6,0x78,0xf0,0xcc,
-0x76,0x01,0xc7,0x4c,0x9a,0xe8,0xfa,0xcd,0x18,0xae,0xa4,0x00,0x84,0x35,0xa0,0xb7,
-0xa1,0xb7,0xa2,0xb7,0x4f,0xa3,0xb7,0x12,0xb6,0x9b,0x78,0xf0,0xcc,0x03,0x27,0x03,
-0xa1,0x05,0x01,0xc6,0x78,0x01,0x5f,0x72,0x79,0x01,0xc7,0x02,0xa6,0x02,0x20,0x0a,
-0xa6,0x0d,0x20,0x05,0x6b,0x01,0xa6,0x7a,0x01,0x5f,0x72,0x05,0x01,0x5f,0x72,0x12,
-0x27,0x4a,0x11,0x27,0x4a,0x18,0x27,0x4a,0x7a,0x01,0xc7,0x7f,0xa4,0x12,0xb6,0x05,
-0x01,0x03,0x35,0x56,0x26,0x4a,0x11,0xb6,0x9a,0x18,0x84,0x00,0x35,0x19,0x84,0x00,
-0x35,0x1a,0x84,0x00,0x35,0x1b,0x84,0x00,0x35,0x9b,0x05,0x01,0x5f,0x72,0x05,0x6b,
-0x4f,0x88,0x88,0x88,0x88,0x88,0x81,0x4f,0x81,0x01,0xa6,0x14,0x00,0xde,0x35,0x13,
-0x00,0xc0,0x35,0x12,0x00,0xad,0x35,0x11,0x00,0xde,0x35,0x65,0xc0,0xcd,0x16,0x27,
-0x85,0x4d,0x4f,0xf2,0xcd,0x11,0xbe,0x12,0xb6,0x80,0x4b,0x81,0x9a,0xcb,0xfa,0xcd,
-0xa4,0xb7,0x46,0xa9,0x41,0x81,0xa4,0xb7,0x00,0xa9,0x41,0x08,0xab,0x81,0x84,0x8b,
-0x41,0x00,0xa9,0x41,0x0b,0xab,0x5b,0x0c,0x6b,0x4f,0x9a,0xe8,0xfa,0xcd,0x30,0xae,
-0xa4,0x00,0x42,0x35,0xd9,0xfb,0xcd,0xa4,0xb7,0x00,0xa9,0x41,0x01,0xab,0x5b,0x73,
-0xfa,0xcd,0xfa,0x26,0x5a,0x90,0x59,0x48,0x06,0x27,0x06,0xe6,0x72,0x5f,0x03,0xa6,
-0x9b,0x01,0x6b,0x30,0x42,0xc6,0x02,0x6b,0x31,0x42,0xc6,0x03,0x6b,0x32,0x42,0xc6,
-0x04,0x6b,0x33,0x42,0xc6,0x06,0x6b,0x04,0xab,0x06,0x7b,0xa0,0x24,0x07,0xe1,0x72,
-0x13,0xb6,0x07,0x6b,0x04,0xab,0x07,0x7b,0x63,0xad,0x04,0xab,0x5c,0x01,0x24,0x07,
-0xeb,0x72,0x52,0x08,0xae,0x06,0x7b,0x1f,0xfc,0xcd,0x6d,0xad,0x5b,0x9b,0xce,0x25,
-0x04,0xa1,0x0c,0x6b,0x4c,0x0c,0x7b,0xa4,0xc7,0x92,0x14,0xe6,0x90,0xa5,0xbf,0x05,
-0x6b,0x4c,0x9f,0x90,0x05,0xe6,0x72,0xa4,0x3c,0x02,0x24,0x97,0xa5,0xbb,0x0c,0xe0,
-0x72,0x03,0xa6,0xa5,0xbf,0x03,0xef,0xcd,0x5b,0x22,0x25,0x05,0xe1,0x72,0x13,0xb6,
-0x0c,0x6b,0x08,0x6b,0x09,0x6b,0x0a,0x6b,0x0b,0x6b,0x4f,0x57,0x20,0x05,0x6b,0x4f,
-0x0b,0xef,0xcd,0x00,0xab,0x52,0x08,0xae,0x06,0x7b,0x1f,0xfc,0xcd,0x03,0xef,0xcd,
-0x5b,0x9b,0x08,0x6b,0x4f,0x09,0x6b,0x13,0xb6,0x0a,0x6b,0x12,0xb6,0x0b,0x6b,0x11,
-0xb6,0x06,0x6b,0x10,0xa6,0x02,0x20,0x0c,0xa6,0x06,0x20,0x08,0xa6,0x0a,0x20,0x04,
-0xa6,0xf7,0xee,0xcc,0x01,0xa6,0x09,0x27,0x4a,0x08,0x27,0x4a,0x17,0x27,0x4a,0x1c,
-0x27,0x4a,0x19,0x27,0x81,0xa0,0x11,0xb6,0x8b,0x41,0x00,0xa2,0x41,0x0c,0xa0,0x5b,
-0x81,0x4f,0x30,0x01,0x01,0x35,0x81,0xe8,0xfa,0xcd,0xb4,0xae,0xa4,0x00,0x84,0x35,
-0x81,0x10,0x4d,0x00,0x35,0x11,0x4d,0x00,0x35,0x12,0x4d,0x00,0x35,0x81,0x1f,0xfc,
-0xcd,0xa4,0xb7,0x00,0xa9,0x41,0x01,0xab,0x81,0x85,0x85,0x85,0x85,0x4f,0x9a,0x31,
-0x01,0x5f,0x72,0x04,0x20,0x31,0x01,0x01,0x35,0x06,0x26,0x91,0xa1,0x11,0xb6,0x06,
-0x27,0x27,0xa1,0x11,0xb6,0x46,0x01,0x12,0x00,0x55,0x47,0x01,0x13,0x00,0x55,0x48,
-0x01,0x14,0x00,0x55,0x49,0x01,0x15,0x00,0x55,0x14,0x48,0x12,0x00,0x55,0x15,0x48,
-0x13,0x00,0x55,0x16,0x48,0x14,0x00,0x55,0x17,0x48,0x15,0x00,0x55,0x42,0x01,0x16,
-0x00,0x55,0x43,0x01,0x17,0x00,0x55,0x44,0x01,0x18,0x00,0x55,0x45,0x01,0x19,0x00,
-0x55,0x10,0x48,0x16,0x00,0x55,0x11,0x48,0x17,0x00,0x55,0x12,0x48,0x18,0x00,0x55,
-0x13,0x48,0x19,0x00,0x55,0x50,0x26,0x28,0xa1,0x11,0xb6,0x56,0x20,0xcb,0xfa,0xcd,
-0xa4,0xb7,0x48,0xa9,0x41,0x44,0xab,0x52,0x08,0xae,0x11,0xb6,0xa7,0xfa,0xcd,0x12,
-0xae,0xcb,0xfa,0xcd,0xa4,0xb7,0x48,0xa9,0x41,0x40,0xab,0x52,0x08,0xae,0x11,0xb6,
-0xa7,0xfa,0xcd,0x16,0xae,0x2a,0x24,0x28,0xa1,0x11,0xb6,0x11,0xb6,0xbb,0xed,0xcc,
-0xe3,0xed,0xcd,0x13,0x4d,0x02,0x35,0xe3,0xed,0xcd,0x13,0x4d,0x42,0x35,0x0c,0x4d,
-0x1e,0x00,0x55,0x0d,0x4d,0x1f,0x00,0x55,0x0e,0x4d,0x20,0x00,0x55,0x0f,0x4d,0x21,
-0x00,0x55,0x08,0x4d,0x1a,0x00,0x55,0x09,0x4d,0x1b,0x00,0x55,0x0a,0x4d,0x1c,0x00,
-0x55,0x0b,0x4d,0x1d,0x00,0x55,0x04,0x4d,0x16,0x00,0x55,0x05,0x4d,0x17,0x00,0x55,
-0x06,0x4d,0x18,0x00,0x55,0x07,0x4d,0x19,0x00,0x55,0x00,0x4d,0x12,0x00,0x55,0x01,
-0x4d,0x13,0x00,0x55,0x02,0x4d,0x14,0x00,0x55,0x03,0x4d,0x15,0x00,0x55,0xf0,0xed,
-0xcd,0xa1,0x1a,0xd8,0xed,0xcd,0x5b,0x6a,0x24,0x92,0xa1,0x11,0xb6,0x70,0x25,0x80,
-0xa1,0x11,0xb6,0xf0,0xed,0xcd,0xa3,0xb7,0x60,0xaa,0xa3,0xb6,0xd8,0xed,0xcd,0x5b,
-0x01,0x6b,0xb4,0x84,0xc6,0x02,0x6b,0xb5,0x84,0xc6,0x03,0x6b,0xb6,0x84,0xc6,0x04,
-0x6b,0xb7,0x84,0xc6,0xe8,0xfa,0xcd,0x04,0xae,0xa4,0x00,0x48,0x35,0xa3,0x18,0xd8,
-0xed,0xcd,0x5b,0x01,0x6b,0x04,0x48,0xc6,0x02,0x6b,0x05,0x48,0xc6,0x03,0x6b,0x06,
-0x48,0xc6,0x04,0x6b,0x07,0x48,0xc6,0x9b,0x88,0x88,0x88,0x88,0x81,0x48,0x42,0x00,
-0x35,0x49,0x42,0x00,0x35,0x4a,0x42,0x00,0x35,0x81,0x85,0x85,0x85,0x85,0x4f,0x9a,
-0xf3,0xe2,0xcd,0x07,0x01,0x01,0x35,0xd8,0xde,0xcd,0x03,0x27,0xc3,0x00,0xc6,0x16,
-0xad,0x4b,0x42,0x01,0x35,0x04,0x20,0x4b,0x42,0x05,0x35,0x06,0x26,0x02,0xa1,0x11,
-0xb6,0x89,0xe1,0xcd,0xe8,0xfa,0xcd,0xb4,0xae,0xa4,0x00,0x84,0x35,0xa2,0x16,0x1f,
-0xfc,0xcd,0xa4,0xb7,0x00,0xa9,0x41,0x01,0xab,0x5b,0x01,0x6b,0xb4,0x84,0xc6,0x02,
-0x6b,0xb5,0x84,0xc6,0x03,0x6b,0xb6,0x84,0xc6,0x04,0x6b,0xb7,0x84,0xc6,0xb7,0xd4,
-0xcd,0x51,0x20,0x5a,0xad,0x4b,0x42,0x01,0x35,0x04,0x20,0x4b,0x42,0x05,0x35,0x06,
-0x26,0x02,0xa1,0x11,0xb6,0x14,0x26,0x4a,0x07,0x01,0xc6,0x6b,0x20,0x22,0xe2,0xcd,
-0x29,0xe1,0xcd,0x08,0x26,0x11,0x3d,0x9b,0x88,0x88,0x88,0x88,0x81,0xe8,0xfa,0xcd,
-0x78,0xae,0xa4,0x00,0x84,0x35,0x81,0x18,0x80,0x00,0x35,0x19,0x80,0x00,0x35,0x1a,
-0x80,0x00,0x35,0x81,0x08,0x80,0x00,0x35,0x09,0x80,0x00,0x35,0x0a,0x80,0x00,0x35,
-0x81,0x1f,0xfc,0xcd,0xa4,0xb7,0x00,0xa9,0x41,0x03,0xab,0x81,0x04,0x80,0x00,0x35,
-0x05,0x80,0x00,0x35,0x06,0x80,0x00,0x35,0x81,0x85,0x85,0x85,0x85,0x85,0x85,0x4f,
-0x9a,0x22,0xe2,0xcd,0x06,0x01,0x5f,0x72,0xbc,0x84,0x00,0x35,0xbd,0x84,0x00,0x35,
-0xbe,0x84,0x18,0x35,0xbf,0x84,0x00,0x35,0x45,0xad,0x1b,0x80,0x80,0x35,0x14,0x80,
-0x00,0x35,0x15,0x80,0x00,0x35,0x16,0x80,0x00,0x35,0x17,0x80,0x00,0x35,0x4e,0xad,
-0x0b,0x80,0x00,0x35,0x3c,0xad,0x07,0x80,0x00,0x35,0x00,0x80,0x00,0x35,0x01,0x80,
-0x00,0x35,0x02,0x80,0x00,0x35,0x03,0x80,0x00,0x35,0xda,0xeb,0xcd,0xa3,0xb7,0xf8,
-0xa4,0xa3,0xb6,0x68,0xad,0x5b,0x03,0x6b,0x78,0x84,0xc6,0x04,0x6b,0x79,0x84,0xc6,
-0x05,0x6b,0x7a,0x84,0xc6,0x06,0x6b,0x7b,0x84,0xc6,0x69,0x20,0xf3,0xe2,0xcd,0x06,
-0x01,0x01,0x35,0x90,0xd3,0xcd,0xbc,0x84,0x00,0x35,0xbd,0x84,0x00,0x35,0xbe,0x84,
-0x1b,0x35,0xbf,0x84,0x40,0x35,0x04,0x20,0xbf,0x84,0x41,0x35,0x06,0x26,0x14,0x3d,
-0xcd,0xeb,0xcd,0x1b,0x80,0x81,0x35,0xe8,0xfa,0xcd,0x14,0xae,0xa4,0x00,0x80,0x35,
-0x73,0xfa,0xcd,0x52,0x80,0xae,0xc0,0xeb,0xcd,0x0b,0x80,0x20,0x35,0x04,0x20,0x0b,
-0x80,0x60,0x35,0x06,0x26,0x6a,0x01,0xc7,0x16,0xb6,0x6b,0x01,0x60,0x20,0x55,0x6c,
-0x01,0x61,0x20,0x55,0x6d,0x01,0x62,0x20,0x55,0x6e,0x01,0x63,0x20,0x55,0x68,0x20,
-0x21,0x35,0x64,0x20,0x6b,0x01,0x55,0x65,0x20,0x6c,0x01,0x55,0x66,0x20,0x6d,0x01,
-0x55,0x67,0x20,0x6e,0x01,0x55,0x9d,0x9d,0x68,0x20,0x27,0x35,0x68,0x20,0x52,0x35,
-0x64,0x20,0x00,0x35,0x65,0x20,0x0f,0x35,0x66,0x20,0x42,0x35,0x67,0x20,0x40,0x35,
-0x68,0x20,0x22,0x35,0x60,0x20,0x01,0x01,0x55,0x61,0x20,0x02,0x01,0x55,0x62,0x20,
-0x03,0x01,0x55,0x63,0x20,0x04,0x01,0x55,0x6b,0x01,0xca,0xf1,0x55,0x6c,0x01,0xcb,
-0xf1,0x55,0x6d,0x01,0xcc,0xf1,0x55,0x6e,0x01,0xcd,0xf1,0x55,0x6f,0x01,0xc7,0x70,
-0x01,0x21,0x35,0x71,0x01,0xe6,0x35,0x72,0x01,0xf0,0x35,0x23,0x20,0x6b,0x01,0xce,
-0xf1,0x55,0x6c,0x01,0xcf,0xf1,0x55,0x6d,0x01,0xd0,0xf1,0x55,0x6e,0x01,0xd1,0xf1,
-0x55,0x6f,0x01,0xc7,0x70,0x01,0x21,0x35,0x71,0x01,0xf0,0x35,0x72,0x01,0x7c,0x35,
-0x48,0x20,0x6b,0x01,0xd2,0xf1,0x55,0x6c,0x01,0xd3,0xf1,0x55,0x6d,0x01,0xd4,0xf1,
-0x55,0x6e,0x01,0xd5,0xf1,0x55,0x6f,0x01,0xc7,0x70,0x01,0x21,0x35,0x71,0x01,0xf6,
-0x35,0x72,0x01,0x94,0x35,0x6d,0x20,0xa8,0xeb,0xcd,0x07,0x80,0xe0,0x35,0x6b,0x01,
-0xc6,0xf1,0x55,0x6c,0x01,0xc7,0xf1,0x55,0x6d,0x01,0xc8,0xf1,0x55,0x6e,0x01,0xc9,
-0xf1,0x55,0x6f,0x01,0x5f,0x72,0x70,0x01,0x2a,0x35,0x71,0x01,0x09,0x35,0x72,0x01,
-0x8b,0x35,0x77,0x27,0x4a,0x55,0x27,0x4a,0x33,0x27,0x4a,0x12,0xb6,0xa8,0xeb,0xcd,
-0x07,0x80,0xc0,0x35,0xe8,0xfa,0xcd,0x5f,0xa4,0x00,0x80,0x35,0x73,0xfa,0xcd,0x06,
-0xaa,0x41,0x01,0xea,0x72,0x41,0x02,0xea,0x72,0x5f,0x28,0xaa,0xc0,0xa4,0x52,0x40,
-0xae,0x12,0xb6,0x01,0xef,0x72,0x02,0x6b,0x52,0x10,0xae,0x15,0xb6,0xda,0xeb,0xcd,
-0xa3,0x10,0xa3,0x12,0xa3,0x14,0xb5,0xeb,0xcd,0x5b,0x03,0x6b,0x78,0x84,0xc6,0x04,
-0x6b,0x79,0x84,0xc6,0x05,0x6b,0x7a,0x84,0xc6,0x06,0x6b,0x7b,0x84,0xc6,0xe8,0xfa,
-0xcd,0xb4,0xae,0xa4,0x00,0x84,0x35,0xa2,0x16,0xb5,0xeb,0xcd,0x5b,0x03,0x6b,0xb4,
-0x84,0xc6,0x04,0x6b,0xb5,0x84,0xc6,0x05,0x6b,0xb6,0x84,0xc6,0x06,0x6b,0xb7,0x84,
-0xc6,0x36,0xeb,0xcc,0x03,0x27,0x4a,0x13,0xb6,0x9b,0x88,0x88,0x88,0x88,0x88,0x88,
-0x81,0x85,0x4f,0x1c,0x01,0x5a,0x72,0x9a,0x0c,0x8c,0x00,0x35,0x0d,0x8c,0x00,0x35,
-0x0e,0x8c,0x00,0x35,0x0f,0x8c,0x01,0x35,0x04,0x20,0x0f,0x8c,0x03,0x35,0x06,0x26,
-0x4a,0x1c,0x01,0xc6,0xe8,0xfa,0xcd,0x10,0xae,0xa4,0x00,0x8c,0x35,0xa0,0xb7,0xa1,
-0xb7,0xa2,0xb7,0x4f,0xa3,0x00,0x1d,0x01,0x55,0xe8,0xfa,0xcd,0x1c,0xae,0xa4,0x00,
-0x8c,0x35,0x73,0xfa,0xcd,0x5f,0x0f,0xa4,0x4e,0x1d,0x01,0xc6,0x9b,0x06,0x20,0xc7,
-0xfa,0xa4,0x06,0x20,0xc6,0x52,0x27,0x1c,0x01,0xc6,0xef,0x25,0x1c,0x01,0xc1,0x01,
-0x6b,0x4c,0x9f,0x1d,0x01,0xd7,0x12,0xe6,0x01,0xee,0x72,0x0a,0x20,0x4f,0x1c,0x01,
-0xc7,0x11,0xb6,0x88,0x81,0x85,0x4f,0x09,0x01,0x5f,0x72,0xef,0x25,0x0a,0x01,0xc1,
-0x01,0x6b,0x4c,0x9f,0x12,0xe7,0x0b,0x01,0xd6,0x01,0xee,0x72,0x0a,0x20,0x4f,0x11,
-0x00,0x0a,0x01,0x55,0x88,0x81,0x4f,0x9a,0xa8,0x84,0x29,0x00,0x55,0xa9,0x84,0x2a,
-0x00,0x55,0xaa,0x84,0x2b,0x00,0x55,0xab,0x84,0x2c,0x00,0x55,0xe8,0xfa,0xcd,0x48,
-0xae,0xa4,0x00,0x84,0x35,0x73,0xfa,0xcd,0x27,0xbe,0x28,0xb6,0xe8,0xfa,0xcd,0x44,
-0xae,0xa4,0x00,0x84,0x35,0x73,0xfa,0xcd,0x25,0xbe,0x26,0xb6,0xe8,0xfa,0xcd,0x40,
-0xae,0xa4,0x00,0x84,0x35,0x73,0xfa,0xcd,0x23,0xbe,0x24,0xb6,0xe8,0xfa,0xcd,0x3c,
-0xae,0xa4,0x00,0x84,0x35,0x73,0xfa,0xcd,0x21,0xbe,0x22,0xb6,0xe8,0xfa,0xcd,0x38,
-0xae,0xa4,0x00,0x84,0x35,0x73,0xfa,0xcd,0x1f,0xbe,0x20,0xb6,0xe8,0xfa,0xcd,0x34,
-0xae,0xa4,0x00,0x84,0x35,0x73,0xfa,0xcd,0x1d,0xbe,0x1e,0xb6,0xe8,0xfa,0xcd,0x30,
-0xae,0xa4,0x00,0x84,0x35,0x73,0xfa,0xcd,0x1b,0xbe,0x1c,0xb6,0xe8,0xfa,0xcd,0x2c,
-0xae,0xa4,0x00,0x84,0x35,0x73,0xfa,0xcd,0x19,0xbe,0x1a,0xb6,0xe8,0xfa,0xcd,0x28,
-0xae,0xa4,0x00,0x84,0x35,0x73,0xfa,0xcd,0x17,0xbe,0x18,0xb6,0xe8,0xfa,0xcd,0x24,
-0xae,0xa4,0x00,0x84,0x35,0x73,0xfa,0xcd,0x15,0xbe,0x16,0xb6,0xe8,0xfa,0xcd,0x20,
-0xae,0xa4,0x00,0x84,0x35,0x73,0xfa,0xcd,0x13,0xbe,0x14,0xb6,0xe8,0xfa,0xcd,0x1c,
-0xae,0xa4,0x00,0x84,0x35,0x73,0xfa,0xcd,0x11,0xbe,0x12,0xb6,0x9b,0x81,0x4f,0x77,
-0x01,0x01,0x35,0xda,0x00,0xcf,0x1f,0xbe,0xdb,0x00,0xc7,0x20,0xb6,0xd8,0x00,0xcf,
-0x1d,0xbe,0xd9,0x00,0xc7,0x1e,0xb6,0xd6,0x00,0xcf,0x1b,0xbe,0xd7,0x00,0xc7,0x1c,
-0xb6,0xd4,0x00,0xcf,0x19,0xbe,0xd5,0x00,0xc7,0x1a,0xb6,0xd2,0x00,0xcf,0x17,0xbe,
-0xd3,0x00,0xc7,0x18,0xb6,0xd0,0x00,0xcf,0x15,0xbe,0xd1,0x00,0xc7,0x16,0xb6,0xce,
-0x00,0xcf,0x13,0xbe,0xcf,0x00,0xc7,0x14,0xb6,0xcc,0x00,0xcf,0x11,0xbe,0xcd,0x00,
-0xc7,0x12,0xb6,0x81,0x4f,0x9a,0xd3,0xcf,0xcd,0xf1,0xd0,0xcd,0x84,0x84,0x84,0x84,
-0x84,0x84,0x84,0x84,0x31,0xd5,0xcd,0x01,0x01,0x3b,0x02,0x01,0x3b,0x03,0x01,0x3b,
-0x04,0x01,0x3b,0xf3,0x00,0x3b,0xf4,0x00,0x3b,0xf5,0x00,0x3b,0xf6,0x00,0x3b,0x1d,
-0xcd,0xcd,0x9b,0xc7,0x20,0x9a,0xd8,0xde,0xcd,0x9b,0xce,0x27,0x07,0x01,0xc6,0xc3,
-0x00,0x01,0x35,0x9a,0xa1,0xda,0xcd,0x9b,0xf1,0x25,0x01,0xe1,0x72,0x02,0x6b,0x4c,
-0x02,0x7b,0x9a,0x4f,0xdd,0xcd,0x9b,0x08,0x20,0x4f,0x01,0x6b,0x12,0xb6,0x02,0x20,
-0x04,0xa6,0x04,0x26,0x02,0xa1,0x11,0xb6,0x81,0x85,0x85,0x4f,0xc3,0x00,0x5f,0x72,
-0x08,0x27,0x17,0x3d,0x88,0x88,0x81,0x85,0x85,0x85,0x85,0x85,0x01,0x7b,0x76,0x01,
-0x01,0x35,0x9a,0xe8,0xfa,0xcd,0xb4,0xae,0xa4,0x00,0x84,0x35,0xa3,0x1f,0x1f,0xfc,
-0xcd,0xa4,0xb7,0x00,0xa9,0x41,0x02,0xab,0x5b,0xb4,0x84,0xc7,0x02,0x7b,0xb5,0x84,
-0xc7,0x03,0x7b,0xb6,0x84,0xc7,0x04,0x7b,0xb7,0x84,0xc7,0x05,0x7b,0xb4,0xfb,0xcd,
-0xa4,0xb7,0x00,0xa9,0x41,0x02,0xab,0x5b,0xa3,0x1e,0xa0,0x3f,0xa1,0x3f,0xa2,0xb7,
-0x03,0xa4,0xa2,0xb6,0xa3,0x3f,0x10,0xfb,0xcd,0x5f,0x90,0xa7,0x00,0x01,0x35,0x5f,
-0x12,0xb6,0x04,0x6b,0xfc,0xa4,0x04,0x7b,0x02,0x6b,0xb4,0x84,0xc6,0x03,0x6b,0xb5,
-0x84,0xc6,0x04,0x6b,0xb6,0x84,0xc6,0x05,0x6b,0xb7,0x84,0xc6,0x4e,0xe0,0xcd,0x1c,
-0xbe,0x20,0xa6,0x9b,0x01,0x01,0x22,0x00,0x55,0x02,0x01,0x23,0x00,0x55,0x03,0x01,
-0x24,0x00,0x55,0x04,0x01,0x25,0x00,0x55,0x14,0x27,0xb9,0xfa,0xcd,0x22,0xae,0x00,
-0x01,0xc7,0x12,0xb6,0xbf,0x00,0xc7,0x21,0xb6,0xc0,0x00,0xcf,0x1f,0xbe,0xc1,0x00,
-0xc7,0x20,0xb6,0xfa,0x00,0xcf,0x19,0xbe,0xfb,0x00,0xc7,0x1a,0xb6,0xfe,0x00,0xcf,
-0x17,0xbe,0xff,0x00,0xc7,0x18,0xb6,0xf8,0x00,0xcf,0x15,0xbe,0xf9,0x00,0xc7,0x16,
-0xb6,0xfc,0x00,0xcf,0x13,0xbe,0xfd,0x00,0xc7,0x14,0xb6,0x22,0xe7,0xcc,0x73,0x01,
-0xc7,0x4c,0x22,0xe7,0xcc,0x01,0x6b,0x01,0xa6,0x45,0x27,0x4a,0x11,0x27,0x4a,0x0d,
-0x27,0x4d,0xbf,0x00,0x5f,0x72,0xc1,0x00,0x5f,0x72,0xc0,0x00,0x5f,0x72,0x05,0x01,
-0xc7,0x11,0xb6,0x01,0x6b,0x4f,0x88,0x88,0x88,0x88,0x88,0x81,0x84,0x84,0x84,0x84,
-0x84,0xe9,0xe4,0xcd,0xaf,0x25,0x10,0xa1,0x04,0x6b,0x4c,0x04,0x7b,0xc2,0x25,0x08,
-0xa1,0x05,0x6b,0x4c,0x05,0x7b,0x31,0xe5,0xcd,0x03,0x27,0x5d,0x03,0x26,0x4d,0x41,
-0x01,0xe4,0x72,0x41,0x02,0xe4,0x72,0xfa,0x26,0x5a,0x90,0x59,0x48,0x06,0x27,0x05,
-0xe6,0x72,0x01,0xa6,0x01,0xef,0x72,0x02,0x6b,0x5f,0x03,0x7b,0x56,0xe5,0xcd,0x03,
-0x20,0x9d,0xad,0x04,0x26,0x05,0x7b,0x08,0x26,0x04,0x7b,0x05,0x6b,0x4f,0x03,0x6b,
-0x11,0xe6,0x04,0xee,0x72,0x04,0x6b,0x4f,0xf5,0x25,0x10,0xa1,0x04,0x6b,0x4c,0x04,
-0x7b,0x97,0xad,0x04,0x6b,0x4f,0x31,0xe5,0xcd,0xe9,0xe4,0xcd,0x13,0xe5,0xcd,0x88,
-0x88,0x88,0x88,0x88,0x81,0xb3,0x84,0x00,0x35,0xb0,0x84,0x00,0x35,0xb1,0x84,0x00,
-0x35,0x81,0xb0,0x84,0x00,0x35,0xb1,0x84,0x00,0x35,0xb2,0x84,0x00,0x35,0x0d,0xad,
-0xb2,0x84,0x03,0x35,0x13,0xad,0xb2,0x84,0x02,0x35,0x19,0xad,0xb2,0x84,0x00,0x35,
-0xb3,0x84,0x00,0x35,0x81,0xb0,0x84,0x00,0x35,0xb1,0x84,0x00,0x35,0xb2,0x84,0x00,
-0x35,0xb3,0x84,0x00,0x35,0x81,0x01,0xad,0xb0,0x84,0x00,0x35,0xb1,0x84,0x00,0x35,
-0xb2,0x84,0x01,0x35,0xb3,0x84,0x00,0x35,0x13,0xad,0x81,0x64,0xa6,0xb0,0x84,0x00,
-0x35,0xb1,0x84,0x00,0x35,0x63,0xdf,0xcc,0x03,0xad,0xb2,0x84,0x00,0x35,0xb3,0x84,
-0x00,0x35,0x63,0xdf,0xcd,0x10,0xad,0xb2,0x84,0x04,0x35,0xb3,0x84,0x00,0x35,0x81,
-0xad,0x84,0x00,0x35,0xae,0x84,0x00,0x35,0xaf,0x84,0x00,0x35,0x81,0xac,0x84,0x00,
-0x35,0x05,0xad,0x81,0xac,0x84,0x80,0x35,0x0c,0xad,0x07,0x27,0x4d,0x63,0xdf,0xcc,
-0x64,0xa6,0xb0,0x84,0x00,0x35,0xb1,0x84,0x00,0x35,0xb2,0x84,0x00,0x35,0xb3,0x84,
-0x00,0x35,0x63,0xdf,0xcd,0x0a,0xa6,0xb0,0x84,0x00,0x35,0xb1,0x84,0x00,0x35,0xb2,
-0x84,0x10,0x35,0xb3,0x84,0x00,0x35,0x81,0x84,0x84,0x84,0x84,0x75,0x01,0x01,0x35,
-0xe8,0xfa,0xcd,0x5f,0xa4,0x00,0x84,0x35,0xa0,0x1a,0x1f,0xfc,0xcd,0xa4,0xb7,0x00,
-0xa9,0x41,0x01,0xab,0x5b,0x01,0x6b,0x00,0x84,0xc6,0x02,0x6b,0x01,0x84,0xc6,0x03,
-0x6b,0x02,0x84,0xc6,0x04,0x6b,0x03,0x84,0xc6,0x88,0x88,0x88,0x88,0x81,0x84,0x84,
-0x84,0x84,0xe8,0xfa,0xcd,0x5f,0xa4,0x00,0x84,0x35,0xa0,0x1b,0x1f,0xfc,0xcd,0xa4,
-0xb7,0x00,0xa9,0x41,0x01,0xab,0x5b,0x01,0x6b,0x00,0x84,0xc6,0x02,0x6b,0x01,0x84,
-0xc6,0x03,0x6b,0x02,0x84,0xc6,0x04,0x6b,0x03,0x84,0xc6,0x88,0x88,0x88,0x88,0x81,
-0xe8,0xfa,0xcd,0x78,0xae,0xa4,0x00,0x84,0x35,0x81,0x1f,0xfc,0xcd,0xa4,0xb7,0x00,
-0xa9,0x41,0x01,0xab,0x81,0x84,0x84,0x84,0x84,0x10,0xad,0xa3,0x1d,0x09,0xad,0x5b,
-0x17,0xad,0xa3,0x1c,0x10,0xad,0x5b,0x01,0x6b,0x78,0x84,0xc6,0x02,0x6b,0x79,0x84,
-0xc6,0x03,0x6b,0x7a,0x84,0xc6,0x04,0x6b,0x7b,0x84,0xc6,0x88,0x88,0x88,0x88,0x81,
-0x07,0xfb,0xcd,0xc0,0x00,0xce,0xc1,0x00,0xc6,0x81,0x84,0x84,0x84,0x84,0xa0,0x84,
-0xc7,0x01,0x7b,0xa1,0x84,0xc7,0x02,0x7b,0xa2,0x84,0xc7,0x03,0x7b,0xa3,0x84,0xc7,
-0x04,0x7b,0x03,0x6b,0x80,0xaa,0x03,0x7b,0x04,0x6b,0x06,0xaa,0x04,0x7b,0x0c,0x20,
-0xb4,0xfb,0xcd,0xa4,0xb7,0x00,0xa9,0x41,0x01,0xab,0x5b,0xa2,0x1e,0x34,0xad,0x11,
-0x24,0x00,0xa2,0xc0,0x00,0xc6,0x06,0xa0,0xc1,0x00,0xc6,0x0c,0x27,0x06,0x01,0xc6,
-0x22,0x25,0x02,0xa1,0xbf,0x00,0xc6,0x29,0x26,0x4a,0x05,0x01,0xc6,0x03,0x6b,0x80,
-0xa4,0x03,0x7b,0x04,0x6b,0x4f,0x01,0x6b,0xa0,0x84,0xc6,0x02,0x6b,0xa1,0x84,0xc6,
-0x03,0x6b,0xa2,0x84,0xc6,0x04,0x6b,0xa3,0x84,0xc6,0x6c,0x25,0x02,0xa1,0xbf,0x00,
-0xc6,0x73,0x26,0x4a,0x05,0x01,0xc6,0x0d,0x27,0x4a,0x06,0x01,0xc6,0xe8,0xfa,0xcd,
-0x78,0xae,0xa4,0x00,0x84,0x35,0xa0,0x1c,0x1f,0xfc,0xcd,0xa4,0xb7,0x00,0xa9,0x41,
-0x01,0xab,0x5b,0x01,0x6b,0x78,0x84,0xc6,0x02,0x6b,0x79,0x84,0xc6,0x03,0x6b,0x7a,
-0x84,0xc6,0x04,0x6b,0x7b,0x84,0xc6,0x48,0x83,0x00,0x35,0x49,0x83,0x00,0x35,0x4a,
-0x83,0x00,0x35,0x4b,0x83,0x0f,0x35,0x10,0x26,0x4a,0x24,0x83,0x00,0x35,0x25,0x83,
-0x00,0x35,0x26,0x83,0x00,0x35,0x27,0x83,0x00,0x35,0x4d,0x27,0x05,0x01,0xc6,0xe8,
-0xfa,0xcd,0xa4,0xae,0xa4,0x00,0x84,0x35,0xa2,0x1e,0xa0,0x3f,0xa1,0x3f,0xa2,0x1f,
-0x37,0xe4,0xcd,0x14,0x26,0x03,0xa1,0x04,0x27,0x01,0xa1,0xbf,0x00,0xc6,0x1f,0x26,
-0x4a,0x05,0x01,0xc6,0xe8,0xfa,0xcd,0xa0,0xae,0xa4,0x00,0x84,0x35,0xa0,0x1f,0xa2,
-0x3f,0xa3,0x3f,0x85,0xfa,0xcd,0x10,0xa6,0x07,0xfb,0xcd,0x5c,0x01,0x24,0x02,0xab,
-0xed,0x00,0xce,0xee,0x00,0xc6,0x0b,0x20,0x78,0x01,0xce,0x79,0x01,0xc6,0x2a,0x26,
-0x4a,0x0b,0x27,0x02,0xa0,0x05,0x01,0xc6,0x7e,0x01,0x5f,0x72,0xb3,0xe3,0xcc,0x03,
-0x27,0x07,0x01,0xc6,0x08,0x27,0x06,0x01,0xc6,0x88,0x88,0x88,0x88,0x81,0x84,0x84,
-0x84,0x84,0xa0,0x84,0xc7,0x01,0x7b,0xa1,0x84,0xc7,0x02,0x7b,0xa2,0x84,0xc7,0x03,
-0x7b,0xa3,0x84,0xc7,0x04,0x7b,0xb4,0xfb,0xcd,0xa4,0xb7,0x00,0xa9,0x41,0x01,0xab,
-0x5b,0xa2,0x1e,0x07,0xfb,0xcd,0xc0,0x00,0xce,0xc1,0x00,0xc6,0x03,0x6b,0x80,0xa4,
-0x03,0x7b,0x04,0x6b,0x4f,0x1f,0x25,0x02,0xa1,0xbf,0x00,0xc6,0x26,0x26,0x4a,0x05,
-0x01,0xc6,0x03,0x6b,0x7f,0xa4,0x03,0x7b,0x01,0x6b,0xa0,0x84,0xc6,0x02,0x6b,0xa1,
-0x84,0xc6,0x03,0x6b,0xa2,0x84,0xc6,0x04,0x6b,0xa3,0x84,0xc6,0x5a,0x26,0x06,0x01,
-0xc6,0x5f,0x20,0x24,0x83,0x00,0x35,0x25,0x83,0x00,0x35,0x26,0x83,0x02,0x35,0x27,
-0x83,0x00,0x35,0xa0,0x84,0x00,0x35,0xa1,0x84,0x00,0x35,0xa2,0x84,0x00,0x35,0xa3,
-0x84,0x00,0x35,0xa4,0x84,0x00,0x35,0xa5,0x84,0x00,0x35,0xa6,0x84,0x00,0x35,0xa7,
-0x84,0x00,0x35,0xe8,0xfa,0xcd,0x78,0xae,0xa4,0x00,0x84,0x35,0xa0,0x1d,0x1f,0xfc,
-0xcd,0xa4,0xb7,0x00,0xa9,0x41,0x01,0xab,0x5b,0x01,0x6b,0x78,0x84,0xc6,0x02,0x6b,
-0x79,0x84,0xc6,0x03,0x6b,0x7a,0x84,0xc6,0x04,0x6b,0x7b,0x84,0xc6,0x7e,0x01,0xc7,
-0x5f,0x26,0x06,0x01,0xce,0x64,0x26,0x07,0x01,0xc6,0x88,0x88,0x88,0x88,0x81,0x1f,
-0xfc,0xcd,0xa4,0xb7,0x00,0xa9,0x41,0x01,0xab,0x81,0x84,0x84,0x84,0x84,0x00,0x40,
-0xc7,0x01,0x7b,0x01,0x40,0xc7,0x02,0x7b,0x02,0x40,0xc7,0x03,0x7b,0x03,0x40,0xc7,
-0x04,0x7b,0xe8,0xfa,0xcd,0x5f,0xa4,0x00,0x40,0x35,0xa0,0x1e,0x23,0xad,0x5b,0x04,
-0x6b,0x02,0xaa,0x04,0x7b,0x06,0x26,0x12,0x3d,0x04,0x6b,0x40,0xaa,0x04,0x7b,0x06,
-0x26,0xf2,0x00,0xc6,0x04,0x6b,0x10,0xaa,0x04,0x7b,0x06,0x26,0xf1,0x00,0xc6,0x01,
-0x6b,0x02,0x6b,0x03,0x6b,0x4f,0x04,0x6b,0x01,0xa6,0xe8,0xfa,0xcd,0xb4,0xae,0xa4,
-0x00,0x84,0x35,0xa3,0x18,0xa2,0x18,0x5e,0xad,0x5b,0x01,0x6b,0xb4,0x84,0xc6,0x02,
-0x6b,0xb5,0x84,0xc6,0x03,0x6b,0xb6,0x84,0xc6,0x04,0x6b,0xb7,0x84,0xc6,0x63,0xdf,
-0xcd,0xfa,0xa6,0x14,0x45,0x00,0x35,0x15,0x45,0x00,0x35,0x16,0x45,0x00,0x35,0x17,
-0x45,0x02,0x35,0x88,0x88,0x88,0x88,0x81,0x01,0x40,0x00,0x35,0x02,0x40,0x00,0x35,
-0x03,0x40,0x00,0x35,0x81,0x84,0x84,0x84,0x84,0x07,0x01,0x5f,0x72,0xe8,0xfa,0xcd,
-0xb4,0xae,0xa4,0x00,0x84,0x35,0xa2,0x19,0x1f,0xfc,0xcd,0xa4,0xb7,0x00,0xa9,0x41,
-0x01,0xab,0x5b,0x01,0x6b,0xb4,0x84,0xc6,0x02,0x6b,0xb5,0x84,0xc6,0x03,0x6b,0xb6,
-0x84,0xc6,0x04,0x6b,0xb7,0x84,0xc6,0x14,0x45,0x00,0x35,0x15,0x45,0x00,0x35,0x16,
-0x45,0x00,0x35,0x17,0x45,0x01,0x35,0x00,0x40,0x00,0x35,0x47,0xad,0x00,0x40,0x80,
-0x35,0x4d,0xad,0x88,0x88,0x88,0x88,0x81,0x00,0x88,0x00,0x35,0x01,0x88,0x00,0x35,
-0x02,0x88,0x00,0x35,0x81,0xa2,0x14,0xa3,0x14,0xa0,0x3f,0xa1,0x3f,0xa2,0xb7,0x01,
-0xa4,0xa2,0xb6,0xa3,0xb7,0xf8,0xa4,0xa3,0xb6,0x27,0xfa,0xcd,0x08,0xae,0x90,0x5f,
-0x26,0xb6,0x81,0x84,0x84,0x21,0xad,0x03,0x88,0x01,0x35,0x08,0x88,0x00,0x35,0x09,
-0x88,0x30,0x35,0x0a,0x88,0x00,0x35,0x0b,0x88,0x00,0x35,0xe8,0xfa,0xcd,0x0c,0xae,
-0xa4,0x00,0x88,0x35,0xa3,0x1e,0xa0,0xb7,0xa1,0xb7,0xa2,0xb7,0x4f,0xa3,0xb7,0x07,
-0xa4,0x01,0x7b,0x18,0x88,0x00,0x35,0x19,0x88,0x00,0x35,0x1a,0x88,0xff,0x35,0x1b,
-0x88,0xff,0x35,0x14,0x88,0x00,0x35,0x15,0x88,0x00,0x35,0x16,0x88,0xff,0x35,0x17,
-0x88,0xff,0x35,0x10,0x88,0x00,0x35,0x11,0x88,0x5f,0x35,0x12,0x88,0xff,0x35,0x13,
-0x88,0xff,0x35,0x1c,0xe1,0xcd,0x03,0x88,0x00,0x35,0xac,0x84,0x00,0x35,0xad,0x84,
-0x00,0x35,0xae,0x84,0x00,0x35,0xaf,0x84,0x20,0x35,0xe8,0xfa,0xcd,0x7c,0xae,0xa4,
-0x00,0x84,0x35,0xa0,0x14,0xa1,0x1a,0xa1,0x10,0xfe,0xe0,0xcd,0x09,0x20,0xa1,0x1a,
-0xa1,0x10,0xfe,0xe0,0xcd,0x12,0x20,0xa1,0x10,0xfe,0xe0,0xcd,0x19,0x20,0xfe,0xe0,
-0xcd,0x27,0x20,0x17,0x27,0x4a,0x11,0x27,0x4a,0x0d,0x27,0x4a,0x0b,0x27,0x4a,0x9f,
-0x89,0x88,0x81,0xac,0x84,0x00,0x35,0xad,0x84,0x00,0x35,0xae,0x84,0x00,0x35,0xaf,
-0x84,0x00,0x35,0x7c,0x84,0x00,0x35,0x7d,0x84,0x00,0x35,0x7e,0x84,0x00,0x35,0x7f,
-0x84,0x00,0x35,0x00,0x88,0x00,0x35,0x01,0x88,0x00,0x35,0x02,0x88,0x00,0x35,0x03,
-0x88,0x00,0x35,0x05,0x01,0x5f,0x72,0x73,0x01,0x5f,0x72,0x81,0x1f,0xfc,0xcd,0xa4,
-0xb7,0x00,0xa9,0x41,0x03,0xab,0xe8,0xfa,0xcc,0x5f,0xa4,0x00,0x84,0x35,0xa0,0x00,
-0x30,0x35,0x0c,0xad,0x5b,0xe8,0xfa,0xcd,0x5f,0xa4,0x00,0x84,0x35,0xa0,0x1a,0xa0,
-0x3f,0x1b,0xad,0x5b,0x81,0xa0,0x3f,0x1f,0xfc,0xcd,0xa4,0xb7,0x00,0xa9,0x41,0x03,
-0xab,0xe8,0xfa,0xcc,0x5f,0xa4,0x00,0x84,0x35,0xa0,0x18,0x0a,0xad,0x5b,0xe8,0xfa,
-0xcd,0x5f,0xa4,0x00,0x84,0x35,0x15,0xad,0x5b,0x81,0x85,0x90,0x85,0x90,0x01,0xee,
-0x72,0x02,0x7b,0x05,0x20,0x05,0xee,0x72,0x06,0x7b,0x07,0x24,0x05,0xe2,0x72,0x9f,
-0x06,0xe0,0x72,0x89,0x88,0x81,0x85,0x90,0x85,0x90,0x05,0xee,0x72,0x06,0x7b,0x05,
-0x20,0x01,0xee,0x72,0x02,0x7b,0x07,0x24,0x05,0xe2,0x72,0x9f,0x06,0xe0,0x72,0x89,
-0x88,0x81,0x84,0x84,0xe9,0x26,0xa4,0xb6,0xed,0x26,0x5d,0x01,0x6b,0x00,0xa2,0xa4,
-0xb7,0x01,0x7b,0x02,0x6b,0x01,0xa0,0x97,0x02,0x7b,0x9d,0x01,0x20,0x01,0xef,0x72,
-0x02,0x6b,0x5c,0xfa,0xcd,0x03,0xae,0x90,0xa7,0x3f,0x5f,0x88,0x88,0x81,0x41,0x20,
-0x40,0x35,0x48,0x20,0x5f,0x72,0x46,0x20,0x5f,0x72,0x45,0x20,0xd8,0x35,0x81,0x9a,
-0x68,0x01,0xcf,0x69,0x01,0xc7,0x9b,0x81,0x44,0x42,0x00,0x35,0x45,0x42,0x00,0x35,
-0x46,0x42,0x00,0x35,0x47,0x42,0x00,0x35,0x00,0x42,0x00,0x35,0x01,0x42,0x00,0x35,
-0x02,0x42,0x01,0x35,0x03,0x42,0x01,0x35,0x10,0x20,0x00,0x42,0x08,0x35,0x01,0x42,
-0x00,0x35,0x02,0x42,0x01,0x35,0x03,0x42,0x00,0x35,0x12,0x26,0x4a,0xc2,0x00,0xc6,
-0x20,0x40,0x00,0x35,0x21,0x40,0x00,0x35,0x22,0x40,0x00,0x35,0x23,0x40,0x01,0x35,
-0x04,0x44,0xc4,0x00,0x55,0x05,0x44,0xc5,0x00,0x55,0x06,0x44,0xc6,0x00,0x55,0x07,
-0x44,0xc7,0x00,0x55,0x00,0x44,0xc8,0x00,0x55,0x01,0x44,0xc9,0x00,0x55,0x02,0x44,
-0xca,0x00,0x55,0x03,0x44,0xcb,0x00,0x55,0x81,0xcb,0xfa,0xcd,0xa0,0x3f,0xa1,0x3f,
-0xa2,0x3f,0x81,0xcb,0xfa,0xcd,0xa4,0xb7,0x01,0xaa,0x41,0x81,0xa0,0xb7,0xa1,0xb7,
-0xa2,0xb7,0x4f,0xa3,0xb7,0x81,0xa4,0xc6,0x92,0xa5,0xbf,0xa4,0xb7,0x81,0x1c,0xad,
-0xa3,0x3f,0xa4,0xb7,0x01,0xaa,0x81,0x84,0x84,0x84,0xdf,0x26,0x03,0xe1,0x72,0x12,
-0xad,0x02,0xaa,0x41,0x03,0xaa,0x01,0xee,0x72,0x02,0x7b,0xcb,0xfa,0xcd,0xa4,0xb7,
-0x02,0xaa,0x01,0x7b,0x02,0xee,0x72,0x32,0xad,0x03,0x7b,0x10,0x20,0x03,0x6b,0x03,
-0xa6,0x02,0x20,0x83,0xa6,0x04,0x26,0x02,0xa1,0x11,0xb6,0x59,0xad,0xa3,0x00,0x3d,
-0x35,0x02,0xee,0x72,0xa4,0xb7,0x01,0x7b,0x66,0xad,0xa3,0x00,0x08,0x35,0xa4,0xb7,
-0x02,0xaa,0x41,0x24,0xaa,0x01,0xee,0x72,0x02,0x7b,0x54,0xad,0x41,0x1c,0xaa,0x01,
-0xee,0x72,0x02,0x7b,0x5e,0xad,0x41,0x18,0xaa,0x01,0xee,0x72,0x02,0x7b,0x68,0xad,
-0x41,0x14,0xaa,0x01,0xee,0x72,0x02,0x7b,0xdf,0x26,0x03,0xe1,0x72,0xb3,0xde,0xcd,
-0x01,0xaa,0x41,0x13,0xaa,0x01,0xee,0x72,0x02,0x7b,0xc5,0xde,0xcd,0x10,0xaa,0x01,
-0xee,0x72,0x02,0x7b,0xbb,0xde,0xcd,0x03,0x7b,0x0f,0x20,0x03,0x6b,0xcf,0xa6,0x02,
-0x20,0x0f,0xa6,0x06,0x20,0x0c,0xa6,0x08,0x20,0x06,0x27,0x4a,0x05,0x27,0x14,0xb6,
-0xda,0x26,0x03,0xe1,0x72,0xb3,0xde,0xcd,0x01,0xaa,0x41,0x0d,0xaa,0x01,0xee,0x72,
-0x02,0x7b,0xc5,0xde,0xcd,0x0c,0xaa,0x01,0xee,0x72,0x02,0x7b,0x85,0xfa,0xcd,0x10,
-0xa6,0xbb,0xde,0xcd,0x03,0x7b,0x14,0x20,0x03,0x6b,0xfc,0xa6,0x02,0x20,0xf0,0xa6,
-0x06,0x20,0xcc,0xa6,0x0a,0x20,0xc0,0xa6,0x0e,0x20,0x0c,0xa6,0x12,0x20,0x0f,0xa6,
-0x04,0x20,0x16,0x27,0x4a,0x15,0x27,0x4a,0x14,0x27,0x4a,0x13,0x27,0x4a,0x12,0x27,
-0x4a,0x27,0x27,0x4a,0x14,0x27,0x13,0xb6,0xd1,0x26,0x03,0xe1,0x72,0xb3,0xde,0xcd,
-0x01,0xaa,0x41,0x0b,0xaa,0x01,0xee,0x72,0x02,0x7b,0xc5,0xde,0xcd,0x08,0xaa,0x01,
-0xee,0x72,0x02,0x7b,0xa0,0xb7,0x03,0xaa,0xa0,0xb6,0xa1,0xb7,0xc3,0xaa,0xa0,0xb7,
-0xa2,0xb7,0x4f,0xa3,0xb7,0x03,0x7b,0x1d,0x20,0x03,0x6b,0x4f,0x01,0x20,0x0c,0xa6,
-0x04,0x27,0x15,0x3d,0xaa,0xde,0xcd,0x41,0x04,0xaa,0x01,0xee,0x72,0x02,0x7b,0xaa,
-0xde,0xcd,0x01,0x6b,0x02,0xef,0x72,0x50,0xaa,0x41,0x4f,0x58,0x58,0x97,0x88,0x88,
-0x88,0x81,0x1f,0xfc,0xcd,0xc8,0xae,0xa4,0x00,0x00,0x35,0x81,0xa0,0xb7,0xa1,0xb7,
-0xa2,0xb7,0x4f,0xa3,0xb7,0x81,0x4d,0x5f,0x12,0xb6,0x81,0xa4,0xb7,0x00,0xa9,0x41,
-0x07,0xab,0x81,0xc8,0x00,0x00,0x35,0xc9,0x00,0x00,0x35,0xca,0x00,0x18,0x35,0x81,
-0xd9,0xfb,0xcd,0xa4,0xb7,0x00,0xa9,0x41,0x01,0xab,0x81,0xa0,0xb7,0x03,0xa4,0xa0,
-0xb6,0xa1,0x3f,0xa2,0x3f,0xa3,0x3f,0x85,0xfa,0xcd,0x18,0xa6,0x73,0xfa,0xcd,0x4a,
-0x81,0x3c,0xad,0x18,0xa4,0x48,0x48,0x48,0x4a,0x12,0xb6,0xe8,0xfa,0xcd,0xa4,0xb7,
-0x00,0xa9,0x41,0x01,0xab,0x81,0x8b,0x41,0x00,0xa9,0x41,0x0a,0xab,0x5b,0xe8,0xfa,
-0xcd,0x0c,0xae,0xa4,0x00,0x84,0x35,0xa3,0x36,0xa2,0x36,0xa1,0x36,0xa0,0x34,0x74,
-0xad,0x0a,0x20,0xa0,0x39,0xa1,0x39,0xa2,0x39,0xa3,0x38,0x45,0xdd,0xcd,0x0d,0x26,
-0x02,0xa1,0x11,0xb6,0x84,0x84,0x84,0x84,0x84,0xe2,0xd6,0xcd,0x88,0x0b,0x7b,0x88,
-0x0b,0x7b,0x88,0x0b,0x7b,0x88,0x0b,0x7b,0x88,0x06,0x7b,0x06,0x6b,0x44,0x44,0x06,
-0x7b,0x95,0xfb,0xcd,0x02,0xa6,0x2e,0xdd,0xcd,0x5b,0x0f,0x26,0x02,0xa1,0x11,0xb6,
-0x06,0x6b,0x08,0xa6,0x07,0x6b,0x4f,0x08,0x6b,0xbb,0xa6,0x09,0x6b,0x80,0xa6,0x0a,
-0x6b,0xc8,0x00,0x00,0x35,0xc9,0x00,0x00,0x35,0xca,0x00,0x60,0x35,0xcb,0x00,0x00,
-0x35,0x18,0x20,0xac,0xa6,0x09,0x6b,0x44,0xa6,0x0a,0x6b,0xc8,0x00,0x00,0x35,0xc9,
-0x00,0x00,0x35,0xca,0x00,0x62,0x35,0xcb,0x00,0x00,0x35,0x39,0x20,0x10,0xa6,0x07,
-0x6b,0x4f,0x08,0x6b,0x5d,0xa6,0x09,0x6b,0xc0,0xa6,0x0a,0x6b,0xc8,0x00,0x00,0x35,
-0xc9,0x00,0x00,0x35,0xca,0x00,0x30,0x35,0xcb,0x00,0x00,0x35,0x18,0x20,0x56,0xa6,
-0x09,0x6b,0x22,0xa6,0x0a,0x6b,0xc8,0x00,0x00,0x35,0xc9,0x00,0x00,0x35,0xca,0x00,
-0x31,0x35,0xcb,0x00,0x00,0x35,0x74,0x20,0x20,0xa6,0x07,0x6b,0x4f,0x08,0x6b,0x2e,
-0xa6,0x09,0x6b,0xe0,0xa6,0x0a,0x6b,0x21,0xdd,0xcd,0xcb,0x00,0x00,0x35,0x8e,0xdc,
-0xcc,0x20,0xa6,0x07,0x6b,0x4f,0x08,0x6b,0x2b,0xa6,0x09,0x6b,0x11,0xa6,0x0a,0x6b,
-0x21,0xdd,0xcd,0xcb,0x00,0x80,0x35,0x8e,0xdc,0xcc,0x20,0xa6,0x07,0x6b,0x4f,0x08,
-0x6b,0x1f,0xa6,0x09,0x6b,0x40,0xa6,0x0a,0x6b,0xc8,0x00,0x00,0x35,0xc9,0x00,0x00,
-0x35,0xca,0x00,0x10,0x35,0xcb,0x00,0x00,0x35,0x8e,0xdc,0xcc,0x20,0xa6,0x07,0x6b,
-0x4f,0x08,0x6b,0x2e,0xa6,0x09,0x6b,0xe0,0xa6,0x0a,0x6b,0x4f,0x21,0xdd,0xcd,0xcb,
-0x00,0x00,0x35,0x6f,0xdc,0xcc,0x03,0x26,0x4a,0x55,0xdc,0xcc,0x03,0x26,0x4a,0x34,
-0xdc,0xcc,0x03,0x26,0x4a,0x1a,0xdc,0xcc,0x03,0x26,0x4a,0x6d,0x27,0x4a,0x57,0x27,
-0x4a,0x38,0x27,0x13,0xb6,0xe8,0xfa,0xcd,0xa4,0xbf,0x84,0xae,0xa3,0x1a,0x1f,0xfc,
-0xcd,0x2e,0xdd,0xcd,0x5b,0xb4,0xfb,0xcd,0x2e,0xdd,0xcd,0x5b,0xa1,0x1c,0x16,0xdd,
-0xcd,0x5b,0xeb,0xdc,0xcd,0x5b,0x00,0xdd,0xcd,0x5a,0x01,0x26,0x36,0xdd,0xcd,0x13,
-0x20,0xa3,0x10,0x16,0xdd,0xcd,0x5b,0xeb,0xdc,0xcd,0x5b,0x00,0xdd,0xcd,0x5a,0x01,
-0x26,0x36,0xdd,0xcd,0x15,0x26,0x4a,0x11,0xb6,0x34,0x20,0x08,0x6b,0x40,0xaa,0x08,
-0x7b,0x0a,0x6b,0x02,0xaa,0x0a,0x7b,0x0e,0x26,0x02,0xa1,0x11,0xb6,0x41,0x20,0x16,
-0xdd,0xcd,0x5b,0xeb,0xdc,0xcd,0x5b,0x00,0xdd,0xcd,0x5a,0x01,0x26,0x36,0xdd,0xcd,
-0x54,0x20,0xa3,0x10,0xa1,0x1c,0x16,0xdd,0xcd,0x5b,0xeb,0xdc,0xcd,0x5b,0x00,0xdd,
-0xcd,0x5a,0x01,0x26,0x36,0xdd,0xcd,0x17,0x26,0x4a,0x11,0xb6,0x77,0x20,0x0a,0x6b,
-0x02,0xaa,0x0a,0x7b,0x08,0x26,0x02,0xa1,0x11,0xb6,0x0a,0x6b,0x04,0xaa,0x0a,0x7b,
-0x43,0x27,0x16,0x3d,0xe8,0xfa,0xcd,0x2e,0xdd,0xcd,0x5b,0xa2,0x1e,0xa0,0x3f,0xa1,
-0xb7,0x3e,0xa4,0xa1,0xb6,0xa2,0x3f,0xa3,0x3f,0x85,0xfa,0xcd,0x11,0xa6,0x3b,0xdd,
-0xcd,0x05,0x7b,0xc2,0x00,0xc7,0x12,0xb6,0x02,0x20,0x04,0xa6,0x04,0x26,0x02,0xa1,
-0x11,0xb6,0x05,0x6b,0x18,0xa6,0x02,0x20,0x14,0xa6,0x06,0x20,0x10,0xa6,0x08,0x20,
-0x06,0x27,0x4a,0x05,0x27,0x14,0xb6,0x8b,0x41,0x00,0xa2,0x41,0x0a,0xa0,0x5b,0x00,
-0x00,0xba,0x42,0x00,0x00,0xb8,0x41,0x0a,0xd7,0x23,0x3c,0x00,0x00,0x80,0x3f,0x81,
-0x1f,0xfc,0xcd,0xb7,0xae,0xa4,0x00,0x00,0x35,0x81,0xa4,0xb7,0x00,0xa9,0x41,0x17,
-0xab,0x81,0xa4,0x00,0x80,0x35,0xa0,0xb7,0xa1,0xb7,0xa2,0xb7,0x4f,0xa3,0xb7,0x81,
-0x8b,0x41,0x00,0xa9,0x41,0x1c,0xab,0x5b,0x20,0x80,0x00,0x35,0x21,0x80,0x00,0x35,
-0x22,0x80,0x00,0x35,0x23,0x80,0x40,0x35,0xe8,0xfa,0xcd,0x30,0xae,0x1e,0xad,0x16,
-0x7b,0xe8,0xfa,0xcd,0x2c,0xae,0x27,0xad,0x15,0x7b,0xe8,0xfa,0xcd,0x28,0xae,0x30,
-0xad,0x14,0x7b,0x6c,0xfb,0xcd,0xa4,0xb7,0x00,0xa9,0x41,0x13,0xab,0x5b,0x1f,0xfc,
-0xcd,0x6f,0xae,0xa4,0x00,0x01,0x35,0x13,0x6b,0x60,0x20,0xc6,0x14,0x6b,0x61,0x20,
-0xc6,0x15,0x6b,0x62,0x20,0xc6,0x16,0x6b,0x63,0x20,0xc6,0x68,0x20,0x26,0x35,0x68,
-0x20,0x21,0x35,0x68,0x20,0x52,0x35,0x64,0x20,0xc7,0x0d,0x7b,0x65,0x20,0xc7,0x0e,
-0x7b,0x66,0x20,0xc7,0x0f,0x7b,0x67,0x20,0xc7,0x10,0x7b,0x60,0x20,0x6b,0x01,0x55,
-0x61,0x20,0x6c,0x01,0x55,0x62,0x20,0x6d,0x01,0x55,0x63,0x20,0x6e,0x01,0x55,0xe8,
-0xfa,0xcd,0xa4,0xb7,0x00,0xa9,0x41,0x0d,0xab,0x5b,0xfc,0xfb,0xcd,0x7f,0xda,0xcd,
-0x5b,0x87,0xda,0xcd,0xf0,0x27,0x1b,0xea,0x72,0x1c,0x7b,0xf7,0x26,0x4a,0x6a,0x01,
-0xc6,0x68,0xda,0xcc,0x03,0x27,0x4a,0x06,0x01,0xc6,0x84,0x84,0x84,0x84,0xec,0xdf,
-0xcd,0x88,0x1a,0x7b,0x88,0x1a,0x7b,0x88,0x1a,0x7b,0x88,0x1a,0x7b,0x0f,0x20,0xc7,
-0xdf,0xcd,0x88,0x1a,0x7b,0x88,0x1a,0x7b,0x88,0x1a,0x7b,0x88,0x1a,0x7b,0x11,0x27,
-0x7c,0x01,0xc6,0x7e,0x01,0x5f,0x72,0x04,0x20,0x6c,0xfb,0xcd,0x7f,0xda,0xcd,0x5b,
-0x87,0xda,0xcd,0x0c,0x2b,0xff,0xa2,0x11,0x7b,0xfd,0xa0,0x12,0x7b,0x0a,0x2b,0x00,
-0xa2,0x11,0x7b,0x04,0xa0,0x12,0x6b,0x18,0x7b,0x11,0x6b,0x17,0x7b,0x17,0x6b,0x60,
-0x20,0xc6,0x18,0x6b,0x61,0x20,0xc6,0x19,0x6b,0x62,0x20,0xc6,0x1a,0x6b,0x63,0x20,
-0xc6,0x68,0x20,0x26,0x35,0x68,0x20,0x24,0x35,0x64,0x20,0xaf,0x00,0x55,0x65,0x20,
-0xb0,0x00,0x55,0x66,0x20,0xb1,0x00,0x55,0x67,0x20,0xb2,0x00,0x55,0x68,0x20,0x21,
-0x35,0x64,0x20,0xc7,0x05,0x7b,0x65,0x20,0xc7,0x06,0x7b,0x66,0x20,0xc7,0x07,0x7b,
-0x67,0x20,0xc7,0x08,0x7b,0x60,0x20,0xb3,0x00,0x55,0x61,0x20,0xb4,0x00,0x55,0x62,
-0x20,0xb5,0x00,0x55,0x63,0x20,0xb6,0x00,0x55,0xaf,0x00,0x60,0x20,0x55,0xb0,0x00,
-0x61,0x20,0x55,0xb1,0x00,0x62,0x20,0x55,0xb2,0x00,0x63,0x20,0x55,0x68,0x20,0x21,
-0x35,0x64,0x20,0xc7,0x01,0x7b,0x65,0x20,0xc7,0x02,0x7b,0x66,0x20,0xc7,0x03,0x7b,
-0x67,0x20,0xc7,0x04,0x7b,0xb3,0x00,0x64,0x20,0x55,0xb4,0x00,0x65,0x20,0x55,0xb5,
-0x00,0x66,0x20,0x55,0xb6,0x00,0x67,0x20,0x55,0x68,0x20,0x64,0x35,0x64,0x20,0xb3,
-0x00,0x55,0x65,0x20,0xb4,0x00,0x55,0x66,0x20,0xb5,0x00,0x55,0x67,0x20,0xb6,0x00,
-0x55,0x68,0x20,0x21,0x35,0x64,0x20,0xc7,0x09,0x7b,0x65,0x20,0xc7,0x0a,0x7b,0x66,
-0x20,0xc7,0x0b,0x7b,0x67,0x20,0xc7,0x0c,0x7b,0x68,0x20,0x22,0x35,0xe8,0xfa,0xcd,
-0x60,0xae,0xa4,0x00,0x20,0x35,0x73,0xfa,0xcd,0x1b,0xee,0x72,0x1c,0x7b,0x8d,0xd9,
-0xcc,0x03,0x26,0x1b,0xea,0x72,0x1c,0x7b,0xe8,0xfa,0xcd,0x7f,0xda,0xcd,0x5b,0xa0,
-0x3f,0x1f,0xfc,0xcd,0x5f,0xa4,0x00,0x84,0x35,0xe8,0xfa,0xcd,0xa4,0xb7,0x00,0xa9,
-0x41,0x09,0xab,0x5b,0x1f,0xfc,0xcd,0x91,0xae,0xa4,0x00,0xda,0x35,0x06,0x20,0x95,
-0xae,0xa4,0x00,0xda,0x35,0x08,0x26,0x4c,0x1b,0x01,0xc6,0x05,0x6b,0x99,0xda,0xc6,
-0x06,0x6b,0x9a,0xda,0xc6,0x07,0x6b,0x9b,0xda,0xc6,0x08,0x6b,0x9c,0xda,0xc6,0x01,
-0x6b,0x9d,0xda,0xc6,0x02,0x6b,0x9e,0xda,0xc6,0x03,0x6b,0x9f,0xda,0xc6,0x04,0x6b,
-0xa0,0xda,0xc6,0x8b,0x41,0x00,0xa2,0x41,0x1a,0xa0,0x5b,0x89,0x88,0x81,0xa0,0xb7,
-0xa1,0xb7,0xa2,0xb7,0x4f,0xa3,0xb7,0x81,0xa4,0xb7,0x00,0xa9,0x41,0x01,0xab,0x81,
-0x84,0x84,0x84,0x84,0xe8,0xfa,0xcd,0x10,0xae,0xa4,0x00,0x84,0x35,0xa1,0x1e,0x1f,
-0xfc,0xcd,0x13,0xad,0x5b,0x10,0x84,0xc7,0x01,0x7b,0x11,0x84,0xc7,0x02,0x7b,0x12,
-0x84,0xc7,0x03,0x7b,0x13,0x84,0xc7,0x04,0x7b,0x02,0x6b,0x7f,0xa4,0x02,0x7b,0xe8,
-0xfa,0xcd,0x33,0xad,0x5b,0xd9,0xfb,0xcd,0xa4,0xb7,0x00,0xa9,0x41,0x07,0xab,0x5b,
-0xa0,0xb7,0x03,0xa4,0xa0,0xb6,0xa1,0x3f,0xa2,0x3f,0xa3,0x3f,0x1f,0xfc,0xcd,0x50,
-0xad,0x5b,0x01,0x6b,0x10,0x84,0xc6,0x02,0x6b,0x11,0x84,0xc6,0x03,0x6b,0x12,0x84,
-0xc6,0x04,0x6b,0x13,0x84,0xc6,0xb4,0xfb,0xcd,0xa4,0xb7,0x00,0xa9,0x41,0x07,0xab,
-0x5b,0x85,0xfa,0xcd,0x14,0xa6,0x09,0xd8,0xcd,0x0b,0x6b,0x4c,0x01,0x20,0x06,0xa6,
-0x05,0x20,0x02,0xa6,0x09,0x20,0x04,0xa6,0x0d,0x20,0x07,0xa6,0x10,0x27,0x10,0xa0,
-0x10,0x27,0x08,0xa0,0x10,0x27,0x04,0xa0,0x10,0x27,0x02,0xa0,0x21,0x27,0x02,0xa0,
-0x0b,0x7b,0x07,0x6b,0x60,0x20,0xc6,0x08,0x6b,0x61,0x20,0xc6,0x09,0x6b,0x62,0x20,
-0xc6,0x0a,0x6b,0x63,0x20,0xc6,0x68,0x20,0x26,0x35,0x68,0x20,0x21,0x35,0x68,0x20,
-0x52,0x35,0x64,0x20,0x00,0x35,0x65,0x20,0x00,0x35,0x66,0x20,0x80,0x35,0x67,0x20,
-0x00,0x35,0x9d,0x9d,0x68,0x20,0x27,0x35,0x60,0x20,0xbb,0x00,0x55,0x61,0x20,0xbc,
-0x00,0x55,0x62,0x20,0xbd,0x00,0x55,0x63,0x20,0xbe,0x00,0x55,0x68,0x20,0x61,0x35,
-0x68,0x20,0x52,0x35,0xe8,0xfa,0xcd,0x64,0xae,0xa4,0x00,0x20,0x35,0x09,0xd8,0xcd,
-0x0b,0x7b,0x68,0x20,0x22,0x35,0x60,0x20,0xc7,0x07,0x7b,0x61,0x20,0xc7,0x08,0x7b,
-0x62,0x20,0xc7,0x09,0x7b,0x63,0x20,0xc7,0x0a,0x7b,0x88,0x88,0x88,0x88,0x81,0x64,
-0x20,0x00,0x35,0x65,0x20,0x00,0x35,0x66,0x20,0x00,0x35,0x81,0x84,0xe8,0xfa,0xcd,
-0x10,0xae,0xa4,0x00,0x84,0x35,0xa2,0xb7,0x55,0xaa,0xa2,0xb6,0xa3,0xb7,0x55,0xaa,
-0xa3,0xb6,0xa1,0xb7,0x55,0xaa,0xa1,0xb6,0x85,0xfa,0xcd,0x18,0xa6,0xa0,0xb7,0xa1,
-0xb7,0xa2,0xb7,0x4f,0xa3,0xb7,0x01,0x7b,0xe8,0xfa,0xcd,0x14,0xae,0xa4,0x00,0x84,
-0x35,0xa0,0xb7,0x3f,0xa4,0xa0,0xb6,0xa1,0x3f,0xa2,0x3f,0xa3,0x3f,0x85,0xfa,0xcd,
-0x18,0xa6,0x1f,0xfc,0xcd,0xa4,0xb7,0x00,0xa9,0x41,0x04,0xab,0x5b,0x25,0x24,0x0f,
-0xa1,0x07,0x7b,0x63,0xdf,0xcd,0x64,0xa6,0x84,0x84,0x84,0x84,0xc7,0xdf,0xcd,0xb7,
-0x00,0x3b,0xb8,0x00,0x3b,0xb9,0x00,0x3b,0xba,0x00,0x3b,0x0f,0x20,0xec,0xdf,0xcd,
-0xb7,0x00,0x3b,0xb8,0x00,0x3b,0xb9,0x00,0x3b,0xba,0x00,0x3b,0x11,0x26,0x4a,0x05,
-0x01,0xc6,0x14,0x84,0x0f,0x35,0x15,0x84,0x00,0x35,0x16,0x84,0x00,0x35,0x17,0x84,
-0x00,0x35,0x04,0x6b,0x60,0x20,0xc6,0x05,0x6b,0x61,0x20,0xc6,0x06,0x6b,0x62,0x20,
-0xc6,0x07,0x6b,0x63,0x20,0xc6,0x68,0x20,0xc7,0x4a,0x9d,0x9d,0x68,0x20,0xc7,0x27,
-0xa6,0x68,0x20,0x52,0x35,0x64,0x20,0x05,0x35,0x65,0x20,0xf5,0x35,0x66,0x20,0xe1,
-0x35,0x67,0x20,0x00,0x35,0x60,0x20,0xbb,0x00,0x55,0x61,0x20,0xbc,0x00,0x55,0x62,
-0x20,0xbd,0x00,0x55,0x63,0x20,0xbe,0x00,0x55,0xb7,0x00,0x60,0x20,0x55,0xb8,0x00,
-0x61,0x20,0x55,0xb9,0x00,0x62,0x20,0x55,0xba,0x00,0x63,0x20,0x55,0x68,0x20,0x26,
-0x35,0x68,0x20,0x21,0x35,0x68,0x20,0x52,0x35,0x64,0x20,0x00,0x35,0x65,0x20,0x00,
-0x35,0x66,0x20,0x80,0x35,0x67,0x20,0x00,0x35,0x68,0x20,0x27,0x35,0xbb,0x00,0x60,
-0x20,0x55,0xbc,0x00,0x61,0x20,0x55,0xbd,0x00,0x62,0x20,0x55,0xbe,0x00,0x63,0x20,
-0x55,0x68,0x20,0x52,0x35,0x64,0x20,0xc7,0x04,0x7b,0x65,0x20,0xc7,0x05,0x7b,0x66,
-0x20,0xc7,0x06,0x7b,0x67,0x20,0xc7,0x07,0x7b,0x68,0x20,0xc7,0x4a,0x68,0x20,0xc7,
-0x22,0xa6,0x60,0x20,0xc7,0x08,0x7b,0x61,0x20,0xc7,0x09,0x7b,0x62,0x20,0xc7,0x0a,
-0x7b,0x63,0x20,0xc7,0x0b,0x7b,0x68,0x20,0x52,0x35,0x10,0x84,0x02,0x35,0x11,0x84,
-0x55,0x35,0x12,0x84,0x55,0x35,0x13,0x84,0x55,0x35,0x01,0x6b,0x02,0xa6,0xd5,0xd6,
-0xcd,0x67,0x20,0x28,0x35,0x09,0x20,0x01,0xa6,0xd5,0xd6,0xcd,0x67,0x20,0x14,0x35,
-0x0b,0x25,0x02,0xa2,0x08,0x7b,0xdd,0xa0,0x09,0x7b,0x1e,0x20,0x4f,0xd5,0xd6,0xcd,
-0x67,0x20,0x0a,0x35,0x0a,0x25,0x04,0xa2,0x08,0x7b,0xd9,0xa0,0x09,0x7b,0x88,0x81,
-0xe7,0x00,0xce,0xe8,0x00,0xc6,0xe8,0xfa,0xcd,0x81,0x84,0x84,0xe8,0xfa,0xcd,0x0c,
-0xae,0xa4,0x00,0x41,0x35,0x07,0xfb,0xcd,0x41,0xdf,0x00,0xc9,0x41,0xe0,0x00,0xcb,
-0x17,0xad,0x08,0xae,0xa4,0x00,0x41,0x35,0x07,0xfb,0xcd,0x5c,0x01,0x26,0x4c,0x26,
-0xad,0x04,0xae,0xa4,0x00,0x41,0x35,0x07,0xfb,0xcd,0x41,0xdd,0x00,0xc9,0x41,0xde,
-0x00,0xcb,0x41,0x01,0xe2,0x72,0x41,0x02,0xe0,0x72,0xe5,0x00,0xce,0xe6,0x00,0xc6,
-0xe8,0xfa,0xcd,0x5f,0xa4,0x00,0x41,0x35,0x07,0xfb,0xcd,0x5c,0x01,0x26,0x4c,0x41,
-0x01,0xe2,0x72,0x41,0x02,0xe0,0x72,0xe5,0x00,0xce,0xe6,0x00,0xc6,0x02,0x6b,0xea,
-0x00,0xc6,0x01,0x6b,0xe9,0x00,0xc6,0x88,0x88,0x81,0xed,0x00,0xce,0xee,0x00,0xc6,
-0xe8,0xfa,0xcd,0x81,0x41,0xe9,0x00,0xc9,0x41,0xea,0x00,0xcb,0x46,0x54,0xe1,0x00,
-0xce,0xe2,0x00,0xc6,0x81,0xe9,0x00,0xce,0xea,0x00,0xc6,0xe8,0xfa,0xcd,0x81,0x85,
-0xfa,0xcd,0x10,0xa6,0x07,0xfb,0xcd,0x81,0xa4,0xb7,0x00,0xa9,0x41,0x01,0xab,0x81,
-0x84,0x84,0x84,0x84,0x84,0x84,0x7c,0x83,0x00,0x35,0x7d,0x83,0x00,0x35,0x7e,0x83,
-0x0f,0x35,0x7f,0x83,0xff,0x35,0xe8,0xfa,0xcd,0x6c,0xae,0xa4,0x00,0x83,0x35,0xd9,
-0xfb,0xcd,0x23,0xad,0x5b,0x2e,0xad,0x43,0xad,0xe8,0xfa,0xcd,0x2d,0xad,0x5b,0x07,
-0xfb,0xcd,0x4e,0xad,0x0d,0x20,0x48,0xad,0x39,0xad,0x5b,0x07,0xfb,0xcd,0xe9,0x00,
-0xce,0xea,0x00,0xc6,0x10,0x26,0x4a,0xdc,0x00,0xc6,0xe8,0xfa,0xcd,0x68,0xae,0xa4,
-0x00,0x83,0x35,0xd9,0xfb,0xcd,0x57,0xad,0x5b,0x62,0xad,0x6d,0xad,0x5e,0xad,0x5b,
-0x07,0xfb,0xcd,0x75,0xad,0x64,0xae,0xa4,0x00,0x83,0x35,0xd9,0xfb,0xcd,0x6f,0xad,
-0x5b,0x7a,0xad,0x41,0xef,0x00,0xc9,0x41,0xf0,0x00,0xcb,0x05,0xee,0x72,0x06,0x7b,
-0xe8,0xfa,0xcd,0x81,0xd4,0xcd,0x5b,0x07,0xfb,0xcd,0x05,0xee,0x72,0x06,0x7b,0xe8,
-0xfa,0xcd,0x60,0xae,0xa4,0x00,0x83,0x35,0xd9,0xfb,0xcd,0x81,0xd4,0xcd,0x5b,0x89,
-0xd4,0xcd,0x41,0xef,0x00,0xc9,0x41,0xf0,0x00,0xcb,0xad,0xd4,0xcd,0x81,0xd4,0xcd,
-0x5b,0x07,0xfb,0xcd,0xad,0xd4,0xcd,0x5c,0xae,0xa4,0x00,0x83,0x35,0x07,0xfb,0xcd,
-0x46,0x54,0xe1,0x00,0xce,0xe2,0x00,0xc6,0x05,0xef,0x72,0x06,0x6b,0x4a,0x5a,0x01,
-0x26,0x4d,0xed,0x00,0xce,0xee,0x00,0xc6,0x10,0x20,0x06,0x6b,0xee,0x00,0xc6,0x05,
-0x6b,0xed,0x00,0xc6,0x0c,0x26,0x4a,0xdc,0x00,0xc6,0x88,0x88,0x88,0x88,0x88,0x88,
-0x81,0xed,0x00,0xce,0xee,0x00,0xc6,0xe8,0xfa,0xcd,0x81,0x4d,0x41,0xdf,0x00,0xc9,
-0x41,0xe0,0x00,0xcb,0x81,0x02,0xa0,0x41,0xdd,0x00,0xc9,0x41,0xde,0x00,0xcb,0x81,
-0x41,0xe9,0x00,0xc9,0x41,0xea,0x00,0xcb,0x46,0x54,0xe1,0x00,0xce,0xe2,0x00,0xc6,
-0x81,0xe5,0x00,0xce,0xe6,0x00,0xc6,0xe8,0xfa,0xcd,0x81,0xe9,0x00,0xce,0xea,0x00,
-0xc6,0xe8,0xfa,0xcd,0x81,0x85,0xfa,0xcd,0x10,0xa6,0x07,0xfb,0xcd,0x81,0xa4,0xb7,
-0x00,0xa9,0x41,0x01,0xab,0x81,0x8b,0x41,0x00,0xa9,0x41,0x0e,0xab,0x5b,0x98,0x83,
-0x00,0x35,0x99,0x83,0x00,0x35,0x9a,0x83,0x00,0x35,0x9b,0x83,0x18,0x35,0xe8,0xfa,
-0xcd,0x3c,0xae,0xa4,0x00,0x83,0x35,0xd9,0xfb,0xcd,0x25,0xad,0x5b,0x30,0xad,0x4f,
-0xad,0xe8,0xfa,0xcd,0x2f,0xad,0x5b,0x07,0xfb,0xcd,0x5a,0xad,0x0d,0x20,0x4a,0xad,
-0x3b,0xad,0x5b,0x07,0xfb,0xcd,0xe9,0x00,0xce,0xea,0x00,0xc6,0x10,0x26,0x4a,0xdc,
-0x00,0xc6,0xe8,0xfa,0xcd,0x38,0xae,0xa4,0x00,0x83,0x35,0xd9,0xfb,0xcd,0x59,0xad,
-0x5b,0x64,0xad,0x6f,0xad,0x60,0xad,0x5b,0x07,0xfb,0xcd,0x77,0xad,0x34,0xae,0xa4,
-0x00,0x83,0x35,0xd9,0xfb,0xcd,0x71,0xad,0x5b,0x7c,0xad,0x41,0xef,0x00,0xc9,0x41,
-0xf0,0x00,0xcb,0x07,0xee,0x72,0x08,0x7b,0xe8,0xfa,0xcd,0x3b,0xd3,0xcd,0x5b,0x07,
-0xfb,0xcd,0x07,0xee,0x72,0x08,0x7b,0xe8,0xfa,0xcd,0x30,0xae,0xa4,0x00,0x83,0x35,
-0xd9,0xfb,0xcd,0x3b,0xd3,0xcd,0x5b,0x43,0xd3,0xcd,0x41,0xef,0x00,0xc9,0x41,0xf0,
-0x00,0xcb,0x86,0xd3,0xcd,0x3b,0xd3,0xcd,0x5b,0x07,0xfb,0xcd,0x86,0xd3,0xcd,0x2c,
-0xae,0xa4,0x00,0x83,0x35,0xd9,0xfb,0xcd,0x3b,0xd3,0xcd,0x5b,0x43,0xd3,0xcd,0x41,
-0xeb,0x00,0xc9,0x41,0xec,0x00,0xcb,0x4c,0xd3,0xcd,0x3b,0xd3,0xcd,0x5b,0x07,0xfb,
-0xcd,0x4c,0xd3,0xcd,0x10,0xae,0xa4,0x00,0x83,0x35,0xd9,0xfb,0xcd,0x3b,0xd3,0xcd,
-0x5b,0x43,0xd3,0xcd,0x4a,0x5a,0x01,0x26,0x7c,0xd3,0xcd,0x0d,0xee,0x72,0x0e,0x7b,
-0xe8,0xfa,0xcd,0x3b,0xd3,0xcd,0x5b,0x07,0xfb,0xcd,0x5a,0x01,0x24,0x71,0xd3,0xcd,
-0x56,0xd3,0xcd,0x0c,0xae,0xa4,0x00,0x83,0x35,0xd9,0xfb,0xcd,0x3b,0xd3,0xcd,0x5b,
-0x43,0xd3,0xcd,0x0d,0xee,0x72,0x0e,0x7b,0xe8,0xfa,0xcd,0x3b,0xd3,0xcd,0x5b,0x07,
-0xfb,0xcd,0x4a,0x5a,0x01,0x26,0x4d,0x56,0xd3,0xcd,0x08,0xae,0xa4,0x00,0x83,0x35,
-0xd9,0xfb,0xcd,0x3b,0xd3,0xcd,0x5b,0x43,0xd3,0xcd,0x4a,0x5a,0x01,0x26,0x7c,0xd3,
-0xcd,0x0d,0xee,0x72,0x0e,0x7b,0xe8,0xfa,0xcd,0x3b,0xd3,0xcd,0x5b,0x07,0xfb,0xcd,
-0x5a,0x01,0x24,0x71,0xd3,0xcd,0x56,0xd3,0xcd,0x04,0xae,0xa4,0x00,0x83,0x35,0xd9,
-0xfb,0xcd,0x3b,0xd3,0xcd,0x5b,0x43,0xd3,0xcd,0x0d,0xee,0x72,0x0e,0x7b,0xe8,0xfa,
-0xcd,0x3b,0xd3,0xcd,0x5b,0x07,0xfb,0xcd,0x4a,0x5a,0x01,0x26,0x4d,0x56,0xd3,0xcd,
-0x40,0xae,0xa4,0x00,0x83,0x35,0xa0,0x3f,0xa1,0x3f,0xa2,0xb7,0x0f,0xa4,0xa2,0xb6,
-0x07,0xfb,0xcd,0x05,0xee,0x72,0x06,0x7b,0xe8,0xfa,0xcd,0x28,0xae,0xa4,0x00,0x83,
-0x35,0xa0,0x3f,0xa1,0x3f,0xa2,0xb7,0x1f,0xa4,0xa2,0xb6,0x07,0xfb,0xcd,0xe1,0x00,
-0xce,0xe2,0x00,0xc6,0x78,0x84,0xc7,0x09,0x7b,0x79,0x84,0xc7,0x0a,0x7b,0x7a,0x84,
-0xc7,0x0b,0x7b,0x7b,0x84,0xc7,0x0c,0x7b,0x07,0xef,0x72,0x08,0x6b,0x4a,0x5a,0x01,
-0x26,0x4d,0xed,0x00,0xce,0xee,0x00,0xc6,0x06,0x6b,0xe4,0x00,0xc6,0x05,0x6b,0xe3,
-0x00,0xc6,0x0a,0x6b,0x05,0xaa,0x0a,0x7b,0x20,0x20,0x08,0x6b,0xee,0x00,0xc6,0x07,
-0x6b,0xed,0x00,0xc6,0x05,0xef,0x72,0x06,0x6b,0x59,0x48,0xe3,0x00,0xce,0xe4,0x00,
-0xc6,0x0a,0x6b,0x01,0xaa,0x0a,0x7b,0x1f,0x26,0x4a,0xdc,0x00,0xc6,0x09,0x6b,0x80,
-0xaa,0x09,0x7b,0x06,0x26,0x04,0xa1,0x00,0x01,0xc6,0x09,0x6b,0x20,0xa6,0x0a,0x6b,
-0x0b,0x6b,0x0c,0x6b,0x4f,0x0d,0x6b,0x0e,0xef,0x72,0xed,0x00,0xc9,0x41,0xee,0x00,
-0xcb,0xe7,0x00,0xce,0xe8,0x00,0xc6,0x8b,0x41,0x00,0xa2,0x41,0x0e,0xa0,0x5b,0x81,
-0x84,0x84,0x84,0x84,0x75,0x01,0x01,0x35,0xe8,0xfa,0xcd,0x78,0xae,0xa4,0x00,0x84,
-0x35,0xd9,0xfb,0xcd,0xa4,0xb7,0x00,0xa9,0x41,0x01,0xab,0x5b,0xa0,0xb7,0x03,0xa4,
-0xa0,0xb6,0xa1,0xb7,0xc0,0xa4,0xa1,0xb6,0xa2,0x3f,0xa3,0x3f,0x85,0xfa,0xcd,0x16,
-0xa6,0xa0,0xb7,0xa1,0xb7,0xa2,0xb7,0x4f,0xa3,0x00,0xf7,0x00,0x55,0x01,0x6b,0xfc,
-0xa4,0x01,0x7b,0x02,0x6b,0x3f,0xa4,0x02,0x7b,0x01,0x6b,0x78,0x84,0xc6,0x02,0x6b,
-0x79,0x84,0xc6,0x03,0x6b,0x7a,0x84,0xc6,0x04,0x6b,0x7b,0x84,0xc6,0xe8,0xfa,0xcd,
-0x74,0xae,0xa4,0x00,0x84,0x35,0x07,0xfb,0xcd,0xda,0x00,0xce,0xdb,0x00,0xc6,0xe8,
-0xfa,0xcd,0x70,0xae,0xa4,0x00,0x84,0x35,0x07,0xfb,0xcd,0xd8,0x00,0xce,0xd9,0x00,
-0xc6,0xe8,0xfa,0xcd,0x6c,0xae,0xa4,0x00,0x84,0x35,0x07,0xfb,0xcd,0xd6,0x00,0xce,
-0xd7,0x00,0xc6,0xe8,0xfa,0xcd,0x68,0xae,0xa4,0x00,0x84,0x35,0x07,0xfb,0xcd,0xd4,
-0x00,0xce,0xd5,0x00,0xc6,0xe8,0xfa,0xcd,0x64,0xae,0xa4,0x00,0x84,0x35,0x07,0xfb,
-0xcd,0xd2,0x00,0xce,0xd3,0x00,0xc6,0x12,0x20,0x64,0x84,0x00,0x35,0x65,0x84,0x00,
-0x35,0x66,0x84,0x02,0x35,0x67,0x84,0xcb,0x35,0x12,0x25,0x02,0xa2,0xd2,0x00,0xc6,
-0xcb,0xa0,0xd3,0x00,0xc6,0x1e,0x26,0x02,0xa1,0x7a,0x01,0xc6,0x25,0x26,0x03,0xa1,
-0x05,0x01,0xc6,0xe8,0xfa,0xcd,0x60,0xae,0xa4,0x00,0x84,0x35,0x07,0xfb,0xcd,0xd0,
-0x00,0xce,0xd1,0x00,0xc6,0xe8,0xfa,0xcd,0x5c,0xae,0xa4,0x00,0x84,0x35,0x07,0xfb,
-0xcd,0xce,0x00,0xce,0xcf,0x00,0xc6,0xe8,0xfa,0xcd,0x58,0xae,0xa4,0x00,0x84,0x35,
-0x07,0xfb,0xcd,0xcc,0x00,0xce,0xcd,0x00,0xc6,0x88,0x88,0x88,0x88,0x81,0xa4,0xc6,
-0x92,0xa5,0xbf,0xa4,0xb7,0x81,0xa4,0xd6,0x92,0xa5,0x3f,0xa4,0xb7,0x81,0x84,0xda,
-0x00,0xcf,0xd2,0x00,0xce,0xdb,0x00,0xc7,0xd3,0x00,0xc6,0xd2,0x00,0xcf,0xd3,0x00,
-0xc7,0x4a,0x5a,0x01,0x26,0x4d,0x59,0x48,0xfa,0x00,0xce,0xfb,0x00,0xc6,0x0b,0x20,
-0x0e,0x26,0x4d,0xfa,0x00,0xce,0xfb,0x00,0xc6,0x0b,0x26,0x4a,0xdc,0x00,0xc6,0xd8,
-0x00,0xcf,0xd0,0x00,0xce,0xd9,0x00,0xc7,0xd1,0x00,0xc6,0xd1,0x00,0x5f,0x72,0xd0,
-0x00,0x5f,0x72,0xd6,0x00,0xcf,0xce,0x00,0xce,0xd7,0x00,0xc7,0xcf,0x00,0xc6,0xce,
-0x00,0xcf,0xcf,0x00,0xc7,0x4a,0x5a,0x01,0x26,0x4d,0xfa,0x26,0x5a,0x90,0x46,0x54,
-0x06,0x27,0xf7,0x00,0xce,0x90,0xf8,0x00,0xce,0xf9,0x00,0xc6,0xd4,0x00,0xcf,0xcc,
-0x00,0xce,0xd5,0x00,0xc7,0xcd,0x00,0xc6,0xcd,0x00,0x5f,0x72,0xcc,0x00,0x5f,0x72,
-0xe7,0x00,0x5f,0x72,0xe8,0x00,0x23,0x35,0x08,0x26,0x03,0xa1,0x7a,0x01,0xc6,0x0f,
-0x26,0x03,0xa1,0xfa,0x00,0xdf,0x00,0x55,0xfb,0x00,0xe0,0x00,0x55,0xfe,0x00,0xe3,
-0x00,0x55,0xff,0x00,0xe4,0x00,0x55,0xf8,0x00,0xdd,0x00,0x55,0xf9,0x00,0xde,0x00,
-0x55,0xfc,0x00,0xe1,0x00,0x55,0xfd,0x00,0xe2,0x00,0x55,0xb6,0xcd,0xcc,0xcb,0xcf,
-0xcd,0xca,0xa9,0x41,0x28,0xab,0x52,0x1c,0xae,0x01,0x7b,0xe8,0xfa,0xcd,0xf3,0xae,
-0xa4,0x00,0x00,0x35,0x3f,0xfa,0xcd,0xa4,0xb7,0xca,0xa9,0x41,0x24,0xab,0x52,0x1c,
-0xae,0x01,0x7b,0xf2,0x00,0xc7,0xcb,0xcf,0xcd,0xca,0xa9,0x41,0x23,0xab,0x52,0x1c,
-0xae,0x01,0x7b,0xf1,0x00,0xc7,0xcb,0xcf,0xcd,0xca,0xa9,0x41,0x22,0xab,0x52,0x1c,
-0xae,0x01,0x7b,0xf0,0x00,0xc7,0xa4,0xd6,0x92,0xa5,0x3c,0xef,0x00,0xc7,0xc3,0xcf,
-0xcd,0xca,0xa9,0x41,0x20,0xab,0x52,0x1c,0xae,0x01,0x7b,0xed,0x00,0x5f,0x72,0xee,
-0x00,0x01,0x35,0xec,0x00,0xc7,0xa4,0xd6,0x92,0xa5,0x3c,0xeb,0x00,0xc7,0xc3,0xcf,
-0xcd,0xca,0xa9,0x41,0x1c,0xab,0x52,0x1c,0xae,0x01,0x7b,0xea,0x00,0xc7,0xa4,0xd6,
-0x92,0xa5,0x3c,0xe9,0x00,0xc7,0xc3,0xcf,0xcd,0xca,0xa9,0x41,0x1a,0xab,0x52,0x1c,
-0xae,0x01,0x7b,0xe8,0x00,0xc7,0xa4,0xd6,0x92,0xa5,0x3c,0xe7,0x00,0xc7,0xc3,0xcf,
-0xcd,0xca,0xa9,0x41,0x18,0xab,0x52,0x1c,0xae,0x01,0x7b,0xe6,0x00,0xc7,0xa4,0xd6,
-0x92,0xa5,0x3c,0xe5,0x00,0xc7,0xc3,0xcf,0xcd,0xca,0xa9,0x41,0x16,0xab,0x52,0x1c,
-0xae,0x01,0x7b,0xe4,0x00,0xc7,0xa4,0xd6,0x92,0xa5,0x3c,0xe3,0x00,0xc7,0xc3,0xcf,
-0xcd,0xca,0xa9,0x41,0x14,0xab,0x52,0x1c,0xae,0x01,0x7b,0xe2,0x00,0xc7,0xa4,0xd6,
-0x92,0xa5,0x3c,0xe1,0x00,0xc7,0xc3,0xcf,0xcd,0xca,0xa9,0x41,0x12,0xab,0x52,0x1c,
-0xae,0x01,0x7b,0xe0,0x00,0xc7,0xa4,0xd6,0x92,0xa5,0x3c,0xdf,0x00,0xc7,0xc3,0xcf,
-0xcd,0xca,0xa9,0x41,0x10,0xab,0x52,0x1c,0xae,0x01,0x7b,0xde,0x00,0xc7,0xa4,0xd6,
-0x92,0xa5,0x3c,0xdd,0x00,0xc7,0xc3,0xcf,0xcd,0xca,0xa9,0x41,0x0e,0xab,0x52,0x1c,
-0xae,0x01,0x7b,0xdc,0x00,0xc7,0xcb,0xcf,0xcd,0xca,0xa9,0x41,0x0d,0xab,0x52,0x1c,
-0xae,0x01,0x7b,0x05,0xcf,0xcc,0x2d,0xcf,0xcc,0x03,0x27,0x02,0xa1,0x05,0xcf,0xcc,
-0x03,0x26,0x03,0xa1,0x05,0x01,0xc6,0xf7,0x00,0xc7,0x29,0xb6,0xf3,0x00,0x2a,0x00,
-0x55,0xf4,0x00,0x2b,0x00,0x55,0xf5,0x00,0x2c,0x00,0x55,0xf6,0x00,0x2d,0x00,0x55,
-0xf1,0x00,0xc7,0x13,0xb6,0x13,0xb6,0xef,0x00,0xcf,0x22,0xbe,0xf0,0x00,0xc7,0x23,
-0xb6,0xed,0x00,0xcf,0x20,0xbe,0xee,0x00,0xc7,0x21,0xb6,0xeb,0x00,0xcf,0x1e,0xbe,
-0xec,0x00,0xc7,0x1f,0xb6,0xe9,0x00,0xcf,0x1c,0xbe,0xea,0x00,0xc7,0x1d,0xb6,0xe7,
-0x00,0xcf,0x26,0xbe,0xe8,0x00,0xc7,0x27,0xb6,0xe5,0x00,0xcf,0x24,0xbe,0xe6,0x00,
-0xc7,0x25,0xb6,0xe3,0x00,0xcf,0x18,0xbe,0xe4,0x00,0xc7,0x19,0xb6,0xe1,0x00,0xcf,
-0x14,0xbe,0xe2,0x00,0xc7,0x15,0xb6,0xdf,0x00,0xcf,0x1a,0xbe,0xe0,0x00,0xc7,0x1b,
-0xb6,0xdd,0x00,0xcf,0x16,0xbe,0xde,0x00,0xc7,0x17,0xb6,0xdc,0x00,0xc7,0x28,0xb6,
-0xcd,0xcd,0xcc,0x03,0x24,0x1d,0xa1,0x11,0xb6,0x09,0x27,0x11,0x3d,0x01,0x6b,0x4a,
-0x11,0xb6,0x88,0x00,0xf0,0x70,0x1c,0x05,0x01,0x01,0x03,0x00,0x03,0x00,0x8f,0x00,
-0x46,0x00,0x1b,0x00,0xaa,0x01,0x1e,0x03,0x00,0x07,0x00,0x03,0x50,0x05,0x01,0x00,
-0x60,0xa0,0x18,0x05,0x01,0x01,0x06,0x00,0x03,0x00,0x70,0x00,0x40,0x00,0x18,0x00,
-0xb0,0x01,0x1b,0x03,0x00,0x07,0x00,0x03,0x50,0x05,0x01,0x00,0xe0,0x1b,0xfa,0x04,
-0x01,0x00,0x06,0x00,0x03,0x00,0x80,0x00,0x48,0x00,0x1c,0x00,0x90,0x01,0x3f,0x03,
-0x90,0x06,0x20,0x03,0x00,0x05,0x01,0x00,0xc0,0x5f,0x3b,0x04,0x00,0x01,0x06,0x00,
-0x03,0x00,0x20,0x00,0x30,0x00,0x14,0x00,0xa0,0x00,0x37,0x03,0xa0,0x05,0x20,0x03,
-0x00,0x05,0x01,0x00,0xe0,0x12,0xbd,0x04,0x01,0x00,0x07,0x00,0x03,0x00,0x80,0x00,
-0x40,0x00,0x1b,0x00,0x80,0x01,0x1e,0x03,0x80,0x06,0x00,0x03,0x00,0x05,0x01,0x00,
-0x90,0x69,0x11,0x04,0x00,0x01,0x07,0x00,0x03,0x00,0x20,0x00,0x30,0x00,0x13,0x00,
-0xa0,0x00,0x16,0x03,0xa0,0x05,0x00,0x03,0x00,0x05,0x01,0x00,0x40,0xd2,0xdf,0x03,
-0x00,0x00,0x06,0x00,0x03,0x00,0x88,0x00,0x18,0x00,0x23,0x00,0x40,0x01,0x26,0x03,
-0x40,0x05,0x00,0x03,0x00,0x04,0x01,0x00,0xf0,0xfb,0x02,0x02,0x01,0x01,0x08,0x00,
-0x06,0x00,0x70,0x00,0x10,0x00,0x1f,0x00,0xf0,0x00,0x05,0x02,0x40,0x04,0xe0,0x01,
-0x50,0x03,0x01,0x00,0x00,0x5a,0x62,0x02,0x01,0x01,0x04,0x00,0x01,0x00,0x80,0x00,
-0x28,0x00,0x1b,0x00,0x00,0x01,0x74,0x02,0x20,0x04,0x58,0x02,0x20,0x03,0x01,0x00,
-0x10,0xf7,0x6c,0x04,0x01,0x01,0x05,0x00,0x01,0x00,0x28,0x00,0xe0,0x06,0x19,0x00,
-0xe4,0x07,0xee,0x02,0xe4,0x0c,0xd0,0x02,0x00,0x05,0x01,0x00,0x10,0xf7,0x6c,0x04,
-0x01,0x01,0x05,0x00,0x01,0x00,0x28,0x00,0x74,0x09,0x19,0x00,0x78,0x0a,0xee,0x02,
-0x78,0x0f,0xd0,0x02,0x00,0x05,0x01,0x00,0x40,0x5f,0x8a,0x03,0x01,0x01,0x05,0x00,
-0x01,0x00,0x28,0x00,0xe0,0x06,0x19,0x00,0xe4,0x07,0xee,0x02,0xe4,0x0c,0xd0,0x02,
-0x00,0x05,0x01,0x00,0x10,0xf7,0x6c,0x04,0x01,0x01,0x05,0x00,0x01,0x00,0x2c,0x00,
-0x58,0x00,0x29,0x00,0x18,0x01,0x65,0x04,0x98,0x08,0x38,0x04,0x80,0x07,0x01,0x00,
-0x10,0xf7,0x6c,0x04,0x01,0x01,0x05,0x00,0x01,0x00,0x2c,0x00,0x10,0x02,0x29,0x00,
-0xd0,0x02,0x65,0x04,0x50,0x0a,0x38,0x04,0x80,0x07,0x01,0x00,0x10,0xf7,0x6c,0x04,
-0x01,0x01,0x05,0x00,0x01,0x00,0x2c,0x00,0x7e,0x02,0x29,0x00,0x3e,0x03,0x65,0x04,
-0xbe,0x0a,0x38,0x04,0x80,0x07,0x01,0x00,0x20,0xee,0xd9,0x08,0x01,0x01,0x05,0x00,
-0x01,0x00,0x2c,0x00,0x10,0x02,0x29,0x00,0xd0,0x02,0x65,0x04,0x50,0x0a,0x38,0x04,
-0x80,0x07,0x01,0x00,0x80,0xf9,0x37,0x03,0x00,0x00,0x05,0x00,0x01,0x00,0x80,0x00,
-0x18,0x00,0x2c,0x00,0x20,0x01,0x71,0x02,0xc0,0x06,0x40,0x02,0xa0,0x05,0x01,0x01,
-0xc0,0xfc,0x9b,0x01,0x00,0x00,0x03,0x00,0x01,0x00,0x7e,0x00,0x18,0x00,0x16,0x00,
-0x20,0x01,0x71,0x02,0xc0,0x06,0x20,0x01,0xa0,0x05,0x00,0x00,0x10,0xf7,0x6c,0x04,
-0x01,0x01,0x05,0x00,0x01,0x00,0x2c,0x00,0x10,0x02,0x14,0x00,0xd0,0x02,0x65,0x04,
-0x50,0x0a,0x1c,0x02,0x80,0x07,0x00,0x00,0x10,0xf7,0x6c,0x04,0x01,0x01,0x05,0x00,
-0x01,0x00,0x28,0x00,0xb8,0x01,0x19,0x00,0xbc,0x02,0xee,0x02,0xbc,0x07,0xd0,0x02,
-0x00,0x05,0x01,0x00,0xc0,0xfc,0x9b,0x01,0x00,0x00,0x05,0x00,0x01,0x00,0x40,0x00,
-0x0c,0x00,0x2c,0x00,0x90,0x00,0x71,0x02,0x60,0x03,0x40,0x02,0xd0,0x02,0x01,0x00,
-0x20,0xee,0xd9,0x08,0x01,0x01,0x05,0x00,0x01,0x00,0x2c,0x00,0x58,0x00,0x29,0x00,
-0x18,0x01,0x65,0x04,0x98,0x08,0x38,0x04,0x80,0x07,0x01,0x00,0x80,0xf9,0x37,0x03,
-0x00,0x00,0x06,0x00,0x07,0x00,0x7c,0x00,0x20,0x00,0x24,0x00,0x14,0x01,0x0d,0x02,
-0xb4,0x06,0xe0,0x01,0xa0,0x05,0x01,0x01,0xc0,0xfc,0x9b,0x01,0x00,0x00,0x03,0x00,
-0x04,0x00,0x7c,0x00,0x26,0x00,0x12,0x00,0x14,0x01,0x0d,0x02,0xb4,0x06,0xf0,0x00,
-0xa0,0x05,0x00,0x00,0x10,0xf7,0x6c,0x04,0x01,0x01,0x05,0x00,0x01,0x00,0x2c,0x00,
-0x58,0x00,0x14,0x00,0x18,0x01,0x65,0x04,0x98,0x08,0x1c,0x02,0x80,0x07,0x00,0x00,
-0x10,0xf7,0x6c,0x04,0x01,0x01,0x05,0x00,0x01,0x00,0x28,0x00,0x6e,0x00,0x19,0x00,
-0x72,0x01,0xee,0x02,0x72,0x06,0xd0,0x02,0x00,0x05,0x01,0x00,0xc0,0xfc,0x9b,0x01,
-0x00,0x00,0x06,0x00,0x07,0x00,0x3e,0x00,0x10,0x00,0x24,0x00,0x8a,0x00,0x0d,0x02,
-0x5a,0x03,0xe0,0x01,0xd0,0x02,0x01,0x00,0x80,0x85,0x80,0x01,0x00,0x00,0x02,0x00,
-0x01,0x00,0x60,0x00,0x10,0x00,0x23,0x00,0xa0,0x00,0x0d,0x02,0x20,0x03,0xe0,0x01,
-0x80,0x02,0x01,0x80,0xae,0x00,0xc7,0x51,0x20,0xc6,0x50,0x20,0x11,0x72,0x80,0x85,
-0x90,0xa6,0x00,0x32,0xa5,0x00,0x32,0xa4,0x00,0x32,0xa9,0x00,0x32,0xa8,0x00,0x32,
-0xa7,0x00,0x32,0x84,0x84,0x84,0x84,0x69,0x01,0x5a,0x72,0x68,0x01,0x5a,0x72,0x04,
-0x26,0x69,0x01,0xc6,0x0d,0x27,0x68,0x01,0xca,0x69,0x01,0xc6,0x32,0x01,0x5f,0x72,
-0x04,0x20,0x32,0x01,0x01,0x35,0x06,0x27,0x10,0xa5,0x04,0x7b,0x01,0x6b,0x10,0x40,
-0xc6,0x02,0x6b,0x11,0x40,0xc6,0x03,0x6b,0x12,0x40,0xc6,0x04,0x6b,0x13,0x40,0xc6,
-0x52,0xdf,0xcd,0x46,0x20,0xc7,0x46,0x20,0xc6,0x41,0x20,0x5f,0x72,0x0a,0x42,0x20,
-0x0d,0x72,0x88,0x88,0x88,0x88,0xa7,0x00,0x3b,0xa8,0x00,0x3b,0xa9,0x00,0x3b,0xa4,
-0x00,0x3b,0xa5,0x00,0x3b,0xa6,0x00,0x3b,0x89,0x90,0x80,0x85,0x90,0xa6,0x00,0x32,
-0xa5,0x00,0x32,0xa4,0x00,0x32,0xa9,0x00,0x32,0xa8,0x00,0x32,0xa7,0x00,0x32,0x00,
-0xc0,0xcd,0x15,0x20,0x10,0x72,0x07,0x27,0x09,0x2b,0x10,0xb6,0x12,0x20,0x01,0x35,
-0xa7,0x00,0x3b,0xa8,0x00,0x3b,0xa9,0x00,0x3b,0xa4,0x00,0x3b,0xa5,0x00,0x3b,0xa6,
-0x00,0x3b,0x89,0x90,0x80,0x0c,0x40,0x00,0x35,0x0d,0x40,0x00,0x35,0x0e,0x40,0x00,
-0x35,0x0f,0x40,0x04,0x35,0x11,0x20,0x80,0x35,0x80,0x11,0x20,0x40,0x35,0x80,0x11,
-0x20,0x20,0x35,0x80,0x11,0x20,0x10,0x35,0x80,0x11,0x20,0x08,0x35,0x80,0x17,0x20,
-0x14,0x72,0x80,0x17,0x20,0x15,0x72,0x05,0x17,0x20,0x05,0x72,0x11,0x20,0x04,0x35,
-0x80,0x75,0x01,0xc7,0x4a,0x05,0x20,0x1a,0x72,0x06,0x20,0x18,0x72,0x11,0x20,0xc7,
-0x02,0xa6,0x80,0x75,0x01,0xc7,0x05,0x20,0x1a,0x72,0x06,0x20,0x19,0x72,0x11,0x20,
-0xc7,0x01,0xa6,0x80,0x04,0x88,0x00,0x35,0x05,0x88,0x30,0x35,0x06,0x88,0x00,0x35,
-0x07,0x88,0x00,0x35,0x10,0x20,0x80,0x35,0x81,0xe8,0xfa,0xcd,0xbc,0xae,0xa4,0x00,
-0x84,0x35,0x81,0xa4,0xb7,0x00,0xa9,0x41,0x01,0xab,0x80,0x85,0x90,0xa6,0x00,0x32,
-0xa5,0x00,0x32,0xa4,0x00,0x32,0xa9,0x00,0x32,0xa8,0x00,0x32,0xa7,0x00,0x32,0xa3,
-0x00,0x32,0xa2,0x00,0x32,0xa1,0x00,0x32,0xa0,0x00,0x32,0x84,0x84,0x84,0x84,0x84,
-0x84,0xe8,0xfa,0xcd,0xa0,0xae,0xa4,0x00,0x84,0x35,0xd9,0xfb,0xcd,0x33,0xad,0x5b,
-0xa0,0x3f,0xa1,0x3f,0xa2,0x1f,0x07,0xfb,0xcd,0xaa,0x00,0xce,0xab,0x00,0xc6,0x03,
-0x6b,0x80,0xa4,0x03,0x7b,0x04,0x6b,0x4f,0x01,0x6b,0xa0,0x84,0xc6,0x02,0x6b,0xa1,
-0x84,0xc6,0x03,0x6b,0xa2,0x84,0xc6,0x04,0x6b,0xa3,0x84,0xc6,0x84,0x84,0xaa,0x00,
-0xcf,0xab,0x00,0xc7,0xab,0xdf,0xcd,0xc0,0x00,0xce,0xc1,0x00,0xc6,0xac,0x00,0x3b,
-0xad,0x00,0x3b,0x0f,0x20,0x8f,0xdf,0xcd,0xc0,0x00,0xce,0xc1,0x00,0xc6,0xac,0x00,
-0x3b,0xad,0x00,0x3b,0x11,0x24,0x05,0xe2,0x72,0xac,0x00,0xc6,0x06,0xe0,0x72,0xad,
-0x00,0xc6,0x1f,0x24,0x05,0xe2,0x72,0xc0,0x00,0xc6,0x06,0xe0,0x72,0xc1,0x00,0xc6,
-0x1c,0x25,0xac,0x00,0xc2,0x05,0x7b,0xad,0x00,0xc0,0x06,0x7b,0x0c,0x24,0xc0,0x00,
-0xc2,0x05,0x7b,0xc1,0x00,0xc0,0x06,0x7b,0x5c,0x20,0xaa,0x00,0xcf,0xc0,0x00,0xce,
-0xab,0x00,0xc1,0x00,0x55,0x0d,0x26,0x06,0x01,0xc6,0x0d,0x20,0xac,0x00,0xce,0xab,
-0x00,0xc7,0xad,0x00,0xc6,0x0b,0x27,0x4a,0x05,0x01,0xc6,0x07,0x20,0x01,0x35,0x07,
-0x20,0x03,0x35,0x08,0x26,0x04,0xa1,0x05,0x20,0x1d,0x72,0x05,0x20,0x1c,0x72,0x08,
-0x25,0x02,0xa1,0xbf,0x00,0xc6,0x1b,0x26,0xc0,0x00,0xc1,0x05,0x7b,0x22,0x26,0xc1,
-0x00,0xc1,0x06,0x7b,0x29,0x26,0x4a,0x05,0x01,0xc6,0xac,0x00,0x5f,0x72,0xad,0x00,
-0xc7,0x06,0xa6,0xce,0xc8,0xcd,0xa2,0xb7,0x18,0xaa,0xa2,0xb6,0x1f,0xfc,0xcd,0xc6,
-0xc8,0xcd,0x5b,0x12,0x20,0x0a,0xa6,0xce,0xc8,0xcd,0xa2,0x18,0x1f,0xfc,0xcd,0xc6,
-0xc8,0xcd,0x5b,0x10,0x24,0x00,0xa2,0x05,0x7b,0x0a,0xa0,0x06,0x7b,0x1a,0x25,0x00,
-0xa2,0x05,0x7b,0x06,0xa0,0x06,0x7b,0x03,0x6b,0xc7,0xa4,0x03,0x7b,0x01,0x6b,0xbc,
-0x84,0xc6,0x02,0x6b,0xbd,0x84,0xc6,0x03,0x6b,0xbe,0x84,0xc6,0x04,0x6b,0xbf,0x84,
-0xc6,0x57,0x27,0x06,0x01,0xc6,0x06,0x6b,0xa7,0x83,0xc6,0x05,0x6b,0xa6,0x83,0xc6,
-0xab,0x00,0x5f,0x72,0xaa,0x00,0x5f,0x72,0xad,0x00,0x5f,0x72,0xac,0x00,0x5f,0x72,
-0x10,0x20,0x40,0x35,0x88,0x88,0x88,0x88,0x88,0x88,0xa0,0x00,0x3b,0xa1,0x00,0x3b,
-0xa2,0x00,0x3b,0xa3,0x00,0x3b,0xa7,0x00,0x3b,0xa8,0x00,0x3b,0xa9,0x00,0x3b,0xa4,
-0x00,0x3b,0xa5,0x00,0x3b,0xa6,0x00,0x3b,0x89,0x90,0x81,0x48,0x83,0x00,0x35,0x49,
-0x83,0x00,0x35,0x4a,0x83,0x00,0x35,0x4b,0x83,0x0f,0x35,0x80,0x85,0x90,0xa6,0x00,
-0x32,0xa5,0x00,0x32,0xa4,0x00,0x32,0xa9,0x00,0x32,0xa8,0x00,0x32,0xa7,0x00,0x32,
-0x84,0x84,0x84,0x84,0x76,0x01,0x5f,0x72,0xb3,0xe4,0xcd,0x20,0xad,0x05,0x26,0x4a,
-0x76,0x01,0xc6,0x0b,0x26,0x03,0xa1,0x05,0x01,0xc6,0x7c,0x01,0x5c,0x72,0x04,0x27,
-0x0f,0xa1,0x7c,0x01,0xc6,0x0b,0x20,0x75,0x01,0x01,0x35,0x11,0x26,0x7c,0x01,0x5a,
-0x72,0x17,0x27,0x7c,0x01,0xc6,0x11,0x26,0x03,0xea,0x72,0x04,0x7b,0x07,0x27,0x4c,
-0x03,0x7b,0x05,0x26,0x4c,0x04,0x7b,0x11,0x27,0x03,0x7b,0x04,0x26,0x4a,0x04,0x7b,
-0x13,0xd8,0xcd,0x03,0xee,0x72,0x9f,0x03,0x6b,0x04,0xef,0x72,0x03,0xe2,0x72,0x41,
-0x04,0xe0,0x72,0x5f,0x01,0xa6,0x03,0x6b,0x01,0xe2,0x72,0x03,0x7b,0x04,0x6b,0x02,
-0xe0,0x72,0x04,0x7b,0x0e,0x24,0x03,0xe2,0x72,0x9f,0x04,0xe0,0x72,0x46,0x54,0x01,
-0xef,0x72,0x02,0x6b,0x46,0x54,0xe3,0x00,0xce,0xe4,0x00,0xc6,0x08,0x20,0xe3,0x00,
-0xce,0xe4,0x00,0xc6,0x08,0x26,0x4a,0xdc,0x00,0xc6,0xe3,0x26,0x03,0xe1,0x72,0xa6,
-0x83,0xc6,0xeb,0x26,0x04,0xe1,0x72,0xa7,0x83,0xc6,0x04,0x6b,0xa7,0x83,0xc6,0x03,
-0x6b,0xa6,0x83,0xc6,0xd6,0xc6,0xcc,0x84,0x84,0x84,0x84,0xb3,0x00,0x35,0x35,0xb4,
-0x00,0x86,0x35,0xb5,0x00,0x37,0x35,0xb6,0x00,0xbd,0x35,0x7c,0x01,0x0f,0x35,0x7e,
-0x01,0x01,0x35,0x05,0xc7,0xcd,0xc7,0xdf,0xcd,0xb7,0x00,0x3b,0xb8,0x00,0x3b,0xb9,
-0x00,0x3b,0xba,0x00,0x3b,0x31,0x26,0x7e,0x01,0xc6,0x81,0xe4,0xcd,0x03,0x27,0x7c,
-0x01,0xc6,0xec,0xc6,0xcc,0x03,0x26,0x02,0xa1,0x74,0x01,0xc6,0xd6,0xc6,0xcc,0x03,
-0x27,0x02,0xa1,0x05,0x01,0xc6,0x10,0x20,0x20,0x35,0x88,0x88,0x88,0x88,0xa7,0x00,
-0x3b,0xa8,0x00,0x3b,0xa9,0x00,0x3b,0xa4,0x00,0x3b,0xa5,0x00,0x3b,0xa6,0x00,0x3b,
-0x89,0x90,0x80,0x10,0x20,0x08,0x35,0x81,0x1f,0xfc,0xcd,0xa4,0xb7,0x00,0xa9,0x41,
-0x02,0xab,0x80,0x85,0x90,0xa6,0x00,0x32,0xa5,0x00,0x32,0xa4,0x00,0x32,0xa9,0x00,
-0x32,0xa8,0x00,0x32,0xa7,0x00,0x32,0xa3,0x00,0x32,0xa2,0x00,0x32,0xa1,0x00,0x32,
-0xa0,0x00,0x32,0x84,0x84,0x84,0x84,0x84,0x41,0xe4,0xcd,0x75,0x01,0x5f,0x72,0x07,
-0x26,0x4a,0x75,0x01,0xc6,0x06,0x27,0x4a,0x05,0x01,0xc6,0xd3,0xcf,0xcd,0x77,0x01,
-0xc7,0x06,0x26,0x4a,0x77,0x01,0xc6,0xe8,0xfa,0xcd,0xa4,0xbf,0x84,0xae,0xa3,0x1a,
-0x4e,0xad,0x5b,0x09,0x20,0x04,0xae,0xa4,0x00,0x44,0x35,0xa0,0x3f,0x5b,0xad,0x5b,
-0x02,0x6b,0x08,0x84,0xc6,0x03,0x6b,0x09,0x84,0xc6,0x04,0x6b,0x0a,0x84,0xc6,0x05,
-0x6b,0x0b,0x84,0xc6,0xe8,0xfa,0xcd,0xa4,0xbf,0x84,0xae,0xa3,0x1b,0x7b,0xad,0x5b,
-0x2d,0x27,0x07,0x01,0xc6,0x32,0x27,0xc3,0x00,0xc6,0x02,0x6b,0x84,0x84,0xc6,0x03,
-0x6b,0x85,0x84,0xc6,0x04,0x6b,0x86,0x84,0xc6,0x05,0x6b,0x87,0x84,0xc6,0x1b,0x01,
-0x5c,0x72,0x04,0x27,0x4c,0x1b,0x01,0xc6,0x0a,0x20,0x1b,0x01,0x5f,0x72,0x06,0x27,
-0x7c,0x01,0xc6,0x7d,0x01,0x5c,0x72,0x04,0x24,0xff,0xa1,0x7d,0x01,0xc6,0x76,0x01,
-0x01,0x35,0xe8,0xfa,0xcd,0xa0,0xae,0xa4,0x00,0x84,0x35,0xa0,0x1f,0xbe,0xc5,0xcd,
-0x5b,0x02,0x6b,0xa0,0x84,0xc6,0x03,0x6b,0xa1,0x84,0xc6,0x04,0x6b,0xa2,0x84,0xc6,
-0x05,0x6b,0xa3,0x84,0xc6,0x84,0x84,0x84,0x84,0xc7,0xdf,0xcd,0xb7,0x00,0x3b,0xb8,
-0x00,0x3b,0xb9,0x00,0x3b,0xba,0x00,0x3b,0x7e,0x01,0x5f,0x72,0x41,0x25,0x04,0xa1,
-0x7d,0x01,0xc6,0x65,0x27,0x4a,0x05,0x01,0xc6,0xe8,0xfa,0xcd,0x9c,0xae,0xa4,0x00,
-0x83,0x35,0xa0,0xb7,0xa1,0xb7,0xa2,0xb7,0x4f,0xa3,0xb7,0x01,0x6b,0x9f,0x83,0xc6,
-0x05,0x20,0x14,0x72,0x10,0x20,0x06,0x35,0x88,0x88,0x88,0x88,0x88,0xa0,0x00,0x3b,
-0xa1,0x00,0x3b,0xa2,0x00,0x3b,0xa3,0x00,0x3b,0xa7,0x00,0x3b,0xa8,0x00,0x3b,0xa9,
-0x00,0x3b,0xa4,0x00,0x3b,0xa5,0x00,0x3b,0xa6,0x00,0x3b,0x89,0x90,0x81,0xa4,0x00,
-0x8c,0x35,0xa0,0xb7,0xa1,0xb7,0xa2,0xb7,0x4f,0xa3,0xb7,0x80,0x85,0x90,0xa6,0x00,
-0x32,0xa5,0x00,0x32,0xa4,0x00,0x32,0xa9,0x00,0x32,0xa8,0x00,0x32,0xa7,0x00,0x32,
-0xa3,0x00,0x32,0xa2,0x00,0x32,0xa1,0x00,0x32,0xa0,0x00,0x32,0x84,0xe8,0xfa,0xcd,
-0x0c,0xae,0x27,0xad,0xf0,0xa4,0x01,0x7b,0x1c,0x01,0x5f,0x72,0x05,0x20,0x16,0x72,
-0x06,0x20,0xc7,0x05,0xaa,0x06,0x20,0xc6,0x1b,0x27,0x04,0xa5,0x01,0x7b,0xe8,0xfa,
-0xcd,0x0c,0xae,0x48,0xad,0xf0,0xa4,0x05,0x20,0x16,0x72,0x06,0x20,0x14,0x72,0x11,
-0x20,0x1c,0x01,0x5a,0x72,0x60,0xc3,0xcd,0x02,0xa6,0x05,0x26,0x4a,0x05,0x20,0x4f,
-0x03,0x25,0x02,0xa1,0x1c,0x01,0xc6,0xe8,0xfa,0xcd,0x10,0xae,0x71,0xad,0x1d,0x01,
-0xd6,0x22,0x27,0x1c,0x01,0xce,0x59,0x27,0x0f,0xa5,0x01,0x7b,0xe8,0xfa,0xcd,0x0c,
-0xae,0x65,0xc4,0xcd,0x0f,0xa4,0x05,0x20,0x16,0x72,0x06,0x20,0x12,0x72,0x09,0x01,
-0x01,0x35,0x18,0x27,0x20,0xa5,0x01,0x7b,0x98,0xad,0x4f,0x05,0x27,0x80,0xa5,0x01,
-0x7b,0x0b,0x01,0xd7,0x17,0x8c,0xc6,0x0a,0x01,0x5c,0x72,0x0a,0x01,0xce,0x0f,0x27,
-0x80,0xa5,0x07,0x20,0x0a,0x01,0xcf,0x06,0x20,0x13,0x72,0x09,0x27,0x10,0xa5,0x20,
-0x26,0x09,0x01,0xce,0x01,0x6b,0x0f,0x8c,0xc6,0x10,0x20,0x10,0x35,0x88,0xa0,0x00,
-0x3b,0xa1,0x00,0x3b,0xa2,0x00,0x3b,0xa3,0x00,0x3b,0xa7,0x00,0x3b,0xa8,0x00,0x3b,
-0xa9,0x00,0x3b,0xa4,0x00,0x3b,0xa5,0x00,0x3b,0xa6,0x00,0x3b,0x89,0x90,0xe8,0xfa,
-0xcc,0x0c,0xae,0xa4,0x00,0x8c,0x35,0xa0,0xb7,0xa1,0xb7,0xa2,0xb7,0x4f,0xa3,0xb7,
-0x80,0x85,0x90,0xa6,0x00,0x32,0xa5,0x00,0x32,0xa4,0x00,0x32,0xa9,0x00,0x32,0xa8,
-0x00,0x32,0xa7,0x00,0x32,0x84,0x84,0x84,0x84,0xa0,0x84,0xc7,0x01,0x7b,0xa1,0x84,
-0xc7,0x02,0x7b,0xa2,0x84,0xc7,0x03,0x7b,0xa3,0x84,0xc7,0x04,0x7b,0x76,0x01,0x01,
-0x35,0x01,0x6b,0x7f,0xa4,0x01,0x7b,0x0a,0x20,0x01,0x6b,0x80,0xaa,0x01,0x7b,0x12,
-0x27,0x02,0xa1,0x74,0x01,0xc6,0x0f,0x26,0x03,0xa1,0x04,0x27,0x02,0xa1,0x05,0x01,
-0xc6,0x1a,0x27,0x06,0x01,0xc6,0x05,0x26,0x07,0x01,0xc6,0x01,0x6b,0xa0,0x84,0xc6,
-0x02,0x6b,0xa1,0x84,0xc6,0x03,0x6b,0xa2,0x84,0xc6,0x04,0x6b,0xa3,0x84,0xc6,0x7d,
-0x01,0x5f,0x72,0x74,0x01,0xc7,0x03,0xa4,0x83,0x84,0xc6,0x15,0xe0,0xcd,0x03,0x26,
-0x4a,0x73,0x01,0xc6,0x05,0x20,0x12,0x72,0x10,0x20,0x01,0x35,0x88,0x88,0x88,0x88,
-0xa7,0x00,0x3b,0xa8,0x00,0x3b,0xa9,0x00,0x3b,0xa4,0x00,0x3b,0xa5,0x00,0x3b,0xa6,
-0x00,0x3b,0x89,0x90,0x80,0x12,0x20,0x10,0x35,0x80,0xe6,0x20,0x8f,0xe9,0x26,0x01,
-0x7b,0x6f,0xf8,0xcd,0x01,0x7b,0x4d,0xf1,0xcd,0x05,0x24,0x20,0xa1,0x0c,0x27,0x01,
-0x6b,0x28,0xc0,0xcd,0x79,0xc0,0xcd,0x88,0x81,0x84,0x06,0x20,0x08,0x35,0x9a,0x1a,
-0x20,0x10,0x72,0x15,0x20,0xc7,0xee,0xa4,0x15,0x20,0xc6,0x14,0x20,0xc7,0x7c,0xa4,
-0x14,0x20,0xc6,0x13,0x20,0xc7,0x08,0xa4,0x13,0x20,0xc6,0x52,0xdf,0xcd,0x84,0x84,
-0x84,0x84,0x84,0x84,0x84,0x84,0x31,0xd5,0xcd,0x01,0x01,0x3b,0x02,0x01,0x3b,0x03,
-0x01,0x3b,0x04,0x01,0x3b,0x01,0x4b,0x80,0x4b,0x85,0x4b,0x80,0x4b,0xb0,0x84,0x00,
-0x35,0xb1,0x84,0x00,0x35,0xb2,0x84,0x00,0x35,0xb3,0x84,0x13,0x35,0xa4,0x84,0x00,
-0x35,0xa5,0x84,0x00,0x35,0xa6,0x84,0x00,0x35,0xa7,0x84,0x00,0x35,0xa0,0x84,0x00,
-0x35,0xa1,0x84,0x00,0x35,0xa2,0x84,0x00,0x35,0xa3,0x84,0x00,0x35,0x0c,0x8c,0x00,
-0x35,0x0d,0x8c,0x00,0x35,0x0e,0x8c,0x00,0x35,0x0f,0x8c,0x00,0x35,0x18,0x8c,0x00,
-0x35,0x19,0x8c,0x00,0x35,0x1a,0x8c,0x00,0x35,0x1b,0x8c,0x03,0x35,0x04,0x8c,0x00,
-0x35,0x05,0x8c,0x00,0x35,0x06,0x8c,0x00,0x35,0x07,0x8c,0x0a,0x35,0x00,0x8c,0x00,
-0x35,0x01,0x8c,0x00,0x35,0x02,0x8c,0x00,0x35,0x03,0x8c,0x00,0x35,0x1c,0x8c,0x00,
-0x35,0x1d,0x8c,0x00,0x35,0x1e,0x8c,0x00,0x35,0x1f,0x8c,0x04,0x35,0x15,0xe0,0xcd,
-0x29,0xe1,0xcd,0x24,0x83,0x00,0x35,0x25,0x83,0x00,0x35,0x26,0x83,0x02,0x35,0x27,
-0x83,0x00,0x35,0x84,0x84,0x00,0x35,0x85,0x84,0x00,0x35,0x86,0x84,0x00,0x35,0x87,
-0x84,0x20,0x35,0xb4,0x84,0x00,0x35,0xb5,0x84,0x00,0x35,0xb6,0x84,0x00,0x35,0xb7,
-0x84,0x80,0x35,0x18,0x84,0x00,0x35,0x19,0x84,0x00,0x35,0x1a,0x84,0x00,0x35,0x1b,
-0x84,0x00,0x35,0x78,0x84,0x00,0x35,0x79,0x84,0x00,0x35,0x7a,0x84,0x00,0x35,0x7b,
-0x84,0x00,0x35,0x3f,0x20,0x01,0x35,0x3d,0x20,0xc7,0xff,0xa6,0x3c,0x20,0xc7,0x04,
-0xa6,0x3e,0x20,0xfe,0x35,0x01,0x01,0x02,0x35,0x02,0x01,0x49,0x35,0x03,0x01,0xf0,
-0x35,0x04,0x01,0xc7,0x0f,0x20,0x01,0x01,0x01,0x35,0x02,0x01,0x9b,0x35,0x03,0x01,
-0xfc,0x35,0x04,0x01,0xc0,0x35,0x0c,0x20,0x02,0x01,0x8c,0x35,0x03,0x01,0xba,0x35,
-0x04,0x01,0x80,0x35,0x1a,0x20,0x02,0x01,0x24,0x35,0x03,0x01,0xf8,0x35,0x04,0x01,
-0xc7,0x3c,0x20,0x01,0x01,0x5f,0x72,0x02,0x01,0x5f,0x72,0x03,0x01,0x5f,0x72,0x04,
-0x01,0x5f,0x72,0x3f,0x27,0x4a,0x30,0x27,0x4a,0x25,0x27,0x4a,0x1b,0x27,0x0f,0xa4,
-0x08,0x20,0xc6,0x7f,0x01,0xc7,0x0f,0xa4,0x4e,0x03,0x20,0xc6,0xf2,0x25,0x10,0xa1,
-0x01,0x6b,0x4c,0x58,0x01,0x4f,0x72,0x01,0xee,0x72,0x01,0x6b,0x4f,0xbf,0x00,0x5f,
-0x72,0xc1,0x00,0x5f,0x72,0xc0,0x00,0x5f,0x72,0x69,0x01,0x5f,0x72,0x68,0x01,0x5f,
-0x72,0x30,0x01,0x5f,0x72,0x38,0x01,0x5f,0x72,0x31,0x01,0x5f,0x72,0x32,0x01,0x5f,
-0x72,0x1b,0x01,0x5f,0x72,0x77,0x01,0x5f,0x72,0x7a,0x01,0x5f,0x72,0x06,0x01,0x5f,
-0x72,0x07,0x01,0x5f,0x72,0xae,0x00,0x5f,0x72,0x09,0x01,0x5f,0x72,0x1c,0x01,0x5f,
-0x72,0x0a,0x01,0x5f,0x72,0xc2,0x00,0x5f,0x72,0xc3,0x00,0x5f,0x72,0x05,0x01,0x5f,
-0x72,0x11,0x3f,0x10,0x3f,0x08,0x01,0x5f,0x72,0x56,0x01,0x5f,0x72,0x57,0x01,0x5f,
-0x72,0x7b,0x01,0x5f,0x72,0x7c,0x01,0xff,0x35,0x7e,0x01,0x5f,0x72,0x76,0x01,0x5f,
-0x72,0x9b,0x06,0x20,0x5f,0x72,0x88,0x81,0x84,0xe3,0xad,0xf4,0x25,0x40,0xa1,0x01,
-0x6b,0x4c,0x12,0x6f,0x01,0xee,0x72,0x01,0x6b,0x4f,0x88,0x81,0x05,0x20,0x10,0x72,
-0x15,0x20,0x11,0x72,0x10,0x1e,0x98,0xc2,0xcc,0x8b,0xff,0xa6,0x04,0xae,0x81,0x85,
-0x01,0x7b,0x9a,0x56,0x01,0xc7,0x0f,0xa4,0x56,0x01,0xc6,0x58,0x01,0x4f,0x72,0x56,
-0x01,0x5c,0x72,0x01,0x6b,0x58,0x01,0xd6,0x56,0x01,0xce,0x18,0x27,0x56,0x01,0xc1,
-0x57,0x01,0xc6,0x9b,0x01,0x6b,0x4f,0x88,0x81,0x84,0x9a,0x57,0x01,0xc7,0x0f,0xa4,
-0x57,0x01,0xc6,0x58,0x01,0xd7,0x57,0x01,0x5c,0x72,0x57,0x01,0xce,0x01,0x7b,0x14,
-0x27,0x01,0xe1,0x72,0x58,0x01,0xd6,0x97,0x0f,0xa4,0x4a,0x57,0x01,0xc6,0x9b,0x88,
-};
-
diff --git a/arch/arm/mach-ux500/include/mach/av8100_p.h b/arch/arm/mach-ux500/include/mach/av8100_p.h
deleted file mode 100755
index 9eadd7c2887..00000000000
--- a/arch/arm/mach-ux500/include/mach/av8100_p.h
+++ /dev/null
@@ -1,227 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * License terms:
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <mach/av8100.h>
-
-/* defines for av8100_ */
-#define AV8100_COMMAND_OFFSET 0x10
-#define AV8100_COMMAND_MAX_LENGTH 0x81
-#define GPIO_AV8100_RSTN 196
-#define GPIO_AV8100_INT 192
-#define AV8100_DRIVER_MINOR_NUMBER 240
-
-/* Standby register */
-#define STANDBY_HPDS_HDMI_PLUGGED 0x04
-#define STANDBY_CVBS_TV_CABLE_PLUGGED 0x08
-
-/* Standby interrupts */
-#define HDMI_HOTPLUG_INTERRUPT 0x1
-#define HDMI_HOTPLUG_INTERRUPT_MASK 0xFE
-#define CVBS_PLUG_INTERRUPT 0x2
-#define CVBS_PLUG_INTERRUPT_MASK 0xFD
-#define STANDBY_INTERRUPT_MASK_ALL 0xF0
-
-/* General interrupts */
-#define UNDER_OVER_FLOW_INTERRUPT 0x20
-#define UNDER_OVER_FLOW_INTERRUPT_MASK 0xDF
-#define TE_INTERRUPT 0x40
-#define TE_INTERRUPT_MASK 0xCF
-#define GENERAL_INTERRUPT_MASK_ALL 0x00
-
-/* General status */
-#define AV8100_GENERAL_STATUS_UC_READY 0x8
-
-#define REG_16_8_LSB(p) (unsigned char)(p & 0xFF)
-#define REG_16_8_MSB(p) (unsigned char)((p & 0xFF00)>>8)
-#define REG_32_8_MSB(p) (unsigned char)((p & 0xFF000000)>>24)
-#define REG_32_8_MMSB(p) (unsigned char)((p & 0x00FF0000)>>16)
-#define REG_32_8_MLSB(p) (unsigned char)((p & 0x0000FF00)>>8)
-#define REG_32_8_LSB(p) (unsigned char)(p & 0x000000FF)
-
-/**
- * struct av8100_cea - CEA(consumer electronic access) standard structure
- * @cea_id:
- * @cea_nb:
- * @vtotale:
- **/
-
- typedef struct {
- char cea_id[40] ;
- int cea_nb ;
- int vtotale;
- int vactive;
- int vsbp ;
- int vslen ;
- int vsfp;
- char vpol[5];
- int htotale;
- int hactive;
- int hbp ;
- int hslen ;
- int hfp;
- int frequence;
- char hpol[5];
- int reg_line_duration;
- int blkoel_duration;
- int uix4;
- int pll_mult;
- int pll_div;
-}av8100_cea;
-
-/**
- * struct av8100_data - av8100_ internal structure
- * @client: pointer to i2c client
- * @work: work_struct scheduled during bottom half
- * @sem: semaphore used for data protection
- * @device_type: hdmi or cvbs
- * @edid: extended display identification data
- **/
-struct av8100_data{
- struct i2c_client *client;
- struct work_struct work;
- struct semaphore sem;
- char device_type;
- char edid[127];
-};
-
-/**
- * struct av8100_platform_data - av8100_ platform data
- * @irq: irq num
- **/
-struct av8100_platform_data {
- unsigned gpio_base;
- int irq;
-};
-
-typedef struct {
- u16 c0;
- u16 c1;
- u16 c2;
- u16 c3;
- u16 c4;
- u16 c5;
- u16 c6;
- u16 c7;
- u16 c8;
- u16 a_offset;
- u16 b_offset;
- u16 c_offset;
- u8 l_max;
- u8 l_min;
- u8 c_max;
- u8 c_min;
-} av8100_color_space_conversion_cmd;
-
-/**
- * struct av8100_video_input_format_cmd - video input format structure
- * @dsi_input_mode:
- * @input_pixel_format:
- * @total_horizontal_pixel:
- **/
-typedef struct {
- av8100_dsi_mode dsi_input_mode;
- av8100_pixel_format input_pixel_format;
- unsigned short total_horizontal_pixel; /*number of total horizontal pixels in the frame*/
- unsigned short total_horizontal_active_pixel; /*number of total horizontal active pixels in the frame*/
- unsigned short total_vertical_lines; /*number of total vertical lines in the frame*/
- unsigned short total_vertical_active_lines; /*number of total vertical active lines*/
- av8100_video_mode video_mode;
- av8100_dsi_nb_data_lane nb_data_lane;
- unsigned char nb_virtual_ch_command_mode;
- unsigned char nb_virtual_ch_video_mode;
- unsigned short TE_line_nb; /* Tearing effect line number*/
- av8100_te_config TE_config;
- unsigned long master_clock_freq; /* Master clock frequency in HZ */
- unsigned char ui_x4;
-} av8100_video_input_format_cmd;
-
-/**
- * struct av8100_video_output_format_cmd - video output format structure
- * @dsi_input_mode:
- * @input_pixel_format:
- * @total_horizontal_pixel:
- **/
-typedef struct {
- av8100_output_CEA_VESA video_output_cea_vesa;
- av8100_video_sync_pol vsync_polarity;
- av8100_video_sync_pol hsync_polarity;
- unsigned short total_horizontal_pixel; /*number of total horizontal pixels in the frame*/
- unsigned short total_horizontal_active_pixel; /*number of total horizontal active pixels in the frame*/
- unsigned short total_vertical_in_half_lines; /*number of total vertical lines in the frame*/
- unsigned short total_vertical_active_in_half_lines; /*number of total vertical active lines*/
- unsigned short hsync_start_in_pixel;
- unsigned short hsync_length_in_pixel;
- unsigned short vsync_start_in_half_line;
- unsigned short vsync_length_in_half_line;
- unsigned long pixel_clock_freq_Hz;
-} av8100_video_output_format_cmd;
-/**
- * struct av8100_pattern_generator_cmd - pattern generator format structure
- * @pattern_type:
- * @pattern_video_format:
- * @pattern_audio_mode:
- **/
-typedef struct {
- av8100_pattern_type pattern_type;
- av8100_pattern_format pattern_video_format;
- av8100_pattern_audio pattern_audio_mode;
-} av8100_pattern_generator_cmd;
-/**
- * struct av8100_audio_input_format_cmd - audio input format structure
- * @audio_input_if_format:
- * @i2s_input_nb:
- * @sample_audio_freq:
- **/
-typedef struct {
- av8100_audio_if_format audio_input_if_format; /* mode of the MSP*/
- unsigned char i2s_input_nb; /* 0, 1 2 3 4*/
- av8100_sample_freq sample_audio_freq;
- av8100_audio_word_length audio_word_lg;
- av8100_audio_format audio_format;
- av8100_audio_if_mode audio_if_mode;
- av8100_audio_mute audio_mute;
-} av8100_audio_input_format_cmd;
-/**
- * struct av8100_video_scaling_format_cmd - video scaling format structure
- * @h_start_in_pixel:
- * @h_stop_in_pixel:
- * @v_start_in_line:
- **/
-typedef struct {
- unsigned short h_start_in_pixel;
- unsigned short h_stop_in_pixel;
- unsigned short v_start_in_line;
- unsigned short v_stop_in_line;
-} av8100_video_scaling_format_cmd;
-/**
- * struct av8100_hdmi_cmd - hdmi command structure
- * @hdmi_mode:
- * @hdmi_format:
- * @dvi_format:
- **/
-typedef struct {
- av8100_hdmi_mode hdmi_mode;
- av8100_hdmi_format hdmi_format;
- av8100_DVI_format dvi_format; /* used only if HDMI_format = DVI*/
-} av8100_hdmi_cmd;
-
-/**
- * struct av8100_denc_cmd - denc command structure
- **/
-typedef struct {
- av8100_TV_lines tv_lines;
- av8100_TV_std tv_std;
- av8100_DENC_State denc;
- av8100_macrovision_state macrovision;
- av8100_internal_generator_state internal_generator;
- av8100_chroma_cws_capture_state chroma;
-} av8100_denc_cmd;
-
-/* STWav8100 Private functions */
diff --git a/arch/arm/mach-ux500/include/mach/devices.h b/arch/arm/mach-ux500/include/mach/devices.h
index 0c998217275..a5973d85d7d 100755
--- a/arch/arm/mach-ux500/include/mach/devices.h
+++ b/arch/arm/mach-ux500/include/mach/devices.h
@@ -27,10 +27,7 @@ extern struct platform_device ux500_i2c_controller1;
extern struct platform_device ux500_i2c_controller2;
extern struct platform_device ux500_i2c_controller3;
extern struct platform_device u8500_i2c4_device;
-extern struct platform_device u8500_mcde2_device;
-extern struct platform_device u8500_mcde3_device;
-extern struct platform_device u8500_mcde1_device;
-extern struct platform_device u8500_mcde0_device;
+extern struct platform_device ux500_mcde_device;
extern struct platform_device u8500_hsit_device;
extern struct platform_device u8500_hsir_device;
extern struct platform_device u8500_shrm_device;
diff --git a/arch/arm/mach-ux500/include/mach/dsi.h b/arch/arm/mach-ux500/include/mach/dsi.h
deleted file mode 100755
index fad90f199d4..00000000000
--- a/arch/arm/mach-ux500/include/mach/dsi.h
+++ /dev/null
@@ -1,770 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * License terms:
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#ifndef _DSI_H_
-#define _DSI_H_
-
-#ifdef _cplusplus
-extern "C" {
-#endif /* _cplusplus */
-#include <mach/mcde.h>
-#ifdef __KERNEL__
-
-#define DSI_DPHY_Z_CALIB_OUT_VALID 0x1
-/*******************************************************************************
-DSI Error Enums
-******************************************************************************/
-
-
- typedef enum
- {
- DSI_OK = 0x1, /** No error.*/
- DSI_NO_PENDING_EVENT_ERROR = 0x2,
- DSI_NO_MORE_FILTER_PENDING_EVENT = 0x3,
- DSI_NO_MORE_PENDING_EVENT = 0x4,
- DSI_REMAINING_FILTER_PENDING_EVENTS = 0x5,
- DSI_REMAINING_PENDING_EVENTS = 0x6,
- DSI_INTERNAL_EVENT = 0x7,
- DSI_INTERNAL_ERROR = 0x8,
- DSI_NOT_CONFIGURED = 0x9,
- DSI_REQUEST_PENDING = 0xA,
- DSI_PLL_PROGRAM_ERROR = 0xB,
- DSI_CLOCK_LANE_NOT_READY = 0xC,
- DSI_DATA_LANE1_NOT_READY = 0xD,
- DSI_DATA_LANE2_NOT_READY = 0xE,
- DSI_REQUEST_NOT_APPLICABLE = 0x10,
- DSI_INVALID_PARAMETER = 0x11,
- DSI_UNSUPPORTED_FEATURE = 0x12,
- DSI_UNSUPPORTED_HW = 0x13
- }dsi_error;
-
-/********************************************************************************
-DSI Interrupt Type Enums
-********************************************************************************/
-#define DSI_NO_INTERRUPT 0x0
-
-typedef enum
-{
- DSI_IRQ_TYPE_MCTL_MAIN = 0x01,
- DSI_IRQ_TYPE_CMD_MODE = 0x02,
- DSI_IRQ_TYPE_DIRECT_CMD_MODE = 0x03,
- DSI_IRQ_TYPE_DIRECT_CMD_RD_MODE = 0x04,
- DSI_IRQ_TYPE_VID_MODE = 0x05,
- DSI_IRQ_TYPE_TG = 0x06,
- DSI_IRQ_TYPE_DPHY_ERROR = 0x07,
- DSI_IRQ_TYPE_DPHY_CLK_TRIM_RD = 0x08
-} dsi_irq_type;
-
-
-
-
-/*******************************************************************************
- DSI Main Setting Registers Enums and structures
-******************************************************************************/
-
- typedef enum
- {
- DSI_INT_MODE_DISABLE = 0x00,
- DSI_INT_MODE_ENABLE = 0x01
- }dsi_int_mode;
-
- typedef enum
- {
- DSI_VSG_MODE_DISABLE = 0x00,
- DSI_VSG_MODE_ENABLE = 0x01
- }dsi_vsg_ctrl;
-
- typedef enum
- {
- DSI_TVG_MODE_DISABLE = 0x00,
- DSI_TVG_MODE_ENABLE = 0x01
- }dsi_tvg_ctrl;
-
- typedef enum
- {
- DSI_TBG_MODE_DISABLE = 0x00,
- DSI_TBG_MODE_ENABLE = 0x01
- }dsi_tbg_ctrl;
-
- typedef enum
- {
- DSI_RD_MODE_DISABLE = 0x00,
- DSI_RD_MODE_ENABLE = 0x01
- }dsi_rd_ctrl;
-
-
- typedef enum
- {
- DSI_SIGNAL_LOW = 0x0,
- DSI_SIGNAL_HIGH = 0x1
- }dsi_signal_state;
-
- typedef enum
- {
- DSI_LINK0 = 0x00,
- DSI_LINK1 = 0x01,
- DSI_LINK2 = 0x02
- }dsi_link;
-
- typedef enum
- {
- DSI_COMMAND_MODE = 0x0,
- DSI_VIDEO_MODE = 0x1,
- DSI_INTERFACE_BOTH = 0x2,
- DSI_INTERFACE_NONE = 0x3
- }dsi_interface_mode;
-
- typedef enum
- {
- DSI_INTERFACE_1 = 0x0,
- DSI_INTERFACE_2 = 0x1
- }dsi_interface;
-
- typedef enum
- {
- DSI_DISABLE = 0x0,
- DSI_ENABLE = 0x1
- }dsi_link_state;
-
- typedef enum
- {
- DSI_SIGNAL_RESET = 0x0,
- DSI_SIGNAL_SET = 0x1
- }dsi_stall_signal_state;
-
- typedef enum
- {
- DSI_IF1_DISABLE = 0x0,
- DSI_IF1_ENABLE = 0x1
- }dsi_if1_state;
-
- typedef enum
- {
- DSI_IF_DISABLE = 0x0,
- DSI_IF_ENABLE = 0x1
- }dsi_if_state;
-
- typedef enum
- {
- DSI_PLL_IN_CLK_27 = 0x0,/** from TV PLL*/
- DSI_PLL_IN_CLK_26 = 0x1 /** from system PLL*/
- }dsi_pll_clk_in;
-
- typedef enum
- {
- DSI_PLL_STOP = 0x0,
- DSI_PLL_START = 0x1
- }dsi_pll_mode;
-
- typedef enum
- {
- DSI_BTA_DISABLE = 0x0,
- DSI_BTA_ENABLE = 0x1
- }dsi_bta_mode;
-
- typedef enum
- {
- DSI_ECC_GEN_DISABLE = 0x0,
- DSI_ECC_GEN_ENABLE = 0x1
- }dsi_ecc_gen_mode;
-
- typedef enum
- {
- DSI_CHECKSUM_GEN_DISABLE = 0x0,
- DSI_CHECKSUM_GEN_ENABLE = 0x1
- }dsi_checksum_gen_mode;
-
- typedef enum
- {
- DSI_EOT_GEN_DISABLE = 0x0,
- DSI_EOT_GEN_ENABLE = 0x1
- }dsi_eot_gen_mode;
-
- typedef enum
- {
- DSI_HOST_EOT_GEN_DISABLE = 0x0,
- DSI_HOST_EOT_GEN_ENABLE = 0x1
- }dsi_host_eot_gen_mode;
-
- typedef enum
- {
- DSI_LANE_STOP = 0x0,
- DSI_LANE_START = 0x1
- }dsi_lane_state;
- typedef enum
- {
- DSI_LANE_DISABLE = 0x0,
- DSI_LANE_ENABLE = 0x1
- }dsi_lane_mode;
- typedef enum
- {
- DSI_CLK_CONTINIOUS_HS_DISABLE = 0x0,
- DSI_CLK_CONTINIOUS_HS_ENABLE = 0x1
- }dsi_clk_continious_hs_mode;
- typedef enum
- {
- DSI_INTERNAL_PLL = 0x0,
- DSI_SYSTEM_PLL = 0x1
- }pll_out_sel; /** DPHY HS bit clock select*/
- typedef enum
- {
- HS_INVERT_DISABLE = 0x0,
- HS_INVERT_ENABLE = 0x1
- }dsi_hs_invert_mode;
- typedef enum
- {
- HS_SWAP_PIN_DISABLE = 0x0,
- HS_SWAP_PIN_ENABLE = 0x1
- }dsi_swap_pin_mode;
- typedef enum
- {
- DSI_PLL_MASTER = 0x0,
- DSI_PLL_SLAVE = 0x1
- }dsi_pll_mode_sel;
-
- typedef struct
- {
- u8 multiplier;
- u8 division_ratio;
- dsi_pll_clk_in pll_in_sel;
- pll_out_sel pll_out_sel;
- dsi_pll_mode_sel pll_master;
- }dsi_pll_ctl;
-
- typedef enum
- {
- DSI_REG_TE = 0x00,
- DSI_IF_TE = 0x01
- }dsi_te_sel;
-
- typedef struct
- {
- dsi_te_sel te_sel;
- dsi_interface interface;
- }dsi_te_en;
-
- typedef enum
- {
- DSI_TE_DISABLE = 0x0,
- DSI_TE_ENABLE = 0x1
- }dsi_te_ctrl;
-
- typedef enum
- {
- DSI_CLK_LANE = 0x00,
- DSI_DATA_LANE1 = 0x01,
- DSI_DATA_LANE2 = 0x02
- }dsi_lane;
-
- typedef enum
- {
- DSI_DAT_LANE1 = 0x0,
- DSI_DAT_LANE2 = 0x1
- }dsi_data_lane;
-
- typedef enum
- {
- DSI_CLK_LANE_START = 0x00,
- DSI_CLK_LANE_IDLE = 0x01,
- DSI_CLK_LANE_HS = 0x02,
- DSI_CLK_LANE_ULPM = 0x03
- }dsi_clk_lane_state;
- typedef enum
- {
- DSI_CLK_LANE_LPM = 0x0,
- DSI_CLK_LANE_HSM = 0x01
- }dsi_interface_mode_type;
- typedef enum
- {
- DSI_DATA_LANE_START = 0x000,
- DSI_DATA_LANE_IDLE = 0x001,
- DSI_DATA_LANE_WRITE = 0x002,
- DSI_DATA_LANE_ULPM = 0x003,
- DSI_DATA_LANE_READ = 0x004
- }dsi_data_lane_state;
-
- typedef struct
- {
- u8 clk_div;
- u16 hs_tx_timeout;
- u16 lp_rx_timeout;
- }dsi_dphy_timeout;
-
- typedef enum
- {
- DSI_PLL_LOCK = 0x01,
- DSI_CLKLANE_READY = 0x02,
- DSI_DAT1_READY = 0x04,
- DSI_DAT2_READY = 0x08,
- DSI_HSTX_TO_ERROR = 0x10,
- DSI_LPRX_TO_ERROR = 0x20,
- DSI_CRS_UNTERM_PCK = 0x40,
- DSI_VRS_UNTERM_PCK = 0x80
- }dsi_link_status;
-
- typedef struct
- {
- u16 if_data;
- dsi_signal_state if_valid;
- dsi_signal_state if_start;
- dsi_signal_state if_frame_sync;
- }dsi_int_read;
-
- typedef enum
- {
- DSI_ERR_SOT_HS_1 = 0x1,
- DSI_ERR_SOT_HS_2 = 0x2,
- DSI_ERR_SOTSYNC_1 = 0x4,
- DSI_ERR_SOTSYNC_2 = 0x8,
- DSI_ERR_EOTSYNC_1 = 0x10,
- DSI_ERR_EOTSYNC_2 = 0x20,
- DSI_ERR_ESC_1 = 0x40,
- DSI_ERR_ESC_2 = 0x80,
- DSI_ERR_SYNCESC_1 = 0x100,
- DSI_ERR_SYNCESC_2 = 0x200,
- DSI_ERR_CONTROL_1 = 0x400,
- DSI_ERR_CONTROL_2 = 0x800,
- DSI_ERR_CONT_LP0_1 = 0x1000,
- DSI_ERR_CONT_LP0_2 = 0x2000,
- DSI_ERR_CONT_LP1_1 = 0x4000,
- DSI_ERR_CONT_LP1_2 = 0x8000,
- }dsi_dphy_err;
-
- typedef enum
- {
- DSI_VIRTUAL_CHANNEL_0 = 0x0,
- DSI_VIRTUAL_CHANNEL_1 = 0x1,
- DSI_VIRTUAL_CHANNEL_2 = 0x2,
- DSI_VIRTUAL_CHANNEL_3 = 0x3
- }dsi_virtual_ch;
-
- typedef enum
- {
- DSI_ERR_NO_TE = 0x1,
- DSI_ERR_TE_MISS = 0x2,
- DSI_ERR_SDI1_UNDERRUN = 0x4,
- DSI_ERR_SDI2_UNDERRUN = 0x8,
- DSI_ERR_UNWANTED_RD = 0x10,
- DSI_CSM_RUNNING = 0x20
- }dsi_cmd_mode_sts;
-
- typedef enum
- {
- DSI_COMMAND_DIRECT = 0x0,
- DSI_COMMAND_GENERIC = 0x1
- }dsi_cmd_type;
-
- typedef struct
- {
- u16 rd_size;
- dsi_virtual_ch rd_id;
- dsi_cmd_type cmd_type;
- }dsi_cmd_rd_property;
-
- typedef enum
- {
- DSI_CMD_WRITE = 0x0,
- DSI_CMD_READ = 0x1,
- DSI_CMD_TE_REQUEST = 0x4,
- DSI_CMD_TRIGGER_REQUEST = 0x5,
- DSI_CMD_BTA_REQUEST = 0x6
- }dsi_cmd_nat;
-
- typedef enum
- {
- DSI_CMD_SHORT = 0x0,
- DSI_CMD_LONG = 0x1
- }dsi_cmd_packet;
-
- typedef struct
- {
- u8 rddat0;
- u8 rddat1;
- u8 rddat2;
- u8 rddat3;
- }dsi_cmd_rddat;
-
- typedef struct
- {
- dsi_cmd_nat cmd_nature;
- dsi_cmd_packet packet_type;
- u8 cmd_header;
- dsi_virtual_ch cmd_id;
- u8 cmd_size;
- dsi_link_state cmd_lp_enable;
- u8 cmd_trigger_val;
- }dsi_cmd_main_setting;
-
- typedef enum
- {
- DSI_CMD_TRANSMISSION = 0x1,
- DSI_WRITE_COMPLETED = 0x2,
- DSI_TRIGGER_COMPLETED = 0x4,
- DSI_READ_COMPLETED = 0x8,
- DSI_ACKNOWLEDGE_RECEIVED = 0x10,
- DSI_ACK_WITH_ERR_RECEIVED = 0x20,
- DSI_TRIGGER_RECEIVED = 0x40,
- DSI_TE_RECEIVED = 0x80,
- DSI_BTA_COMPLETED = 0x100,
- DSI_BTA_FINISHED = 0x200,
- DSI_READ_COMPLETED_WITH_ERR = 0x400,
- DSI_TRIGGER_VAL = 0x7800,
- DSI_ACK_VAL = 0xFFFF0000
- }dsi_direct_cmd_sts;
-
- typedef enum
- {
- DSI_TE_256 = 0x00,
- DSI_TE_512 = 0x01,
- DSI_TE_1024 = 0x02,
- DSI_TE_2048 = 0x03
- }dsi_te_timeout;
-
- typedef enum
- {
- DSI_ARB_MODE_FIXED = 0x0,
- DSI_ARB_MODE_ROUNDROBIN = 0x1
- }dsi_arb_mode;
-
- typedef struct
- {
- dsi_arb_mode arb_mode;
- dsi_interface arb_fixed_if;
- }dsi_arb_ctl;
-
- typedef enum
- {
- DSI_STARTON_VSYNC = 0x00,
- DSI_STARTON_VFP = 0x01,
- }dsi_start_mode;
-
- typedef enum
- {
- DSI_STOPBEFORE_VSYNV = 0x0,
- DSI_STOPAT_LINEEND = 0x1,
- DSI_STOPAT_ACTIVELINEEND = 0x2,
- }dsi_stop_mode;
-
- typedef enum
- {
- DSI_NO_BURST_MODE = 0x0,
- DSI_BURST_MODE = 0x1,
- }dsi_burst_mode;
-
- typedef enum
- {
- DSI_VID_MODE_16_PACKED = 0x0,
- DSI_VID_MODE_18_PACKED = 0x1,
- DSI_VID_MODE_16_LOOSELY = 0x2,
- DSI_VID_MODE_18_LOOSELY = 0x3
- }dsi_vid_pixel_mode;
-
- typedef enum
- {
- DSI_SYNC_PULSE_NOTACTIVE = 0x0,
- DSI_SYNC_PULSE_ACTIVE = 0x1
- }dsi_sync_pulse_active;
-
- typedef enum
- {
- DSI_SYNC_PULSE_HORIZONTAL_NOTACTIVE = 0x0,
- DSI_SYNC_PULSE_HORIZONTAL_ACTIVE = 0x1
- }dsi_sync_pulse_horizontal;
-
- typedef enum
- {
- DSI_NULL_PACKET = 0x0,
- DSI_BLANKING_PACKET = 0x1,
- DSI_LP_MODE = 0x2,
- }dsi_blanking_packet;
-
- typedef enum
- {
- DSI_RECOVERY_HSYNC = 0x0,
- DSI_RECOVERY_VSYNC = 0x1,
- DSI_RECOVERY_STOP = 0x2,
- DSI_RECOVERY_HSYNC_VSYNC = 0x3
- }dsi_recovery_mode;
-
- typedef struct
- {
- dsi_start_mode vid_start_mode;
- dsi_stop_mode vid_stop_mode;
- dsi_virtual_ch vid_id;
- u8 header;
- dsi_vid_pixel_mode vid_pixel_mode;
- dsi_burst_mode vid_burst_mode;
- dsi_sync_pulse_active sync_pulse_active;
- dsi_sync_pulse_horizontal sync_pulse_horizontal;
- dsi_blanking_packet blkline_mode;
- dsi_blanking_packet blkeol_mode;
- dsi_recovery_mode recovery_mode;
- }dsi_vid_main_ctl;
-
- typedef struct
- {
- u16 vact_length;
- u8 vfp_length;
- u8 vbp_length;
- u8 vsa_length;
- }dsi_img_vertical_size;
-
- typedef struct
- {
- u8 hsa_length;
- u8 hbp_length;
- u16 hfp_length;
- u16 rgb_size;
- }dsi_img_horizontal_size;
-
- typedef struct
- {
- u16 line_val;
- u8 line_pos;
- u16 horizontal_val;
- u8 horizontal_pos;
- }dsi_img_position;
-
- typedef enum
- {
- DSI_VSG_RUNNING = 0x1,
- DSI_ERR_MISSING_DATA = 0x2,
- DSI_ERR_MISSING_HSYNC = 0x4,
- DSI_ERR_MISSING_VSYNC = 0x8,
- DSI_ERR_SMALL_LENGTH = 0x10,
- DSI_ERR_SMALL_HEIGHT = 0x20,
- DSI_ERR_BURSTWRITE = 0x40,
- DSI_ERR_LINEWRITE = 0x80,
- DSI_ERR_LONGWRITE = 0x100,
- DSI_ERR_VRS_WRONG_LENGTH = 0x200
- }dsi_vid_mode_sts;
-
- typedef enum
- {
- DSI_NULL_PACK = 0x0,
- DSI_LP = 0x1,
- }dsi_burst_lp;
-
- typedef struct
- {
- dsi_burst_lp burst_lp;
- u16 max_burst_limit;
- u16 max_line_limit;
- u16 exact_burst_limit;
- }dsi_vca_setting;
-
- typedef struct
- {
- u16 blkeol_pck;
- u16 blkline_event_pck;
- u16 blkline_pulse_pck;
- u16 vert_balnking_duration;
- u16 blkeol_duration;
- }dsi_vid_blanking;
-
- typedef struct
- {
- u8 col_red;
- u8 col_green;
- u8 col_blue;
- u8 pad_val;
- }dsi_vid_err_color;
-
- typedef enum
- {
- DSI_TVG_MODE_UNIQUECOLOR = 0x0,
- DSI_TVG_MODE_STRIPES = 0x1,
- }dsi_tvg_mode;
-
- typedef enum
- {
- DSI_TVG_STOP_FRAMEEND = 0x0,
- DSI_TVG_STOP_LINEEND = 0x1,
- DSI_TVG_STOP_IMMEDIATE = 0x2,
- }dsi_tvg_stop_mode;
-
-
-
- typedef struct
- {
- u8 tvg_stripe_size;
- dsi_tvg_mode tvg_mode;
- dsi_tvg_stop_mode stop_mode;
- }dsi_tvg_control;
-
- typedef struct
- {
- u16 tvg_nbline;
- u16 tvg_line_size;
- }dsi_tvg_img_size;
-
- typedef struct
- {
- u8 col_red;
- u8 col_green;
- u8 col_blue;
- }dsi_frame_color;
-
- typedef enum
- {
- DSI_TVG_COLOR1 = 0x0,
- DSI_TVG_COLOR2 = 0x1
- }dsi_color_type;
-
- typedef enum
- {
- DSI_TVG_STOPPED = 0x0,
- DSI_TVG_RUNNING = 0x1
- }dsi_tvg_state;
-
- typedef enum
- {
- DSI_TVG_STOP = 0x0,
- DSI_TVG_START = 0x1
- }dsi_tvg_ctrl_state;
-
- typedef enum
- {
- DSI_TBG_STOPPED = 0x0,
- DSI_TBG_RUNNING = 0x1
- }dsi_tbg_state;
-
- typedef enum
- {
- DSI_SEND_1BYTE = 0x0,
- DSI_SEND_2BYTE = 0x1,
- DSI_SEND_BURST_STOP_COUNTER = 0x3,
- DSI_SEND_BURST_STOP = 0x4
- }dsi_tbg_mode;
-
- typedef enum
- {
- DSI_ERR_FIXED = 0x1,
- DSI_ERR_UNCORRECTABLE = 0x2,
- DSI_ERR_CHECKSUM = 0x4,
- DSI_ERR_UNDECODABLE = 0x8,
- DSI_ERR_RECEIVE = 0x10,
- DSI_ERR_OVERSIZE = 0x20,
- DSI_ERR_WRONG_LENGTH = 0x40,
- DSI_ERR_MISSING_EOT = 0x80,
- DSI_ERR_EOT_WITH_ERR = 0x100
- }dsi_direct_cmd_rd_sts_ctl;
-
- typedef enum
- {
- DSI_TVG_STS = 0x1,
- DSi_TBG_STS = 0x2
- }dsi_tg_sts_ctl;
-
-typedef struct
-{
- dsi_interface_mode dsi_if_mode;
- dsi_interface dsiInterface;
- dsi_if1_state dsi_if1_state;
- dsi_link_state dsi_link_state;
- dsi_int_mode dsi_int_mode;
- dsi_interface_mode_type if_mode_type;
-}dsi_link_context;
-
-struct dsi_dphy_static_conf {
- dsi_hs_invert_mode clocklanehsinvermode;
- dsi_swap_pin_mode clocklaneswappinmode;
- dsi_hs_invert_mode datalane1hsinvermode;
- dsi_swap_pin_mode datalane1swappinmode;
- dsi_hs_invert_mode datalane2hsinvermode;
- dsi_swap_pin_mode datalane2swappinmode;
- u8 ui_x4; /** unit interval time for clock lane*/
-};
-struct dsi_link_conf {
- dsi_link_state dsiLinkState;
- dsi_interface dsiInterface;
- dsi_interface_mode dsiInterfaceMode;
- dsi_interface_mode_type videoModeType; /** for LP/HS mode for vide mode */
- dsi_interface_mode_type commandModeType;/** for LP/HS mode for command mode */
- dsi_lane_mode clockLaneMode;
- dsi_lane_mode dataLane1Mode;
- dsi_lane_mode dataLane2Mode;
- dsi_arb_mode arbMode;
- dsi_te_ctrl if1TeCtrl;
- dsi_te_ctrl if2TeCtrl;
- dsi_te_ctrl regTeCtrl;
- dsi_bta_mode btaMode;
- dsi_rd_ctrl rdCtrl;
- dsi_host_eot_gen_mode hostEotGenMode;
- dsi_eot_gen_mode displayEotGenMode;
- dsi_ecc_gen_mode dispEccGenMode;
- dsi_checksum_gen_mode dispChecksumGenMode;
- dsi_clk_continious_hs_mode clockContiniousMode;
- u8 paddingValue;
-};
-#endif /** __KERNEL_ */
-
-u32 dsiconfdphy1(mcde_pll_ref_clk pll_sel, mcde_ch_id chid, dsi_link link);
-u32 dsidisplayinitLPcmdmode(mcde_ch_id chid, dsi_link link);
-
-dsi_error dsisetlinkstate(dsi_link link, dsi_link_state linkState, mcde_ch_id chid);
-u32 dsiLinkInit(struct dsi_link_conf *pdsiLinkConf, struct dsi_dphy_static_conf dphyStaticConf, mcde_ch_id chid, dsi_link link);
-int mcde_dsi_test_LP_directcommand_mode(struct fb_info *info,u32 key);
-int mcde_dsi_start(struct fb_info *info);
-int mcde_dsi_test_dsi_HS_directcommand_mode(struct fb_info *info,u32 key);
-
-int mcde_dsi_read_reg(struct fb_info *info, u32 reg, u32 *value);
-int mcde_dsi_write_reg(struct fb_info *info, u32 reg, u32 value);
-
-dsi_error dsisetPLLcontrol(dsi_link link, mcde_ch_id chid, dsi_pll_ctl pll_ctl);
-dsi_error dsisetPLLmode(dsi_link link, mcde_ch_id chid, dsi_pll_mode mode);
-dsi_error dsigetlinkstatus(dsi_link link, mcde_ch_id chid, u8 *p_status);
-dsi_error dsisetInterface(dsi_link link, mcde_ch_id chid, dsi_if_state state, dsi_interface interface);
-dsi_error dsisetInterface1mode(dsi_link link, dsi_interface_mode mode, mcde_ch_id chid);
-dsi_error dsisetInterfaceInLpm(dsi_link link, mcde_ch_id chid, dsi_interface_mode_type modType, dsi_interface interface);
-dsi_error dsisetTEtimeout(dsi_link link, mcde_ch_id chid, u32 te_timeout);
-dsi_error dsireadset(dsi_link link, dsi_rd_ctrl state, mcde_ch_id chid);
-dsi_error dsisetBTAmode(dsi_link link, dsi_bta_mode mode, mcde_ch_id chid);
-dsi_error dsisetdispEOTGenmode(dsi_link link, dsi_eot_gen_mode mode, mcde_ch_id chid);
-dsi_error dsisetdispHOSTEOTGenmode(dsi_link link, dsi_host_eot_gen_mode mode, mcde_ch_id chid);
-dsi_error dsisetdispCHKSUMGenmode(dsi_link link, dsi_checksum_gen_mode mode, mcde_ch_id chid);
-dsi_error dsisetdispECCGenmode(dsi_link link, dsi_ecc_gen_mode mode, mcde_ch_id chid);
-dsi_error dsisetCLKHSsendingmode(dsi_link link, dsi_clk_continious_hs_mode mode, mcde_ch_id chid);
-dsi_error dsisetpaddingval(dsi_link link, mcde_ch_id chid, u8 padding);
-dsi_error dsisetTE(dsi_link link, dsi_te_en tearing, dsi_te_ctrl state, mcde_ch_id chid);
-dsi_error dsisetlaneULPwaittime(dsi_link link, mcde_ch_id chid, dsi_lane lane, u16 timeout);
-
-dsi_error dsisetlanestate(dsi_link link, mcde_ch_id chid, dsi_lane_state mode, dsi_lane lane);
-dsi_error dsiset_hs_clock(dsi_link link, struct dsi_dphy_static_conf dphyStaticConf, mcde_ch_id chid);
-dsi_error dsisetDPHYtimeout(dsi_link link, mcde_ch_id chid, dsi_dphy_timeout timeout);
-void mcde_dsi_tpodisplay_init(struct fb_info *info);
-void mcde_dsi_taaldisplay_init(struct fb_info *info);
-
-/* following Apis are used by stw5810 driver for configuration */
-u32 dsisenddirectcommand(dsi_interface_mode_type mode_type, u32 cmd_head,u32 cmd_size,u32 cmd1,u32 cmd2,u32 cmd3,u32 cmd4, dsi_link link, mcde_ch_id chid);
-
-u32 dsiLPdcslongwrite(u32 VC_ID, u32 NoOfParam, u32 Param0, u32 Param1,u32 Param2, u32 Param3,
- u32 Param4,u32 Param5,u32 Param6,u32 Param7,u32 Param8, u32 Param9,u32 Param10,u32 Param11,
- u32 Param12,u32 Param13,u32 Param14, u32 Param15, mcde_ch_id chid, dsi_link link);
-
-u32 dsiLPdcsshortwrite1parm(u32 VC_ID, u32 Param0,u32 Param1, mcde_ch_id chid, dsi_link link);
-u32 dsiLPdcsshortwritenoparam(u32 VC_ID, u32 Param0, mcde_ch_id chid, dsi_link link);
-
-u32 dsiHSdcslongwrite(u32 VC_ID, u32 NoOfParam, u32 Param0, u32 Param1,u32 Param2, u32 Param3,
- u32 Param4,u32 Param5,u32 Param6,u32 Param7,u32 Param8, u32 Param9,u32 Param10,u32 Param11,
- u32 Param12,u32 Param13,u32 Param14, u32 Param15, mcde_ch_id chid, dsi_link link);
-
-u32 dsiHSdcsshortwrite1parm(u32 VC_ID, u32 Param0,u32 Param1, mcde_ch_id chid, dsi_link link);
-u32 dsiHSdcsshortwritenoparam(u32 VC_ID, u32 Param0, mcde_ch_id chid, dsi_link link);
-u32 dsireaddata(u8* byte0, u8* byte1, u8* byte2, u8* byte3, mcde_ch_id chid, dsi_link link);
-
-
-#ifdef _cplusplus
-}
-#endif /* _cplusplus */
-
-#endif /* !defined(_DSI_H_) */
-
-
diff --git a/arch/arm/mach-ux500/include/mach/dsi_reg.h b/arch/arm/mach-ux500/include/mach/dsi_reg.h
deleted file mode 100755
index a02691e5960..00000000000
--- a/arch/arm/mach-ux500/include/mach/dsi_reg.h
+++ /dev/null
@@ -1,488 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * License terms:
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#ifndef _DSIREG_H_
-#define _DSIREG_H_
-
-#ifdef _cplusplus
-extern "C" {
-#endif /* _cplusplus */
-
-#include <linux/types.h>
-
-#define DSI_SET_BIT 0x1
-#define DSI_CLEAR_BIT 0x0
-#define DSI_SET_ALL_BIT 0xFFFFFFFF
-#define DSI_CLEAR_ALL_BIT 0x0
-#define DSI_MCTL_INTMODE_MASK MASK_BIT0
-#define DSI_MCTL_LINKEN_MASK MASK_BIT0
-#define DSI_MCTL_INTERFACE1_MODE_MASK MASK_BIT1
-#define DSI_MCTL_VID_EN_MASK MASK_BIT2
-#define DSI_MCTL_TVG_SEL_MASK MASK_BIT3
-#define DSI_MCTL_TBG_SEL_MASK MASK_BIT4
-#define DSI_MCTL_READEN_MASK MASK_BIT8
-#define DSI_MCTL_BTAEN_MASK MASK_BIT9
-#define DSI_MCTL_DISPECCGEN_MASK MASK_BIT10
-#define DSI_MCTL_DISPCHECKSUMGEN_MASK MASK_BIT11
-#define DSI_MCTL_HOSTEOTGEN_MASK MASK_BIT12
-#define DSI_MCTL_DISPEOTGEN_MASK MASK_BIT13
-#define DSI_PLL_MASTER_MASK MASK_BIT16
-#define DSI_PLL_OUT_SEL_MASK MASK_BIT11
-#define DSI_PLL_IN_SEL_MASK MASK_BIT10
-#define DSI_PLL_DIV_MASK (MASK_BIT7 | MASK_BIT8 | MASK_BIT9)
-#define DSI_PLL_MULT_MASK (MASK_BYTE0 & 0x7F)
-#define DSI_REG_TE_MASK MASK_BIT7
-#define DSI_IF1_TE_MASK MASK_BIT5
-#define DSI_IF2_TE_MASK MASK_BIT6
-#define DSI_LANE2_EN_MASK MASK_BIT0
-#define DSI_FORCE_STOP_MODE_MASK MASK_BIT1
-#define DSI_CLK_CONTINUOUS_MASK MASK_BIT2
-#define DSI_CLK_ULPM_EN_MASK MASK_BIT3
-#define DSI_DAT1_ULPM_EN_MASK MASK_BIT4
-#define DSI_DAT2_ULPM_EN_MASK MASK_BIT5
-#define DSI_WAIT_BURST_MASK (MASK_BIT6 | MASK_BIT7 | MASK_BIT8 | MASK_BIT9)
-#define DSI_CLKLANESTS_MASK (MASK_BIT0 | MASK_BIT1)
-#define DSI_DATALANE1STS_MASK (MASK_BIT2 | MASK_BIT3 | MASK_BIT4)
-#define DSI_DATALANE2STS_MASK (MASK_BIT5 | MASK_BIT6)
-#define DSI_CLK_DIV_MASK MASK_QUARTET0
-#define DSI_HSTX_TO_MASK (MASK_QUARTET1 | MASK_BYTE1 | MASK_BIT16 | MASK_BIT17)
-#define DSI_LPRX_TO_MASK (MASK_BYTE3 | MASK_QUARTET5 | MASK_BIT18 | MASK_BIT18)
-#define DSI_CLK_ULPOUT_MASK (MASK_BYTE0 | MASK_BIT8)
-#define DSI_DATA_ULPOUT_MASK (MASK_QUARTET3 | MASK_BIT9 | MASK_BIT10 | MASK_BIT11 | MASK_BIT16 | MASK_BIT17)
-#define DSI_PLL_START_MASK MASK_BIT0
-#define DSI_CKLANE_EN_MASK MASK_BIT3
-#define DSI_DAT1_EN_MASK MASK_BIT4
-#define DSI_DAT2_EN_MASK MASK_BIT5
-#define DSI_CLK_ULPM_MASK MASK_BIT6
-#define DSI_DAT1_ULPM_MASK MASK_BIT7
-#define DSI_DAT2_ULPM_MASK MASK_BIT8
-#define DSI_IF1_EN_MASK MASK_BIT9
-#define DSI_IF2_EN_MASK MASK_BIT10
-#define DSI_MAIN_STS_MASK MASK_BYTE0
-#define DSI_DPHY_ERROR_MASK MASK_HALFWORD0
-#define DSI_IF_DATA_MASK MASK_HALFWORD0
-#define DSI_IF_VALID_MASK MASK_BIT16
-#define DSI_IF_START_MASK MASK_BIT17
-#define DSI_IF_FRAME_SYNC_MASK MASK_BIT18
-#define DSI_IF_STALL_MASK MASK_BIT0
-#define DSI_INT_VAL_MASK MASK_BIT0
-#define DSI_DIRECT_CMD_RD_STS_MASK (MASK_BYTE0 | MASK_BIT8)
-#define DSI_CMD_MODE_STS_MASK (MASK_QUARTET0 | MASK_BIT4 | MASK_BIT5)
-#define DSI_RD_ID_MASK (MASK_BIT16 | MASK_BIT17 )
-#define DSI_RD_DCSNOTGENERIC_MASK MASK_BIT18
-#define DSI_CMD_NAT_MASK (MASK_BIT0 | MASK_BIT1 | MASK_BIT2)
-#define DSI_CMD_LONGNOTSHORT_MASK MASK_BIT3
-#define DSI_CMD_HEAD_MASK (MASK_QUARTET2 | MASK_BIT12 | MASK_BIT13)
-#define DSI_CMD_ID_MASK (MASK_BIT14 | MASK_BIT15)
-#define DSI_CMD_SIZE_MASK (MASK_QUARTET4 | MASK_BIT20)
-#define DSI_CMD_LP_EN_MASK (MASK_BIT21)
-#define DSI_TRIGGER_VAL_MASK MASK_QUARTET6
-#define DSI_TE_LOWERBIT_MASK MASK_BYTE2
-#define DSI_TE_UPPERBIT_MASK (MASK_BIT24 | MASK_BIT25)
-#define DSI_FIL_VAL_MASK MASK_BYTE1
-#define DSI_ARB_MODE_MASK MASK_BIT6
-#define DSI_ARB_PRI_MASK MASK_BIT7
-#define DSI_START_MODE_MASK (MASK_BIT0 | MASK_BIT1 )
-#define DSI_STOP_MODE_MASK (MASK_BIT2 | MASK_BIT3)
-#define DSI_VID_ID_MASK (MASK_BIT4 | MASK_BIT5)
-#define DSI_HEADER_MASK (MASK_BIT6 | MASK_BIT7 | MASK_BIT8 | MASK_BIT9 | MASK_BIT10 | MASK_BIT11)
-#define DSI_PIXEL_MODE_MASK (MASK_BIT12 | MASK_BIT13)
-#define DSI_BURST_MODE_MASK (MASK_BIT14)
-#define DSI_SYNC_PULSE_ACTIVE_MASK (MASK_BIT15)
-#define DSI_SYNC_PULSE_HORIZONTAL_MASK (MASK_BIT16)
-#define DSI_BLKLINE_MASK (MASK_BIT17 | MASK_BIT18)
-#define DSI_BLKEOL_MASK (MASK_BIT19 | MASK_BIT20)
-#define DSI_RECOVERY_MODE_MASK (MASK_BIT21 | MASK_BIT22)
-#define DSI_VSA_LENGTH_MASK MASK_QUARTET0
-#define DSI_VBP_LENGTH_MASK MASK_QUARTET1
-#define DSI_VFP_LENGTH_MASK MASK_BYTE1
-#define DSI_VACT_LENGTH_MASK (MASK_BYTE2 | MASK_QUARTET6)
-#define DSI_HSA_LENGTH_MASK MASK_BYTE0
-#define DSI_HBP_LENGTH_MASK MASK_BYTE1
-#define DSI_HFP_LENGTH_MASK (MASK_BYTE2 | MASK_BIT24 | MASK_BIT25 | MASK_BIT26)
-#define DSI_RGB_SIZE_MASK (MASK_BYTE0 | MASK_QUARTET2 | MASK_BIT12)
-#define DSI_LINE_POS_MASK (MASK_BIT0 | MASK_BIT1)
-#define DSI_LINE_VAL_MASK (MASK_BIT2 | MASK_BIT3 | MASK_QUARTET1 | MASK_QUARTET2 | MASK_BIT12)
-#define DSI_HORI_POS_MASK (MASK_BIT0 | MASK_BIT1 |MASK_BIT2)
-#define DSI_HORI_VAL_MASK (MASK_BYTE1 | MASK_QUARTET1 | MASK_BIT3)
-#define DSI_VID_MODE_STS_MASK (MASK_BYTE0 | MASK_BIT8 | MASK_BIT9)
-#define DSI_BURST_LP_MASK MASK_BIT16
-#define DSI_MAX_BURST_LIMIT_MASK MASK_HALFWORD0
-#define DSI_MAX_LINE_LIMIT_MASK MASK_HALFWORD1
-#define DSI_EXACT_BURST_LIMIT_MASK MASK_HALFWORD0
-#define DSI_BLKLINE_EVENT_MASK (MASK_BYTE0 | MASK_QUARTET2 | MASK_BIT12)
-#define DSI_BLKEOL_PCK_MASK (MASK_BYTE2 | MASK_BIT15 | MASK_BIT14 | MASK_BIT13 | MASK_BIT24 | MASK_BIT25)
-#define DSI_BLKLINE_PULSE_PCK_MASK (MASK_BYTE0 | MASK_QUARTET2 | MASK_BIT12)
-#define DSI_BLKEOL_DURATION_MASK (MASK_BYTE0 | MASK_QUARTET2 | MASK_BIT12)
-#define DSI_VERT_BLANK_DURATION_MASK (MASK_BYTE2 | MASK_BIT15 | MASK_BIT14 | MASK_BIT13 | MASK_BIT24 | MASK_BIT25)
-#define DSI_COL_RED_MASK MASK_BYTE0
-#define DSI_COL_GREEN_MASK MASK_BYTE1
-#define DSI_COL_BLUE_MASK MASK_BYTE2
-#define DSI_PAD_VAL_MASK MASK_BYTE3
-#define DSI_TVG_STRIPE_MASK (MASK_BIT5 | MASK_BIT6 | MASK_BIT7)
-#define DSI_TVG_MODE_MASK (MASK_BIT3 | MASK_BIT4 )
-#define DSI_TVG_STOPMODE_MASK (MASK_BIT1 | MASK_BIT2 )
-#define DSI_TVG_RUN_MASK MASK_BIT0
-#define DSI_TVG_NBLINE_MASK (MASK_BYTE2 | MASK_BIT24 | MASK_BIT25 | MASK_BIT26)
-#define DSI_TVG_LINE_SIZE_MASK (MASK_BYTE0 | MASK_QUARTET2 | MASK_BIT12)
-#define DSI_CMD_MODE_STATUS_MASK (MASK_QUARTET0 | MASK_BIT4 | MASK_BIT5 )
-#define DSI_DIRECT_CMD_STS_MASK (MASK_BYTE0 | MASK_BIT8 | MASK_BIT9 | MASK_BIT10 )
-#define DSI_DIRECT_CMD_RD_STATUS_MASK (MASK_BYTE0 | MASK_BIT8 )
-#define DSI_VID_MODE_STATUS_MASK (MASK_BYTE0 | MASK_BIT8 | MASK_BIT9 )
-#define DSI_TG_STS_MASK (MASK_BIT0 | MASK_BIT1)
-#define DSI_CLK_TRIM_RD_MASK MASK_BIT0
-#define DSI_IF1_LPM_EN_MASK MASK_BIT4
-#define DSI_IF2_LPM_EN_MASK MASK_BIT5
-#define DSIMCTL_DPHY_STATIC_HS_INVERT_DAT2 MASK_BIT5
-#define DSIMCTL_DPHY_STATIC_SWAP_PINS_DAT2 MASK_BIT4
-#define DSIMCTL_DPHY_STATIC_HS_INVERT_DAT1 MASK_BIT3
-#define DSIMCTL_DPHY_STATIC_SWAP_PINS_DAT1 MASK_BIT2
-#define DSIMCTL_DPHY_STATIC_HS_INVERT_CLK MASK_BIT1
-#define DSIMCTL_DPHY_STATIC_SWAP_PINS_CLK MASK_BIT0
-#define DSIMCTL_DPHY_STATIC_UI_X4 (MASK_BIT6 | MASK_BIT7 | MASK_QUARTET2)
-
-#define DSI_MCTL_INTERFACE1_MODE_SHIFT 1
-#define DSI_MCTL_VID_EN_SHIF 2
-#define DSI_MCTL_TVG_SEL_SHIFT 3
-#define DSI_MCTL_TBG_SEL_SHIFT 4
-#define DSI_MCTL_READEN_SHIFT 8
-#define DSI_MCTL_BTAEN_SHIFT 9
-#define DSI_MCTL_DISPECCGEN_SHIFT 10
-#define DSI_MCTL_DISPCHECKSUMGEN_SHIFT 11
-#define DSI_MCTL_HOSTEOTGEN_SHIFT 12
-#define DSI_MCTL_DISPEOTGEN_SHIFT 13
-#define DSI_PLL_MASTER_SHIFT 16
-#define DSI_PLL_OUT_SEL_SHIFT 11
-#define DSI_PLL_IN_SEL_SHIFT 10
-#define DSI_MCTL_VID_EN_SHIFT 2
-#define DSI_PLL_DIV_SHIFT 7
-#define DSI_REG_TE_SHIFT 7
-#define DSI_IF1_TE_SHIFT 5
-#define DSI_IF2_TE_SHIFT 6
-#define DSI_FORCE_STOP_MODE_SHIFT 1
-#define DSI_CLK_CONTINUOUS_SHIFT 2
-#define DSI_CLK_ULPM_EN_SHIFT 3
-#define DSI_DAT1_ULPM_EN_SHIFT 4
-#define DSI_DAT2_ULPM_EN_SHIFT 5
-#define DSI_WAIT_BURST_SHIFT 6
-#define DSI_DATALANE1STS_SHIFT 2
-#define DSI_DATALANE2STS_SHIFT 5
-#define DSI_HSTX_TO_SHIFT 4
-#define DSI_LPRX_TO_SHIFT 18
-#define DSI_DATA_ULPOUT_SHIFT 9
-#define DSI_CKLANE_EN_SHIFT 3
-#define DSI_DAT1_EN_SHIFT 4
-#define DSI_DAT2_EN_SHIFT 5
-#define DSI_CLK_ULPM_SHIFT 6
-#define DSI_DAT1_ULPM_SHIFT 7
-#define DSI_DAT2_ULPM_SHIFT 8
-#define DSI_IF1_EN_SHIFT 9
-#define DSI_IF2_EN_SHIFT 10
-#define DSI_IF_VALID_SHIFT 16
-#define DSI_IF_START_SHIFT 17
-#define DSI_IF_FRAME_SYNC_SHIFT 18
-#define DSI_RD_ID_SHIFT 16
-#define DSI_RD_DCSNOTGENERIC_SHIFT 18
-#define DSI_CMD_LONGNOTSHORT_SHIFT 3
-#define DSI_CMD_HEAD_SHIFT 8
-#define DSI_CMD_ID_SHIFT 14
-#define DSI_CMD_SIZE_SHIFT 16
-#define DSI_CMD_LP_EN_SHIFT 21
-#define DSI_TRIGGER_VAL_SHIFT 24
-#define DSI_TE_LOWERBIT_SHIFT 16
-#define DSI_TE_UPPERBIT_SHIFT 24
-#define DSI_FIL_VAL_SHIFT 8
-#define DSI_ARB_MODE_SHIFT 6
-#define DSI_ARB_PRI_SHIFT 7
-#define DSI_STOP_MODE_SHIFT 2
-#define DSI_VID_ID_SHIFT 4
-#define DSI_HEADER_SHIFT 6
-#define DSI_PIXEL_MODE_SHIFT 12
-#define DSI_BURST_MODE_SHIFT 14
-#define DSI_SYNC_PULSE_ACTIVE_SHIFT 15
-#define DSI_SYNC_PULSE_HORIZONTAL_SHIFT 16
-#define DSI_BLKLINE_SHIFT 17
-#define DSI_BLKEOL_SHIFT 19
-#define DSI_RECOVERY_MODE_SHIFT 21
-#define DSI_VBP_LENGTH_SHIFT 4
-#define DSI_VFP_LENGTH_SHIFT 8
-#define DSI_VACT_LENGTH_SHIFT 16
-#define DSI_HBP_LENGTH_SHIFT 8
-#define DSI_HFP_LENGTH_SHIFT 16
-#define DSI_LINE_VAL_SHIFT 2
-#define DSI_HORI_VAL_SHIFT 3
-#define DSI_BURST_LP_SHIFT 16
-#define DSI_MAX_LINE_LIMIT_SHIFT 16
-#define DSI_BLKEOL_PCK_SHIFT 13
-#define DSI_VERT_BLANK_DURATION_SHIFT 13
-#define DSI_COL_GREEN_SHIFT 8
-#define DSI_COL_BLUE_SHIFT 16
-#define DSI_PAD_VAL_SHIFT 24
-#define DSI_TVG_STRIPE_SHIFT 1
-#define DSI_TVG_MODE_SHIFT 3
-#define DSI_TVG_STOPMODE_SHIFT 5
-#define DSI_TVG_NBLINE_SHIFT 16
-#define DSIMCTL_DPHY_STATIC_SWAP_PINS_CLK_SHIFT 0
-#define DSIMCTL_DPHY_STATIC_HS_INVERT_CLK_SHIFT 1
-#define DSIMCTL_DPHY_STATIC_SWAP_PINS_DAT1_SHIFT 2
-#define DSIMCTL_DPHY_STATIC_HS_INVERT_DAT1_SHIFT 3
-#define DSIMCTL_DPHY_STATIC_SWAP_PINS_DAT2_SHIFT 4
-#define DSIMCTL_DPHY_STATIC_HS_INVERT_DAT2_SHIFT 5
-#define DSIMCTL_DPHY_STATIC_UI_X4_SHIFT 6
-#define DSI_IF1_LPM_EN_MASK_SHIFT 4
-#define DSI_IF2_LPM_EN_MASK_SHIFT 5
-
-#define DSI_MCTL_MAIN_STS_VRS_UNTERM_PCK 0x80
-#define DSI_MCTL_MAIN_STS_VRS_UNTERM_PCK_SHIFT 7
-
-#define DSI_MCTL_MAIN_STS_CRS_UNTERM_PCK 0x40
-#define DSI_MCTL_MAIN_STS_CRS_UNTERM_PCK_SHIFT 6
-
-#define DSI_MCTL_MAIN_STS_LPRX_TO_ERR 0x20
-#define DSI_MCTL_MAIN_STS_LPRX_TO_ERR_SHIFT 5
-
-#define DSI_MCTL_MAIN_STS_HSTX_TO_ERR 0x10
-#define DSI_MCTL_MAIN_STS_HSTX_TO_ERR_SHIFT 4
-
-#define DSI_MCTL_MAIN_STS_DAT2_READY 0x8
-#define DSI_MCTL_MAIN_STS_DAT2_READY_SHIFT 3
-
-#define DSI_MCTL_MAIN_STS_DAT1_READY 0x4
-#define DSI_MCTL_MAIN_STS_DAT1_READY_SHIFT 2
-
-#define DSI_MCTL_MAIN_STS_CLKLANE_READY 0x2
-#define DSI_MCTL_MAIN_STS_CLKLANE_READY_SHIFT 1
-
-#define DSI_MCTL_MAIN_STS_PLL_LOCK 0x1
-#define DSI_MCTL_MAIN_STS_PLL_LOCK_SHIFT 0
-/** Test mode conf */
-
-//**********************************************************************************************************************
-/** - DIRECT_CMD_WRDAT0 */
-//**********************************************************************************************************************
-
-#define DSIDIRECT_CMD_WRDAT0_WRDAT3 (0xFF000000)
-#define Shift_DSIDIRECT_CMD_WRDAT0_WRDAT3 (24)
-#define DSIDIRECT_CMD_WRDAT0_WRDAT2 (0xFF0000)
-#define Shift_DSIDIRECT_CMD_WRDAT0_WRDAT2 (16)
-#define DSIDIRECT_CMD_WRDAT0_WRDAT1 (0xFF00)
-#define Shift_DSIDIRECT_CMD_WRDAT0_WRDAT1 (8)
-#define DSIDIRECT_CMD_WRDAT0_WRDAT0 (0xFF)
-#define Shift_DSIDIRECT_CMD_WRDAT0_WRDAT0 (0)
-
-//**********************************************************************************************************************
-/** - DIRECT_CMD_WRDAT1 */
-//**********************************************************************************************************************
-
-#define DSIDIRECT_CMD_WRDAT1_WRDAT7 (0xFF000000)
-#define Shift_DSIDIRECT_CMD_WRDAT1_WRDAT7 (24)
-#define DSIDIRECT_CMD_WRDAT1_WRDAT6 (0xFF0000)
-#define Shift_DSIDIRECT_CMD_WRDAT1_WRDAT6 (16)
-#define DSIDIRECT_CMD_WRDAT1_WRDAT5 (0xFF00)
-#define Shift_DSIDIRECT_CMD_WRDAT1_WRDAT5 (8)
-#define DSIDIRECT_CMD_WRDAT1_WRDAT4 (0xFF)
-#define Shift_DSIDIRECT_CMD_WRDAT1_WRDAT4 (0)
-
-
-//**********************************************************************************************************************
-/** - DIRECT_CMD_WRDAT2 */
-//**********************************************************************************************************************
-
-#define DSIDIRECT_CMD_WRDAT2_WRDAT11 (0xFF000000)
-#define Shift_DSIDIRECT_CMD_WRDAT2_WRDAT11 (24)
-#define DSIDIRECT_CMD_WRDAT2_WRDAT10 (0xFF0000)
-#define Shift_DSIDIRECT_CMD_WRDAT2_WRDAT10 (16)
-#define DSIDIRECT_CMD_WRDAT2_WRDAT9 (0xFF00)
-#define Shift_DSIDIRECT_CMD_WRDAT2_WRDAT9 (8)
-#define DSIDIRECT_CMD_WRDAT2_WRDAT8 (0xFF)
-#define Shift_DSIDIRECT_CMD_WRDAT2_WRDAT8 (0)
-
-//**********************************************************************************************************************
-/** - DIRECT_CMD_WRDAT3 */
-//**********************************************************************************************************************
-
-#define DSIDIRECT_CMD_WRDAT3_WRDAT15 (0xFF000000)
-#define Shift_DSIDIRECT_CMD_WRDAT3_WRDAT15 (24)
-#define DSIDIRECT_CMD_WRDAT3_WRDAT14 (0xFF0000)
-#define Shift_DSIDIRECT_CMD_WRDAT3_WRDAT14 (16)
-#define DSIDIRECT_CMD_WRDAT3_WRDAT13 (0xFF00)
-#define Shift_DSIDIRECT_CMD_WRDAT3_WRDAT13 (8)
-#define DSIDIRECT_CMD_WRDAT3_WRDAT12 (0xFF)
-#define Shift_DSIDIRECT_CMD_WRDAT3_WRDAT12 (0)
-//**********************************************************************************************************************
-/** - DIRECT_CMD_READ */
-//**********************************************************************************************************************
-
-#define DSIDIRECT_CMD_RDAT3 (0xFF000000)
-#define Shift_DSIDIRECT_CMD_RDAT3 (24)
-#define DSIDIRECT_CMD_RDAT2 (0xFF0000)
-#define Shift_DSIDIRECT_CMD_RDAT2 (16)
-#define DSIDIRECT_CMD_RDAT1 (0xFF00)
-#define Shift_DSIDIRECT_CMD_RDAT1 (8)
-#define DSIDIRECT_CMD_RDAT0 (0xFF)
-#define Shift_DSIDIRECT_CMD_RDAT0 (0)
-
-/** TPO COMMAND HEADER */
-#define TPO_CMD_NONE 0x00
-#define TPO_CMD_SWRESET 0x01 /** SWRESET: Software Reset (01h) */
-#define TPO_CMD_SLPOUT 0x11 /** SLPOUT: Sleep Out (11h) */
-#define TPO_CMD_NORON 0x13 /** NORON: Normal Display Mode On (13h) */
-#define TPO_CMD_INVOFF 0x20 /** INVOFF: Display Inversion Off (20h) */
-#define TPO_CMD_INVON 0x21 /** INVOFF: Display Inversion Off (20h) */
-#define TPO_CMD_GAMMA_SET 0x26 /** Gamma set//reset GC0G2.2 */
-
-#define TPO_CMD_DISPOFF 0x28 /** DISPON: Display On (29h) */
-#define TPO_CMD_DISPON 0x29 /** DISPON: Display On (29h) */
-#define TPO_CMD_CASET 0x2A /** CASET :Columen address select */
-#define TPO_CMD_RASET 0x2B /** RASET :Row address select */
-#define TPO_CMD_RAMWR 0x2C /** RAMWR ram write */
-
-#define TPO_CMD_MADCTR 0x36 /** MADCTR: Memory Data Access Control (36h) */
-#define TPO_CMD_IDMOFF 0x38 /** IDMON: Idle Mode On (39h) */
-#define TPO_CMD_IDMON 0x39 /** IDMON: Idle Mode On (39h) */
-#define TPO_CMD_COLMOD 0x3A /** COLMOD: Interface Pixel Format (3Ah). */
-#define TPO_CMD_RAMWR_CONTINUE 0x3C /** Ram write continue */
-#define TPO_CMD_IFMODE 0xB0 /** IFMODE: Set Display Interface Mode (B0h) */
-#define TPO_CMD_DISSET6 0xB7 /** Display Function Setting 6 (B7h) */
-#define TPO_CMD_LPTS_FUNCTION_SET3 0xBC /** LPTS_FUNCTION_SET3 (0xBC) */
-#define TPO_CMD_DSLPOUT 0xCA /** deep sleepout 0xca */
-
-
-#define TPO_CMD_GAMCTRP1 0xE0 /** GAMCTRP1: Set Positive Gamma Correction Characteristics (E0h) */
-#define TPO_CMD_GAMCTRN1 0xE1 /** GAMCTRN1: Set Negative Gamma Correction Characteristics (E1h) */
-#define TPO_CMD_GAMCTRP2 0xE2 /** GAMCTRP2: Gamma (‘+’polarity) Correction Characteristics Setting (E2h) */
-#define TPO_CMD_GAMCTRN2 0xE3 /** GAMCTRN2: Gamma (‘-’polarity) Correction Characteristics Setting (E3h) */
-#define TPO_CMD_GAMCTRP3 0xE4 /** GAMCTRP3: Gamma (‘+’polarity) Correction Characteristics Setting (E4h) */
-#define TPO_CMD_GAMCTRN3 0xE5 /** GAMCTRN3: Gamma (‘-’polarity) Correction Characteristics Setting (E5h) */
-#define TPO_CMD_GAM_R_SEL 0xEA /** GAMMA SELECTION */
-
-
-
-#define VC_ID0 0
-#define VC_ID1 1
-
-
-
-
-struct dsi_link_registers
-{
- /** Main control registers */
- volatile u32 mctl_integration_mode;
- volatile u32 mctl_main_data_ctl;
- volatile u32 mctl_main_phy_ctl;
- volatile u32 mctl_pll_ctl;
- volatile u32 mctl_lane_sts;
- volatile u32 mctl_dphy_timeout;
- volatile u32 mctl_ulpout_time;
- volatile u32 mctl_dphy_static;
- volatile u32 mctl_main_en;
- volatile u32 mctl_main_sts;
- volatile u32 mctl_dphy_err;
-
- volatile u32 reserved1;
- /**
- integration mode registers */
- volatile u32 int_vid_rddata;
- volatile u32 int_vid_gnt;
- volatile u32 int_cmd_rddata;
- volatile u32 int_cmd_gnt;
- volatile u32 int_interrupt_ctl;
- volatile u32 reserved2[3];
- /**
- Command mode registers */
- volatile u32 cmd_mode_ctl;
- volatile u32 cmd_mode_sts;
- volatile u32 reserved3[2];
- /**
- Direct Command registers */
- volatile u32 direct_cmd_send;
- volatile u32 direct_cmd_main_settings;
- volatile u32 direct_cmd_sts;
- volatile u32 direct_cmd_rd_init;
- volatile u32 direct_cmd_wrdat0;
- volatile u32 direct_cmd_wrdat1;
- volatile u32 direct_cmd_wrdat2;
- volatile u32 direct_cmd_wrdat3;
- volatile u32 direct_cmd_rddat;
- volatile u32 direct_cmd_rd_property;
- volatile u32 direct_cmd_rd_sts;
- volatile u32 reserved4;
- /**
- Video mode registers */
- volatile u32 vid_main_ctl;
- volatile u32 vid_vsize;
- volatile u32 vid_hsize1;
- volatile u32 vid_hsize2;
- volatile u32 vid_blksize1;
- volatile u32 vid_blksize2;
- volatile u32 vid_pck_time;
- volatile u32 vid_dphy_time;
- volatile u32 vid_err_color;
- volatile u32 vid_vpos;
- volatile u32 vid_hpos;
- volatile u32 vid_mode_sts;
- volatile u32 vid_vca_setting1;
- volatile u32 vid_vca_setting2;
- /**
- Test Video Mode regsiter */
- volatile u32 tvg_ctl;
- volatile u32 tvg_img_size;
- volatile u32 tvg_color1;
- volatile u32 tvg_color2;
- volatile u32 tvg_sts;
- volatile u32 reserved5;
- /**
- Test Byte generator register */
- volatile u32 tbg_ctl;
- volatile u32 tbg_setting;
- volatile u32 tbg_sts;
- volatile u32 reserved6;
- /**
- Interrupt Enable and Edge detection register */
- volatile u32 mctl_main_sts_ctl;
- volatile u32 cmd_mode_sts_ctl;
- volatile u32 direct_cmd_sts_ctl;
- volatile u32 direct_cmd_rd_sts_ctl;
- volatile u32 vid_mode_sts_ctl;
- volatile u32 tg_sts_ctl;
- volatile u32 mctl_dphy_err_ctl;
- volatile u32 dphy_clk_trim_rd_ctl;
- /**
- Error/Interrupt Clear Register */
- volatile u32 mctl_main_sts_clr;
- volatile u32 cmd_mode_sts_clr;
- volatile u32 direct_cmd_sts_clr;
- volatile u32 direct_cmd_rd_sts_clr;
- volatile u32 vid_mode_sts_clr;
- volatile u32 tg_sts_clr;
- volatile u32 mctl_dphy_err_clr;
- volatile u32 dphy_clk_trim_rd_clr;
- /**
- Flag registers */
- volatile u32 mctl_main_sts_flag;
- volatile u32 cmd_mode_sts_flag;
- volatile u32 direct_cmd_sts_flag;
- volatile u32 direct_cmd_rd_sts_flag;
- volatile u32 vid_mode_sts_flag;
- volatile u32 tg_sts_flag;
- volatile u32 mctl_dphy_err_flag;
- volatile u32 dphy_clk_trim_rd_flag;
- volatile u32 dhy_lanes_trim;
-};
-
-
-
-#ifdef _cplusplus
-}
-#endif /* _cplusplus */
-
-#endif /* !defined(_DSI_H_) */
-
-
diff --git a/arch/arm/mach-ux500/include/mach/hardware.h b/arch/arm/mach-ux500/include/mach/hardware.h
index 2cd5a48d02a..a0adb5402ce 100755
--- a/arch/arm/mach-ux500/include/mach/hardware.h
+++ b/arch/arm/mach-ux500/include/mach/hardware.h
@@ -164,7 +164,11 @@
/* B2R2 clock management register */
#define PRCM_B2R2CLK_MGT_REG 0x80157078 /** B2R2 clock selection */
-#include <mach/mcde-base.h>
+#define U8500_DSI_LINK1_BASE 0xA0351000
+#define U8500_DSI_LINK_SIZE 0x1000
+#define U8500_DSI_LINK_COUNT 0x3
+#define U8500_DSI_LINK2_BASE (U8500_DSI_LINK1_BASE + U8500_DSI_LINK_SIZE)
+#define U8500_DSI_LINK3_BASE (U8500_DSI_LINK2_BASE + U8500_DSI_LINK_SIZE)
#ifndef __ASSEMBLY__
diff --git a/arch/arm/mach-ux500/include/mach/mcde-base.h b/arch/arm/mach-ux500/include/mach/mcde-base.h
deleted file mode 100644
index c785fcac2de..00000000000
--- a/arch/arm/mach-ux500/include/mach/mcde-base.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * Copyright (C) 2010 ST-Ericsson
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-/* MCDE specific declaration */
-#ifdef CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT
-
-#define U8500_MCDE_REGISTER_BANK_SIZE 0x20
-#define U8500_MCDE_BASE_SIZE 0x200
-
-#define U8500_MCDE_EXTSRC_BASE (U8500_MCDE_BASE + U8500_MCDE_BASE_SIZE)
-#define U8500_MCDE_EXTSRC_SIZE (U8500_MCDE_REGISTER_BANK_SIZE * 0x10)
-
-#define U8500_MCDE_OVERLAY_BASE (U8500_MCDE_BASE + 0x400)
-#define U8500_MCDE_OVERLAY_SIZE (0x20 * 0x10)
-
-#define U8500_MCDE_CHANNELA_CONFIG_BASE (U8500_MCDE_BASE + 0x600) /* MCDE channel config registers */
-#define U8500_MCDE_CHANNELB_CONFIG_BASE (U8500_MCDE_BASE + 0x600) /* MCDE channel config registers */
-#define U8500_MCDE_CHANNELC0_CONFIG_BASE (U8500_MCDE_BASE + 0x600) /* MCDE channel config registers */
-#define U8500_MCDE_CHANNELC1_CONFIG_BASE (U8500_MCDE_BASE + 0x600) /* MCDE channel config registers */
-#define U8500_MCDE_CHANNEL_CONFIG_SIZE (0x20 * 0x10)
-
-#define U8500_MCDE_CHANNELA_SPECIFIC_REGISTER_BASE (U8500_MCDE_BASE + 0x800) /* MCDE channel A specific registers */
-#define U8500_MCDE_CHANNELA_SPECIFIC_REGISTER_SIZE 0x200
-
-#define U8500_MCDE_CHANNELB_SPECIFIC_REGISTER_BASE (U8500_MCDE_BASE + 0xA00) /* MCDE channel B specific registers */
-#define U8500_MCDE_CHANNELB_SPECIFIC_REGISTER_SIZE 0x200
-
-#define U8500_MCDE_CHANNELC0C1_SPECIFIC_REGISTER_BASE (U8500_MCDE_BASE + 0xC00) /* MCDE channel C0/C1 speicific registers */
-#define U8500_MCDE_CHANNELC0C1_SPECIFIC_REGISTER_SIZE 0xCB
-
-#define U8500_MCDE_DSI_CHANNEL_BASE (U8500_MCDE_BASE + 0xE00) /* MCDE channelC0 config registers */
-#define U8500_MCDE_DSI_CHANNEL_SIZE 0x20
-#define U8500_MCDE_DSI_SIZE 0xF4
-#define U8500_MCDE_DSI_CLOCK_OFFSET 0xF0 /* MCDE DSI clock */
-#define U8500_DSI_LINK1_BASE 0xA0351000
-#define U8500_DSI_LINK_SIZE 0x1000
-#define U8500_DSI_LINK_COUNT 0x3
-#define U8500_DSI_LINK2_BASE (U8500_DSI_LINK1_BASE + U8500_DSI_LINK_SIZE)
-#define U8500_DSI_LINK3_BASE (U8500_DSI_LINK2_BASE + U8500_DSI_LINK_SIZE)
-
-#define PRCM_HDMICLK_MGT_REG 0x80157058 /** HDMI clock selection */
-#define PRCM_MCDECLK_MGT_REG 0x80157064 /** MCDE clock selection */
-#define PRCM_TVCLK_MGT_REG 0x8015707c /** MCDE clock selection */
-
-#else /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */
-
-#define U8500_MCDE_REGISTER_SIZE 0x20
-#define U8500_MCDE_EXTSRC_BASE 0xA0350200
-#define U8500_MCDE_EXTSRC_SIZE (0x20 * 0x10)
-#define U8500_MCDE_OVL_BASE 0xA0350400
-#define U8500_MCDE_OVL_SIZE (0x20 * 0x10)
-#define U8500_MCDE_CHANNELA_CONFIG_BASE 0xA0350600 /* MCDE channelA config registers */
-#define U8500_MCDE_CHANNEL_CONFIG_SIZE (0x20 * 0x10)
-#define U8500_MCDE_CHANNELA_SPECIFIC_REGISTER_BASE 0xA0350800 /* MCDE channelA specific registers */
-#define U8500_MCDE_CHANNEL_SPECIFIC_REGISTER_SIZE 0x80
-#define U8500_MCDE_CHANNELB_CONFIG_BASE 0xA0350600 /* MCDE channelA config registers */
-#define U8500_MCDE_CHANNELB_SPECIFIC_REGISTER_BASE 0xA0350A00 /* MCDE channelA specific registers */
-#define U8500_MCDE_CHANNELC0_CONFIG_BASE 0xA0350600 /* MCDE channelC0 config registers */
-#define U8500_MCDE_CHANNELC_SPECIFIC_REGISTER_BASE 0xA0350C00 /* MCDE channelC specific registers */
-#define U8500_MCDE_CHANNELC1_CONFIG_BASE 0xA0350600 /* MCDE channelC1 config registers */
-#define U8500_MCDE_CHANNELC_SPECIFIC_REGISTER_BASE 0xA0350C00 /* MCDE channelC specific registers */
-#define U8500_MCDE_CHANNELC_SPECIFIC_REGISTER_SIZE 0xA8
-#define U8500_MCDE_DSI_CHANNEL_BASE 0xA0350E00 /* MCDE channelC0 config registers */
-#define U8500_MCDE_DSI_CHANNEL_SIZE 0x20
-#define U8500_MCDE_DSI_SIZE 0xF4
-#define U8500_MCDE_DSI_CLOCK_OFFSET 0xF0 /* MCDE DSI clock */
-#define U8500_DSI_LINK1_BASE 0xA0351000
-#define U8500_DSI_LINK_SIZE 0x1000
-#define U8500_DSI_LINK_COUNT 0x3
-#define U8500_DSI_LINK2_BASE (U8500_DSI_LINK1_BASE + U8500_DSI_LINK_SIZE)
-#define U8500_DSI_LINK3_BASE (U8500_DSI_LINK2_BASE + U8500_DSI_LINK_SIZE)
-
-#define PRCM_HDMICLK_MGT_REG 0x80157058 /** HDMI clock selection */
-#define PRCM_MCDECLK_MGT_REG 0x80157064 /** MCDE clock selection */
-#define PRCM_TVCLK_MGT_REG 0x8015707c /** MCDE clock selection */
-
-#endif /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */
-
diff --git a/arch/arm/mach-ux500/include/mach/mcde.h b/arch/arm/mach-ux500/include/mach/mcde.h
deleted file mode 100755
index 20437af76b9..00000000000
--- a/arch/arm/mach-ux500/include/mach/mcde.h
+++ /dev/null
@@ -1,1387 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * License terms:
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#ifndef _MCDE_H_
-#define _MCDE_H_
-#include <linux/gpio.h>
-#include <linux/fb.h>
-#include <mach/mcde_ioctls.h>
-
-#ifdef __KERNEL__
-
-/*******************************************************************************
- MCDE Control Enums and structures
- ******************************************************************************/
-/* typedef enum
-{
- MCDE_CH_A_LSB = 0x00,
- MCDE_CH_A_MID = 0x01,
- MCDE_CH_A_MSB = 0x02,
- MCDE_CH_B_LSB = 0x03,
- MCDE_CH_B_MID = 0x04,
- MCDE_CH_B_MSB = 0x05,
- MCDE_CH_C_LSB = 0x06
-}mcde_out_mux_cfg;
-
-typedef enum
-{
- MCDE_CH_NORMAL_MODE = 0x0,
- MCDE_CH_MUX_MODE = 0x1
-}mcde_ch_ctrl;
-*/
- typedef enum
- {
- MCDE_CH_FIFO_A_ENABLE = 0x0,
- MCDE_CH_FIFO_B_ENABLE = 0x1
- }mcde_ch_fifo_ab_mux_ctrl;
-
- typedef enum
- {
- MCDE_CH_FIFO_0_ENABLE = 0x0,
- MCDE_CH_FIFO_1_ENABLE = 0x1
- }mcde_ch_fifo_01_mux_ctrl;
-
- typedef enum
- {
- MCDE_INPUT_FIFO_DISABLE = 0x0,
- MCDE_INPUT_FIFO_ENABLE = 0x1
- }mcde_input_fifo_ctrl;
-
- typedef enum
- {
- MCDE_DPI_DISABLE = 0x0,
- MCDE_DPI_ENABLE = 0x1
- }mcde_dpi_ctrl;
-
- typedef enum
- {
- MCDE_DBI_DISABLE = 0x0,
- MCDE_DBI_ENABLE = 0x1
- }mcde_dbi_ctrl;
-
- typedef enum
- {
- MCDE_DSIVID_DISABLE = 0x0,
- MCDE_DSIVID_ENABLE = 0x1
- }mcde_dsivid_ctrl;
-
- typedef enum
- {
- MCDE_DSICMD_DISABLE = 0x0,
- MCDE_DSICMD_ENABLE = 0x1
- }mcde_dsicmd_ctrl;
-
- typedef enum
- {
- MCDE_WTRMRK_LEVEL_0,
- MCDE_WTRMRK_LEVEL_1,
- MCDE_WTRMRK_LEVEL_2,
- MCDE_WTRMRK_LEVEL_3,
- MCDE_WTRMRK_LEVEL_4,
- MCDE_WTRMRK_LEVEL_5,
- MCDE_WTRMRK_LEVEL_6,
- MCDE_WTRMRK_LEVEL_7
- }mcde_fifo_wrtmrk_level;
- typedef enum
- {
- MCDE_CH_AB_FRAMESYNC_DPI = 0x0,
- MCDE_CH_AB_FRAMESYNC_DBI = 0x1
- }mcde_ch_ab_framesync_cfg;
-
-typedef enum
-{
- MCDE_DISABLE = 0x0,
- MCDE_ENABLE = 0x1
-}mcde_state;
-
-typedef enum
-{
- MCDE_CH_A_OUTPUT_FIFO_B = 0x0,
- MCDE_CH_A_OUTPUT_FIFO_C1 = 0x1
- }mcde_fifo_sel_bc1_cfg;
-
- typedef enum
- {
- MCDE_CH_A_OUTPUT_FIFO_A = 0x0,
- MCDE_CH_A_OUTPUT_FIFO_C0 = 0x1
- }mcde_fifo_sel_ac0_cfg;
-
- typedef enum
- {
- MCDE_CH_B_PULSE_PANEL7 = 0x0,
- MCDE_CH_C0C1_PULSE_PANEL = 0x1
- }mcde_sync_mux7_cfg;
-
- typedef enum
- {
- MCDE_CH_A_PULSE_PANEL = 0x0,
- MCDE_CH_B_PULSE_PANEL6 = 0x1
- }mcde_sync_mux6_cfg;
-
- typedef enum
- {
- MCDE_CH_B_CLK_PANEL5 = 0x0,
- MCDE_CH_C_CHIP_SELECT5 = 0x1
- }mcde_sync_mux5_cfg;
-
- typedef enum
- {
- MCDE_CH_A_CLK_PANEL4 = 0x0,
- MCDE_CH_B_CLK_PANEL4 = 0x1
- }mcde_sync_mux4_cfg;
-/*
-typedef enum
-{
- MCDE_CHIPSELECT_C0 = 0x0,
- MCDE_CHIPSELECT_C1 = 0x1
-}mcde_sync_mux23_cfg;
-
-typedef enum
-{
- MCDE_CH_A_OUT_ENABLE = 0x0,
- MCDE_CH_C_OUT_ENABLE = 0x1
-}mcde_sync_mux1_cfg;
-*/
- typedef enum
- {
- MCDE_CH_A_CLK_PANEL0 = 0x0,
- MCDE_CH_C_CHIP_SELECT0 = 0x1
- }mcde_sync_mux0_cfg;
-/*
-struct mcde_config
-{
- mcde_out_mux_cfg data_msb1;
- mcde_out_mux_cfg data_msb0;
- mcde_out_mux_cfg data_mid;
- mcde_out_mux_cfg data_lsb1;
- mcde_out_mux_cfg data_lsb0;
- mcde_fifo_wrtmrk_level fifo_wtrmrk_level;
- mcde_ch_ab_framesync_cfg ch_b_frame_sync_ctrl;
- mcde_ch_ab_framesync_cfg ch_a_frame_sync_ctrl;
- mcde_fifo_sel_bc1_cfg ch_b_fifo_sel;
- mcde_fifo_sel_ac0_cfg ch_a_fifo_sel;
- mcde_sync_mux7_cfg panel_mcdeblp;
- mcde_sync_mux6_cfg panel_mcdeealp;
- mcde_sync_mux4_cfg panel_mcdebcp;
- mcde_sync_mux4_cfg panel_mcdeacp4;
- mcde_sync_mux23_cfg panel_mcdeaspl;
- mcde_sync_mux23_cfg panel_mcdeaps;
- mcde_sync_mux1_cfg panel_mcdealp;
- mcde_sync_mux0_cfg panel_mcdeacp;
-};*/
- struct mcde_control
- {
- mcde_ch_fifo_ab_mux_ctrl ch_fifo_ab_mux;
- mcde_ch_fifo_01_mux_ctrl ch_fifo_01_mux;
- mcde_input_fifo_ctrl input_fifo_enable;
- mcde_dpi_ctrl dpi_a_enable;
- mcde_dpi_ctrl dpi_b_enable;
- mcde_dbi_ctrl dbi_c0_enable;
- mcde_dbi_ctrl dbi_c1_enable;
- mcde_dsivid_ctrl dsi_vid0_enable;
- mcde_dsivid_ctrl dsi_vid1_enable;
- mcde_dsivid_ctrl dsi_vid2_enable;
- mcde_dsicmd_ctrl dsi_cmd0_enable;
- mcde_dsicmd_ctrl dsi_cmd1_enable;
- mcde_dsicmd_ctrl dsi_cmd2_enable;
- };
-/*
-struct mcde_ch_mode_ctrl
-{
- mcde_ch_ctrl sync_ctrl_chA;
- mcde_ch_ctrl sync_ctrl_chB;
- mcde_ch_ctrl flow_ctrl_chA;
- mcde_ch_ctrl flow_ctrl_chB;
-};
-*/
- struct mcde_irq_status
- {
- u32 irq_status;
- u32 event_status;
- u8 is_new;
- } ;
-/*
-typedef enum
-{
- MCDE_EVENT_MASTER_BUS_ERROR = 0x01,
- MCDE_EVENT_END_OF_FRAME_TRANSFER = 0x02,
- MCDE_EVENT_SYNCHRO_CAPTURE_TRIGGER = 0x04,
- MCDE_EVENT_HORIZONTAL_SYNCHRO_CAPTURE = 0x08,
- MCDE_EVENT_VERTICAL_SYNCHRO_CAPTURE = 0x10
-} mcde_event_id;
-*/
-/* Check *********************************/
-
-typedef enum
-{
- MCDE_CH_A_LSB = 0x00,
- MCDE_CH_A_MID = 0x01,
- MCDE_CH_A_MSB = 0x02,
- MCDE_CH_B_LSB = 0x03,
- MCDE_CH_B_MID = 0x04,
- MCDE_CH_B_MSB = 0x05,
- MCDE_CH_C_LSB = 0x06
-}mcde_out_mux_ctrl;
-
-typedef enum
-{
- MCDE_FIFO_FA = 0x0,
- MCDE_FIFO_FB = 0x1,
- MCDE_FIFO_F0 = 0x2,
- MCDE_FIFO_F1 = 0x3
-}mcde_fifo;
-
-typedef enum
-{
- MCDE_DPI_A = 0x0,
- MCDE_DPI_B = 0x1,
- MCDE_DBI_C0 = 0x2,
- MCDE_DBI_C1 = 0x3,
- MCDE_DSI_VID0 = 0x4,
- MCDE_DSI_VID1 = 0x5,
- MCDE_DSI_VID2 = 0x6,
- MCDE_DSI_CMD0 = 0x7,
- MCDE_DSI_CMD1 = 0x8,
- MCDE_DSI_CMD2 = 0x9
-}mcde_fifo_output;
-
-struct mcde_fifo_ctrl
-{
- mcde_fifo_output out_fifoa;
- mcde_fifo_output out_fifob;
- mcde_fifo_output out_fifo0;
- mcde_fifo_output out_fifo1;
-};
-
-typedef enum
-{
- MCDE_CH_NORMAL_MODE = 0x0,
- MCDE_CH_MUX_MODE = 0x1
-}mcde_ch_ctrl;
-
-typedef enum
-{
- MCDE_CHIPSELECT_C0 = 0x0,
- MCDE_CHIPSELECT_C1 = 0x1
-}mcde_sync_mux_ctrl;
-
-typedef enum
-{
- MCDE_CH_A_OUT_ENABLE = 0x0,
- MCDE_CH_C_OUT_ENABLE = 0x1
-}mcde_sync_mux1_ctrl;
-
-typedef enum
-{
- MCDE_CH_A_CLK_PANEL = 0x0,
- MCDE_CH_C_CHIP_SELECT = 0x1
-}mcde_sync_mux0_ctrl;
-
-typedef enum
-{
- MCDE_CDI_CH_A = 0x0,
- MCDE_CDI_CH_B = 0x1
-}mcde_cdi_ctrl;
-
-typedef enum
-{
- MCDE_CDI_DISABLE = 0x0,
- MCDE_CDI_ENABLE = 0x1
-}mcde_cdi;
-/*
-typedef enum
-{
- MCDE_DISABLE = 0x0,
- MCDE_ENABLE = 0x1
-}mcde_state;
-
-typedef struct
-{
- t_mcde_out_mux_ctrl data_msb1;
- t_mcde_out_mux_ctrl data_msb0;
- t_mcde_out_mux_ctrl data_mid;
- t_mcde_out_mux_ctrl data_lsb1;
- t_mcde_out_mux_ctrl data_lsb0;
- u8 ififo_watermark;
-}mcde_control;
-*/
-typedef enum
-{
- MCDE_OUTPUT_FIFO_B = 0x0,
- MCDE_OUTPUT_FIFO_C1 = 0x1
-}mcde_swap_b_c1_ctrl;
-
-typedef enum
-{
- MCDE_CONF_TVA_DPIC0_LCDB = 0x0,
- MCDE_CONF_TVB_DPIC1_LCDA = 0x1,
- MCDE_CONF_DPIC1_LCDA = 0x2,
- MCDE_CONF_DPIC0_LCDB = 0x3,
- MCDE_CONF_LCDA_LCDB = 0x4,
- MCDE_CONF_DSI = 0x5
-}mcde_output_conf;
-
-typedef enum
-{
- MCDE_OUTPUT_FIFO_A = 0x0,
- MCDE_OUTPUT_FIFO_C0 = 0x1
-}mcde_swap_a_c0_ctrl;
-
-/*
-typedef struct
-{
- u32 irq_status;
- u32 event_status;
- t_bool is_new;
-}mcde_irq_status;
-*/
- typedef enum
- {
- MCDE_EVENT_MASTER_BUS_ERROR = 0x01,
- MCDE_EVENT_END_OF_FRAME_TRANSFER = 0x02,
- MCDE_EVENT_SYNCHRO_CAPTURE_TRIGGER = 0x04,
- MCDE_EVENT_HORIZONTAL_SYNCHRO_CAPTURE = 0x08,
- MCDE_EVENT_VERTICAL_SYNCHRO_CAPTURE = 0x10
- } mcde_event_id;
-
-typedef struct
-{
- u8 pllfreq_div;
- u8 datachannels_num;
- u8 delay_clk;
- u8 delay_d2;
- u8 delay_d1;
- u8 delay_d0;
-}mcde_cdi_delay;
-/*******************************************************************************
- External Source Enums and Structures
- ******************************************************************************/
-
- typedef enum
- {
- MCDE_EXT_SRC_0 = 0x0,
- MCDE_EXT_SRC_1 = 0x1,
- MCDE_EXT_SRC_2 = 0x2,
- MCDE_EXT_SRC_3 = 0x3,
- MCDE_EXT_SRC_4 = 0x4,
- MCDE_EXT_SRC_5 = 0x5,
- MCDE_EXT_SRC_6 = 0x6,
- MCDE_EXT_SRC_7 = 0x7,
- MCDE_EXT_SRC_8 = 0x8,
- MCDE_EXT_SRC_9 = 0x9,
- MCDE_EXT_SRC_10 = 0xA,
- MCDE_EXT_SRC_11 = 0xB,
- MCDE_EXT_SRC_12 = 0xC,
- MCDE_EXT_SRC_13 = 0xD,
- MCDE_EXT_SRC_14 = 0xE,
- MCDE_EXT_SRC_15 = 0xF
- }mcde_ext_src;
-
-
- typedef enum
- {
- MCDE_U8500_PANEL_1BPP=1,
- MCDE_U8500_PANEL_2BPP=2,
- MCDE_U8500_PANEL_4BPP=4,
- MCDE_U8500_PANEL_8BPP=8,
- MCDE_U8500_PANEL_16BPP=16,
- MCDE_U8500_PANEL_24BPP_PACKED=24,
- MCDE_U8500_PANEL_24BPP=25,
- MCDE_U8500_PANEL_32BPP=32,
- MCDE_U8500_PANEL_YCBCR=11,
- }mcde_fb_bpp;
-
- typedef enum
- {
- MCDE_U8500_PANEL_16BPP_RGB=35,
- MCDE_U8500_PANEL_16BPP_IRGB=36,
- MCDE_U8500_PANEL_16BPP_ARGB=37,
- MCDE_U8500_PANEL_12BPP=38,
- }mcde_fb_16bpp_type;
-
-
- typedef enum
- {
- MCDE_FS_FREQ_UNCHANGED = 0x0,
- MCDE_FS_FREQ_DIV_2 = 0x1
- }mcde_fs_div;
-
- typedef enum
- {
- MCDE_FS_FREQ_DIV_ENABLE = 0x0,
- MCDE_FS_FREQ_DIV_DISABLE = 0x1
- }mcde_fs_ctrl;
-
- typedef enum
- {
- MCDE_MULTI_CH_CTRL_ALL_OVR = 0x0,
- MCDE_MULTI_CH_CTRL_PRIMARY_OVR = 0x1
- }mcde_multi_ovr_ctrl;
-
- typedef enum
- {
- MCDE_BUFFER_SEL_EXT = 0x0,
- MCDE_BUFFER_AUTO_TOGGLE = 0x1,
- MCDE_BUFFER_SOFTWARE_SELECT = 0x2,
- MCDE_BUFFER_RESERVED
- }mcde_buffer_sel_mode;
-
- struct mcde_ext_src_ctrl
- {
- mcde_fs_div fs_div;
- mcde_fs_ctrl fs_ctrl;
- mcde_multi_ovr_ctrl ovr_ctrl;
- mcde_buffer_sel_mode sel_mode;
- };
-
-
-/*******************************************************************************
- Overlay Enums and Structures
- ******************************************************************************/
-
-
-/* typedef enum
- {
- MCDE_OVERLAY_0,
- MCDE_OVERLAY_1,
- MCDE_OVERLAY_2,
- MCDE_OVERLAY_3,
- MCDE_OVERLAY_4,
- MCDE_OVERLAY_5,
- MCDE_OVERLAY_6,
- MCDE_OVERLAY_7
- }mcde_overlay_id; */
-
-
-
-
-
-
-
- /* typedef enum
- {
- MCDE_OVR_INTERLACE_DISABLE = 0x0,
- MCDE_OVR_INTERLACE_ENABLE = 0x1
- }mcde_ovr_interlace_ctrl;
-
- typedef enum
- {
- MCDE_OVR_INTERLACE_TOPFIELD = 0x0,
- MCDE_OVR_INTERLACE_BOTTOMFIELD = 0x1
- }mcde_ovr_interlace_mode;*/
-
- typedef enum
- {
- MCDE_CH_A = 0x0,
- MCDE_CH_B = 0x1,
- MCDE_CH_C0 = 0x2,
- MCDE_CH_C1 = 0x3
- }mcde_ch_id;
-
- typedef enum
- {
- MCDE_FETCH_INPROGRESS = 0x0,
- MCDE_FETCH_COMPLETE = 0x1
- }mcde_ovr_fetch_status;
-
- typedef enum
- {
- MCDE_OVR_READ_COMPLETE = 0x0,
- MCDE_OVR_READ_INPROGRESS = 0x1
- }mcde_ovr_read_status;
-
- struct mcde_ovr_control
- {
- mcde_rotate_req rot_burst_req;
- mcde_outsnd_req outstnd_req;
- mcde_burst_req burst_req;
- u8 priority;
- mcde_color_key_ctrl color_key;
- mcde_pal_ctrl pal_control;
- mcde_col_conv_ctrl col_ctrl;
- mcde_overlay_ctrl ovr_state;
- mcde_ovr_alpha_enable alpha;
- mcde_ovr_clip_enable clip;
- };
-
- struct mcde_ovr_config
- {
- u32 line_per_frame;
- /* mcde_ovr_interlace_mode ovr_interlace;
- mcde_ovr_interlace_ctrl ovr_intlace_ctrl;*/
- mcde_ext_src src_id;
- u16 ovr_ppl;
- };
-
- struct mcde_ovr_conf2
- {
- u8 alpha_value;
- u8 pixoff;
- mcde_ovr_opq_ctrl ovr_opaq;
- mcde_blend_ctrl ovr_blend;
- u32 watermark_level;
- };
- /*
- struct mcde_ovr_blend_ctrl
- {
- u8 alpha_value;
- mcde_ovr_opq_ctrl ovr_opaq;
- mcde_blend_ctrl ovr_blend;
- u8 ovr_zlevel;
- u16 ovr_xpos;
- u16 ovr_ypos;
- };*/
-
- struct mcde_ovr_comp
- {
- u8 ovr_zlevel;
- u16 ovr_ypos;
- mcde_ch_id ch_id;
- u16 ovr_xpos;
- };
-
- struct mcde_ovr_clipincr
- {
- u32 lineincr;
- u32 yclip;
- u32 xclip;
- };
-
-struct mcde_ovr_clip
-{
- u32 ytlcoor;
- u32 xtlcoor;
- u32 ybrcoor;
- u32 xbrcoor;
-};
-
-typedef struct
-{
- u16 ovr_ypos;
- u16 ovr_xpos;
-}mcde_ovr_xy;
-
-
-typedef enum
-{
- MCDE_OVERLAY_NOT_BLOCKED = 0x0,
- MCDE_OVERLAY_BLOCKED = 0x1
-}mcde_ovr_blocked_status;
- struct mcde_ovr_status
- {
- mcde_ovr_blocked_status ovrb_status;
- mcde_ovr_fetch_status ovr_status;
- mcde_ovr_read_status ovr_read;
- };
-
- /*******************************************************************************
- Channel Configuration Enums and Structures
- ******************************************************************************/
-
-
-
- /* struct
- {
- u16 InitDelay;
- u16 PPDelay;
- }mcde_ch_delay;*/
-
- struct mcde_chsyncconf
- {
- u16 swint_vcnt;
- mcde_frame_events swint_vevent;
- u16 hwreq_vcnt;
- mcde_frame_events hwreq_vevent;
- };
-
- struct mcde_chsyncmod
- {
- mcde_synchro_out_interface out_synch_interface;
- mcde_synchro_source ch_synch_src;
- mcde_sw_trigger sw_trig;
-
- };
-
-
-
- struct mcde_ch_priority
- {
- u8 ch_priority;
- };
-
-typedef enum
-{
- MCDE_CHNL_RUNNING_NORMALLY = 0x0,
- MCDE_CHNL_ABORT_OCCURRED = 0x1
-}mcde_chnl_abort_state;
-
-typedef enum
-{
- MCDE_CHNL_READ_ONGOING = 0x0,
- MCDE_CHNL_READ_DONE = 0x1
-}mcde_chnl_read_status;
-
-typedef struct
-{
- mcde_chnl_abort_state abort_state;
- mcde_chnl_read_status read_state;
-}mcde_chnl_state;
- /*******************************************************************************
- Channel A/B Enums and Structures
- ******************************************************************************/
-
- typedef enum
- {
- MCDE_CLOCKWISE = 0x0,
- MCDE_ANTICLOCKWISE = 0x1
- }mcde_rot_dir;
-
- typedef enum
- {
- MCDE_GAMMA_ENABLE = 0x0,
- MCDE_GAMMA_DISABLE = 0x1
- }mcde_gamma_ctrl;
-
- typedef enum
- {
- MCDE_INPUT_YCrCb = 0x0,
- MCDE_INPUT_RGB = 0x1
- }mcde_flicker_format;
-
- typedef enum
- {
- MCDE_ALPHA_INPUTSRC = 0x0,
- MCDE_ALPHA_REGISTER = 0x1
- }mcde_blend_control;
-
- typedef enum
- {
- MCDE_FORCE_FILTER0 = 0x0,
- MCDE_ADAPTIVE_FILTER = 0x1,
- MCDE_TEST_MODE = 0x2
- }mcde_flicker_filter_mode;
-
-
- typedef enum
- {
- MCDE_ROTATION_DISABLE = 0x0,
- MCDE_ROTATION_ENABLE = 0x1
- }mcde_roten;
-
- typedef enum
- {
- MCDE_CLR_ENHANCE_DISABLE = 0x0,
- MCDE_CLR_ENHANCE_ENABLE = 0x1
- }mcde_clr_enhance_ctrl;
-
- typedef enum
- {
- MCDE_BLEND_DISABLE = 0x0,
- MCDE_BLEND_ENABLE = 0x1
- }mcde_blend_status;
-
-
- typedef enum
- {
- MCDE_VERTICAL_ACTIVE_FRAME_DISABLE = 0x0,
- MCDE_ALL_FRAME_ENABLE = 0x1
- }mcde_va_enable;
-
- typedef enum
- {
- MCDE_OUTPUT_NORMAL = 0x0,
- MCDE_OUTPUT_TOGGLE = 0x1
- }mcde_toggle_enable;
-
- typedef enum
- {
- MCDE_SYNCHRO_HBP = 0x0,
- MCDE_SYNCHRO_CLP = 0x1,
- MCDE_SYNCHRO_HFP = 0x2,
- MCDE_SYNCHRO_HSW = 0x3
- }mcde_loadsel;
-
- typedef enum
- {
- MCDE_DATA_RISING_EDGE = 0x0,
- MCDE_DATA_FALLING_EDGE = 0x1
- }mcde_data_lines;
-
- struct mcde_chx_control0
- {
- mcde_rotate_req chx_read_request;
- u8 alpha_blend;
- mcde_rot_dir rot_dir;
- mcde_gamma_ctrl gamma_ctrl;
- mcde_flicker_format flicker_format;
- mcde_flicker_filter_mode filter_mode;
- mcde_blend_control blend_ctrl;
- mcde_key_ctrl key_ctrl;
- mcde_roten rot_enable;
- mcde_dithering_control dither_ctrl;
- mcde_clr_enhance_ctrl color_enhance;
- mcde_antiflicker_ctrl anti_flicker;
- mcde_blend_status blend;
- };
- struct mcde_chx_rgb_conv_coef
- {
- u16 Yr_red;
- u16 Yr_green;
- u16 Yr_blue;
- u16 Cr_red;
- u16 Cr_green;
- u16 Cr_blue;
- u16 Cb_red;
- u16 Cb_green;
- u16 Cb_blue;
- u16 Off_red;
- u16 Off_green;
- u16 Off_blue;
- };
-
- struct mcde_chx_flickfilter_coef
- {
- u8 threshold_ctrl0;
- u8 threshold_ctrl1;
- u8 threshold_ctrl2;
- u8 Coeff0_N3;
- u8 Coeff0_N2;
- u8 Coeff0_N1;
- u8 Coeff1_N3;
- u8 Coeff1_N2;
- u8 Coeff1_N1;
- u8 Coeff2_N3;
- u8 Coeff2_N2;
- u8 Coeff2_N1;
- };
-
- struct mcde_chx_tv_control
- {
- u16 num_lines;
- mcde_tvmode tv_mode;
- mcde_signal_level ifield;
- mcde_display_mode sel_mode;
- };
-
- struct mcde_chx_tv_blanking_field
- {
- u16 blanking_start;
- u16 blanking_end;
- };
-
-struct mcde_chx_tv_blanking2_field
- {
- u16 blanking_start;
- u16 blanking_end;
- };
-
-
- struct mcde_chx_tv_start_line
- {
- u16 field2_start_line;
- u16 field1_start_line;
- };
-
- struct mcde_chx_tv_dvo_offset
- {
- u16 field2_window_offset;
- u16 field1_window_offset;
- };
-
- struct mcde_chx_tv_swh_time
- {
- u16 tv_swh2;
- u16 tv_swh1;
- };
-
- struct mcde_chx_tv_timing1
- {
- u16 src_window_width;
- u16 destination_hor_offset;
- };
-
- struct mcde_chx_tv_lbalw_timing
- {
- u16 active_line_width;
- u16 line_blanking_width;
- };
-
- struct mcde_chx_tv_background_time
- {
- u8 background_cr;
- u8 background_cb;
- u8 background_lu;
- };
-
-struct mcde_chx_lcd_timing0
- {
- mcde_va_enable rev_va_enable;
- mcde_toggle_enable rev_toggle_enable;
- mcde_loadsel rev_sync_sel;
- u8 rev_delay1;
- u8 rev_delay0;
- mcde_va_enable ps_va_enable;
- mcde_toggle_enable ps_toggle_enable;
- mcde_loadsel ps_sync_sel;
- u8 ps_delay1;
- u8 ps_delay0;
- };
-
- struct mcde_chx_lcd_timing1
- {
- mcde_signal_level io_enable;
- mcde_data_lines ipc;
- mcde_signal_level ihs;
- mcde_signal_level ivs;
- mcde_signal_level ivp;
- mcde_signal_level iclspl;
- mcde_signal_level iclrev;
- mcde_signal_level iclsp;
- mcde_va_enable mcde_spl;
- mcde_toggle_enable spltgen;
- mcde_loadsel spl_sync_sel;
- u8 spl_delay1;
- u8 spl_delay0;
- };
-
-
- struct mcde_chx_palette
- {
- u16 alphared;
- u8 green;
- u8 blue;
- };
-
- struct mcde_chx_gamma
- {
- u8 red;
- u8 green;
- u8 blue;
- };
- typedef enum
- {
- MCDE_ROTATE0 = 0x0,
- MCDE_ROTATE1 = 0x1
-}mcde_rotate_num;
-
-
- /*******************************************************************************
- Channel C Enums
- ******************************************************************************/
-
- typedef enum
- {
- MCDE_SYNCHRO_NONE = 0x0,
- MCDE_SYNCHRO_C0 = 0x1,
- MCDE_SYNCHRO_C1 = 0x2,
- MCDE_SYNCHRO_PINGPONG = 0x3
- }mcde_sync_ctrl;
-
- typedef enum
- {
- MCDE_SIG_INACTIVE_POL_LOW = 0x0,
- MCDE_SIG_INACTIVE_POL_HIGH = 0x1
- }mcde_sig_pol;
-
- typedef enum
- {
- MCDE_CD_LOW = 0x0, /* CD low for data and high for command */
- MCDE_CD_HIGH = 0x1 /* CD high for data and low for command */
- }mcde_cd_polarity;
-
- typedef enum
- {
- MCDE_RES_INACTIVE = 0x0,
- MCDE_RES_ACTIVE = 0x1
- }mcde_resen;
-
- typedef enum
- {
- MCDE_CSEN_DEACTIVATED = 0x0,
- MCDE_CSEN_ACTIVATED = 0x1
- }mcde_cs_enable_rw;
-
- typedef enum
- {
- MCDE_PCLK_TVCLK1 = 0x0,
- MCDE_PCLK_72 = 0x1,
- MCDE_PCLK_TVCLK2 = 0x2
- }mcde_clk_sel;
-
- typedef enum
- {
- MCDE_SELECT_OUTBAND = 0x0,
- MCDE_SELECT_INBAND = 0x1,
- }mcde_inband_select;
-
- typedef enum
- {
- MCDE_BUS_SIZE_8 = 0x0,
- MCDE_BUS_SIZE_16 = 0x1
- }mcde_bus_size;
-
- typedef enum
- {
- MCDE_SYNCHRO_CAPTURE_DISABLE = 0x0,
- MCDE_SYNCHRO_CAPTURE_ENABLE = 0x1
- }mcde_synchro_capture;
-
- typedef enum
- {
- MCDE_VERTICAL_SYNCHRO_CAPTURE1 = 0x0,
- MCDE_VERTICAL_SYNCHRO_CHANNELA = 0x1,
- }mcde_synchro_select;
-
- typedef enum
- {
- MCDE_FIFO_WMLVL_4 = 0x0,
- MCDE_FIFO_WMLVL_8 = 0x1
- }mcde_fifo_wmlvl_sel;
-
- typedef enum
- {
- MCDE_CHANNEL_C_DISABLE = 0x0,
- MCDE_CHANNEL_C_ENABLE = 0x1
- }mcde_chc_enable;
-
- typedef enum
- {
- MCDE_POWER_DISABLE = 0x0,
- MCDE_POWER_ENABLE = 0x1
- }mcde_powen_select;
-
- typedef enum
- {
- MCDE_FLOW_DISABLE = 0x0,
- MCDE_FLOW_ENABLE = 0x1
- }mcde_flow_select;
-
- typedef enum
- {
- MCDE_DUPLX_DISABLE = 0x0,
- MCDE_DUPLX_ENABLE = 0x1
- }mcde_duplx_ctrl;
-
- typedef enum
- {
- MCDE_DUPLX_MODE_NONE = 0x0,
- MCDE_DUPLX_MODE_16_TO_32 = 0x1,
- MCDE_DUPLX_MODE_24_TO_32_RS = 0x2,
- MCDE_DUPLX_MODE_24_TO_32_LS = 0x3
- }mcde_duplx_mode_select;
-
- typedef enum
- {
- MCDE_TRANSFER_8_1 = 0x0,
- MCDE_TRANSFER_8_2 = 0x1,
- MCDE_TRANSFER_8_3 = 0x2,
- MCDE_TRANSFER_16_1 = 0x4,
- MCDE_TRANSFER_16_2 = 0x5
- }mcde_bit_segmentation_select;
-
- typedef enum
- {
- MCDE_TRANSACTION_COMMAND = 0x0,
- MCDE_TRANSACTION_DATA = 0x1
- }mcde_transaction_type;
-
- typedef enum
- {
- MCDE_VSYNC_SELECT = 0x0,
- MCDE_HSYNC_SELECT = 0x1
- }mcde_vertical_sync_sel;
-
- typedef enum
- {
- MCDE_VSYNC_ACTIVE_HIGH = 0x0,
- MCDE_VSYNC_ACTIVE_LOW = 0x1,
- }mcde_vertical_sync_polarity;
-
- typedef enum
- {
- MCDE_STBCLK_DIV_1 = 0x0,
- MCDE_STBCLK_DIV_2 = 0x1,
- MCDE_STBCLK_DIV_4 = 0x2,
- MCDE_STBCLK_DIV_8 = 0x3,
- MCDE_STBCLK_DIV_16 = 0x4,
- MCDE_STBCLK_DIV_32 = 0x5,
- MCDE_STBCLK_DIV_64 = 0x6,
- MCDE_STBCLK_DIV_128 = 0x7
- }mcde_synchro_clk_div_factor;
-
- typedef enum
- {
- MCDE_PANEL_INTEL_SERIES = 0x0,
- MCDE_PANEL_MOTOROLA_SERIES = 0x1
- }mcde_panel_protocol;
-
- typedef enum
- {
- MCDE_PANEL_C0 = 0x0,
- MCDE_PANEL_C1 = 0x1
- }mcde_chc_panel;
-
- typedef enum
- {
- MCDE_TXFIFO_WRITE_DATA = 0,
- MCDE_TXFIFO_READ_DATA,
- MCDE_TXFIFO_WRITE_COMMAND
- } mcde_txfifo_request_type;
-
-
- struct mcde_chc_ctrl
- {
- mcde_sync_ctrl sync;
- mcde_resen resen;
- mcde_synchro_select synsel;
- mcde_clk_sel clksel;
- };
-
- struct mcde_chc_config
- {
- mcde_sig_pol res_pol;
- mcde_sig_pol rd_pol;
- mcde_sig_pol wr_pol;
- mcde_cd_polarity cd_pol;
- mcde_sig_pol cs_pol;
- mcde_cs_enable_rw csen;
- mcde_inband_select inband_mode;
- mcde_bus_size bus_size;
- mcde_synchro_capture syncen;
- mcde_fifo_wmlvl_sel fifo_watermark;
- mcde_chc_enable chcen;
- };
-
- struct mcde_pbc_config
- {
- mcde_duplx_ctrl duplex_ctrl;
- mcde_duplx_mode_select duplex_mode;
- mcde_bit_segmentation_select data_segment;
- mcde_bit_segmentation_select cmd_segment;
- };
-
- struct mcde_pbc_mux
- {
- u32 imux0;
- u32 imux1;
- u32 imux2;
- u32 imux3;
- u32 imux4;
- };
-
- struct mcde_pbc_bitctrl
- {
- u32 bit_ctrl0;
- u32 bit_ctrl1;
- };
-
- struct mcde_sync_conf
- {
- u8 debounce_length;
- mcde_vertical_sync_sel sync_sel;
- mcde_vertical_sync_polarity sync_pol;
- mcde_synchro_clk_div_factor clk_div;
- u16 vsp_max;
- u16 vsp_min;
- };
-
- struct mcde_sync_trigger
- {
- u16 trigger_delay_cx;
- u8 sync_delay_c1;
- u8 sync_delay_c2;
- };
-
- struct mcde_cd_timing_activate
- {
- u8 cs_cd_deactivate;
- u8 cs_cd_activate;
- };
-
- struct mcde_rw_timing
- {
- mcde_panel_protocol panel_type;
- u8 readwrite_activate;
- u8 readwrite_deactivate;
- };
-
- struct mcde_data_out_timing
- {
- u8 data_out_deactivate;
- u8 data_out_activate;
- };
-
- /*********************************************************************
- DSIX typedefs
- *********************************************************************/
- typedef enum
- {
- MCDE_DSI_CH_VID0 = 0x0,
- MCDE_DSI_CH_CMD0 = 0x1,
- MCDE_DSI_CH_VID1 = 0x2,
- MCDE_DSI_CH_CMD1 = 0x3,
- MCDE_DSI_CH_VID2 = 0x4,
- MCDE_DSI_CH_CMD2 = 0x5
- }mcde_dsi_channel;
-
- typedef enum
- {
- MCDE_PLL_OUT_OFF = 0x0,
- MCDE_PLL_OUT_1 = 0x1,
- MCDE_PLL_OUT_2 = 0x2,
- MCDE_PLL_OUT_4 = 0x3
- }mcde_pll_div_sel;
-
- typedef enum
- {
- MCDE_CLK27 = 0x0,
- MCDE_TV1CLK = 0x1,
- MCDE_HDMICLK = 0x2,
- MCDE_TV2CLK = 0x3,
- MCDE_MXTALI = 0x4
- }mcde_pll_ref_clk;
-
- typedef enum
- {
- MCDE_DSI_CLK27 = 0x0,
- MCDE_DSI_MCDECLK = 0x1
- }mcde_clk_divider;
-
- typedef struct
- {
- mcde_pll_div_sel pllout_divsel2;
- mcde_pll_div_sel pllout_divsel1;
- mcde_pll_div_sel pllout_divsel0;
- mcde_pll_ref_clk pll4in_sel;
- mcde_clk_divider txescdiv_sel;
- u32 txescdiv;
- }mcde_dsi_clk_config;
-
- typedef enum
- {
- MCDE_PACKING_RGB565 = 0x0,
- MCDE_PACKING_RGB666 = 0x1,
- MCDE_PACKING_RGB888_R = 0x2,
- MCDE_PACKING_RGB888_B = 0x3,
- MCDE_PACKING_HDTV = 0x4
- }mcde_dsi_packing;
-
- typedef enum
- {
- MCDE_DSI_OUT_GENERIC_CMD = 0x0,
- MCDE_DSI_OUT_VIDEO_DCS = 0x1
- }mcde_dsi_synchro;
-
- typedef enum
- {
- MCDE_DSI_NO_SWAP = 0x0,
- MCDE_DSI_SWAP = 0x1,
- }mcde_dsi_swap;
-
- typedef enum
- {
- MCDE_DSI_CMD_16 = 0x0,
- MCDE_DSI_CMD_8 = 0x1
- }mcde_dsi_cmd;
-
- typedef enum
- {
- MCDE_DSI_CMD_MODE = 0x0,
- MCDE_DSI_VID_MODE = 0x1,
- }mcde_vid_mode;
-
- typedef struct
- {
- mcde_dsi_packing packing;
- mcde_dsi_synchro synchro;
- mcde_dsi_swap byte_swap;
- mcde_dsi_swap bit_swap;
- mcde_dsi_cmd cmd8;
- mcde_vid_mode vid_mode;
- u8 blanking;
- u32 words_per_frame;
- u32 words_per_packet;
- }mcde_dsi_conf;
-
-
-
-/*******************************************************************************
-MCDE Error Enums
-******************************************************************************/
-typedef enum
-{
- MCDE_OK = 0x00, /* No error.*/
- MCDE_NO_PENDING_EVENT_ERROR = 0x01,
- MCDE_NO_MORE_FILTER_PENDING_EVENT = 0x02,
- MCDE_NO_MORE_PENDING_EVENT = 0x03,
- MCDE_REMAINING_FILTER_PENDING_EVENTS = 0x04,
- MCDE_REMAINING_PENDING_EVENTS = 0x05,
- MCDE_INTERNAL_EVENT = 0x06,
- MCDE_INTERNAL_ERROR = 0x07,
- MCDE_NOT_CONFIGURED = 0x08,
- MCDE_REQUEST_PENDING = 0x09,
- MCDE_REQUEST_NOT_APPLICABLE = 0x0A,
- MCDE_INVALID_PARAMETER = 0x0B,
- MCDE_UNSUPPORTED_FEATURE = 0x0C,
- MCDE_UNSUPPORTED_HW = 0x0D
-}mcde_error;
-
-/*******************************************************************************
-MCDE driver specific structures
-******************************************************************************/
-
-typedef enum {
- CHANNEL_A = 0x0,
- CHANNEL_B = 0x1,
- CHANNEL_C0 = 0x2,
- CHANNEL_C1 = 0x3,
-}channel ;
-
-typedef enum {
- RES_QVGA = 0x0,
- RES_VGA = 0x1,
- RES_WVGA = 0x2,
-}screenres;
-
- typedef struct
- {
- u16 alphared;
- u8 green;
- u8 blue;
- }mcde_palette;
-
-typedef struct
-{
- u8 red;
- u8 green;
- u8 blue;
-}t_mcde_gamma;
-
-struct mcde_channel_data{
- channel channelid;
- u8 nopan;
- u8 nowrap;
- const char *restype;
- mcde_bpp_ctrl inbpp;
- mcde_out_bpp outbpp;
- u8 bpp16_type;
- u8 bgrinput;
- gpio_alt_function gpio_alt_func;
-};
-// per channel structure
-struct mcde_ovlextsrc_conf{
- u16 ovl_id; //bitmap of overlays used
- u8 num_ovl;
-};
-
-struct clut_addrmap {
- u32 clutaddr;
- u32 clutdmaaddr;
-};
-
-
-#endif //__KERNEL__
-
-/* FUNCTION PROTOTYPE */
-void mcdefb_enable(struct fb_info *info);
-void mcdefb_disable(struct fb_info *info);
-int mcde_enable(struct fb_info *info);
-int mcde_disable(struct fb_info *info);
-int convertbpp(u8 bpp);
-int mcde_conf_channel_color_key(struct fb_info *info, struct mcde_channel_color_key chnannel_color_key);
-/*inline */unsigned long get_line_length(int x, int bpp);
-/* inline */unsigned long claim_mcde_lock(mcde_ch_id chid);
-/*inline*/ void release_mcde_lock(mcde_ch_id chid, unsigned long flags);
-int mcde_set_buffer(struct fb_info *info, u32 buffer_address, mcde_buffer_id buff_id);
-int mcde_conf_dithering_ctrl(struct mcde_dithering_ctrl_conf dithering_ctrl_conf, struct fb_info *info);
-bool mcde_get_hdmi_flag(void);
-void mcde_configure_hdmi_channel(void);
-#ifdef CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT
-/* HW V1 */
-void mcde_hdmi_display_init_command_mode(mcde_video_mode video_mode);
-#else
-/* HW ED */
-void mcde_hdmi_display_init_command_mode(void);
-#endif
-void mcde_hdmi_display_init_video_mode(void);
-void mcde_hdmi_test_directcommand_mode_highspeed(void);
-void mcde_send_hdmi_cmd_data(char* buf,int length, int dsicommand);
-void mcde_send_hdmi_cmd(char* buf,int length, int dsicommand);
-
-int mcde_extsrc_ovl_create(struct mcde_overlay_create *extsrc_ovl ,struct fb_info *info,u32 *pkey);
-int mcde_extsrc_ovl_remove(struct fb_info *info,u32 key);
-int mcde_alloc_source_buffer(struct mcde_sourcebuffer_alloc source_buff ,struct fb_info *info, u32 *pkey, u8 isUserRequest);
-int mcde_dealloc_source_buffer(struct fb_info *info, u32 srcbufferindex, u8 isUserRequest);
-int mcde_conf_extsource(struct mcde_ext_conf ext_src_config ,struct fb_info *info);
-int mcde_conf_overlay(struct mcde_conf_overlay ovrlayConfig ,struct fb_info *info);
-int mcde_conf_channel(struct mcde_ch_conf ch_config ,struct fb_info *info);
-int mcde_conf_lcd_timing(struct mcde_chnl_lcd_ctrl chnl_lcd_ctrl, struct fb_info *info);
-int mcde_conf_color_conversion_coeff(struct fb_info *info, mcde_colorconv_type color_conv_type);
-int mcde_conf_color_conversion(struct fb_info *info, struct mcde_conf_color_conv color_conv_ctrl);
-int mcde_conf_blend_ctrl(struct fb_info *info, struct mcde_blend_control blend_ctrl);
-int mcde_conf_rotation(struct fb_info *info, mcde_rot_dir rot_dir, mcde_roten rot_ctrl, u32 rot_addr0, u32 rot_addr1);
-int mcde_conf_chnlc(struct mcde_chc_config chnlc_config, struct mcde_chc_ctrl chnlc_control, struct fb_info *info);
-int mcde_conf_dsi_chnl(mcde_dsi_conf dsi_conf, mcde_dsi_clk_config clk_config, struct fb_info *info);
-int mcde_conf_scan_mode(mcde_scan_mode scan_mode, struct fb_info *info);
-
-mcde_error mcdesetextsrcconf(mcde_ch_id chid, mcde_ext_src src_id, struct mcde_ext_conf config);
-mcde_error mcdesetextsrcctrl(mcde_ch_id chid, mcde_ext_src src_id, struct mcde_ext_src_ctrl control);
-mcde_error mcdesetbufferaddr(mcde_ch_id chid, mcde_ext_src src_id, mcde_buffer_id buffer_id, u32 address);
-mcde_error mcdesetovrctrl(mcde_ch_id chid, mcde_overlay_id overlay, struct mcde_ovr_control ovr_cr);
-mcde_error mcdesetovrlayconf(mcde_ch_id chid, mcde_overlay_id overlay, struct mcde_ovr_config ovr_conf);
-mcde_error mcdesetovrconf2(mcde_ch_id chid, mcde_overlay_id overlay, struct mcde_ovr_conf2 ovr_conf2);
-mcde_error mcdesetovrljinc(mcde_ch_id chid, mcde_overlay_id overlay, u32 ovr_ljinc);
-mcde_error mcdesettopleftmargincrop(mcde_ch_id chid, mcde_overlay_id overlay, u32 ovr_topmargin, u16 ovr_leftmargin);
-mcde_error mcdesetovrcomp(mcde_ch_id chid, mcde_overlay_id overlay, struct mcde_ovr_comp ovr_comp);
-mcde_error mcdesetovrclip(mcde_ch_id chid, mcde_overlay_id overlay, struct mcde_ovr_clip ovr_clip);
-mcde_error mcdesetovrstate(mcde_ch_id chid, mcde_overlay_id overlay, mcde_overlay_ctrl state);
-mcde_error mcdesetovrpplandlpf(mcde_ch_id chid, mcde_overlay_id overlay, u16 ppl, u16 lpf);
-mcde_error mcdesetstate(mcde_ch_id chid, mcde_state state);
-mcde_error mcdesetchnlXconf(mcde_ch_id chid, u16 channelnum, struct mcde_chconfig config);
-mcde_error mcdesetswsync(mcde_ch_id chid, u16 channelnum, mcde_sw_trigger sw_trig);
-mcde_error mcdesetchnlbckgndcol(mcde_ch_id chid, u16 channelnum, struct mcde_ch_bckgrnd_col color);
-mcde_error mcdesetchnlsyncprio(mcde_ch_id chid, u16 channelnum, u32 priority);
-mcde_error mcdesetchnlXpowermode(mcde_ch_id chid, mcde_powen_select power);
-mcde_error mcdesetflowXctrl(mcde_ch_id chid, struct mcde_chx_control0 control);
-mcde_error mcdesetpanelctrl(mcde_ch_id chid, struct mcde_chx_control1 control);
-mcde_error mcdesetcolorkey(mcde_ch_id chid, struct mcde_chx_color_key key, mcde_colorkey_type type);
-mcde_error mcdesetcolorconvmatrix(mcde_ch_id chid, struct mcde_chx_rgb_conv_coef coef);
-mcde_error mcdesetflickerfiltercoef(mcde_ch_id chid, struct mcde_chx_flickfilter_coef coef);
-mcde_error mcdesetLCDtiming0ctrl(mcde_ch_id chid, struct mcde_chx_lcd_timing0 control);
-mcde_error mcdesetLCDtiming1ctrl(mcde_ch_id channel, struct mcde_chx_lcd_timing1 control);
-mcde_error mcdesetrotaddr(mcde_ch_id chid, u32 address, mcde_rotate_num rotnum);
-mcde_error mcdesetpalette(mcde_ch_id chid, mcde_palette palette);
-mcde_error mcdesetditherctrl(mcde_ch_id chid, struct mcde_chx_dither_ctrl control);
-mcde_error mcdesetditheroffset(mcde_ch_id chid, struct mcde_chx_dithering_offset offset);
-mcde_error mcdesetgammacoeff(mcde_ch_id chid, struct mcde_chx_gamma gamma);
-mcde_error mcdesetoutmuxconf(mcde_ch_id chid, mcde_out_bpp outbpp);
-mcde_error mcdesetchnlXpowermode(mcde_ch_id chid, mcde_powen_select power);
-mcde_error mcdesetchnlXflowmode(mcde_ch_id chid, mcde_flow_select flow);
-mcde_error mcdesetcflowXcolorkeyctrl(mcde_ch_id chid, mcde_key_ctrl key_ctrl);
-mcde_error mcdesetblendctrl(mcde_ch_id chid, struct mcde_blend_control blend_ctrl);
-mcde_error mcdesetrotation(mcde_ch_id chid, mcde_rot_dir rot_dir, mcde_roten rot_ctrl);
-mcde_error mcdesetcolorconvctrl(mcde_ch_id chid, mcde_overlay_id overlay, mcde_col_conv_ctrl col_ctrl);
-mcde_error mcderesetextsrcovrlay(mcde_ch_id chid);
-mcde_error mcdesetchnlsyncsrc(mcde_ch_id chid, u16 channelnum, struct mcde_chsyncmod sync_mod);
-mcde_error mcdesetchnlsyncevent(mcde_ch_id chid, struct mcde_ch_conf ch_config);
-mcde_error mcdesetchnlLCDctrlreg(mcde_ch_id chid, struct mcde_chnl_lcd_ctrl_reg lcd_ctrl_reg);
-mcde_error mcdesetchnlLCDhorizontaltiming(mcde_ch_id chid, struct mcde_chnl_lcd_horizontal_timing lcd_horizontal_timing);
-mcde_error mcdesetchnlLCDverticaltiming(mcde_ch_id chid, struct mcde_chnl_lcd_vertical_timing lcd_vertical_timing);
-mcde_error mcdesetditheringctrl(mcde_ch_id chid, mcde_dithering_ctrl dithering_control);
-mcde_error mcdesetscanmode(mcde_ch_id chid, mcde_scan_mode scan_mode);
-
-#ifdef CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT
-/* HW V1 */
-mcde_state mcdegetchannelstate(mcde_ch_id chid);
-mcde_error mcdesetchnlCmode(mcde_ch_id chid, mcde_chc_panel panel_id, mcde_chc_enable state);
-#endif /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */
-
-#endif
-
diff --git a/arch/arm/mach-ux500/include/mach/mcde_a0.h b/arch/arm/mach-ux500/include/mach/mcde_a0.h
deleted file mode 100755
index 8c06a628479..00000000000
--- a/arch/arm/mach-ux500/include/mach/mcde_a0.h
+++ /dev/null
@@ -1,896 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * License terms:
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#define WRITE_FIELD(reg, field, value) \
- (reg = (reg & (~((field##_MASK) << (field##_SHIFT)))) | ((value & (field##_MASK)) << (field##_SHIFT)) )
-
-
-#define MCDE_CR (MCDE_BASE + 0x0)
-#define MCDE_CR_MCDEEN 0x80000000
-#define MCDE_CR_AUTOCLKG_EN 0x40000000
-#define MCDE_CR_FABMUX 0x00020000
-#define MCDE_CR_F01MUX 0x00010000
-#define MCDE_CR_IFIFOCTRLEN 0x00008000
-#define MCDE_CR_DPIA_EN 0x00000200
-#define MCDE_CR_DPIB_EN 0x00000100
-#define MCDE_CR_DPIC0_EN 0x00000080
-#define MCDE_CR_DPIC1_EN 0x00000040
-#define MCDE_CR_DSIVID0_EN 0x00000020
-#define MCDE_CR_DSIVID1_EN 0x00000010
-#define MCDE_CR_DSIVID2_EN 0x00000008
-#define MCDE_CR_DSICMD0_EN 0x00000004
-#define MCDE_CR_DSICMD1_EN 0x00000002
-#define MCDE_CR_DSICMD2_EN 0x00000001
-
-
-#define MCDE_CONF0 (MCDE_BASE + 0x4)
-#define MCDE_CONF0_OUTMUX4_SHIFT 28
-#define MCDE_CONF0_OUTMUX4_MASK 0x7
-#define MCDE_CONF0_OUTMUX3_SHIFT 25
-#define MCDE_CONF0_OUTMUX3_MASK 0x7
-#define MCDE_CONF0_OUTMUX2_SHIFT 22
-#define MCDE_CONF0_OUTMUX2_MASK 0x7
-#define MCDE_CONF0_OUTMUX1_SHIFT 19
-#define MCDE_CONF0_OUTMUX1_MASK 0x7
-#define MCDE_CONF0_OUTMUX0_SHIFT 16
-#define MCDE_CONF0_OUTMUX0_MASK 0x7
-#define MCDE_CONF0_IFIFOCTRLWTRMRKLVL_SHIFT 12
-#define MCDE_CONF0_IFIFOCTRLWTRMRKLVL_MASK 0x7
-#define MCDE_CONF0_FSYNCTRLB 0x00000800
-#define MCDE_CONF0_FSYNCTRLA 0x00000400
-#define MCDE_CONF0_SWAP_B_C1 0x00000200
-#define MCDE_CONF0_SWAP_A_C0 0x00000100
-#define MCDE_CONF0_SYNCMUX7 0x00000080
-#define MCDE_CONF0_SYNCMUX6 0x00000040
-#define MCDE_CONF0_SYNCMUX5 0x00000020
-#define MCDE_CONF0_SYNCMUX4 0x00000010
-#define MCDE_CONF0_SYNCMUX3 0x00000008
-#define MCDE_CONF0_SYNCMUX2 0x00000004
-#define MCDE_CONF0_SYNCMUX1 0x00000002
-#define MCDE_CONF0_SYNCMUX0 0x00000001
-
-
-#define MCDE_SSP (MCDE_BASE + 0x8)
-#define MCDE_SSP_SSPEN 0x00010000
-#define MCDE_SSP_SSPCMD 0x00000100
-#define MCDE_SSP_SSPDATA_SHIFT 0
-#define MCDE_SSP_SSPDATA_MASK 0xFF
-
-
-#define MCDE_AIS (MCDE_BASE + 0x100)
-#define MCDE_AIS_DSI2AI 0x00000040
-#define MCDE_AIS_DSI1AI 0x00000020
-#define MCDE_AIS_DSI0AI 0x00000010
-#define MCDE_AIS_MCDEERRI 0x00000008
-#define MCDE_AIS_MCDECHNLI 0x00000004
-#define MCDE_AIS_MCDEOVLI 0x00000002
-#define MCDE_AIS_MCDEPPI 0x00000001
-
-
-#define MCDE_IMSCPP (MCDE_BASE + 0x104)
-#define MCDE_IMSCPP_ROTFDIM_SHIFT 6
-#define MCDE_IMSCPP_ROTFDIM_MASK 0x3
-#define MCDE_IMSCPP_VCMPC1IM 0x00000020
-#define MCDE_IMSCPP_VCMPC0IM 0x00000010
-#define MCDE_IMSCPP_VSCC1IM 0x00000008
-#define MCDE_IMSCPP_VSCC0IM 0x00000004
-#define MCDE_IMSCPP_VCMPBIM 0x00000002
-#define MCDE_IMSCPP_VCMPAIM 0x00000001
-
-
-#define MCDE_IMSCOVL (MCDE_BASE + 0x108)
-#define MCDE_IMSCOVL_OVLFDIM_SHIFT 16
-#define MCDE_IMSCOVL_OVLFDIM_MASK 0xFFFF
-#define MCDE_IMSCOVL_OVLRDIM_SHIFT 0
-#define MCDE_IMSCOVL_OVLRDIM_MASK 0xFFFF
-
-
-#define MCDE_IMSCCHNL (MCDE_BASE + 0x10C)
-#define MCDE_IMSCCHNL_CHNLAIM_SHIFT 16
-#define MCDE_IMSCCHNL_CHNLAIM_MASK 0xFFFF
-#define MCDE_IMSCCHNL_CHNLRDIM_SHIFT 0
-#define MCDE_IMSCCHNL_CHNLRDIM_MASK 0xFFFF
-
-
-#define MCDE_IMSCERR (MCDE_BASE + 0x110)
-#define MCDE_IMSCERR_OVLFERRIM_SHIFT 16
-#define MCDE_IMSCERR_OVLFERRIM_MASK 0xFFFF
-#define MCDE_IMSCERR_FUC1IM 0x00000100
-#define MCDE_IMSCERR_FUC0IM 0x00000080
-#define MCDE_IMSCERR_ROTBFEIM_SHIFT 5
-#define MCDE_IMSCERR_ROTBFEIM_MASK 0x3
-#define MCDE_IMSCERR_ROTAFEIM_SHIFT 3
-#define MCDE_IMSCERR_ROTAFEIM_MASK 0x3
-#define MCDE_IMSCERR_SCHBLCKDIM 0x00000004
-#define MCDE_IMSCERR_FUBIM 0x00000002
-#define MCDE_IMSCERR_FUAIM 0x00000001
-
-
-#define MCDE_RISPP (MCDE_BASE + 0x114)
-#define MCDE_RISPP_ROTFDRIS_SHIFT 6
-#define MCDE_RISPP_ROTFDRIS_MASK 0x3
-#define MCDE_RISPP_VCMPC1RIS 0x00000020
-#define MCDE_RISPP_VCMPC0RIS 0x00000010
-#define MCDE_RISPP_VSCC1RIS 0x00000008
-#define MCDE_RISPP_VSCC0RIS 0x00000004
-#define MCDE_RISPP_VCMPBRIS 0x00000002
-#define MCDE_RISPP_VCMPARIS 0x00000001
-
-
-#define MCDE_RISOVL (MCDE_BASE + 0x118)
-#define MCDE_RISOVL_OVLFDRIS_SHIFT 16
-#define MCDE_RISOVL_OVLFDRIS_MASK 0xFFFF
-#define MCDE_RISOVL_OVLRDRIS_SHIFT 0
-#define MCDE_RISOVL_OVLRDRIS_MASK 0xFFFF
-
-
-#define MCDE_RISCHNL (MCDE_BASE + 0x11C)
-#define MCDE_RISCHNL_CHNLARIS_SHIFT 16
-#define MCDE_RISCHNL_CHNLARIS_MASK 0xFFFF
-#define MCDE_RISCHNL_CHNLRDRIS_SHIFT 0
-#define MCDE_RISCHNL_CHNLRDRIS_MASK 0xFFFF
-
-
-#define MCDE_RISERR (MCDE_BASE + 0x120)
-#define MCDE_RISERR_OVLFERRIS_SHIFT 16
-#define MCDE_RISERR_OVLFERRIS_MASK 0xFFFF
-#define MCDE_RISERR_FUC1RIS 0x00000100
-#define MCDE_RISERR_FUC0RIS 0x00000080
-#define MCDE_RISERR_ROTBFERIS_SHIFT 5
-#define MCDE_RISERR_ROTBFERIS_MASK 0x3
-#define MCDE_RISERR_ROTAFERIS_SHIFT 3
-#define MCDE_RISERR_ROTAFERIS_MASK 0x3
-#define MCDE_RISERR_SCHBLCKDRIS 0x00000004
-#define MCDE_RISERR_FUBRIS 0x00000002
-#define MCDE_RISERR_FUARIS 0x00000001
-
-
-#define MCDE_MISPP (MCDE_BASE + 0x124)
-#define MCDE_MISPP_ROTFDMIS_SHIFT 6
-#define MCDE_MISPP_ROTFDMIS_MASK 0x3
-#define MCDE_MISPP_VCMPC1MIS 0x00000020
-#define MCDE_MISPP_VCMPC0MIS 0x00000010
-#define MCDE_MISPP_VSCC1MIS 0x00000008
-#define MCDE_MISPP_VSCC0MIS 0x00000004
-#define MCDE_MISPP_VCMPBMIS 0x00000002
-#define MCDE_MISPP_VCMPAMIS 0x00000001
-
-
-#define MCDE_MISOVL (MCDE_BASE + 0x128)
-#define MCDE_MISOVL_OVLFDMIS_SHIFT 16
-#define MCDE_MISOVL_OVLFDMIS_MASK 0xFFFF
-#define MCDE_MISOVL_OVLRDMIS_SHIFT 0
-#define MCDE_MISOVL_OVLRDMIS_MASK 0xFFFF
-
-
-#define MCDE_MISCHNL (MCDE_BASE + 0x12C)
-#define MCDE_MISCHNL_CHNLAMIS_SHIFT 16
-#define MCDE_MISCHNL_CHNLAMIS_MASK 0xFFFF
-#define MCDE_MISCHNL_CHNLRDMIS_SHIFT 0
-#define MCDE_MISCHNL_CHNLRDMIS_MASK 0xFFFF
-#define MCDE_MISCHNL_CHNL_A 0x00000001
-#define MCDE_MISCHNL_CHNL_B 0x00000002
-#define MCDE_MISCHNL_CHNL_C0 0x00000004
-#define MCDE_MISCHNL_CHNL_C1 0x00000008
-
-
-#define MCDE_MISERR (MCDE_BASE + 0x130)
-#define MCDE_MISERR_OVLFERMIS_SHIFT 16
-#define MCDE_MISERR_OVLFERMIS_MASK 0xFFFF
-#define MCDE_MISERR_FUC1MIS 0x00000100
-#define MCDE_MISERR_FUC0MIS 0x00000080
-#define MCDE_MISERR_ROTBFEMIS_SHIFT 5
-#define MCDE_MISERR_ROTBFEMIS_MASK 0x3
-#define MCDE_MISERR_ROTAFEMIS_SHIFT 3
-#define MCDE_MISERR_ROTAFEMIS_MASK 0x3
-#define MCDE_MISERR_SCHBLCKDMIS 0x00000004
-#define MCDE_MISERR_FUBMIS 0x00000002
-#define MCDE_MISERR_FUAMIS 0x00000001
-
-
-#define MCDE_SISPP (MCDE_BASE + 0x134)
-#define MCDE_SISOVL (MCDE_BASE + 0x138)
-#define MCDE_SISCHNL (MCDE_BASE + 0x13C)
-#define MCDE_SISERR (MCDE_BASE + 0x140)
-
-
-#define MCDE_PID (MCDE_BASE + 0x1FC)
-#define MCDE_PID_MAJOR_SHIFT 24
-#define MCDE_PID_MAJOR_MASK 0xFF
-#define MCDE_PID_MINOR_SHIFT 16
-#define MCDE_PID_MINOR_MASK 0xFF
-#define MCDE_PID_DEV_SHIFT 8
-#define MCDE_PID_DEV_MASK 0xFF
-#define MCDE_PID_METALFIX_SHIFT 0
-#define MCDE_PID_METALFIX_MASK 0xFF
-
-
-#define MCDE_EXTSRCA0 (MCDE_BASE + 0x200)
-#define MCDE_EXTSRCA1 (MCDE_BASE + 0x204)
-#define MCDE_EXTSRCA2 (MCDE_BASE + 0x2C8)
-
-
-#define MCDE_EXTSRCCONF (MCDE_BASE + 0x20C)
-#define MCDE_EXTSRCCONF_BEPO 0x00004000
-#define MCDE_EXTSRCCONF_BEBO 0x00002000
-#define MCDE_EXTSRCCONF_BGR 0x00001000
-#define MCDE_EXTSRCCONF_BPP_SHIFT 8
-#define MCDE_EXTSRCCONF_BPP_MASK 0xF
-#define MCDE_EXTSRCCONF_PRI_OVLID_SHIFT 4
-#define MCDE_EXTSRCCONF_PRI_OVLID_MASK 0xF
-#define MCDE_EXTSRCCONF_BUF_NB_SHIFT 2
-#define MCDE_EXTSRCCONF_BUF_NB_MASK 0x3
-#define MCDE_EXTSRCCONF_BUF_ID_SHIFT 0
-#define MCDE_EXTSRCCONF_BUF_ID_MASK 0x3
-
-
-#define MCDE_EXTSRCCR (MCDE_BASE + 0x210)
-#define MCDE_EXTSRCCR_FORCE_FS_DIV 0x00000008
-#define MCDE_EXTSRCCR_FS_DIV_DISABLE 0x00000004
-#define MCDE_EXTSRCCR_MULTIOVL_CTRL 0x00000002
-#define MCDE_EXTSRCCR_SEL_MOD_SHIFT 0
-#define MCDE_EXTSRCCR_SEL_MOD_MASK 0x3
-
-
-#define MCDE_OVLCR (MCDE_BASE + 0x400)
-#define MCDE_OVLCR_ROTBURSTSIZE_SHIFT 28
-#define MCDE_OVLCR_ROTBURSTSIZE_MASK 0xF
-#define MCDE_OVLCR_MAXOUTSTANDING_SHIFT 24
-#define MCDE_OVLCR_MAXOUTSTANDING_MASK 0xF
-#define MCDE_OVLCR_BURSTSIZE_SHIFT 20
-#define MCDE_OVLCR_BURSTSIZE_MASK 0xF
-#define MCDE_OVLCR_STBPRIO_SHIFT 16
-#define MCDE_OVLCR_STBPRIO_MASK 0xF
-#define MCDE_OVLCR_FETCH_ROPC_SHIFT 8
-#define MCDE_OVLCR_GETCH_ROPC_MASK 0xFF
-#define MCDE_OVLCR_OVLB 0x00000080
-#define MCDE_OVLCR_OVLR 0x00000040
-#define MCDE_OVLCR_OVLF 0x00000020
-#define MCDE_OVLCR_ALPHAPMEN 0x00000010
-#define MCDE_OVLCR_CKEYEN 0x00000008
-#define MCDE_OVLCR_COLCCTRL_SHIFT 1
-#define MCDE_OVLCR_COLCCTRL_MASK 0x3
-#define MCDE_OVLCR_OVLEN 0x00000001
-
-
-#define MCDE_OVLCONF (MCDE_BASE + 0x404)
-#define MCDE_OVLCONF_LPF_SHIFT 16
-#define MCDE_OVLCONF_LPF_MASK 0x7FF
-#define MCDE_OVLCONF_EXTSRC_ID_SHIFT 11
-#define MCDE_OVLCONF_EXTSRC_ID_MASK 0xF
-#define MCDE_OVLCONF_PPL_SHIFT 0
-#define MCDE_OVLCONF_PPL_MASK 0x7FF
-
-
-#define MCDE_OVLCONF2 (MCDE_BASE + 0x408)
-#define MCDE_OVLCONF2_PIXELFETCHWATERMARKLEVEL_SHIFT 16
-#define MCDE_OVLCONF2_PIXELFETCHWATERMARKLEVEL_MASK 0x1FFF
-#define MCDE_OVLCONF2_PIXOFF_SHIFT 10
-#define MCDE_OVLCONF2_PIXOFF_MASK 0x3F
-#define MCDE_OVLCONF2_OPQ 0x00000200
-#define MCDE_OVLCONF2_ALPHAVALUE_SHIFT 1
-#define MCDE_OVLCONF2_ALPHAVALUE_MASK 0xFF
-#define MCDE_OVLCONF2_BP 0x00000001
-
-
-#define MCDE_OVLLJINC (MCDE_BASE + 0x40C)
-
-
-#define MCDE_OVLCROP (MCDE_BASE + 0x410)
-#define MCDE_OVLCROP_LMRGN_SHIFT 22
-#define MCDE_OVLCROP_LMRGN_MASK 0x3FF
-#define MCDE_OVLCROP_TMRGN_SHIFT 0
-#define MCDE_OVLCROP_TMRGN_MASK 0x3FFFFF
-
-
-#define MCDE_OVLCOMP (MCDE_BASE + 0x414)
-#define MCDE_OVLCOMP_Z_SHIFT 27
-#define MCDE_OVLCOMP_Z_MASK 0xF
-#define MCDE_OVLCOMP_YPOS_SHIFT 16
-#define MCDE_OVLCOMP_YPOS_MASK 0x7FF
-#define MCDE_OVLCOMP_CH_ID_SHIFT 11
-#define MCDE_OVLCOMP_CH_ID_MASK 0xF
-#define MCDE_OVLCOMP_XPOS_SHIFT 0
-#define MCDE_OVLCOMP_XPOS_MASK 0x7FF
-
-
-#define MCDE_CHNLCONF (MCDE_BASE + 0x600)
-#define MCDE_CHNLCONF_LPF_SHIFT 16
-#define MCDE_CHNLCONF_LPF_MASK 0x7FF
-#define MCDE_CHNLCONF_PPL_SHIFT 0
-#define MCDE_CHNLCONF_PPL_MASK 0x7FF
-
-
-#define MCDE_CHNLSTAT (MCDE_BASE + 0x604)
-#define MCDE_CHNLSTAT_CHNLBLBCKGND_EN 0x00010000
-#define MCDE_CHNLSTAT_CHNLA 0x00000002
-#define MCDE_CHNLSTAT_CHNLRD 0x00000001
-
-
-#define MCDE_CHNLSYNCHMOD (MCDE_BASE + 0x608)
-#define MCDE_CHNLSYNCHMOD_OUT_SYNCH_SRC_SHIFT 2
-#define MCDE_CHNLSYNCHMOD_OUT_SYNCH_SRC_MASK 0x7
-#define MCDE_CHNLSYNCHMOD_SRC_SYNCH_SHIFT 0
-#define MCDE_CHNLSYNCHMOD_SRC_SYNCH_MASK 0x3
-#define MCDE_CHNLSYNCHMOD_OUT_SYNCH_SRC_FROM_SELECTED_FORMATER 0x0
-#define MCDE_CHNLSYNCHMOD_OUT_SYNCH_SRC_FROM_MCDEVSYNC0 0x1
-#define MCDE_CHNLSYNCHMOD_OUT_SYNCH_SRC_FROM_MCDEVSYNC1 0x2
-#define MCDE_CHNLSYNCHMOD_SRC_SYNCH_OUTPUT 0x0
-#define MCDE_CHNLSYNCHMOD_SRC_SYNCH_AUTO 0x1
-#define MCDE_CHNLSYNCHMOD_SRC_SYNCH_SW 0x2
-#define MCDE_CHNLSYNCHMOD_SRC_SYNCH_EXTERNAL 0x3
-
-
-#define MCDE_CHNLSYNCHSW (MCDE_BASE + 0x60C)
-#define MCDE_CHNLSYNCHSW_SW_TRIG 0x00000001
-
-
-#define MCDE_CHNLBCKGNDCOL (MCDE_BASE + 0x610)
-#define MCDE_CHNLBCKGNDCOL_R_SHIFT 16
-#define MCDE_CHNLBCKGNDCOL_R_MASK 0xFF
-#define MCDE_CHNLBCKGNDCOL_G_SHIFT 8
-#define MCDE_CHNLBCKGNDCOL_G_MASK 0xFF
-#define MCDE_CHNLBCKGNDCOL_B_SHIFT 0
-#define MCDE_CHNLBCKGNDCOL_B_MASK 0xFF
-
-
-#define MCDE_CHNLPRIO (MCDE_BASE + 0x614)
-#define MCDE_CHNLPRIO_CHNLPRIO_SHIFT 0
-#define MCDE_CHNLPRIO_CHNLPRIO_MASK 0xF
-
-
-#define MCDE_CR0 (MCDE_BASE + 0x800)
-#define MCDE_CR0_ROTBURSTSIZE_SHIFT 25
-#define MCDE_CR0_ROTBURSTSIZE_MASK 0x7F
-#define MCDE_CR0_ROTEN 0x01000000
-#define MCDE_CR0_ALPHABLEND_SHIFT 16
-#define MCDE_CR0_ALPHABLEND_MASK 0xFF
-#define MCDE_CR0_OLEDEN 0x00008000
-#define MCDE_CR0_PALMODE 0x00004000
-#define MCDE_CR0_FLICKFORMAT 0x00002000
-#define MCDE_CR0_FLICKMODE_SHIFT 11
-#define MCDE_CR0_FLICKMODE_MASK 0x3
-#define MCDE_CR0_BLENDCTRL 0x00000400
-#define MCDE_CR0_KEYCTRL_SHIFT 7
-#define MCDE_CR0_KEYCTRL_MASK 0x7
-#define MCDE_CR0_GAMEN 0x00000040
-#define MCDE_CR0_DITHEN 0x00000020
-#define MCDE_CR0_PALEN 0x00000010
-#define MCDE_CR0_AFLICKEN 0x00000008
-#define MCDE_CR0_BLENDEN 0x00000004
-#define MCDE_CR0_POWEREN 0x00000002
-#define MCDE_CR0_FLOEN 0x00000001
-
-#define MCDE_CR1 (MCDE_BASE + 0x804)
-#define MCDE_CR1_TEFFECTEN 0x80000000
-#define MCDE_CR1_CLKTYPE 0x40000000
-#define MCDE_CR1_BCD 0x20000000
-#define MCDE_CR1_OUTBPP_SHIFT 25
-#define MCDE_CR1_OUTBPP_MASK 0xF
-#define MCDE_CR1_CDWIN_SHIFT 13
-#define MCDE_CR1_CDWIN_MASK 0xF
-#define MCDE_CR1_CLKSEL_SHIFT 10
-#define MCDE_CR1_CLKSEL_MASK 0x7
-#define MCDE_CR1_PCD_SHIFT 0
-#define MCDE_CR1_PCD_MASK 0x3FF
-
-
-#define MCDE_COLKEY (MCDE_BASE + 0x808)
-#define MCDE_COLKEY_KEYA_SHIFT 24
-#define MCDE_COLKEY_KEYA_MASK 0xFF
-#define MCDE_COLKEY_KEYR_SHIFT 16
-#define MCDE_COLKEY_KEYR_MASK 0xFF
-#define MCDE_COLKEY_KEYG_SHIFT 8
-#define MCDE_COLKEY_KEYG_MASK 0xFF
-#define MCDE_COLKEY_KEYB_SHIFT 0
-#define MCDE_COLKEY_KEYB_MASK 0xFF
-
-
-#define MCDE_FCOLKEY (MCDE_BASE + 0x80C)
-#define MCDE_FCOLKEY_FKEYA_SHIFT 24
-#define MCDE_FCOLKEY_FKEYA_MASK 0xFF
-#define MCDE_FCOLKEY_FKEYR_SHIFT 16
-#define MCDE_FCOLKEY_FKEYR_MASK 0xFF
-#define MCDE_FCOLKEY_FKEYG_SHIFT 8
-#define MCDE_FCOLKEY_FKEYG_MASK 0xFF
-#define MCDE_FCOLKEY_FKEYB_SHIFT 0
-#define MCDE_FCOLKEY_FKEYB_MASK 0xFF
-
-
-#define MCDE_RGBCONV1 (MCDE_BASE + 0x810)
-#define MCDE_RGBCONV1_YR_RED_SHIFT 16
-#define MCDE_RGBCONV1_YR_RED_MASK 0x7FF
-#define MCDE_RGBCONV1_YR_GREEN_SHIFT 0
-#define MCDE_RGBCONV1_YR_GREEN_MASK 0x7FF
-
-
-#define MCDE_RGBCONV2 (MCDE_BASE + 0x814)
-#define MCDE_RGBCONV2_YR_BLUE_SHIFT 16
-#define MCDE_RGBCONV2_YR_BLUE_MASK 0x7FF
-#define MCDE_RGBCONV2_CR_RED_SHIFT 0
-#define MCDE_RGBCONV2_CR_RED_MASK 0x7FF
-
-
-#define MCDE_RGBCONV3 (MCDE_BASE + 0x818)
-#define MCDE_RGBCONV3_CR_GREEN_SHIFT 16
-#define MCDE_RGBCONV3_CR_GREEN_MASK 0x7FF
-#define MCDE_RGBCONV3_CR_BLUE_SHIFT 0
-#define MCDE_RGBCONV3_CR_BLUE_MASK 0x7FF
-
-
-#define MCDE_RGBCONV4 (MCDE_BASE + 0x81C)
-#define MCDE_RGBCONV4_CB_RED_SHIFT 16
-#define MCDE_RGBCONV4_CB_RED_MASK 0x7FF
-#define MCDE_RGBCONV4_CB_GREEN_SHIFT 0
-#define MCDE_RGBCONV4_CB_GREEN_MASK 0x7FF
-
-
-#define MCDE_RGBCONV5 (MCDE_BASE + 0x820)
-#define MCDE_RGBCONV5_CB_BLUE_SHIFT 16
-#define MCDE_RGBCONV5_CB_BLUE_MASK 0x7FF
-#define MCDE_RGBCONV5_OFF_RED_SHIFT 0
-#define MCDE_RGBCONV5_OFF_RED_MASK 0x7FF
-
-
-#define MCDE_RGBCONV6 (MCDE_BASE + 0x824)
-#define MCDE_RGBCONV6_OFF_GREEN_SHIFT 16
-#define MCDE_RGBCONV6_OFF_GREEN_MASK 0x7FF
-#define MCDE_RGBCONV6_OFF_BLUE_SHIFT 0
-#define MCDE_RGBCONV6_OFF_BLUE_MASK 0x7FF
-
-
-#define MCDE_FFCOEF0 (MCDE_BASE + 0x828)
-#define MCDE_FFCOEF0_TO_SHIFT 24
-#define MCDE_FFCOEF0_TO_MASK 0x0xF
-#define MCDE_FFCOEF0_COEFF0_N3_SHIFT 16
-#define MCDE_FFCOEF0_COEFF0_N3_MASK 0xFF
-#define MCDE_FFCOEF0_COEFF0_N2_SHIFT 8
-#define MCDE_FFCOEF0_COEFF0_N2_MASK 0xFF
-#define MCDE_FFCOEF0_COEFF0_N1_SHIFT 0
-#define MCDE_FFCOEF0_COEFF0_N1_MASK 0xFF
-
-
-#define MCDE_FFCOEF1 (MCDE_BASE + 0x82C)
-#define MCDE_FFCOEF1_T1_SHIFT 24
-#define MCDE_FFCOEF1_T1_MASK 0x0xF
-#define MCDE_FFCOEF1_COEFF1_N3_SHIFT 16
-#define MCDE_FFCOEF1_COEFF1_N3_MASK 0xFF
-#define MCDE_FFCOEF1_COEFF1_N2_SHIFT 8
-#define MCDE_FFCOEF1_COEFF1_N2_MASK 0xFF
-#define MCDE_FFCOEF1_COEFF1_N1_SHIFT 0
-#define MCDE_FFCOEF1_COEFF1_N1_MASK 0xFF
-
-
-#define MCDE_FFCOEF2 (MCDE_BASE + 0x830)
-#define MCDE_FFCOEF2_T2_SHIFT 24
-#define MCDE_FFCOEF2_T2_MASK 0x0xF
-#define MCDE_FFCOEF2_COEFF2_N3_SHIFT 16
-#define MCDE_FFCOEF2_COEFF2_N3_MASK 0xFF
-#define MCDE_FFCOEF2_COEFF2_N2_SHIFT 8
-#define MCDE_FFCOEF2_COEFF2_N2_MASK 0xFF
-#define MCDE_FFCOEF2_COEFF2_N1_SHIFT 0
-#define MCDE_FFCOEF2_COEFF2_N1_MASK 0xFF
-
-
-#define MCDE_TVCR (MCDE_BASE + 0x838)
-#define MCDE_TVCR_AVRGEN 0x00000100
-#define MCDE_TVCR_SDTVMODE_SHIFT 6
-#define MCDE_TVCR_SDTVMODE_MASK 0x3
-#define MCDE_TVCR_SDTVMODE_YC 0x0
-#define MCDE_TVCR_SDTVMODE_CY 0x1
-#define MCDE_TVCR_TVMODE_SHIFT 3
-#define MCDE_TVCR_TVMODE_MASK 0x7
-#define MCDE_TVCR_TVMODE_SDTV 0x0
-#define MCDE_TVCR_TVMODE_HDTV_480P 0x1
-#define MCDE_TVCR_TVMODE_HDTV_720P 0x2
-#define MCDE_TVCR_TVMODE_SDTV_DDR_LS_1ST 0x3
-#define MCDE_TVCR_TVMODE_SDTV_DDR_MS_1ST 0x4
-#define MCDE_TVCR_IFIELD_SHIFT 2
-#define MCDE_TVCR_IFIELD_MASK 0x1
-#define MCDE_TVCR_IFIELD_ACT_HGH 0x0
-#define MCDE_TVCR_IFIELD_ACT_LOW 0x1
-#define MCDE_TVCR_INTEREN 0x00000002
-#define MCDE_TVCR_SEL_MOD_SHIFT 0
-#define MCDE_TVCR_SEL_MOD_MASK 0x1
-#define MCDE_TVCR_SEL_MOD_LCD 0x0
-#define MCDE_TVCR_SEL_MOD_TV 0x1
-
-#define MCDE_TVBL1 (MCDE_BASE + 0x83C)
-#define MCDE_TVBL1_BSL1_SHIFT 16
-#define MCDE_TVBL1_BSL1_MASK 0x7FF
-#define MCDE_TVBL1_BEL1_SHIFT 0
-#define MCDE_TVBL1_BEL1_MASK 0x7FF
-
-
-#define MCDE_TVISL (MCDE_BASE + 0x840)
-#define MCDE_TVISL_FSL2_SHIFT 16
-#define MCDE_TVISL_FSL2_MASK 0x7FF
-#define MCDE_TVISL_FSL1_SHIFT 0
-#define MCDE_TVISL_FSL1_MASK 0x7FF
-
-
-#define MCDE_TVDVO (MCDE_BASE + 0x844)
-#define MCDE_TVDVO_DVO2_SHIFT 16
-#define MCDE_TVDVO_DVO2_MASK 0x7FF
-#define MCDE_TVDVO_DVO1_SHIFT 0
-#define MCDE_TVDVO_DVO1_MASK 0x7FF
-
-
-#define MCDE_TVTIM1 (MCDE_BASE + 0x84C)
-#define MCDE_TVTIM1_DHO_SHIFT 0
-#define MCDE_TVTIM1_DHO_MASK 0x7FF
-
-
-#define MCDE_TVLBALW (MCDE_BASE + 0x850)
-#define MCDE_TVLBALW_ALW_SHIFT 16
-#define MCDE_TVLBALW_ALW_MASK 0x7FF
-#define MCDE_TVLBALW_LBW_SHIFT 0
-#define MCDE_TVLBALW_LBW_MASK 0x7FF
-
-
-#define MCDE_TVBL2 (MCDE_BASE + 0x854)
-#define MCDE_TVBL2_BSL2_SHIFT 16
-#define MCDE_TVBL2_BSL2_MASK 0x7FF
-#define MCDE_TVBL2_BEL2_SHIFT 0
-#define MCDE_TVBL2_BEL2_MASK 0x7FF
-
-
-#define MCDE_TVBLU (MCDE_BASE + 0x858)
-#define MCDE_TVBLU_TVBCR_SHIFT 16
-#define MCDE_TVBLU_TVBCR_MASK 0xFF
-#define MCDE_TVBLU_TVBCB_SHIFT 8
-#define MCDE_TVBLU_TVBCB_MASK 0xFF
-#define MCDE_TVBLU_TVBLU_SHIFT 0
-#define MCDE_TVBLU_TVBLU_MASK 0xFF
-
-
-#define MCDE_LDCTIM0 (MCDE_BASE + 0x85C)
-#define MCDE_LDCTIM0_REVVAEN 0x80000000
-#define MCDE_LDCTIM0_REVTGEN 0x40000000
-#define MCDE_LDCTIM0_REVLOADSEL_SHIFT 28
-#define MCDE_LDCTIM0_REVLOADSEL_MASK 0x3
-#define MCDE_LDCTIM0_REVDEL1_SHIFT 24
-#define MCDE_LDCTIM0_REVDEL1_MASK 0xF
-#define MCDE_LDCTIM0_REVDEL0_SHIFT 16
-#define MCDE_LDCTIM0_REVDEL0_MASK 0xFF
-#define MCDE_LDCTIM0_PSVAEN 0x00008000
-#define MCDE_LDCTIM0_PSTGEN 0x00004000
-#define MCDE_LDCTIM0_PSLOADSEL_SHIFT 12
-#define MCDE_LDCTIM0_PSLOADSEL_MASK 0x3
-#define MCDE_LDCTIM0_PSDEL1_SHIFT 8
-#define MCDE_LDCTIM0_PSDEL1_MASK 0xF
-#define MCDE_LDCTIM0_PSDEL0_SHIFT 0
-#define MCDE_LDCTIM0_PSDEL0_MASK 0xFF
-
-
-#define MCDE_LCDTIM1 (MCDE_BASE + 0x860)
-#define MCDE_LCDTIM1_IOE 0x00800000
-#define MCDE_LCDTIM1_IPC 0x00400000
-#define MCDE_LCDTIM1_IHS 0x00200000
-#define MCDE_LCDTIM1_IVS 0x00100000
-#define MCDE_LCDTIM1_IVP 0x00080000
-#define MCDE_LCDTIM1_ICLSPL 0x00040000
-#define MCDE_LCDTIM1_ICLREV 0x00020000
-#define MCDE_LCDTIM1_ICLSP 0x00010000
-#define MCDE_LCDTIM1_SPLVAEN 0x00008000
-#define MCDE_LCDTIM1_SPLTGEN 0x00004000
-#define MCDE_LCDTIM1_SPLLOADSEL_SHIFT 12
-#define MCDE_LCDTIM1_SPLLOADSEL_MASK 0x3
-#define MCDE_LCDTIM1_SPLDEL1_SHIFT 8
-#define MCDE_LCDTIM1_SPLDEL1_MASK 0xF
-#define MCDE_LCDTIM1_SPLDEL0_SHIFT 0
-#define MCDE_LCDTIM1_SPLDEL0_MASK 0xFF
-
-
-#define MCDE_DITCTRL (MCDE_BASE + 0x864)
-#define MCDE_DITCTRL_FOFFY_SHIFT 10
-#define MCDE_DITCTRL_FOFFY_MASK 0x1F
-#define MCDE_DITCTRL_FOFFX_SHIFT 5
-#define MCDE_DITCTRL_FOFFX_MASK 0x1F
-#define MCDE_DITCTRL_MASK 0x00000010
-#define MCDE_DITCTRL_MODE_SHIFT 2
-#define MCDE_DITCTRL_MODE_MASK 0x3
-#define MCDE_DITCTRL_COMP 0x00000002
-#define MCDE_DITCTRL_TEMP 0x00000001
-
-
-#define MCDE_DITOFF (MCDE_BASE + 0x868)
-#define MCDE_DITOFF_YB_SHIFT 24
-#define MCDE_DITOFF_YB_MASK 0x1F
-#define MCDE_DITOFF_XB_SHIFT 16
-#define MCDE_DITOFF_XB_MASK 0x1F
-#define MCDE_DITOFF_YG_SHIFT 8
-#define MCDE_DITOFF_YG_MASK 0x1F
-#define MCDE_DITOFF_XG_SHIFT 0
-#define MCDE_DITOFF_XG_MASK 0x1F
-
-
-#define MCDE_PAL0 (MCDE_BASE + 0x86C)
-#define MCDE_PAL0_GREEN_SHIFT 16
-#define MCDE_PAL0_GREEN_MASK 0xFFF
-#define MCDE_PAL0_BLUE_SHIFT 0
-#define MCDE_PAL0_BLUE_MASK 0xFFF
-
-
-#define MCDE_PAL1 (MCDE_BASE + 0x870)
-#define MCDE_PAL1_RED_SHIFT 0
-#define MCDE_PAL1_RED_MASK 0xFFF
-
-
-#define MCDE_ROTADD0 (MCDE_BASE + 0x874)
-//#define MCDE_ROTADD0_SHIFT 3
-//#define MCDE_ROTADD0_MASK
-#define MCDE_ROTADD1 (MCDE_BASE + 0x878)
-
-
-#define MCDE_ROTCONF (MCDE_BASE + 0x87C)
-#define MCDE_ROTCONF_RD_ROPC_SHIFT 24
-#define MCDE_ROTCONF_RD_ROPC_MASK 0xFF
-#define MCDE_ROTCONF_WR_ROPC_SHIFT 16
-#define MCDE_ROTCONF_WR_ROPC_MASK 0xFF
-#define MCDE_ROTCONF_STRIP_WIDTH_SHIFT 8
-#define MCDE_ROTCONF_STRIP_WIDTH_MASK 0xFF
-#define MCDE_ROTCONF_RD_MAXOUT_SHIFT 6
-#define MCDE_ROTCONF_RD_MAXOUT_MASK 0x3
-#define MCDE_ROTCONF_WR_MAXOUT_SHIFT 4
-#define MCDE_ROTCONF_WR_MAXOUT_MASK 0x3
-#define MCDE_ROTCONF_ROTDIR 0x00000008
-#define MCDE_ROTCONF_ROTBURSTSIZE_SHIFT 0
-#define MCDE_ROTCONF_ROTBURSTSIZE_MASK 0x7
-
-
-#define MCDE_SYNCHCONF (MCDE_BASE + 0x880)
-#define MCDE_SYNCHCONF_SWINTVCNT_SHIFT 18
-#define MCDE_SYNCHCONF_SWINTVCNT_MASK 0x3FFF
-#define MCDE_SYNCHCONF_SWINTVEVENT_SHIFT 16
-#define MCDE_SYNCHCONF_SWINTVEVENT_MASK 0x3
-#define MCDE_SYNCHCONF_HWREQVCNT_SHIFT 2
-#define MCDE_SYNCHCONF_HWREQVCNT_MASK 0x3FFF
-#define MCDE_SYNCHCONF_HWREQVEVENT_SHIFT 0
-#define MCDE_SYNCHCONF_HWREQVEVENT_MASK 0x3
-
-
-#define MCDE_GAM0 (MCDE_BASE + 0x888)
-#define MCDE_GAM0_BLUE_SHIFT 0
-#define MCDE_GAM0_BLUE_MASK 0x00FFFFFF
-
-
-#define MCDE_GAM1 (MCDE_BASE + 0x88C)
-#define MCDE_GAM1_GREEN_SHIFT 0
-#define MCDE_GAM1_GREEN_MASK 0x00FFFFFF
-
-
-#define MCDE_GAM2 (MCDE_BASE + 0x890)
-#define MCDE_GAM2_RED_SHIFT 0
-#define MCDE_GAM2_RED_MASK 0x00FFFFFF
-
-
-#define MCDE_OLEDCONV1 (MCDE_BASE + 0x894)
-#define MCDE_OLEDCONV1_ALPHA_GREEN_SHIFT 16
-#define MCDE_OLEDCONV1_ALPHA_GREEN_MASK 0x3FFF
-#define MCDE_OLEDCONV1_ALPHA_RED_SHIFT 0
-#define MCDE_OLEDCONV1_ALPHA_RED_MASK 0x3FFF
-
-
-#define MCDE_OLEDCONV2 (MCDE_BASE + 0x898)
-#define MCDE_OLEDCONV2_BETA_RED_SHIFT 16
-#define MCDE_OLEDCONV2_BETA_RED_MASK 0x3FFF
-#define MCDE_OLEDCONV2_ALPHA_BLUE_SHIFT 0
-#define MCDE_OLEDCONV2_ALPHA_BLUE_MASK 0x3FFF
-
-
-#define MCDE_OLEDCONV3 (MCDE_BASE + 0x89C)
-#define MCDE_OLEDCONV3_BETA_BLUE_SHIFT 16
-#define MCDE_OLEDCONV3_BETA_BLUE_MASK 0x3FFF
-#define MCDE_OLEDCONV3_BETA_GREEN_SHIFT 0
-#define MCDE_OLEDCONV3_BETA_GREEN_MASK 0x3FFF
-
-
-#define MCDE_OLEDCONV4 (MCDE_BASE + 0x8A0)
-#define MCDE_OLEDCONV4_GAMMA_GREEN_SHIFT 16
-#define MCDE_OLEDCONV4_GAMMA_GREEN_MASK 0x3FFF
-#define MCDE_OLEDCONV4_GAMMA_RED_SHIFT 0
-#define MCDE_OLEDCONV4_GAMMA_RED_MASK 0x3FFF
-
-
-#define MCDE_OLEDCONV5 (MCDE_BASE + 0x8A4)
-#define MCDE_OLEDCONV5_OFF_RED_SHIFT 16
-#define MCDE_OLEDCONV5_OFF_RED_MASK 0x3FFF
-#define MCDE_OLEDCONV5_GAMMA_BLUE_SHIFT 0
-#define MCDE_OLEDCONV5_GAMMA_BLUE_MASK 0x3FFF
-
-
-#define MCDE_OLEDCONV6 (MCDE_BASE + 0x8A8)
-#define MCDE_OLEDCONV6_OFF_BLUE_SHIFT 16
-#define MCDE_OLEDCONV6_OFF_BLUE_MASK 0x3FFF
-#define MCDE_OLEDCONV6_OFF_GREEN_SHIFT 0
-#define MCDE_OLEDCONV6_OFF_GREEN_MASK 0x3FFF
-
-
-#define MCDE_CRC (MCDE_BASE + 0xC00)
-#define MCDE_CRC_CLAMPC1EN 0x80000000
-#define MCDE_CRC_SYNCCTRL_SHIFT 29
-#define MCDE_CRC_SYNCCTRL_MASK 0x3
-#define MCDE_CRC_RES2POL 0x10000000
-#define MCDE_CRC_RES1POL 0x08000000
-#define MCDE_CRC_RD2POL 0x04000000
-#define MCDE_CRC_RD1POL 0x02000000
-#define MCDE_CRC_WR2POL 0x01000000
-#define MCDE_CRC_WR1POL 0x00800000
-#define MCDE_CRC_CD2POL 0x00400000
-#define MCDE_CRC_CD1POL 0x00200000
-#define MCDE_CRC_CS2POL 0x00100000
-#define MCDE_CRC_CS1POL 0x00080000
-#define MCDE_CRC_RESEN 0x00040000
-#define MCDE_CRC_CS2EN 0x00020000
-#define MCDE_CRC_CS1EN 0x00010000
-#define MCDE_CRC_YUVCONVC1EN 0x00008000
-#define MCDE_CRC_CLKSEL_SHIFT 13
-#define MCDE_CRC_CLKSEL_MASK 0x3
-#define MCDE_CRC_INBAND2 0x00001000
-#define MCDE_CRC_INBAND1 0x00000800
-#define MCDE_CRC_SIZE2 0x00000400
-#define MCDE_CRC_SIZE1 0x00000200
-#define MCDE_CRC_SYCEN1 0x00000100
-#define MCDE_CRC_SYCEN0 0x00000080
-#define MCDE_CRC_SYNCSEL 0x00000040
-#define MCDE_CRC_WMLVL2 0x00000020
-#define MCDE_CRC_WMLVL1 0x00000010
-#define MCDE_CRC_C2EN 0x00000008
-#define MCDE_CRC_C1EN 0x00000004
-#define MCDE_CRC_POWEREN 0x00000002
-#define MCDE_CRC_FLOEN 0x00000001
-
-
-#define MCDE_PBCCRC (MCDE_BASE + 0xC04)
-#define MCDE_PBCCRC_BPP_SHIFT 13
-#define MCDE_PBCCRC_BPP_MASK 0x7
-#define MCDE_PBCCRC_PDCTRL 0x00001000
-#define MCDE_PBCCRC_PDM_SHIFT 8
-#define MCDE_PBCCRC_PDM_MASK 0x3
-#define MCDE_PBCCRC_BSDM_SHIFT 4
-#define MCDE_PBCCRC_BSDM_MASK 0x7
-#define MCDE_PBCCRC_BSCM_SHIFT 0
-#define MCDE_PBCCRC_BSCM_MASK 0x7
-
-
-#define MCDE_PBCBMRC (MCDE_BASE + 0xC0C)
-#define MCDE_PBCBCRC (MCDE_BASE + 0xC34)
-
-
-#define MCDE_VSCRC (MCDE_BASE + 0xC5C)
-#define MCDE_VSCRC_VSDBL_SHIFT 29
-#define MCDE_VSCRC_VSDBL_MASK 0x7
-#define MCDE_VSCRC_VSSEL 0x10000000
-#define MCDE_VSCRC_VSPOL 0x08000000
-#define MCDE_VSCRC_VSPDIV_SHIFT 24
-#define MCDE_VSCRC_VSPDIV_MASK 0x7
-#define MCDE_VSCRC_VSPMAX_SHIFT 12
-#define MCDE_VSCRC_VSPMAX_MASK 0xFFF
-#define MCDE_VSCRC_VSPMIN_SHIFT 0
-#define MCDE_VSCRC_VSPMIN_MASK 0xFFF
-
-
-#define MCDE_SCTRC (MCDE_BASE + 0xC64)
-#define MCDE_SCTRC_TRDELC_SHIFT 16
-#define MCDE_SCTRC_TRDELC_MASK 0xFFF
-#define MCDE_SCTRC_SYNCDELC1_SHIFT 8
-#define MCDE_SCTRC_SYNCDELC1_MASK 0xFF
-#define MCDE_SCTRC_SYNCDELC0_SHIFT 0
-#define MCDE_SCTRC_SYNCDELC0_MASK 0xFF
-
-
-#define MCDE_SCSRC (MCDE_BASE + 0xC68)
-#define MCDE_SCSRC_VSTAC1 0x00000002
-#define MCDE_SCSRC_VSTAC0 0x00000001
-
-
-#define MCDE_BCNR (MCDE_BASE + 0xC6C)
-#define MCDE_BCNR_BCN_SHIFT 0
-#define MCDE_BCNR_BCN_MASK 0xFF
-
-
-#define MCDE_CSCDTR (MCDE_BASE + 0xC74)
-#define MCDE_CSCDTR_CSCDDEACT_SHIFT 8
-#define MCDE_CSCDTR_CSCDDEACT_MASK 0xFF
-#define MCDE_CSCDTR_CSCDACT_SHIFT 0
-#define MCDE_CSCDTR_CSCDACT_MASK 0xFF
-
-
-#define MCDE_RDWRTR (MCDE_BASE + 0xC7C)
-#define MCDE_RDWRTR_MOTINT 0x00010000
-#define MCDE_RDWRTR_RWDEACT_SHIFT 8
-#define MCDE_RDWRTR_RWDEACT_MASK 0xFF
-#define MCDE_RDWRTR_RWACT_SHIFT 0
-#define MCDE_RDWRTR_RWACT_MASK 0xFF
-
-
-#define MCDE_DOTR (MCDE_BASE + 0xC84)
-#define MCDE_DOTR_DODEACT_SHIFT 8
-#define MCDE_DOTR_DODEACT_MASK 0xFF
-#define MCDE_DOTR_DOACT_SHIFT 0
-#define MCDE_DOTR_DOACT_MASK 0xFF
-
-
-#define MCDE_WCMDC (MCDE_BASE + 0xC8C)
-#define MCDE_WDATADC (MCDE_BASE + 0xC94)
-
-
-#define MCDE_RDATADC (MCDE_BASE + 0xC9C)
-#define MCDE_RDATADC_STARTREAD 0x00010000
-#define MCDE_RDATADC_DATAREADFROMDISPLAYMODULE_SHIFT 0
-#define MCDE_RDATADC_DATAREADFROMDISPLAYMODULE_MASK 0xFF
-
-
-#define MCDE_STATC (MCDE_BASE + 0xCA4)
-#define MCDE_STATC_FIFOCMDFULL1 0x00000200
-#define MCDE_STATC_FIFOCMDEMPTY1 0x00000100
-#define MCDE_STATC_FIFOFULL1 0x00000080
-#define MCDE_STATC_FIFOEMPTY1 0x00000040
-#define MCDE_STATC_STATBUSY1 0x00000020
-#define MCDE_STATC_FIFOCMDFULL0 0x00000010
-#define MCDE_STATC_FIFOCMDEMPTY0 0x00000008
-#define MCDE_STATC_FIFOFULL0 0x00000004
-#define MCDE_STATC_FIFOEMPTY0 0x00000002
-#define MCDE_STATC_STATBUSY0 0x00000001
-
-
-#define MCDE_CTRLC (MCDE_BASE + 0xCA8)
-#define MCDE_CTRLC_FIFOWTRMRK_SHIFT 0
-#define MCDE_CTRLC_FIFOWTRMRK_MASK 0xFF
-
-
-#define MCDE_DSICONF0 (MCDE_BASE + 0xE00)
-#define MCDE_DSICONF0_PACKING_SHIFT 20
-#define MCDE_DSICONF0_PACKING_MASK 0x7
-#define MCDE_DSICONF0_DCSVID_NOTGEN 0x00040000
-#define MCDE_DSICONF0_BYTE_SWAP 0x00020000
-#define MCDE_DSICONF0_BIT_SWAP 0x00010000
-#define MCDE_DSICONF0_CMD8 0x00002000
-#define MCDE_DSICONF0_VID_MODE 0x00001000
-#define MCDE_DSICONF0_BLANKING_SHIFT 0
-#define MCDE_DSICONF0_BLANKING_MASK 0xFF
-
-
-#define MCDE_DSIFRAME (MCDE_BASE + 0xE04)
-
-#define MCDE_DSIPKT (MCDE_BASE + 0xE08)
-#define MCDE_DSIPKT_PACKET_SHIFT 0
-#define MCDE_DSIPKT_PACKET_MASK 0xFFFF
-
-
-#define MCDE_DSISYNC (MCDE_BASE + 0xE0C)
-#define MCDE_DSISYNC_SW_SHIFT 16
-#define MCDE_DSISYNC_SW_MASK 0xFFF
-#define MCDE_DSISYNC_DMA_SHIFT 0
-#define MCDE_DSISYNC_DMA_MASK 0xFFF
-
-
-#define MCDE_DSICMDW (MCDE_BASE + 0xE10)
-#define MCDE_DSICMDW_CMDW_START_SHIFT 16
-#define MCDE_DSICMDW_CMDW_START_MASK 0xFFFF
-#define MCDE_DSICMDW_CMDW_CONTINUE_SHIFT 0
-#define MCDE_DSICMDW_CMDW_CONTINUE_MASK 0xFFFF
-#define MCDE_DSICMDW_CMD_START_MEMORY_WRITE 0x2C
-#define MCDE_DSICMDW_CMD_CONTINUE_MEMORY_WRITE 0x3C
-
-
-#define MCDE_DSIDELAY0 (MCDE_BASE + 0xE14)
-#define MCDE_DSIDELAY0_INTPKTDEL_SHIFT 0
-#define MCDE_DSIDELAY0_INTPKTDEL_MASK 0xFFFF
-
-
-#define MCDE_DSIDELAY1 (MCDE_BASE + 0xE18)
-#define MCDE_DSIDELAY1_FRAMESTARTDEL_SHIFT 16
-#define MCDE_DSIDELAY1_FRAMESTARTDEL_MASK 0xFF
-#define MCDE_DSIDELAY1_TEREQDEL_SHIFT 0
-#define MCDE_DSIDELAY1_TEREQDEL_MASK 0xFFF
-
-
diff --git a/arch/arm/mach-ux500/include/mach/mcde_common.h b/arch/arm/mach-ux500/include/mach/mcde_common.h
deleted file mode 100755
index b906114c6a4..00000000000
--- a/arch/arm/mach-ux500/include/mach/mcde_common.h
+++ /dev/null
@@ -1,168 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * License terms:
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#ifndef _MCDE_COMMON_H_
-#define _MCDE_COMMON_H_
-#include <linux/fb.h>
-#include <linux/interrupt.h>
-#include <linux/platform_device.h>
-#include <linux/spinlock.h>
-#include <linux/mm.h>
-#include <linux/dma-mapping.h>
-
-#include <mach/bit_mask.h>
-#include <mach/mcde.h>
-#include <mach/mcde_reg.h>
-#include <mach/dsi.h>
-#include <mach/dsi_reg.h>
-
-#define MCDE_NAME "DRIVER MCDE"
-
-#define MCDE_DEFAULT_LOG_LEVEL 3
-#ifdef CONFIG_FB_NDK_MCDE
-extern int mcde_debug;
-module_param(mcde_debug, int, 0644);
-#endif
-#ifdef CONFIG_FB_NDK_MCDE
-MODULE_PARM_DESC(mcde_debug,"Debug level for messages");
-#define dbgprintk(num, format, args...) \
- do { \
- if(num >= mcde_debug ) \
- printk("MCDE:"format, ##args); \
- } while(0)
-#else
-#define dbgprintk(num, format, args...) \
- do { \
- printk("MCDE:"format, ##args); \
- } while(0)
-#endif
-
-#define MCDE_DEBUG_INFO 1
-#define MCDE_ERROR_INFO 3
-
-/** Global data */
-
-#define MAX_LPF 1080
-#define MAX_PPL 1920
-#define NUM_MCDE_FLOWS 4
-#ifdef CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT
-#define NUM_OVERLAYS 6
-#define NUM_EXT_SRC 10
-#define NUM_MCDE_CHANNELS 4
-#else
-#define NUM_OVERLAYS 16
-#define NUM_EXT_SRC 16
-#define NUM_MCDE_CHANNELS 16
-#endif /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */
-#define NUM_FLOWS_A_B 2
-#define NUM_DSI_LINKS 3
-#define NUM_DSI_CHANNEL 6
-#define MCDE_MAX_FRAMEBUFF 16
-#define COLCONV_COEFF_OFF 6
-
-/** clcd events for double buffering */
-struct clcd_event_struct {
- spinlock_t lock;
- int event;
- wait_queue_head_t wait;
- unsigned int base;
-};
-
-/** bitmap of which overlays are in use (set) and unused (cleared) */
-//static u32 mcde_ovl_bmp;
-
-/** MCDE private struct - pointer available in fbinfo */
-struct mcdefb_info {
- struct mcde_channel_data *chnl_info;
- mcde_ch_id chid;
- mcde_video_mode video_mode;
- mcde_fifo_output fifoOutput;
- mcde_output_conf output_conf;
- mcde_dsi_clk_config clk_config;
- mcde_ch_id dsi_formatter_plugged_channel[NUM_DSI_CHANNEL];
- mcde_dsi_channel mcdeDsiChnl;
- mcde_out_bpp outbpp;
- int bpp16_type;
- u8 bgrinput;
- u8 isHwInitalized;
- u16 palette_size;
- u32 cmap[16];
-
- mcde_ch_id pixel_pipeline;
- u32 vcomp_irq;
- u32 dsi_formatter;
- u32 dsi_mode;
- u32 swap;
- u32 started;
-
- /** phy-virtual addresses allocated for framebuffer and overlays */
- struct mcde_addrmap buffaddr[MCDE_MAX_FRAMEBUFF*2];
- struct mcde_addrmap rotationbuffaddr0;
- struct mcde_addrmap rotationbuffaddr1;
-
- /** total number of overlays used in the system */
- u8 tot_ovl_used;
-
- /** bitmap of which overlays are in use (set) and unused (cleared) */
- u16 mcde_cur_ovl_bmp;
- u16 mcde_ovl_bmp_arr[MCDE_MAX_FRAMEBUFF];
- spinlock_t mcde_spin_lock;
-
- /** event for double buffering */
- struct clcd_event_struct clcd_event;
- u8 tvout;
- u32 actual_bpp;
-#ifdef CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT
- struct mcde_top_reg __iomem *regbase;
-#else
- struct mcde_register_base __iomem * regbase;
-#endif /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */
- struct mcde_ext_src_reg __iomem * extsrc_regbase[NUM_EXT_SRC];
- struct mcde_ovl_reg __iomem * ovl_regbase[NUM_OVERLAYS];
-#ifdef CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT
- struct mcde_chnl_conf_reg __iomem *ch_regbase1[NUM_MCDE_CHANNELS];
- struct mcde_chAB_reg __iomem *ch_regbase2[NUM_FLOWS_A_B];
- struct mcde_chC0C1_reg __iomem *ch_c_reg;
-#else
- struct mcde_ch_synch_reg __iomem *ch_regbase1[NUM_MCDE_CHANNELS];
- struct mcde_ch_reg __iomem *ch_regbase2[NUM_FLOWS_A_B];
- struct mcde_chc_reg __iomem *ch_c_reg;
-#endif /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */
- struct mcde_dsi_reg __iomem *mcde_dsi_channel_reg[NUM_DSI_CHANNEL];
- volatile u32 __iomem *mcde_clkdsi;
- struct dsi_link_registers __iomem *dsi_lnk_registers[NUM_DSI_LINKS];
- volatile u32 __iomem *prcm_mcde_clk;
- volatile u32 __iomem *prcm_hdmi_clk;
- volatile u32 __iomem *prcm_tv_clk;
- dsi_link dsi_lnk_no;
- dsi_link_context dsi_lnk_context;
- struct dsi_link_conf dsi_lnk_conf;
-
- /* Added by QCSPWAN below for "pink display" */
-#ifdef CONFIG_DEBUG_FS
- struct dentry *debugfs_dentry;
- char debugfs_name[10];
-#endif
- /* To serialize access from user space */
- struct semaphore fb_sem;
- /* End QCSPWAN */
-};
-
-
-//volatile mcde_system_context g_mcde_system_context;
-
-#define NUM_TOTAL_MODES ARRAY_SIZE(mcde_modedb)
-
-mcde_error mcdesetdsiclk(dsi_link link, mcde_ch_id chid, mcde_dsi_clk_config clk_config);
-mcde_error mcdesetfifoctrl(dsi_link link, mcde_ch_id chid, struct mcde_fifo_ctrl fifo_ctrl);
-mcde_error mcdesetoutputconf(dsi_link link, mcde_ch_id chid, mcde_output_conf output_conf);
-mcde_error mcdesetdsicommandword(dsi_link link,mcde_ch_id chid,mcde_dsi_channel dsichannel,u8 cmdbyte_lsb,u8 cmdbyte_msb);
-mcde_error mcdesetdsiconf(dsi_link link, mcde_ch_id chid, mcde_dsi_channel dsichannel, mcde_dsi_conf dsi_conf);
-#endif
diff --git a/arch/arm/mach-ux500/include/mach/mcde_ioctls.h b/arch/arm/mach-ux500/include/mach/mcde_ioctls.h
deleted file mode 100755
index 1ba82ea0dbb..00000000000
--- a/arch/arm/mach-ux500/include/mach/mcde_ioctls.h
+++ /dev/null
@@ -1,737 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * License terms:
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#ifndef _MCDE_IOCTLS_H_
-#define _MCDE_IOCTLS_H_
-
-typedef enum
-{
- COLOR_CONV_NONE = 0x0,
- COLOR_CONV_YUV_RGB = 0x1,
- COLOR_CONV_RGB_YUV = 0x2,
- COLOR_CONV_YUV422_YUV444 = 0x3
-}mcde_colorconv_type;
-
-typedef enum
-{
- MCDE_COL_CONV_DISABLE = 0x0,
- MCDE_COL_CONV_NOT_SAT = 0x1,
- MCDE_COL_CONV_SAT = 0x2,
- MCDE_COL_CONV_RESERVED
-}mcde_col_conv_ctrl;
-
-struct mcde_ovr_blend_ctrl
-{
- char alpha_value;
- char ovr_opaq;
- char ovr_blend;
- char ovr_zlevel;
- unsigned int ovr_xpos;
- unsigned int ovr_ypos;
-};
-
-typedef enum
-{
- MCDE_ROTATE_BURST_WORD_1 = 0x0,
- MCDE_ROTATE_BURST_WORD_2 = 0x1,
- MCDE_ROTATE_BURST_WORD_4 = 0x2,
- MCDE_ROTATE_BURST_WORD_8 = 0x3,
- MCDE_ROTATE_BURST_WORD_16 = 0x04,
- MCDE_ROTATE_BURST_WORD_RESERVED
- }mcde_rotate_req;
-
-typedef enum
-{
- MCDE_OUTSTND_REQ_1 = 0x0,
- MCDE_OUTSTND_REQ_2 = 0x1,
- MCDE_OUTSTND_REQ_4 = 0x2,
- MCDE_OUTSTND_REQ_8 = 0x3,
- MCDE_OUTSTND_REQ_16 = 0x4,
- MCDE_OUTSTND_REQ_RESERVED
-}mcde_outsnd_req;
-typedef enum
-{
- MCDE_BURST_WORD_1 = 0x00,
- MCDE_BURST_WORD_2 = 0x01,
- MCDE_BURST_WORD_4 = 0x02,
- MCDE_BURST_WORD_8 = 0x03,
- MCDE_BURST_WORD_16 = 0x04,
- MCDE_BURST_WORD_HW_1 = 0x8,
- MCDE_BURST_WORD_HW_2 = 0x09,
- MCDE_BURST_WORD_HW_4 = 0x0A,
- MCDE_BURST_WORD_HW_8 = 0x0B,
- MCDE_BURST_WORD_HW_16 = 0x0C
-}mcde_burst_req;
-typedef enum
-{
- MCDE_COLOR_KEY_DISABLE = 0x0,
- MCDE_COLOR_KEY_ENABLE = 0x01
-}mcde_color_key_ctrl;
-typedef enum
-{
- MCDE_PAL_GAMA_DISABLE = 0x0,
- MCDE_GAMA_ENABLE = 0x1,
- MCDE_PAL_ENABLE = 0x2,
- MCDE_PAL_GAMA_RESERVED
-}mcde_pal_ctrl;
-typedef enum
-{
- MCDE_OVERLAY_DISABLE = 0x0,
- MCDE_OVERLAY_ENABLE = 0x1
-}mcde_overlay_ctrl;
-typedef enum
-{
- MCDE_PIXEL_ALPHA_SOURCE = 0x0,
- MCDE_CONST_ALPHA_SOURCE = 0x1
-}mcde_blend_ctrl;
-typedef enum
-{
- MCDE_OVR_OPAQUE_DISABLE = 0x0,
- MCDE_OVR_OPAQUE_ENABLE = 0x1
-}mcde_ovr_opq_ctrl;
-typedef enum
-{
- MCDE_OVR_PREMULTIPLIED_ALPHA_DISABLE = 0x0,
- MCDE_OVR_PREMULTIPLIED_ALPHA_ENABLE = 0x1
-}mcde_ovr_alpha_enable;
-typedef enum
-{
- MCDE_OVR_CLIP_DISABLE = 0x0,
- MCDE_OVR_CLIP_ENABLE = 0x1
-}mcde_ovr_clip_enable;
-
-struct mcde_chconfig
-{
- unsigned short lpf;
- unsigned short ppl;
-};
-typedef enum
-{
- MCDE_LCD_TV_0 = 0x0,
- MCDE_LCD_TV_1 = 0x1,
- MCDE_MDIF_IN_0 = 0x2,
- MCDE_MDIF_IN_1 = 0x3,
- MCDE_MDIF_OUT_0 = 0x4,
- MCDE_MDIF_OUT_1 = 0x5
-}mcde_synchro_out_interface;
-typedef enum
-{
- MCDE_SYNCHRO_OUTPUT_SOURCE = 0x0,
- MCDE_SYNCHRO_AUTO = 0x1,
- MCDE_SYNCHRO_SOFTWARE = 0x2,
- MCDE_SYNCHRO_EXTERNAL_SOURCE = 0x3
-}mcde_synchro_source;
-typedef enum
-{
- MCDE_NO_ACTION = 0x0,
- MCDE_NEW_FRAME_SYNCHRO = 0x1
-}mcde_sw_trigger;
-typedef enum
-{
- MCDE_VERTICAL_SYNCHRO = 0x00,
- MCDE_BACK_PORCH = 0x01,
- MCDE_ACTIVE_VIDEO = 0x02,
- MCDE_FRONT_PORCH = 0x03
-}mcde_frame_events;
-struct mcde_ch_bckgrnd_col
-{
- unsigned char red;
- unsigned char green;
- unsigned char blue;
-};
-typedef enum
-{
- MCDE_TVCLK_EXTERNAL = 0x0,
- MCDE_TVCLK_INTERNAL = 0x1
-}mcde_tv_clk;
-typedef enum
-{
- MCDE_PCD_ENABLE = 0x0,
- MCDE_PCD_BYPASS = 0x1
-}mcde_bcd_ctrl;
-typedef enum
-{
- MCDE_BPP_1_TO_8 = 0x0,
- MCDE_BPP_12 = 0x1,
- MCDE_BPP_16 = 0x2,
- MCDE_BPP_18 = 0x3,
- MCDE_BPP_24 = 0x4
-}mcde_out_bpp;
-typedef enum
-{
- MCDE_BUS_16_CONF1 = 0x0,
- MCDE_BUS_16_CONF2 = 0x1,
- MCDE_BUS_16_CONF3 = 0x2,
- MCDE_BUS_18_CONF1 = 0x3,
- MCDE_BUS_18_CONF2 = 0x4,
- MCDE_BUS_24 = 0x5
-}mcde_lcd_bus;
-typedef enum
-{
- MCDE_CLK_STBUS = 0x0,
- MCDE_CLK_72 = 0x1,
- MCDE_CLK_42 = 0x2,
- MCDE_CLK_27 = 0x3,
- MCDE_CLK_TVCLK1 = 0x4,
- MCDE_CLK_TVCLK2 = 0x5
-}mcde_dpi2_clksel;
-
-struct mcde_chx_control1
-{
- mcde_tv_clk tv_clk;
- mcde_bcd_ctrl bcd_ctrl;
- mcde_out_bpp out_bpp;
- unsigned short clk_per_line;
- mcde_lcd_bus lcd_bus;
- mcde_dpi2_clksel dpi2_clk;
- unsigned short pcd;
-};
-typedef enum
-{
- MCDE_CLR_KEY_DISABLE = 0x0,
- MCDE_ALPHA_RGB_KEY = 0x1,
- MCDE_RGB_KEY = 0x2,
- MCDE_FALPHA_FRGB_KEY = 0x4,
- MCDE_FRGB_KEY = 0x5
-}mcde_key_ctrl;
-typedef enum
-{
- MCDE_COLORKEY_NORMAL = 0x0,
- MCDE_COLORKEY_FORCE= 0x1
-}mcde_colorkey_type;
-struct mcde_chx_color_key
-{
- unsigned char alpha;
- unsigned char red;
- unsigned char green;
- unsigned char blue;
-};
-typedef enum
-{
- MCDE_SDTV_656P = 0x0,
- MCDE_HDTV_480P = 0x1,
- MCDE_HDTV_720P = 0x2,
- MCDE_TV_NOTUSED = 0x3,
-}mcde_tvmode;
-typedef enum
-{
- MCDE_ACTIVE_HIGH = 0x0,
- MCDE_ACTIVE_LOW = 0x1
-}mcde_signal_level;
-typedef enum
-{
- MCDE_MODE_LCD = 0x0,
- MCDE_MODE_TV = 0x1
-}mcde_display_mode;
-typedef enum
-{
- MCDE_SCAN_PROGRESSIVE_MODE = 0x0,
- MCDE_SCAN_INTERLACED_MODE = 0x1,
-}mcde_scan_mode;
-
-typedef enum
-{
- MCDE_TV_PAL = 0x0,
- MCDE_TV_NTSC = 0x1,
-}mcde_tv_mode;
-
-struct mcde_chnl_lcd_ctrl_reg
-{
- unsigned short num_lines;
- unsigned short ppl;
- mcde_tvmode tv_mode;
- mcde_signal_level ifield;
- mcde_scan_mode scan_mode;
- mcde_display_mode sel_mode;
-};
-struct mcde_chnl_lcd_horizontal_timing
-{
- unsigned short hbp;
- unsigned short hfp;
- unsigned short hsw;
-};
-struct mcde_chnl_lcd_vertical_timing
-{
- unsigned short vbp;
- unsigned short vfp;
- unsigned short vsw;
-};
-
-typedef enum
-{
- MCDE_ANTIFLICKER_DISABLE = 0x0,
- MCDE_ANTIFLICKER_ENABLE = 0x1
-}mcde_antiflicker_ctrl;
-
-typedef enum
-{
- MCDE_PIXEL_ORDER_LITTLE = 0x0,
- MCDE_PIXEL_ORDER_BIG = 0x1
-}mcde_pixel_order_in_byte;
-
-typedef enum
-{
- MCDE_BYTE_LITTLE = 0x0,
- MCDE_BYTE_BIG = 0x1
-}mcde_byte_endianity;
-
-typedef enum
-{
- MCDE_COL_RGB = 0x0,
- MCDE_COL_BGR = 0x1
-}mcde_rgb_format_sel;
-
-typedef enum
-{
- MCDE_PAL_1_BIT = 0x0,
- MCDE_PAL_2_BIT = 0x1,
- MCDE_PAL_4_BIT = 0x2,
- MCDE_PAL_8_BIT = 0x3,
- MCDE_RGB444_12_BIT = 0x4,
- MCDE_ARGB_16_BIT = 0x5,
- MCDE_IRGB1555_16_BIT = 0x6,
- MCDE_RGB565_16_BIT = 0x7,
- MCDE_RGB_PACKED_24_BIT = 0x8,
- MCDE_RGB_UNPACKED_24_BIT = 0x9,
- MCDE_ARGB_32_BIT =0xA,
- MCDE_YCbCr_8_BIT = 0xB
-}mcde_bpp_ctrl;
-
-typedef enum
-{
- MCDE_OVERLAY_0 = 0x0,
- MCDE_OVERLAY_1 = 0x1,
- MCDE_OVERLAY_2 = 0x2,
- MCDE_OVERLAY_3 = 0x3,
- MCDE_OVERLAY_4 = 0x4,
- MCDE_OVERLAY_5 = 0x5,
- MCDE_OVERLAY_6 = 0x6,
- MCDE_OVERLAY_7 = 0x7
-}mcde_overlay_id;
-
-typedef enum
-{
- MCDE_BUFFER_USED_NONE = 0x0,
- MCDE_BUFFER_USED_1 = 0x1,
- MCDE_BUFFER_USED_2 = 0x2,
- MCDE_BUFFER_USED_3 = 0x3
-}mcde_num_buffer_used;
-
-typedef enum
-{
- MCDE_BUFFER_ID_0 = 0x0,
- MCDE_BUFFER_ID_1 = 0x1,
- MCDE_BUFFER_ID_2 = 0x2,
- MCDE_BUFFER_ID_RESERVED
-}mcde_buffer_id;
-
-typedef enum
-{
- MCDE_MASK_DISABLE = 0x0,
- MCDE_MASK_ENABLE = 0x1
-}mcde_masking_bit_ctrl;
-
-typedef enum
-{
- MCDE_DITHERING_RESET = 0x0,
- MCDE_DITHERING_ACTIVATE = 0x1
-}mcde_dithering_control;
-typedef enum
-{
- MCDE_DITHERING_DISABLE = 0x0,
- MCDE_DITHERING_ENABLE = 0x1
-}mcde_dithering_ctrl;
-struct mcde_chx_dither_ctrl
-{
- unsigned char y_offset;
- unsigned char x_offset;
- mcde_masking_bit_ctrl masking_ctrl;
- unsigned char mode;
- mcde_dithering_ctrl comp_dithering;
- mcde_dithering_ctrl temp_dithering;
-};
-struct mcde_chx_dithering_offset
-{
- unsigned char y_offset_rb;
- unsigned char x_offset_rb;
- unsigned char y_offset_rg;
- unsigned char x_offset_rg;
-};
-
-typedef enum{
- VMODE_640_350_85_P,
- VMODE_640_400_85_P,
- VMODE_720_400_85_P,
- VMODE_640_480_60_P,
- VMODE_640_480_CRT_60_P,
- VMODE_240_320_60_P,
- VMODE_320_240_60_P,
- VMODE_712_568_60_P,
- VMODE_640_480_75_P,
- VMODE_640_480_85_P,
-//#ifdef CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT
- VMODE_480_864_60_P,
-//#endif
- VMODE_864_480_60_P,
- VMODE_800_600_56_P,
- VMODE_800_600_60_P,
- VMODE_800_600_72_P,
- VMODE_800_600_75_P,
- VMODE_800_600_85_P,
- VMODE_1024_768_60_P,
- VMODE_1024_768_70_P,
- VMODE_1024_768_75_P,
- VMODE_1024_768_85_P,
- VMODE_1152_864_75_P,
- VMODE_1280_960_60_P,
- VMODE_1280_960_85_P,
- VMODE_1280_1024_60_P,
- VMODE_1280_1024_75_P,
- VMODE_1280_1024_85_P,
- VMODE_1600_1200_60_P,
- VMODE_1600_1200_65_P,
- VMODE_1600_1200_70_P,
- VMODE_1600_1200_75_P,
- VMODE_1600_1200_85_P,
- VMODE_1792_1344_60_P,
- VMODE_1792_1344_75_P,
- VMODE_1856_1392_60_P,
- VMODE_1856_1392_75_P,
- VMODE_1920_1440_60_P,
- VMODE_1920_1440_75_P,
- VMODE_720_480_60_P,
- VMODE_720_480_60_I,
- VMODE_720_576_50_P,
- VMODE_720_576_50_I,
- VMODE_1280_720_50_P,
- VMODE_1280_720_60_P,
- VMODE_1920_1080_50_I,
- VMODE_1920_1080_60_I,
- VMODE_1920_1080_60_P,
-#ifdef CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT
- VMODE_1280_720_24_P,
- VMODE_1280_720_30_P,
- VMODE_1920_1080_24_P,
- VMODE_1920_1080_25_P,
- VMODE_1920_1080_30_P,
-#endif
-}mcde_video_mode;
-/*****************************************************************************
-IOCTLs for access from user space
-*******************************************************************************/
-
-#define MCDE_IOC_MAGIC 'm'
-
-#define MCDE_IOCTL_OVERLAY_CREATE _IOWR(MCDE_IOC_MAGIC, 0x0,struct mcde_overlay_create)
-#define MCDE_IOCTL_OVERLAY_REMOVE _IOR(MCDE_IOC_MAGIC, 0x1,unsigned long)
-#define MCDE_IOCTL_COLOR_KEYING_ENABLE _IOWR(MCDE_IOC_MAGIC, 0x2,struct mcde_channel_color_key)
-#define MCDE_IOCTL_COLOR_KEYING_DISABLE _IOR(MCDE_IOC_MAGIC, 0x3,unsigned long)
-#define MCDE_IOCTL_COLOR_COVERSION_ENABLE _IOWR(MCDE_IOC_MAGIC, 0x4,struct mcde_conf_color_conv)
-#define MCDE_IOCTL_COLOR_COVERSION_DISABLE _IOR(MCDE_IOC_MAGIC, 0x5,unsigned long)
-#define MCDE_IOCTL_ROTATION_ENABLE _IOR(MCDE_IOC_MAGIC, 0x6,unsigned char)
-#define MCDE_IOCTL_ROTATION_DISABLE _IOR(MCDE_IOC_MAGIC, 0x7,unsigned char)
-#define MCDE_IOCTL_SET_VIDEOMODE _IOR(MCDE_IOC_MAGIC, 0x8, unsigned long)
-#define MCDE_IOCTL_ALLOC_FRAMEBUFFER _IOWR(MCDE_IOC_MAGIC, 0x9,struct mcde_sourcebuffer_alloc)
-#define MCDE_IOCTL_DEALLOC_FRAMEBUFFER _IOWR(MCDE_IOC_MAGIC, 0xA, unsigned long)
-#define MCDE_IOCTL_CONFIGURE_EXTSRC _IOR(MCDE_IOC_MAGIC, 0xB,struct mcde_ext_conf)
-#define MCDE_IOCTL_CONFIGURE_OVRLAY _IOR(MCDE_IOC_MAGIC, 0xC,struct mcde_conf_overlay)
-#define MCDE_IOCTL_CONFIGURE_CHANNEL _IOR(MCDE_IOC_MAGIC, 0xD,struct mcde_ch_conf)
-#define MCDE_IOCTL_CONFIGURE_PANEL _IOR(MCDE_IOC_MAGIC, 0xE,struct mcde_chnl_lcd_ctrl)
-#define MCDE_IOCTL_MCDE_ENABLE _IOR(MCDE_IOC_MAGIC, 0xF,unsigned long)
-#define MCDE_IOCTL_MCDE_DISABLE _IOR(MCDE_IOC_MAGIC, 0x10,unsigned long)
-#define MCDE_IOCTL_CHANNEL_BLEND_ENABLE _IOWR(MCDE_IOC_MAGIC,0x11,struct mcde_blend_control)
-#define MCDE_IOCTL_CHANNEL_BLEND_DISABLE _IOR(MCDE_IOC_MAGIC, 0x12,unsigned long)
-#define MCDE_IOCTL_CONFIGURE_DENC _IOR(MCDE_IOC_MAGIC, 0x13,unsigned long)
-#define MCDE_IOCTL_CONFIGURE_HDMI _IOR(MCDE_IOC_MAGIC, 0x14,unsigned long)
-#define MCDE_IOCTL_SET_SOURCE_BUFFER _IOR(MCDE_IOC_MAGIC, 0x15,struct mcde_source_buffer)
-#define MCDE_IOCTL_DITHERING_ENABLE _IOR(MCDE_IOC_MAGIC, 0x16,struct mcde_dithering_ctrl_conf)
-#define MCDE_IOCTL_DITHERING_DISABLE _IOR(MCDE_IOC_MAGIC, 0x16,unsigned long)
-#define MCDE_IOCTL_ANTIFLICKER_ENABLE _IOR(MCDE_IOC_MAGIC, 0x17,unsigned long)
-#define MCDE_IOCTL_ANTIFLICKER_DISABLE _IOR(MCDE_IOC_MAGIC, 0x18,unsigned long)
-#define MCDE_IOCTL_TEST_DSI_LPMODE _IOR(MCDE_IOC_MAGIC, 0x19,unsigned long)
-#define MCDE_IOCTL_TEST_DSI_HSMODE _IOR(MCDE_IOC_MAGIC, 0x1A,unsigned long)
-#define MCDE_IOCTL_SET_SCAN_MODE _IOWR(MCDE_IOC_MAGIC, 0x1B,unsigned long)
-#define MCDE_IOCTL_GET_SCAN_MODE _IOR(MCDE_IOC_MAGIC, 0x1C,unsigned long)
-
-#define MCDE_IOCTL_TV_PLUG_STATUS _IOR(MCDE_IOC_MAGIC, 0x1D,unsigned long)
-#define MCDE_IOCTL_TV_CHANGE_MODE _IOWR(MCDE_IOC_MAGIC, 0x1E,unsigned long)
-#define MCDE_IOCTL_TV_GET_MODE _IOR(MCDE_IOC_MAGIC, 0x1F,unsigned long)
-
-#define MCDE_IOCTL_REG_DUMP _IOR(MCDE_IOC_MAGIC, 0x20,unsigned long)
-
-/**
- * struct mcde_overlay_create - To create overlay
- * @xorig: frame buffer x-offset
- * @yorig: frame buffer y-offset
- * @xwidth: frame buffer x-width
- * @yheight - frame buffer y-height
- * @bpp: input source bits per pixel
- * @fg: if set then overlay goes to foreground,else remains in background
- * @key: unique framebuffer key returned by driver
- * @bgrinput: if set then implies BGR input
- * @usedefault: if set then uses base overlay buffer
- *
- *
- **/
-struct mcde_overlay_create {
- unsigned long xorig;
- unsigned long yorig;
- unsigned long xwidth;
- unsigned long yheight;
- char bpp; /** input source bits per pixel */
- char fg; /** if set then overlay goes to foreground,else remains in background */
- unsigned long key; /** unique framebuffer key returned by driver */
- unsigned long bgrinput; /** if set then implies BGR input */
- char usedefault; // if set then uses base overlay buffer
-};
-/**
- * struct mcde_addrmap - source frame buffer address map structure
- * @cpuaddr: logical address of the framebuffer
- * @dmaaddr: physical address of the framebuffer
- * @bufflength: buffer length
- *
- *
- **/
-struct mcde_addrmap {
- unsigned long cpuaddr;
- unsigned long dmaaddr;
- unsigned long bufflength;
-};
-/**
- * struct mcde_source_buffer - source frame buffer addresses structure
- * @buff_addr: frame buffer addresses structure
- * @buffid: buffer id
- *
- *
- **/
-struct mcde_source_buffer
-{
- struct mcde_addrmap buffaddr;
- unsigned char buffid;
-};
-/**
- * struct mcde_sourcebuffer_alloc - source frame buffer allocation structure
- * @xwidth: frame buffer x-width
- * @yheight: frame buffer y-height
- * @bpp: input source bits per pixel
- * @doubleBufferingEnabled: double buffer control
- * @key: unique framebuffer key returned by driver
- * @buff_addr: frame buffer addresses structure
- *
- *
- **/
-struct mcde_sourcebuffer_alloc {
- unsigned long xwidth;
- unsigned long yheight;
- char bpp; /** input source bits per pixel */
- char doubleBufferingEnabled;
- unsigned long key; /** unique framebuffer key returned by driver */
- struct mcde_addrmap buff_addr;
-};
-
-/**
- * struct mcde_dithering_ctrl_conf - Structure of overlay configuration
- * @rot_burst_req: rotation burst request
- * @outstnd_req: outstanding request
- * @burst_req: burst request
- * @priority: priority
- * @color_key: color key control
- * @pal_control: pal control
- * @col_ctrl: color conversion control
- * @convert_format: conversion format
- * @ovr_state: overlay control
- * @ovr_ypos: overlay y-position
- * @ovr_xpos: overlay x-position
- * @alpha: alpha control
- * @alpha_value: alpha value
- * @pixoff: pixel offset
- * @ovr_opaq: overlay opaque control
- * @ovr_blend: overlay blend control
- * @watermark_level: watermark level
- * @ovr_zlevel: foreground level
- * @clip: clip control
- * @ytlcoor: clip y-topleft coordinates
- * @xtlcoor: clip x-topleft coordinates
- * @ybrcoor: clip y-bottomright coordinates
- * @xbrcoor: clip x-bottomright coordinates
- * @xwidth: x-width
- * @yheight: y-height
- * @bpp: input bpp
- *
- *
- **/
-struct mcde_conf_overlay {
- mcde_rotate_req rot_burst_req;
- mcde_outsnd_req outstnd_req;
- mcde_burst_req burst_req;
- unsigned char priority;
- mcde_color_key_ctrl color_key;
- mcde_pal_ctrl pal_control;
- mcde_col_conv_ctrl col_ctrl;
- mcde_colorconv_type convert_format;
- mcde_overlay_ctrl ovr_state;
-
- unsigned short ovr_ypos;
- unsigned short ovr_xpos;
-
- mcde_ovr_alpha_enable alpha;
- unsigned char alpha_value;
- unsigned char pixoff;
- mcde_ovr_opq_ctrl ovr_opaq;
- mcde_blend_ctrl ovr_blend;
- unsigned long watermark_level;
- unsigned char ovr_zlevel;
-
- mcde_ovr_clip_enable clip;
- unsigned long ytlcoor;
- unsigned long xtlcoor;
- unsigned long ybrcoor;
- unsigned long xbrcoor;
-
- unsigned long xwidth;
- unsigned long yheight;
- char bpp; /** input source bits per pixel */
-
-};
-/**
- * struct mcde_blend_control - channel configuration structure
- * @chconfig: channel config structure
- * @out_synch_interface: out sync interface
- * @ch_synch_src: channel sync source
- * @sw_trig: software trigger param
- * @swint_vcnt: int count param
- * @swint_vevent: event count param
- * @chbckgrndcolor: channel background color
- * @ch_priority: channel priority
- * @control1: channel control structure
- *
- *
- **/
-struct mcde_ch_conf
-{
- struct mcde_chconfig chconfig;
- mcde_synchro_out_interface out_synch_interface;
- mcde_synchro_source ch_synch_src;
- mcde_sw_trigger sw_trig;
- unsigned short swint_vcnt;
- mcde_frame_events swint_vevent;
- unsigned short hwreq_vcnt;
- mcde_frame_events hwreq_vevent;
- struct mcde_ch_bckgrnd_col chbckgrndcolor;
- unsigned char ch_priority;
- struct mcde_chx_control1 control1;
-};
-/**
- * struct mcde_blend_control - color keying configuration structure
- * @key_ctrl: color key control
- * @color_key_type: color key type
- * @color_key: channel color key structure
- *
- *
- **/
-struct mcde_channel_color_key
-{
- mcde_key_ctrl key_ctrl;
- mcde_colorkey_type color_key_type;
- struct mcde_chx_color_key color_key;
-};
-/**
- * struct mcde_conf_color_conv - color conversion configuration structure
- * @convert_format: convert format type
- * @col_ctrl: color conversion control
- *
- *
- **/
-struct mcde_conf_color_conv
-{
- mcde_colorconv_type convert_format;
- mcde_col_conv_ctrl col_ctrl;
-};
-/**
- * struct mcde_blend_control - blend control configuration structure
- * @blenden: blend enable
- * @blend_ctrl: blend control
- * @alpha_blend: alpha blend
- * @ovr1_id: overlay1 ID
- * @ovr2_id: overlay2 ID
- * @ovr2_enable: overlay2 enable
- * @ovr1_blend_ctrl: overlay1 blend control structure
- * @ovr2_blend_ctrl: overlay2 blend control structure
- *
- *
- **/
-struct mcde_blend_control
-{
- char blenden;
- char blend_ctrl;
- char alpha_blend;
- char ovr1_id;
- char ovr2_id;
- char ovr2_enable;
- struct mcde_ovr_blend_ctrl ovr1_blend_ctrl;
- struct mcde_ovr_blend_ctrl ovr2_blend_ctrl;
-
-};
-/**
- * struct mcde_chnl_lcd_ctrl - LCD control structure
- * @lcd_ctrl_reg: lcd control reg structure
- * @lcd_horizontal_timing: lcd horizontal timing structure
- * @lcd_vertical_timing: lcd vertical timing structure
- *
- *
- **/
-struct mcde_chnl_lcd_ctrl
-{
- struct mcde_chnl_lcd_ctrl_reg lcd_ctrl_reg;
- struct mcde_chnl_lcd_horizontal_timing lcd_horizontal_timing;
- struct mcde_chnl_lcd_vertical_timing lcd_vertical_timing;
-
-};
-/**
- * struct mcde_ext_conf - External source configuration structure
- * @ovr_pxlorder: overlay pixel order
- * @endianity: byte endianity
- * @rgb_format: format type
- * @bpp: input bpp
- * @provr_id: overlay id
- * @buf_num: number of buffers used
- * @buf_id: buffer id to be used
- *
- *
- **/
-struct mcde_ext_conf
-{
- mcde_pixel_order_in_byte ovr_pxlorder;
- mcde_byte_endianity endianity;
- mcde_rgb_format_sel rgb_format;
- mcde_bpp_ctrl bpp;
- mcde_overlay_id provr_id;
- mcde_num_buffer_used buf_num;
- mcde_buffer_id buf_id;
-};
-/**
- * struct mcde_dithering_ctrl_conf - Structure of dithering configuration
- * @dithering_ctrl: dithering control
- * @input_bpp: input bpp
- * @output_bpp: output bpp
- * @mcde_chx_dither_ctrl: structure of dithering control
- * @mcde_chx_dithering_offset: structure of the dithering offset
- *
- *
- **/
-struct mcde_dithering_ctrl_conf
-{
- mcde_dithering_ctrl dithering_ctrl;
- mcde_bpp_ctrl input_bpp;
- mcde_out_bpp output_bpp;
- struct mcde_chx_dither_ctrl mcde_chx_dither_ctrl;
- struct mcde_chx_dithering_offset mcde_chx_dithering_offset;
-};
-#endif
diff --git a/arch/arm/mach-ux500/include/mach/mcde_reg.h b/arch/arm/mach-ux500/include/mach/mcde_reg.h
deleted file mode 100755
index 7b379cd962c..00000000000
--- a/arch/arm/mach-ux500/include/mach/mcde_reg.h
+++ /dev/null
@@ -1,787 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * License terms:
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#ifndef _MCDEREG_H_
-#define _MCDEREG_H_
-
-#include <linux/types.h>
-#include <mach/bit_mask.h>
-
-/*******************************************************************
- MCDE Control Register Fields
-********************************************************************/
-#define MCDE_DISABLE 0x00000000
-#define MCDE_ENABLE 0x80000000
-#define MCDE_SET_BIT 0x1
-#define MCDE_CLEAR_BIT 0x0
-#define MCDE_CTRL_MCDEEN_MASK MASK_BIT31
-#define MCDE_CTRL_MCDEEN_SHIFT 31
-#define MCDE_CTRL_FABMUX_MASK MASK_BIT17
-#define MCDE_CTRL_FABMUX_SHIFT 17
-#define MCDE_CTRL_F01MUX_MASK MASK_BIT16
-#define MCDE_CTRL_F01MUX_SHIFT 16
-#define MCDE_CTRL_IFIFICTRL_MASK MASK_BIT15
-#define MCDE_CTRL_IFIFICTRL_SHIFT 15
-#define MCDE_CTRL_DPIA_EN_MASK MASK_BIT9
-#define MCDE_CTRL_DPIA_EN_SHIFT 9
-#define MCDE_CTRL_DPIB_EN_MASK MASK_BIT8
-#define MCDE_CTRL_DPIB_EN_SHIFT 8
-#define MCDE_CTRL_DBIC0_EN_MASK MASK_BIT7
-#define MCDE_CTRL_DBIC0_EN_SHIFT 7
-#define MCDE_CTRL_DBIC1_EN_MASK MASK_BIT6
-#define MCDE_CTRL_DBIC1_EN_SHIFT 6
-#define MCDE_DSIVID0_EN_MASK MASK_BIT5
-#define MCDE_DSIVID1_EN_MASK MASK_BIT4
-#define MCDE_DSIVID2_EN_MASK MASK_BIT3
-#define MCDE_DSICMD0_EN_MASK MASK_BIT2
-#define MCDE_DSICMD1_EN_MASK MASK_BIT1
-#define MCDE_DSICMD2_EN_MASK MASK_BIT0
-#define MCDE_DSIVID0_EN_SHIFT 5
-#define MCDE_DSIVID1_EN_SHIFT 4
-#define MCDE_DSIVID2_EN_SHIFT 3
-#define MCDE_DSICMD0_EN_SHIFT 2
-#define MCDE_DSICMD1_EN_SHIFT 1
-#define MCDE_SYNCMUX_MASK 0xFF
-#define MCDE_TVA_DPIC0_LCDB_MASK 0x06
-#define MCDE_TVB_DPIC1_LCDA_MASK 0xD4
-#define MCDE_DPIC1_LCDA_MASK 0xF8
-#define MCDE_DPIC0_LCDB_MASK 0x07
-#define MCDE_LCDA_LCDB_MASK 0x00
-#define MCDE_DSI_MASK 0x01
-#define MCDE_OVR_ALPHAPMEN_SHIFT 6
-#define MCDE_OVR_CLIPEN_SHIFT 7
-
-#define MCDE_CFG_OUTMUX4_MASK (MASK_BIT28 | MASK_BIT29 | MASK_BIT30)
-#define MCDE_CFG_OUTMUX3_MASK (MASK_BIT25 | MASK_BIT26 | MASK_BIT27)
-#define MCDE_CFG_OUTMUX2_MASK (MASK_BIT22 | MASK_BIT23 | MASK_BIT24)
-#define MCDE_CFG_OUTMUX1_MASK (MASK_BIT19 | MASK_BIT20 | MASK_BIT21)
-#define MCDE_CFG_OUTMUX0_MASK (MASK_BIT16 | MASK_BIT17 | MASK_BIT18)
-#define MCDE_CFG_IFIFOCTRLWTRMRKLVL_MASK (MASK_BIT12 | MASK_BIT13 | MASK_BIT14)
-#define MCDE_CFG_FSYNCTRLB_MASK MASK_BIT11
-#define MCDE_CFG_FSYNCTRLA_MASK MASK_BIT10
-#define MCDE_CFG_SWAP_B_C1_MASK MASK_BIT9
-#define MCDE_CFG_SWAP_A_C0_MASK MASK_BIT8
-#define MCDE_CFG_SYNCMUX7_MASK MASK_BIT7
-#define MCDE_CFG_SYNCMUX6_MASK MASK_BIT6
-#define MCDE_CFG_SYNCMUX5_MASK MASK_BIT5
-#define MCDE_CFG_SYNCMUX4_MASK MASK_BIT4
-#define MCDE_CFG_SYNCMUX3_MASK MASK_BIT3
-#define MCDE_CFG_SYNCMUX2_MASK MASK_BIT2
-#define MCDE_CFG_SYNCMUX1_MASK MASK_BIT1
-#define MCDE_CFG_SYNCMUX0_MASK MASK_BIT0
-
-#define MCDE_CFG_OUTMUX4_SHIFT 28
-#define MCDE_CFG_OUTMUX3_SHIFT 25
-#define MCDE_CFG_OUTMUX2_SHIFT 22
-#define MCDE_CFG_OUTMUX1_SHIFT 19
-#define MCDE_CFG_OUTMUX0_SHIFT 16
-#define MCDE_CFG_IFIFOCTRLWTRMRKLVL_SHIFT 12
-#define MCDE_CFG_FSYNCTRLB_SHIFT 11
-#define MCDE_CFG_FSYNCTRLA_SHIFT 10
-#define MCDE_CFG_SWAP_B_C1_SHIFT 9
-#define MCDE_CFG_SWAP_A_C0_SHIFT 8
-#define MCDE_CFG_SYNCMUX7_SHIFT 7
-#define MCDE_CFG_SYNCMUX6_SHIFT 6
-#define MCDE_CFG_SYNCMUX5_SHIFT 5
-#define MCDE_CFG_SYNCMUX4_SHIFT 4
-#define MCDE_CFG_SYNCMUX3_SHIFT 3
-#define MCDE_CFG_SYNCMUX2_SHIFT 2
-#define MCDE_CFG_SYNCMUX1_SHIFT 1
-#define MCDE_CFG_SYNCMUX0_SHIFT 0
-
-
-/*******************************************************************
- MCDE External Source Register Fields
-********************************************************************/
-#define MCDE_EXT_BUFFER_MASK /*(MASK_HALFWORD1 | MASK_BYTE1 | MASK_QUARTET1 | MASK_BIT3)*/0xFFFFFFFF
-#define MCDE_EXT_PRI_OVR_MASK MASK_QUARTET1
-#define MCDE_EXT_BUFFER_NUM_MASK (MASK_BIT2 | MASK_BIT3)
-#define MCDE_EXT_BUFFER_ID_MASK (MASK_BIT0 | MASK_BIT1)
-#define MCDE_EXT_FORCEFSDIV_MASK MASK_BIT4
-#define MCDE_EXT_FSDISABLE_MASK MASK_BIT3
-#define MCDE_EXT_OVR_CTRL_MASK MASK_BIT2
-#define MCDE_EXT_BUF_MODE_MASK (MASK_BIT0 | MASK_BIT1)
-#define MCDE_EXT_BEPO_MASK MASK_BIT14
-#define MCDE_EXT_BEBO_MASK MASK_BIT13
-#define MCDE_EXT_BGR_MASK MASK_BIT12
-#define MCDE_EXT_BPP_MASK (MASK_BIT11 | MASK_BIT10 | MASK_BIT9 | MASK_BIT8)
-
-
-#define MCDE_EXT_BUFFER_SHIFT 0
-#define MCDE_EXT_PRI_OVR_SHIFT SHIFT_QUARTET1
-#define MCDE_EXT_BUFFER_NUM_SHIFT 2
-#define MCDE_EXT_OVR_CTRL_SHIFT 2
-#define MCDE_EXT_FORCEFSDIV_SHIFT 4
-#define MCDE_EXT_FSDISABLE_SHIFT 3
-#define MCDE_EXT_BEPO_SHIFT 14
-#define MCDE_EXT_BEBO_SHIFT 13
-#define MCDE_EXT_BGR_SHIFT 12
-#define MCDE_EXT_BPP_SHIFT 8
-/*******************************************************************
- MCDE Overlay Register Fields
-********************************************************************/
-#define MCDE_OVR_OVLEN_MASK MASK_BIT0
-#define MCDE_OVR_COLCTRL_MASK (MASK_BIT1 | MASK_BIT2)
-#define MCDE_OVR_PALCTRL_MASK (MASK_BIT3 | MASK_BIT4)
-#define MCDE_OVR_CKEYEN_MASK (MASK_BIT5)
-#define MCDE_OVR_STBPRIO_MASK MASK_QUARTET4
-#define MCDE_OVR_BURSTSZ_MASK MASK_QUARTET5
-#define MCDE_OVR_MAXREQ_MASK MASK_QUARTET6
-#define MCDE_OVR_ROTBURSTSIZE_MASK MASK_QUARTET7
-#define MCDE_OVR_BLEND_MASK MASK_BIT0
-#define MCDE_OVR_OPQ_MASK MASK_BIT9
-#define MCDE_OVR_INTERMDE_MASK MASK_BIT29
-#define MCDE_OVR_INTERON_MASK MASK_BIT28
-#define MCDE_OVR_ALPHAPMEN_MASK MASK_BIT6
-#define MCDE_OVR_CLIPEN_MASK MASK_BIT7
-#define MCDE_OVR_LPF_MASK (MASK_BYTE2 | MASK_BIT24 |MASK_BIT25 | MASK_BIT26)
-#define MCDE_OVR_PPL_MASK (MASK_BYTE0 | MASK_BIT8 |MASK_BIT9 |MASK_BIT10)
-#define MCDE_ALPHAVALUE_MASK (MASK_BYTE0 << 1)
-/**#define MCDE_EXT_SRCID_MASK (MASK_BIT9 | MASK_BIT8 | MASK_BIT7 | MASK_BIT6)*/
-#define MCDE_EXT_SRCID_MASK (MASK_BIT14 | MASK_BIT13 | MASK_BIT12 | MASK_BIT11)
-#define MCDE_PIXOFF_MASK (MASK_BIT10 | MASK_BIT11 |MASK_QUARTET3)
-#define MCDE_OVR_ZLEVEL_MASK (MASK_BIT30 | MASK_BIT27 | MASK_BIT28 | MASK_BIT29)
-#define MCDE_OVR_YPOS_MASK (MASK_BYTE2 | MASK_BIT24 | MASK_BIT25 | MASK_BIT26)
-#define MCDE_OVR_CHID_MASK (MASK_BIT14 | MASK_BIT13 | MASK_BIT12 | MASK_BIT11)
-#define MCDE_OVR_XPOS_MASK (MASK_BYTE0 | MASK_BIT8 |MASK_BIT9 |MASK_BIT10)
-#define MCDE_OVR_READ_MASK MASK_BIT9
-#define MCDE_OVR_FETCH_MASK MASK_BIT8
-#define MCDE_OVR_BLOCKED_MASK MASK_BIT10
-//#define MCDE_OVR_READ_MASK MASK_BIT1
-//#define MCDE_OVR_FETCH_MASK MASK_BIT0
-#define MCDE_WATERMARK_MASK (MASK_BYTE2 | MASK_QUARTET6 | MASK_BIT28)
-#define MCDE_LINEINCREMENT_MASK 0xFFFFFFFF
-#define MCDE_YCLIP_MASK 0xFFFFFFFF
-#define MCDE_XCLIP_MASK 0xFFFFFFFF
-#define MCDE_XBRCOOR_MASK 0x7FF
-#define MCDE_YBRCOOR_MASK 0x07FF0000
-
-#define MCDE_OVR_COLCTRL_SHIFT 1
-#define MCDE_OVR_PALCTRL_SHIFT 3
-#define MCDE_OVR_CKEYEN_SHIFT 5
-#define MCDE_OVR_STBPRIO_SHIFT SHIFT_QUARTET4
-#define MCDE_OVR_BURSTSZ_SHIFT SHIFT_QUARTET5
-#define MCDE_OVR_MAXREQ_SHIFT SHIFT_QUARTET6
-#define MCDE_OVR_ROTBURSTSIZE_SHIFT SHIFT_QUARTET7
-#define MCDE_OVR_OPQ_SHIFT 9
-#define MCDE_OVR_INTERMDE_SHIFT 29
-#define MCDE_OVR_INTERON_SHIFT 28
-#define MCDE_OVR_LPF_SHIFT SHIFT_HALFWORD1
-#define MCDE_ALPHAVALUE_SHIFT 1
-//#define MCDE_EXT_SRCID_SHIFT 6
-#define MCDE_EXT_SRCID_SHIFT 11
-#define MCDE_OVR_ZLEVEL_SHIFT 27
-#define MCDE_OVR_YPOS_SHIFT SHIFT_HALFWORD1
-#define MCDE_OVR_CHID_SHIFT 11
-#define MCDE_OVR_READ_SHIFT 1
-#define MCDE_WATERMARK_SHIFT SHIFT_HALFWORD1
-#define MCDE_PIXOFF_SHIFT 10
-#define MCDE_LINEINCREMENT_SHIFT 0
-#define MCDE_YCLIP_SHIFT 0
-#define MCDE_XCLIP_SHIFT 0
-#define MCDE_YBRCOOR_SHIFT 16
-
-/*******************************************************************
- MCDE Channel Configuration Register Fields
-********************************************************************/
-#define MCDE_INITDELAY_MASK MASK_HALFWORD1
-#define MCDE_PPDELAY_MASK MASK_HALFWORD0
-#define MCDE_SWINTVCNT_MASK (MASK_BYTE3 | MASK_QUARTET5 | MASK_BIT18 |MASK_BIT19)
-#define MCDE_SWINTVEVENT_MASK (MASK_BIT16 | MASK_BIT17)
-#define MCDE_HWREQVCNT_MASK (MASK_BYTE1 | MASK_QUARTET1 | MASK_BIT3 | MASK_BIT2)
-#define MCDE_HWREQVEVENT_MASK (MASK_BIT0 | MASK_BIT1)
-#define MCDE_OUTINTERFACE_MASK (MASK_BIT4 | MASK_BIT3 |MASK_BIT2)
-#define MCDE_SRCSYNCH_MASK (MASK_BIT0 | MASK_BIT1)
-#define MCDE_SW_TRIG_MASK MASK_BIT0
-#define MCDE_REDCOLOR_MASK MASK_BYTE2
-#define MCDE_GREENCOLOR_MASK MASK_BYTE1
-#define MCDE_BLUECOLOR_MASK MASK_BYTE0
-#define MCDE_CHPRIORITY_MASK MASK_QUARTET0
-#define MCDE_CHXLPF_MASK (0x03FF0000)
-#define MCDE_CHXPPL_MASK (MASK_BYTE0 | MASK_BIT8 |MASK_BIT9 |MASK_BIT10)
-#define MCDE_CHX_ABORT_MASK MASK_BIT1
-#define MCDE_CHX_READ_MASK MASK_BIT0
-
-#define MCDE_INITDELAY_SHIFT SHIFT_HALFWORD1
-#define MCDE_SWINTVCNT_SHIFT 18
-#define MCDE_SWINTVEVENT_SHIFT SHIFT_HALFWORD1
-#define MCDE_HWREQVCNT_SHIFT 2
-#define MCDE_OUTINTERFACE_SHIFT 2
-#define MCDE_REDCOLOR_SHIFT SHIFT_HALFWORD1
-#define MCDE_GREENCOLOR_SHIFT SHIFT_BYTE1
-#define MCDE_CHPRIORITY_SHIFT SHIFT_QUARTET7
-#define MCDE_CHXLPF_SHIFT 16
-#define MCDE_CHX_ABORT_SHIFT 1
-
-/*******************************************************************
- MCDE Channel A/B Register Fields
-********************************************************************/
-#define MCDE_CHX_BURSTSIZE_MASK (MASK_QUARTET6 & 0x07000000)
-#define MCDE_CHX_ALPHA_MASK (MASK_BYTE2)
-#define MCDE_CHX_ROTDIR_MASK (MASK_BIT15)
-#define MCDE_CHX_GAMAEN_MASK (MASK_BIT14)
-#define MCDE_FLICKFORMAT_MASK (MASK_BIT13)
-#define MCDE_FLICKMODE_MASK (MASK_BIT11 | MASK_BIT12)
-#define MCDE_BLENDCONTROL_MASK (MASK_BIT10)
-#define MCDE_KEYCTRL_MASK (MASK_BIT7|MASK_BIT8|MASK_BIT9)
-#define MCDE_ROTEN_MASK (MASK_BIT6)
-#define MCDE_DITHEN_MASK (MASK_BIT5)
-#define MCDE_CEAEN_MASK (MASK_BIT4)
-#define MCDE_AFLICKEN_MASK (MASK_BIT3)
-#define MCDE_BLENDEN_MASK (MASK_BIT2)
-#define MCDE_CLK_MASK (MASK_BIT30)
-#define MCDE_BCD_MASK (MASK_BIT29)
-#define MCDE_OUTBPP_MASK (MASK_BIT25 |MASK_BIT26 | MASK_BIT27 | MASK_BIT28)
-#define MCDE_CDWIN_MASK (MASK_BIT13 | MASK_BIT14 | MASK_BIT15)
-#define MCDE_CLOCKSEL_MASK (MASK_BIT12 | MASK_BIT11 | MASK_BIT10)
-#define MCDE_PCD_MASK (MASK_BYTE0 | MASK_BIT8 | MASK_BIT9)
-#define MCDE_KEYA_MASK (MASK_BYTE3)
-#define MCDE_KEYR_MASK (MASK_BYTE2)
-#define MCDE_KEYG_MASK (MASK_BYTE1)
-#define MCDE_KEYB_MASK (MASK_BYTE0)
-#define MCDE_RGB_MASK1 (MASK_BYTE2 | MASK_BIT24 | MASK_BIT25)
-#define MCDE_RGB_MASK2 (MASK_BYTE0 | MASK_BIT8 | MASK_BIT9)
-#define MCDE_THRESHOLD_MASK (MASK_QUARTET6)
-#define MCDE_COEFFN3_MASK (MASK_BYTE2)
-#define MCDE_COEFFN2_MASK (MASK_BYTE1)
-#define MCDE_COEFFN1_MASK (MASK_BYTE0)
-#define MCDE_TV_LINES_MASK (MASK_BYTE2 | MASK_BIT24 | MASK_BIT25 | MASK_BIT26)
-#define MCDE_TVMODE_MASK (MASK_BIT3 | MASK_BIT4)
-#define MCDE_IFIELD_MASK (MASK_BIT2)
-#define MCDE_INTEREN_MASK (MASK_BIT1)
-#define MCDE_SELMODE_MASK (MASK_BIT0)
-#define MCDE_BSL_MASK (MASK_BYTE2 | MASK_BIT24 | MASK_BIT25 | MASK_BIT26)
-#define MCDE_BEL_MASK (MASK_BYTE0 | MASK_BIT8 | MASK_BIT9 | MASK_BIT10)
-#define MCDE_FSL2_MASK (MASK_BYTE2 | MASK_BIT24 | MASK_BIT25 | MASK_BIT26)
-#define MCDE_FSL1_MASK (MASK_BYTE0 | MASK_BIT8 | MASK_BIT9 | MASK_BIT10)
-#define MCDE_DVO2_MASK (MASK_BYTE2 | MASK_BIT24 | MASK_BIT25 | MASK_BIT26)
-#define MCDE_DVO1_MASK (MASK_BYTE0 | MASK_BIT8 | MASK_BIT9 | MASK_BIT10)
-#define MCDE_SWH2_MASK (MASK_BYTE2 | MASK_BIT24 | MASK_BIT25 | MASK_BIT26)
-#define MCDE_SWH1_MASK (MASK_BYTE0 | MASK_BIT8 | MASK_BIT9 | MASK_BIT10)
-#define MCDE_SWW_MASK (MASK_BYTE2 | MASK_BIT24 | MASK_BIT25 | MASK_BIT26)
-#define MCDE_DHO_MASK (MASK_BYTE0 | MASK_BIT8 | MASK_BIT9 | MASK_BIT10)
-#define MCDE_ALW_MASK (MASK_BYTE2 | MASK_BIT24 | MASK_BIT25 | MASK_BIT26)
-#define MCDE_LBW_MASK (MASK_BYTE0 | MASK_BIT8 | MASK_BIT9 | MASK_BIT10)
-#define MCDE_TVBCR_MASK MASK_BYTE2
-#define MCDE_TVBCB_MASK MASK_BYTE1
-#define MCDE_TVBLU_MASK MASK_BYTE0
-#define MCDE_REVVAEN_MASK MASK_BIT31
-#define MCDE_REVTGEN_MASK MASK_BIT30
-#define MCDE_REVLOADSEL_MASK (MASK_BIT28 | MASK_BIT29)
-#define MCDE_REVDEL1_MASK (MASK_QUARTET6)
-#define MCDE_REVDEL0_MASK (MASK_BYTE2)
-#define MCDE_PSVAEN_MASK (MASK_BIT15)
-#define MCDE_PSTGEN_MASK (MASK_BIT14)
-#define MCDE_PSLOADSEL_MASK (MASK_BIT12 | MASK_BIT13)
-#define MCDE_PSDEL1_MASK (MASK_QUARTET2)
-#define MCDE_PSDEL0_MASK (MASK_BYTE0)
-#define MCDE_IOE_MASK (MASK_BIT23)
-#define MCDE_IPC_MASK (MASK_BIT22)
-#define MCDE_IHS_MASK (MASK_BIT21)
-#define MCDE_IVS_MASK (MASK_BIT20)
-#define MCDE_IVP_MASK (MASK_BIT19)
-#define MCDE_ICLSPL_MASK (MASK_BIT18)
-#define MCDE_ICLREV_MASK (MASK_BIT17)
-#define MCDE_ICLSP_MASK (MASK_BIT16)
-#define MCDE_SPLVAEN_MASK (MASK_BIT15)
-#define MCDE_SPLTGEN_MASK (MASK_BIT14)
-#define MCDE_SPLLOADSEL_MASK (MASK_BIT12 | MASK_BIT13)
-#define MCDE_SPLDEL1_MASK (MASK_QUARTET2)
-#define MCDE_SPLDEL0_MASK (MASK_BYTE0)
-#define MCDE_FOFFY_MASK (MASK_BIT14 | MASK_BIT13 | MASK_BIT12 | MASK_BIT11 | MASK_BIT10)
-#define MCDE_FOFFX_MASK (MASK_BIT5 | MASK_BIT6 | MASK_BIT7 | MASK_BIT8 | MASK_BIT9)
-#define MCDE_MASK_BITCTRL_MASK (MASK_BIT4)
-#define MCDE_MODE_MASK (MASK_BIT2 | MASK_BIT3)
-#define MCDE_COMP_MASK (MASK_BIT1)
-#define MCDE_TEMP_MASK (MASK_BIT0)
-#define MCDE_YB_MASK (MASK_BIT28 | MASK_BIT27 | MASK_BIT26 | MASK_BIT25 | MASK_BIT24)
-#define MCDE_XB_MASK (MASK_BIT20 | MASK_BIT19 | MASK_BIT18 | MASK_BIT17 | MASK_BIT16)
-#define MCDE_YG_MASK (MASK_BIT12 | MASK_BIT11 | MASK_BIT10 | MASK_BIT9 | MASK_BIT8 | MASK_BIT7 | MASK_BIT6 | MASK_BIT5)
-#define MCDE_XG_MASK (MASK_BIT0 | MASK_BIT1 | MASK_BIT2 | MASK_BIT3 | MASK_BIT4)
-#define MCDE_ARED_MASK (MASK_BYTE2 | MASK_BIT24 | MASK_BIT25)
-#define MCDE_GREEN_MASK (MASK_BYTE1)
-#define MCDE_BLUE_MASK (MASK_BYTE0)
-#define MCDE_RED_MASK (MASK_BYTE2)
-
-#define MCDE_CHX_BURSTSIZE_SHIFT SHIFT_QUARTET6
-#define MCDE_CHX_ALPHA_SHIFT SHIFT_HALFWORD1
-#define MCDE_CHX_ROTDIR_SHIFT 15
-#define MCDE_CHX_GAMAEN_SHIFT 14
-#define MCDE_FLICKFORMAT_SHIFT 13
-#define MCDE_FLICKMODE_SHIFT 11
-#define MCDE_BLENDCONTROL_SHIFT 10
-#define MCDE_KEYCTRL_SHIFT 7
-#define MCDE_ROTEN_SHIFT 6
-#define MCDE_DITHEN_SHIFT 5
-#define MCDE_CEAEN_SHIFT 4
-#define MCDE_AFLICKEN_SHIFT 3
-#define MCDE_BLENDEN_SHIFT 2
-#define MCDE_CLK_SHIFT 30
-#define MCDE_BCD_SHIFT 29
-#define MCDE_OUTBPP_SHIFT 25
-#define MCDE_CDWIN_SHIFT 13
-#define MCDE_CLOCKSEL_SHIFT 10
-#define MCDE_KEYA_SHIFT SHIFT_BYTE3
-#define MCDE_KEYR_SHIFT SHIFT_BYTE2
-#define MCDE_KEYG_SHIFT SHIFT_BYTE1
-#define MCDE_RGB_SHIFT SHIFT_HALFWORD1
-#define MCDE_THRESHOLD_SHIFT SHIFT_QUARTET6
-#define MCDE_COEFFN3_SHIFT SHIFT_BYTE2
-#define MCDE_COEFFN2_SHIFT SHIFT_BYTE1
-#define MCDE_COEFFN1_SHIFT (SHIFT_BYTE0)
-#define MCDE_TV_LINES_SHIFT SHIFT_HALFWORD1
-#define MCDE_TVMODE_SHIFT 3
-#define MCDE_IFIELD_SHIFT 2
-#define MCDE_INTEREN_SHIFT 1
-#define MCDE_BSL_SHIFT 16
-#define MCDE_FSL2_SHIFT 16
-#define MCDE_DVO2_SHIFT 16
-#define MCDE_SWW_SHIFT 16
-#define MCDE_ALW_SHIFT 16
-#define MCDE_TVBCR_SHIFT SHIFT_BYTE2
-#define MCDE_TVBCB_SHIFT SHIFT_BYTE1
-#define MCDE_REVVAEN_SHIFT 31
-#define MCDE_REVTGEN_SHIFT 30
-#define MCDE_REVLOADSEL_SHIFT 28
-#define MCDE_REVDEL1_SHIFT SHIFT_QUARTET6
-#define MCDE_REVDEL0_SHIFT SHIFT_HALFWORD1
-#define MCDE_PSVAEN_SHIFT 15
-#define MCDE_PSTGEN_SHIFT 14
-#define MCDE_PSLOADSEL_SHIFT 12
-#define MCDE_PSDEL1_SHIFT 8
-#define MCDE_IOE_SHIFT 23
-#define MCDE_IPC_SHIFT 22
-#define MCDE_IHS_SHIFT 21
-#define MCDE_IVS_SHIFT 20
-#define MCDE_IVP_SHIFT 19
-#define MCDE_ICLSPL_SHIFT 18
-#define MCDE_ICLREV_SHIFT 17
-#define MCDE_ICLSP_SHIFT 16
-#define MCDE_SPLVAEN_SHIFT 15
-#define MCDE_SPLTGEN_SHIFT 14
-#define MCDE_SPLLOADSEL_SHIFT 12
-#define MCDE_SPLDEL1_SHIFT 8
-#define MCDE_FOFFY_SHIFT 10
-#define MCDE_FOFFX_SHIFT 5
-#define MCDE_MASK_BITCTRL_SHIFT 4
-#define MCDE_MODE_SHIFT 2
-#define MCDE_COMP_SHIFT 1
-#define MCDE_YB_SHIFT 24
-#define MCDE_XB_SHIFT SHIFT_HALFWORD1
-#define MCDE_YG_SHIFT 5
-#define MCDE_ARED_SHIFT SHIFT_HALFWORD1
-#define MCDE_GREEN_SHIFT SHIFT_BYTE1
-/*******************************************************************
- MCDE Channel C Register Fields
-********************************************************************/
-#define MCDE_SYNCCTRL_MASK (MASK_BIT30 | MASK_BIT29)
-#define MCDE_RESEN_MASK (MASK_BIT18)
-#define MCDE_CLKSEL_MASK (MASK_BIT14 | MASK_BIT13)
-#define MCDE_SYNCSEL_MASK MASK_BIT6
-#define MCDE_RES2_MASK MASK_BIT28
-#define MCDE_RES1_MASK MASK_BIT27
-#define MCDE_RD2_MASK MASK_BIT26
-#define MCDE_RD1_MASK MASK_BIT25
-#define MCDE_WR2_MASK MASK_BIT24
-#define MCDE_WR1_MASK MASK_BIT23
-#define MCDE_CD2_MASK MASK_BIT22
-#define MCDE_CD1_MASK MASK_BIT21
-#define MCDE_CS2_MASK MASK_BIT20
-#define MCDE_CS1_MASK MASK_BIT19
-#define MCDE_CS2EN_MASK MASK_BIT17
-#define MCDE_CS1EN_MASK MASK_BIT16
-#define MCDE_INBAND2_MASK MASK_BIT12
-#define MCDE_INBAND1_MASK MASK_BIT11
-#define MCDE_BUSSIZE2_MASK MASK_BIT10
-#define MCDE_BUSSIZE1_MASK MASK_BIT9
-#define MCDE_SYNCEN2_MASK MASK_BIT8
-#define MCDE_SYNCEN1_MASK MASK_BIT7
-#define MCDE_WMLVL2_MASK MASK_BIT5
-#define MCDE_WMLVL1_MASK MASK_BIT4
-#define MCDE_C2EN_MASK MASK_BIT3
-#define MCDE_C1EN_MASK MASK_BIT2
-#define MCDE_POWEREN_MASK MASK_BIT1
-#define MCDE_FLOEN_MASK MASK_BIT0
-#define MCDE_PDCTRL_MASK (MASK_BIT10 |MASK_BIT11 | MASK_BIT12)
-#define MCDE_DUPLEXER_MASK (MASK_BIT7 |MASK_BIT8 | MASK_BIT9)
-#define MCDE_BSDM_MASK (MASK_BIT6 | MASK_BIT5 | MASK_BIT4)
-#define MCDE_BSCM_MASK (MASK_BIT2 | MASK_BIT1 | MASK_BIT0)
-#define MCDE_VSDBL_MASK (MASK_BIT29 | MASK_BIT30 | MASK_BIT31)
-#define MCDE_VSSEL_MASK MASK_BIT28
-#define MCDE_VSPOL_MASK MASK_BIT27
-#define MCDE_VSPDIV_MASK (MASK_BIT24 | MASK_BIT25 | MASK_BIT26)
-#define MCDE_VSPMAX_MASK (MASK_BYTE2 | MASK_QUARTET3)
-#define MCDE_VSPMIN_MASK (MASK_BYTE0 | MASK_QUARTET2)
-#define MCDE_TRDELC_MASK (MASK_BYTE2 | MASK_QUARTET6)
-#define MCDE_SYNCDELC1_MASK (MASK_BYTE1)
-#define MCDE_SYNCDELC0_MASK (MASK_BYTE0)
-#define MCDE_VSTAC1_MASK MASK_BIT1
-#define MCDE_VSTAC0_MASK MASK_BIT0
-#define MCDE_BCN_MASK MASK_BYTE0
-#define MCDE_CSCDDEACT_MASK MASK_BYTE1
-#define MCDE_CSCDACT_MASK MASK_BYTE0
-#define MCDE_MOTINT_MASK MASK_BIT16
-#define MCDE_RWDEACT_MASK MASK_BYTE1
-#define MCDE_RWACT_MASK MASK_BYTE0
-#define MCDE_DODEACT_MASK MASK_BYTE1
-#define MCDE_DOACT_MASK MASK_BYTE0
-#define MCDE_READDATA_MASK MASK_HALFWORD0
-#define MCDE_DATACOMMANDMASK 0x01FFFFFF
-
-#define MCDE_SYNCCTRL_SHIFT 29
-#define MCDE_RESEN_SHIFT 18
-#define MCDE_CLKSEL_SHIFT 13
-#define MCDE_SYNCSEL_SHIFT 6
-#define MCDE_RES2_SHIFT 28
-#define MCDE_RES1_SHIFT 27
-#define MCDE_RD2_SHIFT 26
-#define MCDE_RD1_SHIFT 25
-#define MCDE_WR2_SHIFT 24
-#define MCDE_WR1_SHIFT 23
-#define MCDE_CD2_SHIFT 22
-#define MCDE_CD1_SHIFT 21
-#define MCDE_CS2_SHIFT 20
-#define MCDE_CS1_SHIFT 19
-#define MCDE_CS2EN_SHIFT 17
-#define MCDE_CS1EN_SHIFT 16
-#define MCDE_INBAND2_SHIFT 12
-#define MCDE_INBAND1_SHIFT 11
-#define MCDE_BUSSIZE2_SHIFT 10
-#define MCDE_BUSSIZE1_SHIFT 9
-#define MCDE_SYNCEN2_SHIFT 8
-#define MCDE_SYNCEN1_SHIFT 7
-#define MCDE_WMLVL2_SHIFT 5
-#define MCDE_WMLVL1_SHIFT 4
-#define MCDE_C2EN_SHIFT 3
-#define MCDE_C1EN_SHIFT 2
-#define MCDE_POWEREN_SHIFT 1
-#define MCDE_PDCTRL_SHIFT 12
-#define MCDE_DUPLEXER_SHIFT 7
-#define MCDE_BSDM_SHIFT 4
-#define MCDE_VSDBL_SHIFT 29
-#define MCDE_VSSEL_SHIFT 28
-#define MCDE_VSPOL_SHIFT 27
-#define MCDE_VSPDIV_SHIFT 24
-#define MCDE_VSPMAX_SHIFT 12
-#define MCDE_TRDELC_SHIFT SHIFT_HALFWORD1
-#define MCDE_SYNCDELC1_SHIFT SHIFT_BYTE1
-#define MCDE_VSTAC1_SHIFT 1
-#define MCDE_CSCDDEACT_SHIFT SHIFT_BYTE1
-#define MCDE_MOTINT_SHIFT SHIFT_HALFWORD1
-#define MCDE_RWDEACT_SHIFT 8
-#define MCDE_DODEACT_SHIFT SHIFT_BYTE1
-
-/*******************************************************************
- MCDE DSI Register Fields
-********************************************************************/
-#define MCDE_PLLOUT_DIVSEL1_MASK (MASK_BIT22 | MASK_BIT23)
-#define MCDE_PLLOUT_DIVSEL0_MASK (MASK_BIT20 | MASK_BIT21)
-#define MCDE_PLL4IN_SEL_MASK (MASK_BIT16 | MASK_BIT17)
-#define MCDE_TXESCDIV_SEL_MASK MASK_BIT8
-#define MCDE_TXESCDIV_MASK 0xFF
-#define MCDE_CMDBYTE_LSB_MASK 0xFF
-#define MCDE_CMDBYTE_MSB_MASK 0xFF00
-#define MCDE_DSI_SW_MASK 0xFFF0000
-#define MCDE_DSI_DMA_MASK 0xFFF
-#define MCDE_DSI_PACK_MASK (MASK_BIT20 | MASK_BIT21 | MASK_BIT22)
-#define MCDE_DSI_DCSVID_MASK MASK_BIT18
-#define MCDE_DSI_BYTE_SWAP_MASK MASK_BIT17
-#define MCDE_DSI_BIT_SWAP_MASK MASK_BIT16
-#define MCDE_DSI_CMD8_MASK MASK_BIT13
-#define MCDE_DSI_VID_MODE_MASK MASK_BIT12
-#define MCDE_BLANKING_MASK MASK_QUARTET0
-#define MCDE_DSI_FRAME_MASK (MASK_HALFWORD0 | MASK_BYTE2)
-#define MCDE_DSI_PACKET_MASK MASK_HALFWORD0
-
-#define MCDE_PLLOUT_DIVSEL1_SHIFT 22
-#define MCDE_PLLOUT_DIVSEL0_SHIFT 20
-#define MCDE_PLL4IN_SEL_SHIFT 16
-#define MCDE_TXESCDIV_SEL_SHIFT 8
-#define MCDE_CMDBYTE_MSB_SHIFT 8
-#define MCDE_DSI_SW_SHIFT 16
-#define MCDE_DSI_PACK_SHIFT 20
-#define MCDE_DSI_DCSVID_SHIFT 18
-#define MCDE_DSI_BYTE_SWAP_SHIFT 17
-#define MCDE_DSI_BIT_SWAP_SHIFT 16
-#define MCDE_DSI_CMD8_SHIFT 13
-#define MCDE_DSI_VID_MODE_SHIFT 12
-
-/*******************************************************************
- Register Structure
-********************************************************************/
-
-#ifdef CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT
-
-struct mcde_ext_src_reg
-{
- volatile u32 mcde_extsrc_a0;
- volatile u32 mcde_extsrc_a1;
- volatile u32 mcde_extsrc_a2;
- volatile u32 mcde_extsrc_conf;
- volatile u32 mcde_extsrc_cr;
- volatile u32 mcde_unused1[3];
-};
-
-struct mcde_ovl_reg
-{
- volatile u32 mcde_ovl_cr;
- volatile u32 mcde_ovl_conf;
- volatile u32 mcde_ovl_conf2;
- volatile u32 mcde_ovl_ljinc;
- volatile u32 mcde_ovl_crop;
- volatile u32 mcde_ovl_comp;
- volatile u32 mcde_unused1[2];
-};
-
-struct mcde_chnl_conf_reg
-{
- volatile u32 mcde_chnl_conf;
- volatile u32 mcde_chnl_stat;
- volatile u32 mcde_chnl_synchmod;
- volatile u32 mcde_chnl_synchsw;
- volatile u32 mcde_chnl_bckgndcol;
- volatile u32 mcde_chnl_prio;
- volatile u32 mcde_unused[2];
-};
-
-struct mcde_chAB_reg
-{
- volatile u32 mcde_cr0;
- volatile u32 mcde_cr1;
- volatile u32 mcde_colkey;
- volatile u32 mcde_fcolkey;
- volatile u32 mcde_rgbconv1;
- volatile u32 mcde_rgbconv2;
- volatile u32 mcde_rgbconv3;
- volatile u32 mcde_rgbconv4;
- volatile u32 mcde_rgbconv5;
- volatile u32 mcde_rgbconv6;
- volatile u32 mcde_ffcoef0;
- volatile u32 mcde_ffcoef1;
- volatile u32 mcde_ffcoef2;
- volatile u32 mcde_unused1[1];
- volatile u32 mcde_tvcr;
- volatile u32 mcde_tvbl1;
- volatile u32 mcde_tvisl;
- volatile u32 mcde_tvdvo;
- volatile u32 mcde_unused2[1];
- volatile u32 mcde_tvtim1;
- volatile u32 mcde_tvlbalw;
- volatile u32 mcde_tvbl2;
- volatile u32 mcde_tvblu;
- volatile u32 mcde_lcdtim0;
- volatile u32 mcde_lcdtim1;
- volatile u32 mcde_ditctrl;
- volatile u32 mcde_ditoff;
- volatile u32 mcde_pal0;
- volatile u32 mcde_pal1;
- volatile u32 mcde_rotadd0;
- volatile u32 mcde_rotadd1;
- volatile u32 mcde_rot_conf;
- volatile u32 mcde_synchconf;
- volatile u32 mcde_unused3[1];
- volatile u32 mcde_gam0;
- volatile u32 mcde_gam1;
- volatile u32 mcde_gam2;
- volatile u32 mcde_oledconv1;
- volatile u32 mcde_oledconv2;
- volatile u32 mcde_oledconv3;
- volatile u32 mcde_oledconv4;
- volatile u32 mcde_oledconv5;
- volatile u32 mcde_oledconv6;
- volatile u32 mcde_unused4[85];
-};
-
-struct mcde_chC0C1_reg
-{
- volatile u32 mcde_crc;
- volatile u32 mcde_pbccrc[2];
- volatile u32 mcde_pbcbmrc0[5];
- volatile u32 mcde_pbcbmrc1[5];
- volatile u32 mcde_pbcbcrc0[2];
- volatile u32 mcde_unused1[3];
- volatile u32 mcde_pbcbcrc1[2];
- volatile u32 mcde_unused2[3];
- volatile u32 mcde_vscrc[2];
- volatile u32 mcde_sctrc;
- volatile u32 mcde_scsrc;
- volatile u32 mcde_bcnr[2];
- volatile u32 mcde_cscdtr[2];
- volatile u32 mcde_rdwrtr[2];
- volatile u32 mcde_dotr[2];
- volatile u32 mcde_wcmdc[2];
- volatile u32 mcde_wdatadc[2];
- volatile u32 mcde_rdatadc[2];
- volatile u32 mcde_statc;
- volatile u32 mcde_ctrlc[2];
-};
-
-struct mcde_dsi_reg
-{
- volatile u32 mcde_dsi_conf0;
- volatile u32 mcde_dsi_frame;
- volatile u32 mcde_dsi_pkt;
- volatile u32 mcde_dsi_sync;
- volatile u32 mcde_dsi_cmdw;
- volatile u32 mcde_dsi_delay0;
- volatile u32 mcde_dsi_delay1;
- volatile u32 mcde_unused1[1];
-};
-
-struct mcde_top_reg
-{
- volatile u32 mcde_cr;
- volatile u32 mcde_conf0;
- volatile u32 mcde_ssp;
- volatile u32 mcde_reserved1[61];
- volatile u32 mcde_ais;
- volatile u32 mcde_imscpp;
- volatile u32 mcde_imscovl;
- volatile u32 mcde_imscchnl;
- volatile u32 mcde_imscerr;
- volatile u32 mcde_rispp;
- volatile u32 mcde_risovl;
- volatile u32 mcde_rischnl;
- volatile u32 mcde_riserr;
- volatile u32 mcde_mispp;
- volatile u32 mcde_misovl;
- volatile u32 mcde_mischnl;
- volatile u32 mcde_miserr;
- volatile u32 mcde_sispp;
- volatile u32 mcde_sisovl;
- volatile u32 mcde_sischnl;
- volatile u32 mcde_siserr;
- volatile u32 mcde_reserved2[46];
- volatile u32 mcde_pid;
-};
-
-#else /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */
-
-struct mcde_ext_src_reg
-{
- volatile u32 mcde_extsrc_a0;
- volatile u32 mcde_extsrc_a1;
- volatile u32 mcde_extsrc_a2;
- volatile u32 mcde_extsrc_conf;
- volatile u32 mcde_extsrc_cr;
- volatile u32 mcde_unused1[3];
-};
-
-struct mcde_ovl_reg
-{
- volatile u32 mcde_ovl_cr;
- volatile u32 mcde_ovl_conf;
- volatile u32 mcde_ovl_conf2;
- volatile u32 mcde_ovl_ljinc;
- volatile u32 mcde_ovl_crop;
- volatile u32 mcde_ovl_top_left_clip;
- volatile u32 mcde_ovl_bot_rht_clip;
- volatile u32 mcde_ovl_comp;
-};
-
-struct mcde_ch_synch_reg
-{
- volatile u32 mcde_ch_conf;
- volatile u32 mcde_ch_stat;
- volatile u32 mcde_chsyn_mod;
- volatile u32 mcde_chsyn_sw;
- volatile u32 mcde_chsyn_bck;
- volatile u32 mcde_chsyn_prio;
- volatile u32 mcde_unused3[2];
-};
-
-struct mcde_ch_reg
-{
- volatile u32 mcde_ch_cr0;
- volatile u32 mcde_ch_cr1;
- volatile u32 mcde_ch_colkey;
- volatile u32 mcde_ch_fcolkey;
- volatile u32 mcde_ch_rgbconv1;
- volatile u32 mcde_ch_rgbconv2;
- volatile u32 mcde_ch_rgbconv3;
- volatile u32 mcde_ch_rgbconv4;
- volatile u32 mcde_ch_rgbconv5;
- volatile u32 mcde_ch_rgbconv6;
- volatile u32 mcde_ch_ffcoef0;
- volatile u32 mcde_ch_ffcoef1;
- volatile u32 mcde_ch_ffcoef2;
- volatile u32 unused;
- volatile u32 mcde_ch_tvcr;
- volatile u32 mcde_ch_tvbl1;
- volatile u32 mcde_ch_tvisl;
- volatile u32 mcde_ch_tvdvo;
- volatile u32 mcde_ch_tvswh;
- volatile u32 mcde_ch_tvtim1;
- volatile u32 mcde_ch_tvbalw;
- volatile u32 mcde_ch_tvbl2;
- volatile u32 mcde_ch_tvblu;
- volatile u32 mcde_ch_lcdtim0;
- volatile u32 mcde_ch_lcdtim1;
- volatile u32 mcde_ch_ditctrl;
- volatile u32 mcde_ch_ditoff;
- volatile u32 mcde_ch_pal;
- volatile u32 mcde_ch_gam;
- volatile u32 mcde_rotadd0;
- volatile u32 mcde_rotadd1;
- volatile u32 mcde_chsyn_con;
- volatile u32 mcde_unused7[96];
-};
-
-struct mcde_dsi_reg
-{
- volatile u32 mcde_dsi_conf0;
- volatile u32 mcde_dsi_frame;
- volatile u32 mcde_dsi_pkt;
- volatile u32 mcde_dsi_sync;
- volatile u32 mcde_dsi_cmd;
- volatile u32 mcde_reserved2[3];
-};
-
-struct mcde_chc_reg
-{
- volatile u32 mcde_chc_crc;
- volatile u32 mcde_chc_pbcrc0;
- volatile u32 mcde_chc_pbcrc1;
- volatile u32 mcde_chc_pbcbmrc0[5];
- volatile u32 mcde_chc_pbcbmrc1[5];
- volatile u32 mcde_chc_pbcbcrc0[2];
- volatile u32 mcde_unused5[3];
- volatile u32 mcde_chc_pbcbcrc1[2];
- volatile u32 mcde_unused6[3];
- volatile u32 mcde_chc_vscrc[2];
- volatile u32 mcde_chc_sctrc;
- volatile u32 mcde_chc_scsr;
- volatile u32 mcde_chc_bcnr[2];
- volatile u32 mcde_chc_cscdtr[2];
- volatile u32 mcde_chc_rdwrtr[2];
- volatile u32 mcde_chc_dotr[2];
- volatile u32 mcde_chc_wcmd[2];
- volatile u32 mcde_chc_wd[2];
- volatile u32 mcde_chc_rdata[2];
-};
-
-struct mcde_register_base
-{
- volatile u32 mcde_cr;
- volatile u32 mcde_cfg0;
- volatile u32 mcde_reserved1[62];
- volatile u32 mcde_ais;
- volatile u32 mcde_imsc;
- volatile u32 mcde_ris;
- volatile u32 mcde_mis;
- volatile u32 mcde_sis;
- volatile u32 mcde_ssi;
- volatile u32 mcde_reserved2[57];
- volatile u32 mcde_pid;
-};
-
-#endif /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */
-
-#endif
diff --git a/arch/arm/mach-ux500/mcde.c b/arch/arm/mach-ux500/mcde.c
index ede2bf310ec..b7b5991cbff 100644
--- a/arch/arm/mach-ux500/mcde.c
+++ b/arch/arm/mach-ux500/mcde.c
@@ -1,777 +1,81 @@
/*
- * Copyright (C) 2010 ST Ericsson
+ * Copyright (C) ST-Ericsson AB 2010
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2, as
- * published by the Free Software Foundation.
+ * MOP500/HREF500 ed/v1 Display platform devices
+ *
+ * Author: Marcus Lorentzon <marcus.xm.lorentzon@stericsson.com>
+ * for ST-Ericsson.
+ *
+ * License terms: GNU General Public License (GPL), version 2.
*/
-
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
#include <linux/platform_device.h>
-#include <linux/io.h>
-
-#include <mach/devices.h>
#include <mach/hardware.h>
-#include <mach/mcde.h>
-#include <mach/mcde_common.h>
-
-#ifdef CONFIG_FB_U8500_MCDE_CHANNELC0
-/* Channel C0 */
-
-#ifdef CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT
-
-static struct resource mcde2_resources[] = {
- [0] = {
- .start = U8500_MCDE_BASE,
- .end = U8500_MCDE_BASE + (U8500_MCDE_BASE_SIZE - 1),
- .name = "mcde_top",
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = U8500_MCDE_EXTSRC_BASE,
- .end = U8500_MCDE_EXTSRC_BASE + (U8500_MCDE_EXTSRC_SIZE - 1),
- .name = "mcde_extsrc",
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .start = U8500_MCDE_OVERLAY_BASE,
- .end = U8500_MCDE_OVERLAY_BASE + (U8500_MCDE_OVERLAY_SIZE - 1),
- .name = "mcde_overlay",
- .flags = IORESOURCE_MEM,
- },
- [3] = {
- .start = U8500_MCDE_CHANNELC0_CONFIG_BASE,
- .end = U8500_MCDE_CHANNELC0_CONFIG_BASE + (U8500_MCDE_CHANNEL_CONFIG_SIZE - 1),
- .name = "mcde_chc0_config",
- .flags = IORESOURCE_MEM,
- },
- [4] = {
- .start = U8500_MCDE_CHANNELC0C1_SPECIFIC_REGISTER_BASE,
- .end = U8500_MCDE_CHANNELC0C1_SPECIFIC_REGISTER_BASE + (U8500_MCDE_CHANNELC0C1_SPECIFIC_REGISTER_SIZE - 1),
- .name = "mcde_chc0c1_specific",
- .flags = IORESOURCE_MEM,
- },
- [5] = {
- .start = U8500_MCDE_DSI_CHANNEL_BASE,
- .end = U8500_MCDE_DSI_CHANNEL_BASE + (U8500_MCDE_DSI_CHANNEL_SIZE - 1),
- .name = "mcde_dsi_channel",
- .flags = IORESOURCE_MEM,
- },
- [6] = {
- .start = U8500_DSI_LINK1_BASE,
- .end = U8500_DSI_LINK1_BASE + ((U8500_DSI_LINK_SIZE * U8500_DSI_LINK_COUNT) - 1),
- .name = "dsi_link",
- .flags = IORESOURCE_MEM,
- },
- [7] = {
- .start = PRCM_MCDECLK_MGT_REG,
- .end = PRCM_MCDECLK_MGT_REG + (sizeof(u32) - 1),
- .name = "prcm_mcde_clk",
- .flags = IORESOURCE_MEM,
- },
- [8] = {
- .start = PRCM_HDMICLK_MGT_REG,
- .end = PRCM_HDMICLK_MGT_REG + (sizeof(u32) - 1),
- .name = "prcm_hdmi_clk",
- .flags = IORESOURCE_MEM,
- },
- [9] = {
- .start = PRCM_TVCLK_MGT_REG,
- .end = PRCM_TVCLK_MGT_REG + (sizeof(u32) - 1),
- .name = "prcm_tv_clk",
- .flags = IORESOURCE_MEM,
- },
- [10] = {
- .start = IRQ_DISP,
- .end = IRQ_DISP,
- .name = "mcde_irq",
- .flags = IORESOURCE_IRQ
- },
- [11] = {
- .start = U8500_MCDE_CHANNELA_SPECIFIC_REGISTER_BASE,
- .end = U8500_MCDE_CHANNELA_SPECIFIC_REGISTER_BASE +
- (U8500_MCDE_CHANNELA_SPECIFIC_REGISTER_SIZE - 1),
- .name = "cha_specific",
- .flags = IORESOURCE_MEM,
- },
- [12] = {
- .start = U8500_MCDE_CHANNELB_SPECIFIC_REGISTER_BASE,
- .end = U8500_MCDE_CHANNELB_SPECIFIC_REGISTER_BASE +
- (U8500_MCDE_CHANNELB_SPECIFIC_REGISTER_SIZE - 1),
- .name = "chb_specific",
- .flags = IORESOURCE_MEM,
- },
-};
-
-#else /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */
-
-static struct resource mcde2_resources[] = {
- [0] = {
- .start = U8500_MCDE_BASE,
- .end = U8500_MCDE_BASE + (U8500_MCDE_REGISTER_SIZE - 1),
- .name = "mcde_base",
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = U8500_MCDE_EXTSRC_BASE,
- .end = U8500_MCDE_EXTSRC_BASE + (U8500_MCDE_EXTSRC_SIZE - 1),
- .name = "mcde_extsrc_base",
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .start = U8500_MCDE_OVL_BASE,
- .end = U8500_MCDE_OVL_BASE + (U8500_MCDE_OVL_SIZE - 1),
- .name = "mcde_overlay_base",
- .flags = IORESOURCE_MEM,
- },
- [3] = {
- .start = U8500_MCDE_CHANNELC0_CONFIG_BASE,
- .end = U8500_MCDE_CHANNELC0_CONFIG_BASE +
- (U8500_MCDE_CHANNEL_CONFIG_SIZE - 1),
- .name = "chc0_config",
- .flags = IORESOURCE_MEM,
- },
- [4] = {
- .start = U8500_MCDE_CHANNELC_SPECIFIC_REGISTER_BASE,
- .end = U8500_MCDE_CHANNELC_SPECIFIC_REGISTER_BASE +
- (U8500_MCDE_CHANNELC_SPECIFIC_REGISTER_SIZE - 1),
- .name = "chb_specific",
- .flags = IORESOURCE_MEM,
- },
- [5] = {
- .start = U8500_MCDE_DSI_CHANNEL_BASE,
- .end = U8500_MCDE_DSI_CHANNEL_BASE + (U8500_MCDE_DSI_SIZE - 1),
- .name = "mcde_dsi_channel_base",
- .flags = IORESOURCE_MEM,
- },
- [6] = {
- .start = U8500_DSI_LINK1_BASE,
- .end = U8500_DSI_LINK1_BASE +
- ((U8500_DSI_LINK_SIZE*U8500_DSI_LINK_COUNT) - 1),
- .name = "dsi_link_base",
- .flags = IORESOURCE_MEM,
- },
- [7] = {
- .start = PRCM_MCDECLK_MGT_REG,
- .end = PRCM_MCDECLK_MGT_REG + (sizeof(u32) - 1),
- .name = "prcm_mcde_clk",
- .flags = IORESOURCE_MEM,
- },
- [8] = {
- .start = PRCM_HDMICLK_MGT_REG,
- .end = PRCM_HDMICLK_MGT_REG + (sizeof(u32) - 1),
- .name = "prcm_hdmi_clk",
- .flags = IORESOURCE_MEM,
- },
- [9] = {
- .start = PRCM_TVCLK_MGT_REG,
- .end = PRCM_TVCLK_MGT_REG + (sizeof(u32) - 1),
- .name = "prcm_tv_clk",
- .flags = IORESOURCE_MEM,
- },
- [10] = {
- .start = IRQ_DISP,
- .end = IRQ_DISP,
- .name = "mcde_irq",
- .flags = IORESOURCE_IRQ
- },
- [11] = {
- .start = U8500_MCDE_CHANNELA_SPECIFIC_REGISTER_BASE,
- .end = U8500_MCDE_CHANNELA_SPECIFIC_REGISTER_BASE +
- (U8500_MCDE_CHANNEL_SPECIFIC_REGISTER_SIZE - 1),
- .name = "cha_specific",
- .flags = IORESOURCE_MEM,
- },
-};
-
-#endif /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */
-
-static struct mcde_channel_data mcde2_channel_data = {
- .channelid = CHANNEL_C0,
- .nopan = 1,
- .nowrap = 1,
-#ifdef CONFIG_FB_U8500_MCDE_CHANNELC0
- .restype = CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_TYPE,
- .inbpp = CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_BPP,
- .outbpp = CONFIG_FB_U8500_MCDE_CHANNELC0_OUTPUT_BPP,
- .bpp16_type = CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_TYPE,
- .bgrinput = CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_BGR,
-#else
- .restype = "WVGA",
- .inbpp = 16,
- .outbpp = 0x2,
- .bpp16_type = 1,
- .bgrinput = 0x0,
-#endif
-};
-
-struct platform_device u8500_mcde2_device = {
- .name = "U8500-MCDE",
- .id = 2,
- .dev = {
- .init_name = "mcde_bus",
- .coherent_dma_mask = ~0,
- .platform_data = &mcde2_channel_data,
- },
- .num_resources = ARRAY_SIZE(mcde2_resources),
- .resource = mcde2_resources
-};
-#endif /* CONFIG_FB_U8500_MCDE_CHANNELC0 */
-
-#ifdef CONFIG_FB_U8500_MCDE_CHANNELC1
-/* Channel C1 */
-
-#ifdef CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT
-
-static struct resource mcde3_resources[] = {
- [0] = {
- .start = U8500_MCDE_BASE,
- .end = U8500_MCDE_BASE + (U8500_MCDE_BASE_SIZE - 1),
- .name = "mcde_top",
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = U8500_MCDE_EXTSRC_BASE,
- .end = U8500_MCDE_EXTSRC_BASE + (U8500_MCDE_EXTSRC_SIZE - 1),
- .name = "mcde_extsrc",
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .start = U8500_MCDE_OVERLAY_BASE,
- .end = U8500_MCDE_OVERLAY_BASE + (U8500_MCDE_OVERLAY_SIZE - 1),
- .name = "mcde_overlay",
- .flags = IORESOURCE_MEM,
- },
- [3] = {
- .start = U8500_MCDE_CHANNELC1_CONFIG_BASE,
- .end = U8500_MCDE_CHANNELC1_CONFIG_BASE + (U8500_MCDE_CHANNEL_CONFIG_SIZE - 1),
- .name = "mcde_chc1_config",
- .flags = IORESOURCE_MEM,
- },
- [4] = {
- .start = U8500_MCDE_CHANNELC0C1_SPECIFIC_REGISTER_BASE,
- .end = U8500_MCDE_CHANNELC0C1_SPECIFIC_REGISTER_BASE + (U8500_MCDE_CHANNELC0C1_SPECIFIC_REGISTER_SIZE - 1),
- .name = "mcde_chc0c1_specific",
- .flags = IORESOURCE_MEM,
- },
- [5] = {
- .start = U8500_MCDE_DSI_CHANNEL_BASE,
- .end = U8500_MCDE_DSI_CHANNEL_BASE + (U8500_MCDE_DSI_SIZE - 1),
- .name = "mcde_dsi_channel",
- .flags = IORESOURCE_MEM,
- },
- [6] = {
- .start = U8500_DSI_LINK1_BASE,
- .end = U8500_DSI_LINK1_BASE + ((U8500_DSI_LINK_SIZE * U8500_DSI_LINK_COUNT) - 1),
- .name = "dsi_link",
- .flags = IORESOURCE_MEM,
- },
- [7] = {
- .start = PRCM_MCDECLK_MGT_REG,
- .end = PRCM_MCDECLK_MGT_REG + (sizeof(u32) - 1),
- .name = "prcm_mcde_clk",
- .flags = IORESOURCE_MEM,
- },
- [8] = {
- .start = PRCM_HDMICLK_MGT_REG,
- .end = PRCM_HDMICLK_MGT_REG + (sizeof(u32) - 1),
- .name = "prcm_hdmi_clk",
- .flags = IORESOURCE_MEM,
- },
- [9] = {
- .start = PRCM_TVCLK_MGT_REG,
- .end = PRCM_TVCLK_MGT_REG + (sizeof(u32) - 1),
- .name = "prcm_tv_clk",
- .flags = IORESOURCE_MEM,
- },
- [10] = {
- .start = IRQ_DISP,
- .end = IRQ_DISP,
- .name = "mcde_irq",
- .flags = IORESOURCE_IRQ
- },
- [11] = {
- .start = U8500_MCDE_CHANNELA_SPECIFIC_REGISTER_BASE,
- .end = U8500_MCDE_CHANNELA_SPECIFIC_REGISTER_BASE +
- (U8500_MCDE_CHANNELA_SPECIFIC_REGISTER_SIZE - 1),
- .name = "cha_specific",
- .flags = IORESOURCE_MEM,
- },
- [12] = {
- .start = U8500_MCDE_CHANNELB_SPECIFIC_REGISTER_BASE,
- .end = U8500_MCDE_CHANNELB_SPECIFIC_REGISTER_BASE +
- (U8500_MCDE_CHANNELB_SPECIFIC_REGISTER_SIZE - 1),
- .name = "chb_specific",
- .flags = IORESOURCE_MEM,
- },
-};
-
-#else /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */
-
-static struct resource mcde3_resources[] = {
- [0] = {
- .start = U8500_MCDE_BASE,
- .end = U8500_MCDE_BASE + (U8500_MCDE_REGISTER_SIZE - 1),
- .name = "mcde_base",
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = U8500_MCDE_EXTSRC_BASE,
- .end = U8500_MCDE_EXTSRC_BASE + (U8500_MCDE_EXTSRC_SIZE - 1),
- .name = "mcde_extsrc_base",
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .start = U8500_MCDE_OVL_BASE,
- .end = U8500_MCDE_OVL_BASE + (U8500_MCDE_OVL_SIZE - 1),
- .name = "mcde_overlay_base",
- .flags = IORESOURCE_MEM,
- },
- [3] = {
- .start = U8500_MCDE_CHANNELC1_CONFIG_BASE,
- .end = U8500_MCDE_CHANNELC1_CONFIG_BASE +
- (U8500_MCDE_CHANNEL_CONFIG_SIZE - 1),
- .name = "chc1_config",
- .flags = IORESOURCE_MEM,
- },
- [4] = {
- .start = U8500_MCDE_CHANNELC_SPECIFIC_REGISTER_BASE,
- .end = U8500_MCDE_CHANNELC_SPECIFIC_REGISTER_BASE +
- (U8500_MCDE_CHANNELC_SPECIFIC_REGISTER_SIZE - 1),
- .name = "chb_specific",
- .flags = IORESOURCE_MEM,
- },
- [5] = {
- .start = U8500_MCDE_DSI_CHANNEL_BASE,
- .end = U8500_MCDE_DSI_CHANNEL_BASE + (U8500_MCDE_DSI_SIZE - 1),
- .name = "mcde_dsi_channel_base",
- .flags = IORESOURCE_MEM,
- },
- [6] = {
- .start = U8500_DSI_LINK1_BASE,
- .end = U8500_DSI_LINK1_BASE +
- ((U8500_DSI_LINK_SIZE*U8500_DSI_LINK_COUNT) - 1),
- .name = "dsi_link_base",
- .flags = IORESOURCE_MEM,
- },
- [7] = {
- .start = PRCM_MCDECLK_MGT_REG,
- .end = PRCM_MCDECLK_MGT_REG + (sizeof(u32) - 1),
- .name = "prcm_mcde_clk",
- .flags = IORESOURCE_MEM,
- },
- [8] = {
- .start = PRCM_HDMICLK_MGT_REG,
- .end = PRCM_HDMICLK_MGT_REG + (sizeof(u32) - 1),
- .name = "prcm_hdmi_clk",
- .flags = IORESOURCE_MEM,
- },
- [9] = {
- .start = PRCM_TVCLK_MGT_REG,
- .end = PRCM_TVCLK_MGT_REG + (sizeof(u32) - 1),
- .name = "prcm_tv_clk",
- .flags = IORESOURCE_MEM,
- },
- [10] = {
- .start = IRQ_DISP,
- .end = IRQ_DISP,
- .name = "mcde_irq",
- .flags = IORESOURCE_IRQ
- },
-};
+#include <mach/irqs.h>
+#include <video/mcde.h>
-#endif /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */
-
-static struct mcde_channel_data mcde3_channel_data = {
- .channelid = CHANNEL_C1,
- .nopan = 1,
- .nowrap = 1,
-#ifdef CONFIG_FB_U8500_MCDE_CHANNELC1
- .restype = CONFIG_FB_U8500_MCDE_CHANNELC1_DISPLAY_TYPE,
- .inbpp = CONFIG_FB_U8500_MCDE_CHANNELC1_INPUT_BPP,
- .outbpp = CONFIG_FB_U8500_MCDE_CHANNELC1_OUTPUT_BPP,
- .bpp16_type = CONFIG_FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_TYPE,
- .bgrinput = CONFIG_FB_U8500_MCDE_CHANNELC1_INPUT_BGR,
-#else
- .restype = "WVGA",
- .inbpp = 16,
- .outbpp = 0x2,
- .bpp16_type = 1,
- .bgrinput = 0x0,
-#endif
-};
-
-struct platform_device u8500_mcde3_device = {
- .name = "U8500-MCDE",
- .id = 3,
- .dev = {
- .bus_id = "mcde_bus",
- .coherent_dma_mask = ~0,
- .platform_data = &mcde3_channel_data,
- },
-
- .num_resources = ARRAY_SIZE(mcde3_resources),
- .resource = mcde3_resources
-};
-#endif /* CONFIG_FB_U8500_MCDE_CHANNELC1 */
-
-#ifdef CONFIG_FB_U8500_MCDE_CHANNELB
-/* Channel B */
-
-#ifdef CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT
-
-static struct resource mcde1_resources[] = {
+static struct resource mcde_resources[] = {
[0] = {
+ .name = MCDE_IO_AREA,
.start = U8500_MCDE_BASE,
- .end = U8500_MCDE_BASE + (U8500_MCDE_BASE_SIZE - 1),
- .name = "mcde_base",
+ .end = U8500_MCDE_BASE + 0x1000 - 1, /* TODO: Fix size */
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = U8500_MCDE_EXTSRC_BASE,
- .end = U8500_MCDE_EXTSRC_BASE + (U8500_MCDE_EXTSRC_SIZE - 1),
- .name = "mcde_extsrc",
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .start = U8500_MCDE_OVERLAY_BASE,
- .end = U8500_MCDE_OVERLAY_BASE + (U8500_MCDE_OVERLAY_SIZE - 1),
- .name = "mcde_overlay",
- .flags = IORESOURCE_MEM,
- },
- [3] = {
- .start = U8500_MCDE_CHANNELB_CONFIG_BASE,
- .end = U8500_MCDE_CHANNELB_CONFIG_BASE + (U8500_MCDE_CHANNEL_CONFIG_SIZE - 1),
- .name = "mcde_chb_config",
- .flags = IORESOURCE_MEM,
- },
- [4] = {
- .start = U8500_MCDE_CHANNELB_SPECIFIC_REGISTER_BASE,
- .end = U8500_MCDE_CHANNELB_SPECIFIC_REGISTER_BASE + (U8500_MCDE_CHANNELB_SPECIFIC_REGISTER_SIZE - 1),
- .name = "mcde_chb_specific",
- .flags = IORESOURCE_MEM,
- },
- [5] = {
- .start = U8500_MCDE_DSI_CHANNEL_BASE,
- .end = U8500_MCDE_DSI_CHANNEL_BASE + (U8500_MCDE_DSI_SIZE - 1),
- .name = "mcde_dsi_channel",
- .flags = IORESOURCE_MEM,
- },
- [6] = {
+ .name = MCDE_IO_AREA,
.start = U8500_DSI_LINK1_BASE,
- .end = U8500_DSI_LINK1_BASE + ((U8500_DSI_LINK_SIZE*U8500_DSI_LINK_COUNT) - 1),
- .name = "dsi_link",
- .flags = IORESOURCE_MEM,
- },
- [7] = {
- .start = PRCM_MCDECLK_MGT_REG,
- .end = PRCM_MCDECLK_MGT_REG + (sizeof(u32) - 1),
- .name = "prcm_mcde_clk",
- .flags = IORESOURCE_MEM,
- },
- [8] = {
- .start = PRCM_HDMICLK_MGT_REG,
- .end = PRCM_HDMICLK_MGT_REG + (sizeof(u32) - 1),
- .name = "prcm_hdmi_clk",
- .flags = IORESOURCE_MEM,
- },
- [9] = {
- .start = PRCM_TVCLK_MGT_REG,
- .end = PRCM_TVCLK_MGT_REG + (sizeof(u32) - 1),
- .name = "prcm_tv_clk",
- .flags = IORESOURCE_MEM,
- },
- [10] = {
- .start = IRQ_DISP,
- .end = IRQ_DISP,
- .name = "mcde_irq",
- .flags = IORESOURCE_IRQ
- },
-};
-
-#else /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */
-
-static struct resource mcde1_resources[] = {
- [0] = {
- .start = U8500_MCDE_BASE,
- .end = U8500_MCDE_BASE + (U8500_MCDE_REGISTER_SIZE - 1),
- .name = "mcde_base",
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = U8500_MCDE_EXTSRC_BASE,
- .end = U8500_MCDE_EXTSRC_BASE + (U8500_MCDE_EXTSRC_SIZE - 1),
- .name = "mcde_extsrc_base",
+ .end = U8500_DSI_LINK1_BASE + U8500_DSI_LINK_SIZE - 1,
.flags = IORESOURCE_MEM,
},
[2] = {
- .start = U8500_MCDE_OVL_BASE,
- .end = U8500_MCDE_OVL_BASE + (U8500_MCDE_OVL_SIZE - 1),
- .name = "mcde_overlay_base",
+ .name = MCDE_IO_AREA,
+ .start = U8500_DSI_LINK2_BASE,
+ .end = U8500_DSI_LINK2_BASE + U8500_DSI_LINK_SIZE - 1,
.flags = IORESOURCE_MEM,
},
[3] = {
- .start = U8500_MCDE_CHANNELB_CONFIG_BASE,
- .end = U8500_MCDE_CHANNELB_CONFIG_BASE +
- (U8500_MCDE_CHANNEL_CONFIG_SIZE - 1),
- .name = "chb_config",
+ .name = MCDE_IO_AREA,
+ .start = U8500_DSI_LINK3_BASE,
+ .end = U8500_DSI_LINK3_BASE + U8500_DSI_LINK_SIZE - 1,
.flags = IORESOURCE_MEM,
},
[4] = {
- .start = U8500_MCDE_CHANNELB_SPECIFIC_REGISTER_BASE,
- .end = U8500_MCDE_CHANNELB_SPECIFIC_REGISTER_BASE +
- (U8500_MCDE_CHANNEL_SPECIFIC_REGISTER_SIZE - 1),
- .name = "chb_specific",
- .flags = IORESOURCE_MEM,
- },
- [5] = {
- .start = U8500_MCDE_DSI_CHANNEL_BASE,
- .end = U8500_MCDE_DSI_CHANNEL_BASE + (U8500_MCDE_DSI_SIZE - 1),
- .name = "mcde_dsi_channel_base",
- .flags = IORESOURCE_MEM,
- },
- [6] = {
- .start = U8500_DSI_LINK1_BASE,
- .end = U8500_DSI_LINK1_BASE +
- ((U8500_DSI_LINK_SIZE*U8500_DSI_LINK_COUNT) - 1),
- .name = "dsi_link_base",
- .flags = IORESOURCE_MEM,
- },
- [7] = {
- .start = PRCM_MCDECLK_MGT_REG,
- .end = PRCM_MCDECLK_MGT_REG + (sizeof(u32) - 1),
- .name = "prcm_mcde_clk",
- .flags = IORESOURCE_MEM,
- },
- [8] = {
- .start = PRCM_HDMICLK_MGT_REG,
- .end = PRCM_HDMICLK_MGT_REG + (sizeof(u32) - 1),
- .name = "prcm_hdmi_clk",
- .flags = IORESOURCE_MEM,
- },
- [9] = {
- .start = PRCM_TVCLK_MGT_REG,
- .end = PRCM_TVCLK_MGT_REG + (sizeof(u32) - 1),
- .name = "prcm_tv_clk",
- .flags = IORESOURCE_MEM,
- },
- [10] = {
+ .name = MCDE_IRQ,
.start = IRQ_DISP,
- .end = IRQ_DISP,
- .name = "mcde_irq",
- .flags = IORESOURCE_IRQ
+ .end = IRQ_DISP,
+ .flags = IORESOURCE_IRQ,
},
};
-#endif /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */
+static void dev_release_noop(struct device *dev)
+{
+ /* Do nothing */
+}
-static struct mcde_channel_data mcde1_channel_data = {
- .channelid = CHANNEL_B,
- .nopan = 1,
- .nowrap = 1,
-#ifdef CONFIG_FB_U8500_MCDE_CHANNELB
- .restype = CONFIG_FB_U8500_MCDE_CHANNELB_DISPLAY_TYPE,
- .inbpp = CONFIG_FB_U8500_MCDE_CHANNELB_INPUT_BPP,
- .outbpp = CONFIG_FB_U8500_MCDE_CHANNELB_OUTPUT_BPP,
- .bpp16_type = CONFIG_FB_U8500_MCDE_CHANNELB_INPUT_16BPP_TYPE,
- .bgrinput = CONFIG_FB_U8500_MCDE_CHANNELB_INPUT_BGR,
-#else
- .restype = "PAL",
- .inbpp = 16,
- .outbpp = 0x2,
- .bpp16_type = 1,
- .bgrinput = 0x0,
-#endif
-#ifdef CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT
- .gpio_alt_func = GPIO_ALT_LCD_PANELB
-#else
- .gpio_alt_func = GPIO_ALT_LCD_PANELB_ED
-#endif
+static struct mcde_platform_data mcde_pdata = {
+ .num_dsilinks = 3,
+ /* YCbCr to AB8500 on D[8:15]: connect LSB Ch B */
+ .outmux = { 0, 3, 0, 0, 0 },
+ .syncmux = 0x01,
+ .regulator_id = "v-ana",
+ .clock_dsi_id = "hdmi",
+ .clock_dsi_lp_id = "tv",
+ .clock_mcde_id = "mcde",
};
-struct platform_device u8500_mcde1_device = {
- .name = "U8500-MCDE",
- .id = 1,
+struct platform_device ux500_mcde_device = {
+ .name = "mcde",
+ .id = -1,
.dev = {
- .bus_id = "mcde_bus",
- .coherent_dma_mask = ~0,
- .platform_data = &mcde1_channel_data,
+ .release = dev_release_noop,
+ .platform_data = &mcde_pdata,
},
- .num_resources = ARRAY_SIZE(mcde1_resources),
- .resource = mcde1_resources
+ .num_resources = ARRAY_SIZE(mcde_resources),
+ .resource = mcde_resources,
};
-#endif /* CONFIG_FB_U8500_MCDE_CHANNELB */
-#ifdef CONFIG_FB_U8500_MCDE_CHANNELA
-/* Channel A */
-#ifdef CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT
-static struct resource mcde0_resources[] = {
- [0] = {
- .start = U8500_MCDE_BASE,
- .end = U8500_MCDE_BASE + (U8500_MCDE_BASE_SIZE - 1),
- .name = "mcde_base",
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = U8500_MCDE_EXTSRC_BASE,
- .end = U8500_MCDE_EXTSRC_BASE + (U8500_MCDE_EXTSRC_SIZE - 1),
- .name = "mcde_extsrc",
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .start = U8500_MCDE_OVERLAY_BASE,
- .end = U8500_MCDE_OVERLAY_BASE + (U8500_MCDE_OVERLAY_SIZE - 1),
- .name = "mcde_overlay",
- .flags = IORESOURCE_MEM,
- },
- [3] = {
- .start = U8500_MCDE_CHANNELA_CONFIG_BASE,
- .end = U8500_MCDE_CHANNELA_CONFIG_BASE + (U8500_MCDE_CHANNEL_CONFIG_SIZE - 1),
- .name = "mcde_cha_config",
- .flags = IORESOURCE_MEM,
- },
- [4] = {
- .start = U8500_MCDE_CHANNELA_SPECIFIC_REGISTER_BASE,
- .end = U8500_MCDE_CHANNELA_SPECIFIC_REGISTER_BASE + (U8500_MCDE_CHANNELA_SPECIFIC_REGISTER_SIZE - 1),
- .name = "mcde_cha_specific",
- .flags = IORESOURCE_MEM,
- },
- [5] = {
- .start = U8500_MCDE_DSI_CHANNEL_BASE,
- .end = U8500_MCDE_DSI_CHANNEL_BASE + (U8500_MCDE_DSI_SIZE - 1),
- .name = "mcde_dsi_channel",
- .flags = IORESOURCE_MEM,
- },
- [6] = {
- .start = U8500_DSI_LINK1_BASE,
- .end = U8500_DSI_LINK1_BASE + ((U8500_DSI_LINK_SIZE * U8500_DSI_LINK_COUNT) - 1),
- .name = "dsi_link",
- .flags = IORESOURCE_MEM,
- },
- [7] = {
- .start = PRCM_MCDECLK_MGT_REG,
- .end = PRCM_MCDECLK_MGT_REG + (sizeof(u32) - 1),
- .name = "prcm_mcde_clk",
- .flags = IORESOURCE_MEM,
- },
- [8] = {
- .start = PRCM_HDMICLK_MGT_REG,
- .end = PRCM_HDMICLK_MGT_REG + (sizeof(u32) - 1),
- .name = "prcm_hdmi_clk",
- .flags = IORESOURCE_MEM,
- },
- [9] = {
- .start = PRCM_TVCLK_MGT_REG,
- .end = PRCM_TVCLK_MGT_REG + (sizeof(u32) - 1),
- .name = "prcm_tv_clk",
- .flags = IORESOURCE_MEM,
- },
- [10] = {
- .start = IRQ_DISP,
- .end = IRQ_DISP,
- .name = "mcde_irq",
- .flags = IORESOURCE_IRQ
- },
-};
-
-#else /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */
-
-static struct resource mcde0_resources[] = {
- [0] = {
- .start = U8500_MCDE_BASE,
- .end = U8500_MCDE_BASE + (U8500_MCDE_REGISTER_SIZE - 1),
- .name = "mcde_base",
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = U8500_MCDE_EXTSRC_BASE,
- .end = U8500_MCDE_EXTSRC_BASE + (U8500_MCDE_EXTSRC_SIZE - 1),
- .name = "mcde_extsrc_base",
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .start = U8500_MCDE_OVL_BASE,
- .end = U8500_MCDE_OVL_BASE + (U8500_MCDE_OVL_SIZE - 1),
- .name = "mcde_overlay_base",
- .flags = IORESOURCE_MEM,
- },
- [3] = {
- .start = U8500_MCDE_CHANNELA_CONFIG_BASE,
- .end = U8500_MCDE_CHANNELA_CONFIG_BASE +
- (U8500_MCDE_CHANNEL_CONFIG_SIZE - 1),
- .name = "cha_config",
- .flags = IORESOURCE_MEM,
- },
- [4] = {
- .start = U8500_MCDE_CHANNELA_SPECIFIC_REGISTER_BASE,
- .end = U8500_MCDE_CHANNELA_SPECIFIC_REGISTER_BASE +
- (U8500_MCDE_CHANNEL_SPECIFIC_REGISTER_SIZE - 1),
- .name = "cha_specific",
- .flags = IORESOURCE_MEM,
- },
- [5] = {
- .start = U8500_MCDE_DSI_CHANNEL_BASE,
- .end = U8500_MCDE_DSI_CHANNEL_BASE + (U8500_MCDE_DSI_SIZE - 1),
- .name = "mcde_dsi_channel_base",
- .flags = IORESOURCE_MEM,
- },
- [6] = {
- .start = U8500_DSI_LINK1_BASE,
- .end = U8500_DSI_LINK1_BASE +
- ((U8500_DSI_LINK_SIZE*U8500_DSI_LINK_COUNT) - 1),
- .name = "dsi_link_base",
- .flags = IORESOURCE_MEM,
- },
- [7] = {
- .start = PRCM_MCDECLK_MGT_REG,
- .end = PRCM_MCDECLK_MGT_REG + (sizeof(u32) - 1),
- .name = "prcm_mcde_clk",
- .flags = IORESOURCE_MEM,
- },
- [8] = {
- .start = PRCM_HDMICLK_MGT_REG,
- .end = PRCM_HDMICLK_MGT_REG + (sizeof(u32) - 1),
- .name = "prcm_hdmi_clk",
- .flags = IORESOURCE_MEM,
- },
- [9] = {
- .start = PRCM_TVCLK_MGT_REG,
- .end = PRCM_TVCLK_MGT_REG + (sizeof(u32) - 1),
- .name = "prcm_tv_clk",
- .flags = IORESOURCE_MEM,
- },
- [10] = {
- .start = IRQ_DISP,
- .end = IRQ_DISP,
- .name = "mcde_irq",
- .flags = IORESOURCE_IRQ
- },
-};
-
-#endif /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */
-
-static struct mcde_channel_data mcde0_channel_data = {
- .channelid = CHANNEL_A,
- .nopan = 1,
- .nowrap = 1,
- .restype = CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_TYPE,
- .inbpp = CONFIG_FB_U8500_MCDE_CHANNELA_INPUT_BPP,
- .outbpp = CONFIG_FB_U8500_MCDE_CHANNELA_OUTPUT_BPP,
- .bpp16_type = CONFIG_FB_U8500_MCDE_CHANNELA_INPUT_16BPP_TYPE,
- .bgrinput = CONFIG_FB_U8500_MCDE_CHANNELA_INPUT_BGR,
- .gpio_alt_func = GPIO_ALT_LCD_PANELA
-};
-struct platform_device u8500_mcde0_device = {
- .name = "U8500-MCDE",
- .id = 0,
- .dev = {
- .bus_id = "mcde_bus",
- .coherent_dma_mask = ~0,
- .platform_data = &mcde0_channel_data,
- },
- .num_resources = ARRAY_SIZE(mcde0_resources),
- .resource = mcde0_resources
-};
-#endif /* CONFIG_FB_U8500_MCDE_CHANNELA */
diff --git a/arch/arm/mach-ux500/mop500-regulators.c b/arch/arm/mach-ux500/mop500-regulators.c
index 4b1cea6a14c..977d54b67e6 100644
--- a/arch/arm/mach-ux500/mop500-regulators.c
+++ b/arch/arm/mach-ux500/mop500-regulators.c
@@ -59,30 +59,10 @@ static struct platform_device db8500_vape_regulator_dev = {
#define U8500_VANA_REGULATOR_MAX_VOLTAGE (1200000)
static struct regulator_consumer_supply db8500_vana_consumers[] = {
-#ifdef CONFIG_FB_U8500_MCDE_CHANNELA
{
- .dev = &u8500_mcde0_device.dev,
+ .dev = &ux500_mcde_device.dev,
.supply = "v-ana",
},
-#endif
-#ifdef CONFIG_FB_U8500_MCDE_CHANNELB
- {
- .dev = &u8500_mcde1_device.dev,
- .supply = "v-ana",
- },
-#endif
-#ifdef CONFIG_FB_U8500_MCDE_CHANNELC0
- {
- .dev = &u8500_mcde2_device.dev,
- .supply = "v-ana",
- },
-#endif
-#ifdef CONFIG_FB_U8500_MCDE_CHANNELC1
- {
- .dev = &u8500_mcde3_device.dev,
- .supply = "v-ana",
- },
-#endif
};
static struct regulator_init_data db8500_vana_init = {
@@ -117,30 +97,10 @@ extern struct platform_device sensors1p_device;
#define AB8500_VAUXN_LDO_MAX_VOLTAGE (3300000)
static struct regulator_consumer_supply ab8500_vaux1_consumers[] = {
-#ifdef CONFIG_FB_U8500_MCDE_CHANNELA
- {
- .dev = &u8500_mcde0_device.dev,
- .supply = "v-mcde",
- },
-#endif
-#ifdef CONFIG_FB_U8500_MCDE_CHANNELB
{
- .dev = &u8500_mcde1_device.dev,
- .supply = "v-mcde",
+ .dev = NULL,
+ .supply = "v-display",
},
-#endif
-#ifdef CONFIG_FB_U8500_MCDE_CHANNELC0
- {
- .dev = &u8500_mcde2_device.dev,
- .supply = "v-mcde",
- },
-#endif
-#ifdef CONFIG_FB_U8500_MCDE_CHANNELC1
- {
- .dev = &u8500_mcde3_device.dev,
- .supply = "v-mcde",
- },
-#endif
#ifdef CONFIG_SENSORS1P_MOP
{
.dev = &sensors1p_device.dev,