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authorKuninori Morimoto <morimoto.kuninori@renesas.com>2010-02-22 05:18:10 +0000
committerPaul Mundt <lethal@linux-sh.org>2010-02-22 19:14:18 +0900
commit16afc9fb0298a66da25ee015eb3c8a8f55e3744a (patch)
tree5e8eb1bda9c3ce75906f93903b06265ec2f2adbf /arch
parent6f26d19fce5907cdd0fd953ac1a1d0b1e6e5982c (diff)
sh: sh7724: Update FSI/SPU2 clock
When FSI and Network (= NFS file system) were used at the same time, the I/O of FSI was unstable. This patch updates the SPU2 clock (which is used for FSI) to solve this issue. Special thanks to Jeremy. Signed-off-by: Jeremy Baker <Jeremy.Baker@renesas.com> Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/sh/boards/mach-ecovec24/setup.c5
-rw-r--r--arch/sh/boards/mach-se/7724/setup.c15
2 files changed, 15 insertions, 5 deletions
diff --git a/arch/sh/boards/mach-ecovec24/setup.c b/arch/sh/boards/mach-ecovec24/setup.c
index a17dbb3ac73..6f2e8a78b46 100644
--- a/arch/sh/boards/mach-ecovec24/setup.c
+++ b/arch/sh/boards/mach-ecovec24/setup.c
@@ -1105,6 +1105,11 @@ static int __init arch_setup(void)
gpio_request(GPIO_FN_FSIOBLRCK, NULL);
gpio_request(GPIO_FN_CLKAUDIOBO, NULL);
+ /* set SPU2 clock to 83.4 MHz */
+ clk = clk_get(NULL, "spu_clk");
+ clk_set_rate(clk, clk_round_rate(clk, 83333333));
+ clk_put(clk);
+
/* change parent of FSI B */
clk = clk_get(NULL, "fsib_clk");
clk_register(&fsimckb_clk);
diff --git a/arch/sh/boards/mach-se/7724/setup.c b/arch/sh/boards/mach-se/7724/setup.c
index 50e4d159957..1f6cf860494 100644
--- a/arch/sh/boards/mach-se/7724/setup.c
+++ b/arch/sh/boards/mach-se/7724/setup.c
@@ -586,7 +586,7 @@ arch_initcall(arch_setup);
static int __init devices_setup(void)
{
u16 sw = __raw_readw(SW4140); /* select camera, monitor */
- struct clk *fsia_clk;
+ struct clk *clk;
/* register board specific self-refresh code */
sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF,
@@ -755,13 +755,18 @@ static int __init devices_setup(void)
gpio_request(GPIO_FN_CLKAUDIOBO, NULL);
gpio_request(GPIO_FN_FSIIASD, NULL);
+ /* set SPU2 clock to 83.4 MHz */
+ clk = clk_get(NULL, "spu_clk");
+ clk_set_rate(clk, clk_round_rate(clk, 83333333));
+ clk_put(clk);
+
/* change parent of FSI A */
- fsia_clk = clk_get(NULL, "fsia_clk");
+ clk = clk_get(NULL, "fsia_clk");
clk_register(&fsimcka_clk);
- clk_set_parent(fsia_clk, &fsimcka_clk);
- clk_set_rate(fsia_clk, 11000);
+ clk_set_parent(clk, &fsimcka_clk);
+ clk_set_rate(clk, 11000);
clk_set_rate(&fsimcka_clk, 11000);
- clk_put(fsia_clk);
+ clk_put(clk);
/* SDHI0 connected to cn7 */
gpio_request(GPIO_FN_SDHI0CD, NULL);