aboutsummaryrefslogtreecommitdiff
path: root/arch/mips/include
diff options
context:
space:
mode:
authorRalf Baechle <ralf@linux-mips.org>2010-03-23 00:02:43 +0100
committerRalf Baechle <ralf@linux-mips.org>2010-04-12 17:26:19 +0100
commit8d9df29db273ab9a330828f4f4f6669d293a730a (patch)
tree7f5e9c87125d53fc2a512be150b01f6116918b3f /arch/mips/include
parent9538ca636f2fa28ae1514327328e2869f0215981 (diff)
downloadlinux-2.6.34-ux500-8d9df29db273ab9a330828f4f4f6669d293a730a.tar.gz
MIPS: Sibyte: Apply M3 workaround only on affected chip types and versions.
Previously it was unconditionally used on all Sibyte family SOCs. The M3 bug has to be handled in the TLB exception handler which is extremly performance sensitive, so this modification is expected to deliver around 2-3% performance improvment. This is important as required changes to the M3 workaround will make it more costly. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include')
-rw-r--r--arch/mips/include/asm/mach-sibyte/war.h6
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/mips/include/asm/mach-sibyte/war.h b/arch/mips/include/asm/mach-sibyte/war.h
index 7950ef4f032..743385d7b5f 100644
--- a/arch/mips/include/asm/mach-sibyte/war.h
+++ b/arch/mips/include/asm/mach-sibyte/war.h
@@ -16,7 +16,11 @@
#if defined(CONFIG_SB1_PASS_1_WORKAROUNDS) || \
defined(CONFIG_SB1_PASS_2_WORKAROUNDS)
-#define BCM1250_M3_WAR 1
+#ifndef __ASSEMBLY__
+extern int sb1250_m3_workaround_needed(void);
+#endif
+
+#define BCM1250_M3_WAR sb1250_m3_workaround_needed()
#define SIBYTE_1956_WAR 1
#else