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authorDavid Daney <ddaney@caviumnetworks.com>2010-01-22 14:41:15 -0800
committerRalf Baechle <ralf@linux-mips.org>2010-02-27 12:53:13 +0100
commit1b362e3e350f72c6cb4b3346f6ba92a529082a09 (patch)
treede172b4853b1aaa6684e5b7afed679c88d8ab655 /arch/mips/include
parent2a880986d899f556f5a327bc77cc8760d5bb9c64 (diff)
downloadlinux-2.6.34-ux500-1b362e3e350f72c6cb4b3346f6ba92a529082a09.tar.gz
MIPS: Decode c0_config4 for large TLBs.
For processors that have more than 64 TLBs, we need to decode both config1 and config4 to determine the total number TLBs. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/866/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include')
-rw-r--r--arch/mips/include/asm/mipsregs.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index f4ab3139d73..edda1daf742 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -576,6 +576,10 @@
#define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
+#define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0)
+#define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14)
+#define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
+
#define MIPS_CONF7_WII (_ULCAST_(1) << 31)
#define MIPS_CONF7_RPS (_ULCAST_(1) << 2)