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authorWu Zhangjin <wuzhangjin@gmail.com>2010-04-13 13:16:34 +0800
committerRalf Baechle <ralf@linux-mips.org>2010-05-21 21:31:14 +0100
commitb8853aa3d912f47f649ad8de784ac3afd932437d (patch)
tree02939e404694eb0067b149d54c6191fea04de68f /arch/mips/include/asm
parented1bbdefc39477a1301fb466139ffb0c00f0d006 (diff)
downloadlinux-2.6.34-ux500-b8853aa3d912f47f649ad8de784ac3afd932437d.tar.gz
MIPS: Loongson: update cpu-feature-overrides.h
Loongson doesn't support MIPSR2, therefore, MIPSR2 vectored interrupts (cpu_has_vint) and MIPSR2 external interrupt controller mode (cpu_has_veic) are 0. Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/1112/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm')
-rw-r--r--arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h
index 16210cedd92..675bd8641d5 100644
--- a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h
@@ -52,6 +52,8 @@
#define cpu_has_tx39_cache 0
#define cpu_has_userlocal 0
#define cpu_has_vce 0
+#define cpu_has_veic 0
+#define cpu_has_vint 0
#define cpu_has_vtag_icache 0
#define cpu_has_watch 1